1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
// SPDX-License-Identifier: Apache-2.0
package firrtlTests.annotationTests
import firrtl.annotations.{CircuitTarget, GenericTarget, ModuleTarget, Target}
import firrtl.annotations.TargetToken._
import firrtl.testutils.FirrtlPropSpec
class TargetSpec extends FirrtlPropSpec {
def check(comp: Target): Unit = {
val named = Target.convertTarget2Named(comp)
val comp2 = Target.convertNamed2Target(named)
assert(comp.toGenericTarget.complete == comp2)
}
property("Serialization of Targets should work") {
val circuit = CircuitTarget("Circuit")
val top = circuit.module("Top")
val targets: Seq[(Target, String)] =
Seq(
(circuit, "~Circuit"),
(top, "~Circuit|Top"),
(top.instOf("i", "I"), "~Circuit|Top/i:I"),
(top.ref("r"), "~Circuit|Top>r"),
(top.ref("r").index(1).field("hi").clock, "~Circuit|Top>r[1].hi@clock"),
(GenericTarget(None, None, Vector(Ref("r"))), "~???|???>r")
)
targets.foreach {
case (t, str) =>
assert(t.serialize == str, s"$t does not properly serialize")
}
}
property("Should convert to/from Named") {
check(Target(Some("Top"), None, Nil))
check(Target(Some("Top"), Some("Top"), Nil))
check(Target(Some("Top"), Some("Other"), Nil))
val r1 = Seq(Ref("r1"), Field("I"))
val r2 = Seq(Ref("r2"), Index(0))
check(Target(Some("Top"), Some("Top"), r1))
check(Target(Some("Top"), Some("Top"), r2))
}
property("Should enable creating from API") {
val top = ModuleTarget("Top", "Top")
val x_reg0_data = top.instOf("x", "X").ref("reg0").field("data")
top.instOf("x", "x")
top.ref("y")
}
property("Should serialize and deserialize") {
val circuit = CircuitTarget("Circuit")
val top = circuit.module("Top")
val targets: Seq[Target] =
Seq(
circuit,
top,
top.instOf("i", "I"),
top.ref("r"),
top.ref("r").index(1).field("hi").clock,
GenericTarget(None, None, Vector(Ref("r")))
)
targets.foreach { t =>
assert(Target.deserialize(t.serialize) == t, s"$t does not properly serialize/deserialize")
}
}
property("Pretty Printer should work") {
val circuit = CircuitTarget("A")
val top = circuit.module("B")
val targets = Seq(
(circuit, "circuit A:"),
(top, """|circuit A:
|└── module B:""".stripMargin),
(top.instOf("c", "C"), """|circuit A:
|└── module B:
| └── inst c of C:""".stripMargin),
(top.ref("r"), """|circuit A:
|└── module B:
| └── r""".stripMargin),
(top.ref("r").index(1).field("hi").clock, """|circuit A:
|└── module B:
| └── r[1].hi@clock""".stripMargin),
(GenericTarget(None, None, Vector(Ref("r"))), """|circuit ???:
|└── module ???:
| └── r""".stripMargin)
)
targets.foreach { case (t, str) => assert(t.prettyPrint() == str, s"$t didn't properly prettyPrint") }
}
}
|
