1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
; SPDX-License-Identifier: Apache-2.0
circuit PresetTester :
module Test :
input clock : Clock
input reset : AsyncReset
input x : UInt<4>
output z : UInt<4>
reg r : UInt<4>, clock with : (reset => (reset, UInt(12)))
r <= x
z <= r
module PresetTester :
input clock : Clock
input reset : UInt<1>
reg div : UInt<2>, clock with : (reset => (reset, UInt(0)))
div <= tail(add(div, UInt(1)), 1)
reg slowClkReg : UInt<1>, clock with : (reset => (reset, UInt(0)))
slowClkReg <= eq(div, UInt(0))
node slowClk = asClock(slowClkReg)
reg counter : UInt<4>, clock with : (reset => (reset, UInt(0)))
counter <= tail(add(counter, UInt(1)), 1)
reg x : UInt<5>, slowClk with : (reset => (reset, UInt(9)))
wire z : UInt<5>
wire preset : AsyncReset
preset <= asAsyncReset(UInt(0)) ; should be annotated as Preset
inst i of Test
i.clock <= slowClk
i.reset <= preset
i.x <= x
z <= i.z
when eq(counter, UInt(0)) :
when neq(z, UInt(12)) :
printf(clock, UInt(1), "Assertion 1 failed! z=%d \n",z)
stop(clock, UInt(1), 1)
; Do the async reset
when eq(counter, UInt(1)) :
when neq(z, UInt(9)) :
printf(clock, UInt(1), "Assertion 2 failed! z=%d \n",z)
stop(clock, UInt(1), 1)
; Success!
when eq(counter, UInt(3)) :
stop(clock, UInt(1), 0)
|
