blob: fcba38d5e5eee3d31e6fb3604edbf206e86f90da (
plain)
1
2
3
4
5
6
7
8
|
// See LICENSE for license details.
module ParameterizedViaHeaderAdderExtModule(
input [15:0] foo,
output [15:0] bar
);
`include "VerilogHeaderFile.vh"
assign bar = foo + VALUE;
endmodule
|