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defpackage firrtl/compiler :
import core
import verse
import firrtl/passes
import firrtl/chirrtl
import firrtl/errors
;import firrtl/flo
;import firrtl/verilog
import firrtl/ir2
import firrtl/ir-utils
import firrtl/firrtl
;public defstruct StandardFlo <: Compiler :
; with-output : (() -> False) -> False with: (as-method => true)
;public defmethod passes (c:StandardFlo) -> List<Pass> :
; to-list $ [
; RemoveSpecialChars()
; RemoveScopes()
; CheckHighForm()
; ;; TempElimination()
; ToWorkingIR()
; ResolveKinds()
; CheckKinds()
; InferTypes()
; CheckTypes()
; ResolveGenders()
; CheckGenders()
; ExpandAccessors()
; LowerToGround()
; InlineIndexed()
; ExpandWhens()
; InferWidths()
; Pad()
; Inline()
; SplitExp()
; ToRealIR()
; CheckWidths()
; ;RemoveSpecialChars()
; CheckHighForm()
; CheckLowForm()
; Flo(with-output(c))
; ]
public defstruct StandardVerilog <: Compiler :
with-output : (() -> False) -> False with: (as-method => true)
public defmethod backend (c:StandardVerilog) -> List<Pass> :
to-list $ [ Verilog(with-output(c)) ]
public defmethod passes (c:StandardVerilog) -> List<Pass> :
to-list $ [
;RemoveSpecialChars()
;TempElimination() ; Needs to check number of uses
;===============
CInferTypes()
CInferMDir()
RemoveCHIRRTL()
;===============
CheckHighForm()
;===============
ToWorkingIR()
;===============
ResolveKinds()
InferTypes()
CheckTypes()
ResolveGenders()
CheckGenders()
InferWidths()
CheckWidths()
;===============
PullMuxes()
;===============
ExpandConnects()
;===============
RemoveAccesses()
;===============
ExpandWhens()
;===============
CheckInitialization()
;===============
ConstProp()
;===============
SplitExp()
;===============
ResolveKinds()
InferTypes()
CheckTypes()
ResolveGenders()
CheckGenders()
InferWidths()
CheckWidths()
;===============
LowerTypes()
;===============
ResolveKinds()
InferTypes()
CheckTypes()
ResolveGenders()
CheckGenders()
InferWidths()
CheckWidths()
;===============
VerilogRename()
Verilog(with-output(c))
;===============
;ToRealIR()
;Pad()
;CheckWidths()
;CheckHighForm()
;CheckLowForm()
;Verilog(with-output(c))
]
public defstruct StandardFIRRTL <: Compiler :
with-output : (() -> False) -> False with: (as-method => true)
public defmethod backend (c:StandardFIRRTL) -> List<Pass> :
to-list $ [ FIRRTL(with-output(c)) ]
public defmethod passes (c:StandardFIRRTL) -> List<Pass> :
to-list $ [
CheckHighForm()
FIRRTL(with-output(c))
]
public defstruct StandardLoFIRRTL <: Compiler :
with-output : (() -> False) -> False with: (as-method => true)
public defmethod backend (c:StandardLoFIRRTL) -> List<Pass> :
to-list $ [ FIRRTL(with-output(c)) ]
public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> :
to-list $ [
;===============
RemoveCHIRRTL()
;===============
CheckHighForm()
;===============
ToWorkingIR()
;===============
ResolveKinds()
InferTypes()
CheckTypes()
ResolveGenders()
CheckGenders()
InferWidths()
CheckWidths()
;===============
Resolve()
;===============
ExpandConnects()
;===============
RemoveAccesses()
;===============
ExpandWhens()
;===============
CheckInitialization()
;===============
ConstProp()
;===============
SplitExp()
;===============
ResolveKinds()
InferTypes()
CheckTypes()
ResolveGenders()
CheckGenders()
InferWidths()
CheckWidths()
;===============
LowerTypes()
;===============
ResolveKinds()
InferTypes()
CheckTypes()
ResolveGenders()
CheckGenders()
InferWidths()
CheckWidths()
;===============
FIRRTL(with-output(c))
]
;============= DRIVER ======================================
public defn run-backend (c:Circuit,comp:Compiler) :
run-passes(c,backend(comp))
public defn run-passes (c:Circuit,comp:Compiler) -> Circuit:
run-passes(c,passes(comp))
public defn run-passes (c:Circuit,ls:List<Pass>) -> Circuit:
var c*:Circuit = c
println("Compiling!")
if PRINT-CIRCUITS : println("Original Circuit")
if PRINT-CIRCUITS : print(c)
;val start-time = current-time-us()
val start-time = to-int(to-string(current-time-us() / to-long(1000)))
var t = start-time
val time-table = Vector<[String,Int]>()
for p in ls do :
println-all(["Starting " name(p)])
if PRINT-CIRCUITS : println(name(p))
c* = pass(p)(c*)
if PRINT-CIRCUITS : print(c*)
val current-time = to-int(to-string(current-time-us() / to-long(1000)))
println-all(["Finished " name(p)])
println-all(["Milliseconds since start: " current-time - start-time])
println-all(["Milliseconds for this pass: " current-time - t])
println-all(["\n"])
;println-all([current-time - t])
add(time-table,[name(p), current-time - t])
t = current-time
println("===== Time Breakdown =====")
for x in time-table do :
println-all([x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%" " --- " to-float(x[1] as Int * 100) "ms"])
println-all(["Total Time --- " to-float(t - start-time) "ms"])
println("==========================")
println("Done!")
c*
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