blob: ad3616ad2ec9ca9a74840e124ba55b2ad2fccf3b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
|
// See LICENSE for license details.
package firrtl
package passes
package memlib
import ir._
import annotations._
import wiring._
class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform {
def inputForm = MidForm
def outputForm = MidForm
def execute(state: CircuitState): CircuitState = reader match {
case None => state
case Some(r) =>
import CustomYAMLProtocol._
val configs = r.parse[Config]
val cN = CircuitName(state.circuit.main)
val oldAnnos = state.annotations.getOrElse(AnnotationMap(Seq.empty)).annotations
val (as, pins) = configs.foldLeft((oldAnnos, Seq.empty[String])) { case ((annos, pins), config) =>
val source = SourceAnnotation(ComponentName(config.source.name, ModuleName(config.source.module, cN)), config.pin.name)
(annos, pins :+ config.pin.name)
}
state.copy(annotations = Some(AnnotationMap(as :+ PinAnnotation(cN, pins.toSeq))))
}
}
|