src/main/scala/firrtl/backends/verilog/MinimumVerilogEmitter.scala


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package firrtl

import firrtl.stage.TransformManager

class MinimumVerilogEmitter extends VerilogEmitter with Emitter {

  override def prerequisites = firrtl.stage.Forms.AssertsRemoved ++
    firrtl.stage.Forms.LowFormMinimumOptimized

  override def transforms =
    new TransformManager(firrtl.stage.Forms.VerilogMinimumOptimized, prerequisites).flattenedTransformOrder

}