path: root/regress/rocket.fir

circuit Top : 
  module Htif : 
    input clk : Clock
    input reset : UInt<1>
    output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, flip cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    io.host.debug_stats_csr <= io.cpu[0].debug_stats_csr
    reg rx_count : UInt<15>, clk with : (reset => (reset, UInt<15>("h00")))
    reg rx_shifter : UInt<64>, clk
    node T_1212 = bits(rx_shifter, 63, 16)
    node rx_shifter_in = cat(io.host.in.bits, T_1212)
    node next_cmd = bits(rx_shifter_in, 3, 0)
    reg cmd : UInt, clk
    reg size : UInt, clk
    reg pos : UInt, clk
    reg seqno : UInt, clk
    reg addr : UInt, clk
    node T_1225 = and(io.host.in.valid, io.host.in.ready)
    when T_1225 :
      rx_shifter <= rx_shifter_in
      node T_1227 = add(rx_count, UInt<1>("h01"))
      node T_1228 = tail(T_1227, 1)
      rx_count <= T_1228
      node T_1230 = eq(rx_count, UInt<2>("h03"))
      when T_1230 :
        cmd <= next_cmd
        node T_1231 = bits(rx_shifter_in, 15, 4)
        size <= T_1231
        node T_1232 = bits(rx_shifter_in, 15, 7)
        pos <= T_1232
        node T_1233 = bits(rx_shifter_in, 23, 16)
        seqno <= T_1233
        node T_1234 = bits(rx_shifter_in, 63, 24)
        addr <= T_1234
        skip
      skip
    node rx_word_count = shr(rx_count, 2)
    node T_1236 = bits(rx_count, 1, 0)
    node T_1237 = not(T_1236)
    node T_1239 = eq(T_1237, UInt<1>("h00"))
    node rx_word_done = and(io.host.in.valid, T_1239)
    cmem packet_ram : UInt<64>[8]
    node T_1244 = and(rx_word_done, io.host.in.ready)
    when T_1244 :
      node T_1245 = bits(rx_word_count, 2, 0)
      node T_1247 = sub(T_1245, UInt<1>("h01"))
      node T_1248 = tail(T_1247, 1)
      infer mport T_1249 = packet_ram[T_1248], clk
      T_1249 <= rx_shifter_in
      skip
    node csr_addr = bits(addr, 11, 0)
    node csr_coreid = bits(addr, 21, 20)
    infer mport csr_wdata = packet_ram[UInt<1>("h00")], clk
    node T_1261 = bits(size, 2, 0)
    node T_1263 = neq(T_1261, UInt<1>("h00"))
    node T_1264 = bits(addr, 2, 0)
    node T_1266 = neq(T_1264, UInt<1>("h00"))
    node bad_mem_packet = or(T_1263, T_1266)
    node T_1268 = eq(cmd, UInt<1>("h00"))
    node T_1269 = eq(cmd, UInt<1>("h01"))
    node T_1270 = or(T_1268, T_1269)
    node T_1271 = eq(cmd, UInt<2>("h02"))
    node T_1272 = eq(cmd, UInt<2>("h03"))
    node T_1273 = or(T_1271, T_1272)
    node T_1275 = neq(size, UInt<1>("h01"))
    node T_1277 = mux(T_1273, T_1275, UInt<1>("h01"))
    node nack = mux(T_1270, bad_mem_packet, T_1277)
    reg tx_count : UInt<15>, clk with : (reset => (reset, UInt<15>("h00")))
    node tx_subword_count = bits(tx_count, 1, 0)
    node tx_word_count = bits(tx_count, 14, 2)
    node T_1283 = bits(tx_word_count, 2, 0)
    node T_1285 = sub(T_1283, UInt<1>("h01"))
    node packet_ram_raddr = tail(T_1285, 1)
    node T_1287 = and(io.host.out.valid, io.host.out.ready)
    when T_1287 :
      node T_1289 = add(tx_count, UInt<1>("h01"))
      node T_1290 = tail(T_1289, 1)
      tx_count <= T_1290
      skip
    node T_1292 = eq(rx_word_count, UInt<1>("h00"))
    node T_1293 = neq(next_cmd, UInt<1>("h01"))
    node T_1294 = neq(next_cmd, UInt<2>("h03"))
    node T_1295 = and(T_1293, T_1294)
    node T_1296 = eq(rx_word_count, size)
    node T_1297 = bits(rx_word_count, 2, 0)
    node T_1299 = eq(T_1297, UInt<1>("h00"))
    node T_1300 = or(T_1296, T_1299)
    node T_1301 = mux(T_1292, T_1295, T_1300)
    node rx_done = and(rx_word_done, T_1301)
    node T_1304 = eq(nack, UInt<1>("h00"))
    node T_1305 = eq(cmd, UInt<1>("h00"))
    node T_1306 = eq(cmd, UInt<2>("h02"))
    node T_1307 = or(T_1305, T_1306)
    node T_1308 = eq(cmd, UInt<2>("h03"))
    node T_1309 = or(T_1307, T_1308)
    node T_1310 = and(T_1304, T_1309)
    node tx_size = mux(T_1310, size, UInt<1>("h00"))
    node T_1313 = not(tx_subword_count)
    node T_1315 = eq(T_1313, UInt<1>("h00"))
    node T_1316 = and(io.host.out.ready, T_1315)
    node T_1317 = eq(tx_word_count, tx_size)
    node T_1319 = gt(tx_word_count, UInt<1>("h00"))
    node T_1320 = not(packet_ram_raddr)
    node T_1322 = eq(T_1320, UInt<1>("h00"))
    node T_1323 = and(T_1319, T_1322)
    node T_1324 = or(T_1317, T_1323)
    node tx_done = and(T_1316, T_1324)
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1336 = eq(state, UInt<3>("h04"))
    node T_1337 = and(T_1336, io.mem.acquire.ready)
    node T_1338 = eq(state, UInt<3>("h05"))
    node T_1339 = and(T_1338, io.mem.grant.valid)
    node T_1340 = or(T_1337, T_1339)
    reg cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_1340 :
      node T_1344 = eq(cnt, UInt<2>("h03"))
      node T_1346 = and(UInt<1>("h00"), T_1344)
      node T_1349 = add(cnt, UInt<1>("h01"))
      node T_1350 = tail(T_1349, 1)
      node T_1351 = mux(T_1346, UInt<1>("h00"), T_1350)
      cnt <= T_1351
      skip
    node cnt_done = and(T_1340, T_1344)
    node T_1354 = eq(rx_word_count, UInt<1>("h00"))
    node rx_cmd = mux(T_1354, next_cmd, cmd)
    node T_1356 = eq(state, UInt<1>("h00"))
    node T_1357 = and(T_1356, rx_done)
    when T_1357 :
      node T_1358 = eq(rx_cmd, UInt<1>("h00"))
      node T_1359 = eq(rx_cmd, UInt<1>("h01"))
      node T_1360 = eq(rx_cmd, UInt<2>("h02"))
      node T_1361 = eq(rx_cmd, UInt<2>("h03"))
      node T_1362 = or(T_1360, T_1361)
      node T_1363 = mux(T_1362, UInt<1>("h01"), UInt<3>("h07"))
      node T_1364 = mux(T_1359, UInt<3>("h04"), T_1363)
      node T_1365 = mux(T_1358, UInt<2>("h03"), T_1364)
      state <= T_1365
      skip
    node T_1366 = eq(state, UInt<3>("h04"))
    when T_1366 :
      when cnt_done :
        state <= UInt<3>("h06")
        skip
      skip
    node T_1367 = eq(state, UInt<2>("h03"))
    when T_1367 :
      when io.mem.acquire.ready :
        state <= UInt<3>("h05")
        skip
      skip
    node T_1368 = eq(state, UInt<3>("h06"))
    node T_1369 = and(T_1368, io.mem.grant.valid)
    when T_1369 :
      node T_1370 = eq(cmd, UInt<1>("h00"))
      node T_1372 = eq(pos, UInt<1>("h01"))
      node T_1373 = or(T_1370, T_1372)
      node T_1374 = mux(T_1373, UInt<3>("h07"), UInt<1>("h00"))
      state <= T_1374
      node T_1376 = sub(pos, UInt<1>("h01"))
      node T_1377 = tail(T_1376, 1)
      pos <= T_1377
      node T_1379 = add(addr, UInt<4>("h08"))
      node T_1380 = tail(T_1379, 1)
      addr <= T_1380
      skip
    node T_1381 = eq(state, UInt<3>("h05"))
    node T_1382 = and(T_1381, cnt_done)
    when T_1382 :
      node T_1383 = eq(cmd, UInt<1>("h00"))
      node T_1385 = eq(pos, UInt<1>("h01"))
      node T_1386 = or(T_1383, T_1385)
      node T_1387 = mux(T_1386, UInt<3>("h07"), UInt<1>("h00"))
      state <= T_1387
      node T_1389 = sub(pos, UInt<1>("h01"))
      node T_1390 = tail(T_1389, 1)
      pos <= T_1390
      node T_1392 = add(addr, UInt<4>("h08"))
      node T_1393 = tail(T_1392, 1)
      addr <= T_1393
      skip
    node T_1394 = eq(state, UInt<3>("h07"))
    node T_1395 = and(T_1394, tx_done)
    when T_1395 :
      node T_1396 = eq(tx_word_count, tx_size)
      when T_1396 :
        rx_count <= UInt<1>("h00")
        tx_count <= UInt<1>("h00")
        skip
      node T_1399 = eq(cmd, UInt<1>("h00"))
      node T_1401 = neq(pos, UInt<1>("h00"))
      node T_1402 = and(T_1399, T_1401)
      node T_1403 = mux(T_1402, UInt<2>("h03"), UInt<1>("h00"))
      state <= T_1403
      skip
    node T_1405 = eq(state, UInt<3>("h05"))
    node T_1406 = and(T_1405, io.mem.grant.valid)
    when T_1406 :
      node T_1407 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h00"))
      infer mport T_1408 = packet_ram[T_1407], clk
      node T_1409 = bits(io.mem.grant.bits.data, 63, 0)
      T_1408 <= T_1409
      skip
    node T_1410 = cat(cnt, UInt<1>("h00"))
    infer mport T_1411 = packet_ram[T_1410], clk
    node T_1413 = eq(state, UInt<3>("h05"))
    node T_1414 = and(T_1413, io.mem.grant.valid)
    when T_1414 :
      node T_1415 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h01"))
      infer mport T_1416 = packet_ram[T_1415], clk
      node T_1417 = bits(io.mem.grant.bits.data, 127, 64)
      T_1416 <= T_1417
      skip
    node T_1418 = cat(cnt, UInt<1>("h01"))
    infer mport T_1419 = packet_ram[T_1418], clk
    node mem_req_data = cat(T_1419, T_1411)
    node init_addr = shr(addr, 3)
    node T_1422 = eq(state, UInt<2>("h03"))
    node T_1423 = eq(state, UInt<3>("h04"))
    node T_1424 = or(T_1422, T_1423)
    io.mem.acquire.valid <= T_1424
    node T_1425 = eq(cmd, UInt<1>("h01"))
    node T_1453 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_1459 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1460 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1461 = cat(T_1459, T_1460)
    node T_1463 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1464 = cat(UInt<3>("h07"), T_1463)
    node T_1466 = cat(T_1453, UInt<1>("h01"))
    node T_1468 = cat(T_1453, UInt<1>("h01"))
    node T_1470 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1471 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1472 = cat(T_1470, T_1471)
    node T_1474 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1476 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_1477 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_1478 = mux(T_1477, T_1476, UInt<1>("h00"))
    node T_1479 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_1480 = mux(T_1479, T_1474, T_1478)
    node T_1481 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_1482 = mux(T_1481, T_1472, T_1480)
    node T_1483 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_1484 = mux(T_1483, T_1468, T_1482)
    node T_1485 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_1486 = mux(T_1485, T_1466, T_1484)
    node T_1487 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_1488 = mux(T_1487, T_1464, T_1486)
    node T_1489 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_1490 = mux(T_1489, T_1461, T_1488)
    wire T_1522 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    T_1522 is invalid
    T_1522.is_builtin_type <= UInt<1>("h01")
    T_1522.a_type <= UInt<3>("h03")
    T_1522.client_xact_id <= UInt<1>("h00")
    T_1522.addr_block <= init_addr
    T_1522.addr_beat <= cnt
    T_1522.data <= mem_req_data
    T_1522.union <= T_1490
    node T_1563 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1564 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1565 = cat(T_1563, T_1564)
    node T_1567 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1568 = cat(UInt<3>("h07"), T_1567)
    node T_1570 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1572 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1574 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1575 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1576 = cat(T_1574, T_1575)
    node T_1578 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1580 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_1581 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_1582 = mux(T_1581, T_1580, UInt<1>("h00"))
    node T_1583 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_1584 = mux(T_1583, T_1578, T_1582)
    node T_1585 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_1586 = mux(T_1585, T_1576, T_1584)
    node T_1587 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_1588 = mux(T_1587, T_1572, T_1586)
    node T_1589 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_1590 = mux(T_1589, T_1570, T_1588)
    node T_1591 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_1592 = mux(T_1591, T_1568, T_1590)
    node T_1593 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_1594 = mux(T_1593, T_1565, T_1592)
    wire T_1626 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    T_1626 is invalid
    T_1626.is_builtin_type <= UInt<1>("h01")
    T_1626.a_type <= UInt<3>("h01")
    T_1626.client_xact_id <= UInt<1>("h00")
    T_1626.addr_block <= init_addr
    T_1626.addr_beat <= UInt<1>("h00")
    T_1626.data <= UInt<1>("h00")
    T_1626.union <= T_1594
    node T_1657 = mux(T_1425, T_1522, T_1626)
    io.mem.acquire.bits <- T_1657
    io.mem.grant.ready <= UInt<1>("h01")
    reg csrReadData : UInt<64>, clk
    reg T_1692 : UInt<1>, clk with : (reset => (reset, UInt<1>("h01")))
    node T_1694 = eq(csr_coreid, UInt<1>("h00"))
    node T_1695 = eq(state, UInt<1>("h01"))
    node T_1696 = and(T_1695, T_1694)
    node T_1698 = neq(csr_addr, UInt<11>("h0782"))
    node T_1699 = and(T_1696, T_1698)
    io.cpu[0].csr.req.valid <= T_1699
    node T_1700 = eq(cmd, UInt<2>("h03"))
    io.cpu[0].csr.req.bits.rw <= T_1700
    io.cpu[0].csr.req.bits.addr <= csr_addr
    io.cpu[0].csr.req.bits.data <= csr_wdata
    io.cpu[0].reset <= T_1692
    node T_1701 = and(io.cpu[0].csr.req.ready, io.cpu[0].csr.req.valid)
    when T_1701 :
      state <= UInt<2>("h02")
      skip
    node T_1702 = eq(state, UInt<1>("h01"))
    node T_1703 = and(T_1702, T_1694)
    node T_1705 = eq(csr_addr, UInt<11>("h0782"))
    node T_1706 = and(T_1703, T_1705)
    when T_1706 :
      node T_1707 = eq(cmd, UInt<2>("h03"))
      when T_1707 :
        node T_1708 = bits(csr_wdata, 0, 0)
        T_1692 <= T_1708
        skip
      csrReadData <= T_1692
      state <= UInt<3>("h07")
      skip
    io.cpu[0].csr.resp.ready <= UInt<1>("h01")
    node T_1710 = eq(state, UInt<2>("h02"))
    node T_1711 = and(T_1710, io.cpu[0].csr.resp.valid)
    when T_1711 :
      csrReadData <= io.cpu[0].csr.resp.bits
      state <= UInt<3>("h07")
      skip
    node T_1712 = eq(state, UInt<1>("h01"))
    node T_1713 = not(csr_coreid)
    node T_1715 = eq(T_1713, UInt<1>("h00"))
    node T_1716 = and(T_1712, T_1715)
    io.scr.req.valid <= T_1716
    node T_1717 = bits(addr, 5, 0)
    io.scr.req.bits.addr <= T_1717
    io.scr.req.bits.data <= csr_wdata
    node T_1718 = eq(cmd, UInt<2>("h03"))
    io.scr.req.bits.rw <= T_1718
    io.scr.resp.ready <= UInt<1>("h01")
    node T_1720 = and(io.scr.req.ready, io.scr.req.valid)
    when T_1720 :
      state <= UInt<2>("h02")
      skip
    node T_1721 = eq(state, UInt<2>("h02"))
    node T_1722 = and(T_1721, io.scr.resp.valid)
    when T_1722 :
      csrReadData <= io.scr.resp.bits
      state <= UInt<3>("h07")
      skip
    node tx_cmd = mux(nack, UInt<3>("h05"), UInt<3>("h04"))
    node tx_cmd_ext = cat(UInt<1>("h00"), tx_cmd)
    node T_1726 = cat(addr, seqno)
    node T_1727 = cat(tx_size, tx_cmd_ext)
    node tx_header = cat(T_1726, T_1727)
    node T_1730 = eq(tx_word_count, UInt<1>("h00"))
    node T_1731 = eq(cmd, UInt<2>("h02"))
    node T_1732 = eq(cmd, UInt<2>("h03"))
    node T_1733 = or(T_1731, T_1732)
    infer mport T_1734 = packet_ram[packet_ram_raddr], clk
    node T_1735 = mux(T_1733, csrReadData, T_1734)
    node tx_data = mux(T_1730, tx_header, T_1735)
    node T_1737 = eq(state, UInt<1>("h00"))
    io.host.in.ready <= T_1737
    node T_1738 = eq(state, UInt<3>("h07"))
    io.host.out.valid <= T_1738
    node T_1739 = bits(tx_count, 1, 0)
    node T_1741 = cat(T_1739, UInt<4>("h00"))
    node T_1742 = dshr(tx_data, T_1741)
    io.host.out.bits <= T_1742
    
  module ClientTileLinkIOWrapper : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}
    
    io is invalid
    io.out.acquire <- io.in.acquire
    io.in.grant <- io.out.grant
    io.out.probe.ready <= UInt<1>("h01")
    io.out.release.valid <= UInt<1>("h00")
    
  module FinishQueue : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, count : UInt<2>}
    
    io is invalid
    cmem T_877 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}[2]
    reg T_879 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_881 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_883 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_884 = eq(T_879, T_881)
    node T_886 = eq(T_883, UInt<1>("h00"))
    node T_887 = and(T_884, T_886)
    node T_888 = and(T_884, T_883)
    node T_890 = and(UInt<1>("h00"), T_887)
    node T_891 = and(T_890, io.deq.ready)
    node T_892 = and(io.enq.ready, io.enq.valid)
    node T_894 = eq(T_891, UInt<1>("h00"))
    node T_895 = and(T_892, T_894)
    node T_896 = and(io.deq.ready, io.deq.valid)
    node T_898 = eq(T_891, UInt<1>("h00"))
    node T_899 = and(T_896, T_898)
    when T_895 :
      infer mport T_900 = T_877[T_879], clk
      T_900 <- io.enq.bits
      node T_997 = eq(T_879, UInt<1>("h01"))
      node T_999 = and(UInt<1>("h00"), T_997)
      node T_1002 = add(T_879, UInt<1>("h01"))
      node T_1003 = tail(T_1002, 1)
      node T_1004 = mux(T_999, UInt<1>("h00"), T_1003)
      T_879 <= T_1004
      skip
    when T_899 :
      node T_1006 = eq(T_881, UInt<1>("h01"))
      node T_1008 = and(UInt<1>("h00"), T_1006)
      node T_1011 = add(T_881, UInt<1>("h01"))
      node T_1012 = tail(T_1011, 1)
      node T_1013 = mux(T_1008, UInt<1>("h00"), T_1012)
      T_881 <= T_1013
      skip
    node T_1014 = neq(T_895, T_899)
    when T_1014 :
      T_883 <= T_895
      skip
    node T_1016 = eq(T_887, UInt<1>("h00"))
    node T_1018 = and(UInt<1>("h00"), io.enq.valid)
    node T_1019 = or(T_1016, T_1018)
    io.deq.valid <= T_1019
    node T_1021 = eq(T_888, UInt<1>("h00"))
    node T_1023 = and(UInt<1>("h00"), io.deq.ready)
    node T_1024 = or(T_1021, T_1023)
    io.enq.ready <= T_1024
    infer mport T_1025 = T_877[T_881], clk
    node T_1121 = mux(T_890, io.enq.bits, T_1025)
    io.deq.bits <- T_1121
    node T_1217 = sub(T_879, T_881)
    node T_1218 = tail(T_1217, 1)
    node T_1219 = and(T_883, T_884)
    node T_1220 = cat(T_1219, T_1218)
    io.count <= T_1220
    
  module FinishUnit : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>}
    
    io is invalid
    node T_1178 = and(io.grant.ready, io.grant.valid)
    wire T_1183 : UInt<3>[1]
    T_1183[0] <= UInt<3>("h05")
    node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type)
    node T_1188 = or(UInt<1>("h00"), T_1186)
    wire T_1190 : UInt<1>[2]
    T_1190[0] <= UInt<1>("h00")
    T_1190[1] <= UInt<1>("h01")
    node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type)
    node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type)
    node T_1197 = or(UInt<1>("h00"), T_1194)
    node T_1198 = or(T_1197, T_1195)
    node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198)
    node T_1200 = and(UInt<1>("h01"), T_1199)
    node T_1201 = and(T_1178, T_1200)
    reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_1201 :
      node T_1205 = eq(T_1203, UInt<2>("h03"))
      node T_1207 = and(UInt<1>("h00"), T_1205)
      node T_1210 = add(T_1203, UInt<1>("h01"))
      node T_1211 = tail(T_1210, 1)
      node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211)
      T_1203 <= T_1212
      skip
    node T_1213 = and(T_1201, T_1205)
    node T_1214 = mux(T_1200, T_1203, UInt<1>("h00"))
    node T_1215 = mux(T_1200, T_1213, T_1178)
    inst T_1312 of FinishQueue
    T_1312.io is invalid
    T_1312.clk <= clk
    T_1312.reset <= reset
    node T_1313 = and(io.grant.ready, io.grant.valid)
    node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318)
    node T_1321 = eq(T_1319, UInt<1>("h00"))
    node T_1322 = and(T_1316, T_1321)
    node T_1323 = and(T_1313, T_1322)
    wire T_1327 : UInt<3>[1]
    T_1327[0] <= UInt<3>("h05")
    node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type)
    node T_1332 = or(UInt<1>("h00"), T_1330)
    wire T_1334 : UInt<1>[2]
    T_1334[0] <= UInt<1>("h00")
    T_1334[1] <= UInt<1>("h01")
    node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type)
    node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type)
    node T_1341 = or(UInt<1>("h00"), T_1338)
    node T_1342 = or(T_1341, T_1339)
    node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342)
    node T_1344 = and(UInt<1>("h01"), T_1343)
    node T_1346 = eq(T_1344, UInt<1>("h00"))
    node T_1347 = or(T_1346, T_1215)
    node T_1348 = and(T_1323, T_1347)
    T_1312.io.enq.valid <= T_1348
    wire T_1374 : {manager_xact_id : UInt<4>}
    T_1374 is invalid
    T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id
    T_1312.io.enq.bits.fin <- T_1374
    T_1312.io.enq.bits.dst <= io.grant.bits.header.src
    io.finish.bits.header.src <= UInt<1>("h00")
    io.finish.bits.header.dst <= T_1312.io.deq.bits.dst
    io.finish.bits.payload <- T_1312.io.deq.bits.fin
    io.finish.valid <= T_1312.io.deq.valid
    T_1312.io.deq.ready <= io.finish.ready
    node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404)
    node T_1407 = eq(T_1405, UInt<1>("h00"))
    node T_1408 = and(T_1402, T_1407)
    node T_1410 = eq(T_1408, UInt<1>("h00"))
    node T_1411 = or(T_1312.io.enq.ready, T_1410)
    node T_1412 = and(T_1411, io.grant.valid)
    io.refill.valid <= T_1412
    io.refill.bits <- io.grant.bits.payload
    node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417)
    node T_1420 = eq(T_1418, UInt<1>("h00"))
    node T_1421 = and(T_1415, T_1420)
    node T_1423 = eq(T_1421, UInt<1>("h00"))
    node T_1424 = or(T_1312.io.enq.ready, T_1423)
    node T_1425 = and(T_1424, io.refill.ready)
    io.grant.ready <= T_1425
    io.ready <= T_1312.io.enq.ready
    
  module ClientTileLinkNetworkPort : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}}
    
    io is invalid
    inst finisher of FinishUnit
    finisher.io is invalid
    finisher.clk <= clk
    finisher.reset <= reset
    finisher.io.grant <- io.network.grant
    io.network.finish <- finisher.io.finish
    wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}
    acq_with_header is invalid
    acq_with_header.bits.payload <- io.client.acquire.bits
    acq_with_header.bits.header.src <= UInt<1>("h00")
    acq_with_header.bits.header.dst <= UInt<1>("h00")
    acq_with_header.valid <= io.client.acquire.valid
    io.client.acquire.ready <= acq_with_header.ready
    wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}
    rel_with_header is invalid
    rel_with_header.bits.payload <- io.client.release.bits
    rel_with_header.bits.header.src <= UInt<1>("h00")
    rel_with_header.bits.header.dst <= UInt<1>("h00")
    rel_with_header.valid <= io.client.release.valid
    io.client.release.ready <= rel_with_header.ready
    wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}
    prb_without_header is invalid
    prb_without_header.valid <= io.network.probe.valid
    prb_without_header.bits <- io.network.probe.bits.payload
    io.network.probe.ready <= prb_without_header.ready
    io.network.acquire.bits <- acq_with_header.bits
    node T_4978 = and(acq_with_header.valid, finisher.io.ready)
    io.network.acquire.valid <= T_4978
    node T_4979 = and(io.network.acquire.ready, finisher.io.ready)
    acq_with_header.ready <= T_4979
    io.network.release <- rel_with_header
    io.client.probe <- prb_without_header
    io.client.grant <- finisher.io.refill
    
  module Queue : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, count : UInt<2>}
    
    io is invalid
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2]
    reg T_1160 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_1162 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_1160, T_1162)
    node T_1167 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_1167)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_1173 = and(io.enq.ready, io.enq.valid)
    node T_1175 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_1173, T_1175)
    node T_1177 = and(io.deq.ready, io.deq.valid)
    node T_1179 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_1177, T_1179)
    when do_enq :
      infer mport T_1181 = ram[T_1160], clk
      T_1181 <- io.enq.bits
      node T_1309 = eq(T_1160, UInt<1>("h01"))
      node T_1311 = and(UInt<1>("h00"), T_1309)
      node T_1314 = add(T_1160, UInt<1>("h01"))
      node T_1315 = tail(T_1314, 1)
      node T_1316 = mux(T_1311, UInt<1>("h00"), T_1315)
      T_1160 <= T_1316
      skip
    when do_deq :
      node T_1318 = eq(T_1162, UInt<1>("h01"))
      node T_1320 = and(UInt<1>("h00"), T_1318)
      node T_1323 = add(T_1162, UInt<1>("h01"))
      node T_1324 = tail(T_1323, 1)
      node T_1325 = mux(T_1320, UInt<1>("h00"), T_1324)
      T_1162 <= T_1325
      skip
    node T_1326 = neq(do_enq, do_deq)
    when T_1326 :
      maybe_full <= do_enq
      skip
    node T_1328 = eq(empty, UInt<1>("h00"))
    node T_1330 = and(UInt<1>("h00"), io.enq.valid)
    node T_1331 = or(T_1328, T_1330)
    io.deq.valid <= T_1331
    node T_1333 = eq(full, UInt<1>("h00"))
    node T_1335 = and(UInt<1>("h00"), io.deq.ready)
    node T_1336 = or(T_1333, T_1335)
    io.enq.ready <= T_1336
    infer mport T_1337 = ram[T_1162], clk
    node T_1464 = mux(maybe_flow, io.enq.bits, T_1337)
    io.deq.bits <- T_1464
    node T_1591 = sub(T_1160, T_1162)
    node ptr_diff = tail(T_1591, 1)
    node T_1593 = and(maybe_full, ptr_match)
    node T_1594 = cat(T_1593, ptr_diff)
    io.count <= T_1594
    
  module Queue_2 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, count : UInt<2>}
    
    io is invalid
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2]
    reg T_1115 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_1117 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_1115, T_1117)
    node T_1122 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_1122)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_1128 = and(io.enq.ready, io.enq.valid)
    node T_1130 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_1128, T_1130)
    node T_1132 = and(io.deq.ready, io.deq.valid)
    node T_1134 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_1132, T_1134)
    when do_enq :
      infer mport T_1136 = ram[T_1115], clk
      T_1136 <- io.enq.bits
      node T_1259 = eq(T_1115, UInt<1>("h01"))
      node T_1261 = and(UInt<1>("h00"), T_1259)
      node T_1264 = add(T_1115, UInt<1>("h01"))
      node T_1265 = tail(T_1264, 1)
      node T_1266 = mux(T_1261, UInt<1>("h00"), T_1265)
      T_1115 <= T_1266
      skip
    when do_deq :
      node T_1268 = eq(T_1117, UInt<1>("h01"))
      node T_1270 = and(UInt<1>("h00"), T_1268)
      node T_1273 = add(T_1117, UInt<1>("h01"))
      node T_1274 = tail(T_1273, 1)
      node T_1275 = mux(T_1270, UInt<1>("h00"), T_1274)
      T_1117 <= T_1275
      skip
    node T_1276 = neq(do_enq, do_deq)
    when T_1276 :
      maybe_full <= do_enq
      skip
    node T_1278 = eq(empty, UInt<1>("h00"))
    node T_1280 = and(UInt<1>("h00"), io.enq.valid)
    node T_1281 = or(T_1278, T_1280)
    io.deq.valid <= T_1281
    node T_1283 = eq(full, UInt<1>("h00"))
    node T_1285 = and(UInt<1>("h00"), io.deq.ready)
    node T_1286 = or(T_1283, T_1285)
    io.enq.ready <= T_1286
    infer mport T_1287 = ram[T_1117], clk
    node T_1409 = mux(maybe_flow, io.enq.bits, T_1287)
    io.deq.bits <- T_1409
    node T_1531 = sub(T_1115, T_1117)
    node ptr_diff = tail(T_1531, 1)
    node T_1533 = and(maybe_full, ptr_match)
    node T_1534 = cat(T_1533, ptr_diff)
    io.count <= T_1534
    
  module Queue_3 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<2>}
    
    io is invalid
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2]
    reg T_1151 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_1153 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_1151, T_1153)
    node T_1158 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_1158)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_1164 = and(io.enq.ready, io.enq.valid)
    node T_1166 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_1164, T_1166)
    node T_1168 = and(io.deq.ready, io.deq.valid)
    node T_1170 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_1168, T_1170)
    when do_enq :
      infer mport T_1172 = ram[T_1151], clk
      T_1172 <- io.enq.bits
      node T_1299 = eq(T_1151, UInt<1>("h01"))
      node T_1301 = and(UInt<1>("h00"), T_1299)
      node T_1304 = add(T_1151, UInt<1>("h01"))
      node T_1305 = tail(T_1304, 1)
      node T_1306 = mux(T_1301, UInt<1>("h00"), T_1305)
      T_1151 <= T_1306
      skip
    when do_deq :
      node T_1308 = eq(T_1153, UInt<1>("h01"))
      node T_1310 = and(UInt<1>("h00"), T_1308)
      node T_1313 = add(T_1153, UInt<1>("h01"))
      node T_1314 = tail(T_1313, 1)
      node T_1315 = mux(T_1310, UInt<1>("h00"), T_1314)
      T_1153 <= T_1315
      skip
    node T_1316 = neq(do_enq, do_deq)
    when T_1316 :
      maybe_full <= do_enq
      skip
    node T_1318 = eq(empty, UInt<1>("h00"))
    node T_1320 = and(UInt<1>("h00"), io.enq.valid)
    node T_1321 = or(T_1318, T_1320)
    io.deq.valid <= T_1321
    node T_1323 = eq(full, UInt<1>("h00"))
    node T_1325 = and(UInt<1>("h00"), io.deq.ready)
    node T_1326 = or(T_1323, T_1325)
    io.enq.ready <= T_1326
    infer mport T_1327 = ram[T_1153], clk
    node T_1453 = mux(maybe_flow, io.enq.bits, T_1327)
    io.deq.bits <- T_1453
    node T_1579 = sub(T_1151, T_1153)
    node ptr_diff = tail(T_1579, 1)
    node T_1581 = and(maybe_full, ptr_match)
    node T_1582 = cat(T_1581, ptr_diff)
    io.count <= T_1582
    
  module Queue_4 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, count : UInt<2>}
    
    io is invalid
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}[2]
    reg T_1151 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_1153 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_1151, T_1153)
    node T_1158 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_1158)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_1164 = and(io.enq.ready, io.enq.valid)
    node T_1166 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_1164, T_1166)
    node T_1168 = and(io.deq.ready, io.deq.valid)
    node T_1170 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_1168, T_1170)
    when do_enq :
      infer mport T_1172 = ram[T_1151], clk
      T_1172 <- io.enq.bits
      node T_1299 = eq(T_1151, UInt<1>("h01"))
      node T_1301 = and(UInt<1>("h00"), T_1299)
      node T_1304 = add(T_1151, UInt<1>("h01"))
      node T_1305 = tail(T_1304, 1)
      node T_1306 = mux(T_1301, UInt<1>("h00"), T_1305)
      T_1151 <= T_1306
      skip
    when do_deq :
      node T_1308 = eq(T_1153, UInt<1>("h01"))
      node T_1310 = and(UInt<1>("h00"), T_1308)
      node T_1313 = add(T_1153, UInt<1>("h01"))
      node T_1314 = tail(T_1313, 1)
      node T_1315 = mux(T_1310, UInt<1>("h00"), T_1314)
      T_1153 <= T_1315
      skip
    node T_1316 = neq(do_enq, do_deq)
    when T_1316 :
      maybe_full <= do_enq
      skip
    node T_1318 = eq(empty, UInt<1>("h00"))
    node T_1320 = and(UInt<1>("h00"), io.enq.valid)
    node T_1321 = or(T_1318, T_1320)
    io.deq.valid <= T_1321
    node T_1323 = eq(full, UInt<1>("h00"))
    node T_1325 = and(UInt<1>("h00"), io.deq.ready)
    node T_1326 = or(T_1323, T_1325)
    io.enq.ready <= T_1326
    infer mport T_1327 = ram[T_1153], clk
    node T_1453 = mux(maybe_flow, io.enq.bits, T_1327)
    io.deq.bits <- T_1453
    node T_1579 = sub(T_1151, T_1153)
    node ptr_diff = tail(T_1579, 1)
    node T_1581 = and(maybe_full, ptr_match)
    node T_1582 = cat(T_1581, ptr_diff)
    io.count <= T_1582
    
  module Queue_5 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, count : UInt<2>}
    
    io is invalid
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}[2]
    reg T_1106 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_1108 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_1106, T_1108)
    node T_1113 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_1113)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_1119 = and(io.enq.ready, io.enq.valid)
    node T_1121 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_1119, T_1121)
    node T_1123 = and(io.deq.ready, io.deq.valid)
    node T_1125 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_1123, T_1125)
    when do_enq :
      infer mport T_1127 = ram[T_1106], clk
      T_1127 <- io.enq.bits
      node T_1249 = eq(T_1106, UInt<1>("h01"))
      node T_1251 = and(UInt<1>("h00"), T_1249)
      node T_1254 = add(T_1106, UInt<1>("h01"))
      node T_1255 = tail(T_1254, 1)
      node T_1256 = mux(T_1251, UInt<1>("h00"), T_1255)
      T_1106 <= T_1256
      skip
    when do_deq :
      node T_1258 = eq(T_1108, UInt<1>("h01"))
      node T_1260 = and(UInt<1>("h00"), T_1258)
      node T_1263 = add(T_1108, UInt<1>("h01"))
      node T_1264 = tail(T_1263, 1)
      node T_1265 = mux(T_1260, UInt<1>("h00"), T_1264)
      T_1108 <= T_1265
      skip
    node T_1266 = neq(do_enq, do_deq)
    when T_1266 :
      maybe_full <= do_enq
      skip
    node T_1268 = eq(empty, UInt<1>("h00"))
    node T_1270 = and(UInt<1>("h00"), io.enq.valid)
    node T_1271 = or(T_1268, T_1270)
    io.deq.valid <= T_1271
    node T_1273 = eq(full, UInt<1>("h00"))
    node T_1275 = and(UInt<1>("h00"), io.deq.ready)
    node T_1276 = or(T_1273, T_1275)
    io.enq.ready <= T_1276
    infer mport T_1277 = ram[T_1108], clk
    node T_1398 = mux(maybe_flow, io.enq.bits, T_1277)
    io.deq.bits <- T_1398
    node T_1519 = sub(T_1106, T_1108)
    node ptr_diff = tail(T_1519, 1)
    node T_1521 = and(maybe_full, ptr_match)
    node T_1522 = cat(T_1521, ptr_diff)
    io.count <= T_1522
    
  module TileLinkEnqueuer : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}}
    
    io is invalid
    inst T_7778 of Queue
    T_7778.io is invalid
    T_7778.clk <= clk
    T_7778.reset <= reset
    T_7778.io.enq.valid <= io.client.acquire.valid
    T_7778.io.enq.bits <- io.client.acquire.bits
    io.client.acquire.ready <= T_7778.io.enq.ready
    io.manager.acquire <- T_7778.io.deq
    inst T_7901 of Queue_2
    T_7901.io is invalid
    T_7901.clk <= clk
    T_7901.reset <= reset
    T_7901.io.enq.valid <= io.manager.probe.valid
    T_7901.io.enq.bits <- io.manager.probe.bits
    io.manager.probe.ready <= T_7901.io.enq.ready
    io.client.probe <- T_7901.io.deq
    inst T_8028 of Queue_3
    T_8028.io is invalid
    T_8028.clk <= clk
    T_8028.reset <= reset
    T_8028.io.enq.valid <= io.client.release.valid
    T_8028.io.enq.bits <- io.client.release.bits
    io.client.release.ready <= T_8028.io.enq.ready
    io.manager.release <- T_8028.io.deq
    inst T_8155 of Queue_4
    T_8155.io is invalid
    T_8155.clk <= clk
    T_8155.reset <= reset
    T_8155.io.enq.valid <= io.manager.grant.valid
    T_8155.io.enq.bits <- io.manager.grant.bits
    io.manager.grant.ready <= T_8155.io.enq.ready
    io.client.grant <- T_8155.io.deq
    inst T_8277 of Queue_5
    T_8277.io is invalid
    T_8277.clk <= clk
    T_8277.reset <= reset
    T_8277.io.enq.valid <= io.client.finish.valid
    T_8277.io.enq.bits <- io.client.finish.bits
    io.client.finish.ready <= T_8277.io.enq.ready
    io.manager.finish <- T_8277.io.deq
    
  module FinishUnit_7 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>}
    
    io is invalid
    node T_1178 = and(io.grant.ready, io.grant.valid)
    wire T_1183 : UInt<3>[1]
    T_1183[0] <= UInt<3>("h05")
    node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type)
    node T_1188 = or(UInt<1>("h00"), T_1186)
    wire T_1190 : UInt<1>[2]
    T_1190[0] <= UInt<1>("h00")
    T_1190[1] <= UInt<1>("h01")
    node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type)
    node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type)
    node T_1197 = or(UInt<1>("h00"), T_1194)
    node T_1198 = or(T_1197, T_1195)
    node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198)
    node T_1200 = and(UInt<1>("h01"), T_1199)
    node T_1201 = and(T_1178, T_1200)
    reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_1201 :
      node T_1205 = eq(T_1203, UInt<2>("h03"))
      node T_1207 = and(UInt<1>("h00"), T_1205)
      node T_1210 = add(T_1203, UInt<1>("h01"))
      node T_1211 = tail(T_1210, 1)
      node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211)
      T_1203 <= T_1212
      skip
    node T_1213 = and(T_1201, T_1205)
    node T_1214 = mux(T_1200, T_1203, UInt<1>("h00"))
    node T_1215 = mux(T_1200, T_1213, T_1178)
    inst T_1312 of FinishQueue
    T_1312.io is invalid
    T_1312.clk <= clk
    T_1312.reset <= reset
    node T_1313 = and(io.grant.ready, io.grant.valid)
    node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318)
    node T_1321 = eq(T_1319, UInt<1>("h00"))
    node T_1322 = and(T_1316, T_1321)
    node T_1323 = and(T_1313, T_1322)
    wire T_1327 : UInt<3>[1]
    T_1327[0] <= UInt<3>("h05")
    node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type)
    node T_1332 = or(UInt<1>("h00"), T_1330)
    wire T_1334 : UInt<1>[2]
    T_1334[0] <= UInt<1>("h00")
    T_1334[1] <= UInt<1>("h01")
    node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type)
    node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type)
    node T_1341 = or(UInt<1>("h00"), T_1338)
    node T_1342 = or(T_1341, T_1339)
    node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342)
    node T_1344 = and(UInt<1>("h01"), T_1343)
    node T_1346 = eq(T_1344, UInt<1>("h00"))
    node T_1347 = or(T_1346, T_1215)
    node T_1348 = and(T_1323, T_1347)
    T_1312.io.enq.valid <= T_1348
    wire T_1374 : {manager_xact_id : UInt<4>}
    T_1374 is invalid
    T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id
    T_1312.io.enq.bits.fin <- T_1374
    T_1312.io.enq.bits.dst <= io.grant.bits.header.src
    io.finish.bits.header.src <= UInt<1>("h01")
    io.finish.bits.header.dst <= T_1312.io.deq.bits.dst
    io.finish.bits.payload <- T_1312.io.deq.bits.fin
    io.finish.valid <= T_1312.io.deq.valid
    T_1312.io.deq.ready <= io.finish.ready
    node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404)
    node T_1407 = eq(T_1405, UInt<1>("h00"))
    node T_1408 = and(T_1402, T_1407)
    node T_1410 = eq(T_1408, UInt<1>("h00"))
    node T_1411 = or(T_1312.io.enq.ready, T_1410)
    node T_1412 = and(T_1411, io.grant.valid)
    io.refill.valid <= T_1412
    io.refill.bits <- io.grant.bits.payload
    node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417)
    node T_1420 = eq(T_1418, UInt<1>("h00"))
    node T_1421 = and(T_1415, T_1420)
    node T_1423 = eq(T_1421, UInt<1>("h00"))
    node T_1424 = or(T_1312.io.enq.ready, T_1423)
    node T_1425 = and(T_1424, io.refill.ready)
    io.grant.ready <= T_1425
    io.ready <= T_1312.io.enq.ready
    
  module ClientTileLinkNetworkPort_6 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}}
    
    io is invalid
    inst finisher of FinishUnit_7
    finisher.io is invalid
    finisher.clk <= clk
    finisher.reset <= reset
    finisher.io.grant <- io.network.grant
    io.network.finish <- finisher.io.finish
    wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}
    acq_with_header is invalid
    acq_with_header.bits.payload <- io.client.acquire.bits
    acq_with_header.bits.header.src <= UInt<1>("h01")
    acq_with_header.bits.header.dst <= UInt<1>("h00")
    acq_with_header.valid <= io.client.acquire.valid
    io.client.acquire.ready <= acq_with_header.ready
    wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}
    rel_with_header is invalid
    rel_with_header.bits.payload <- io.client.release.bits
    rel_with_header.bits.header.src <= UInt<1>("h01")
    rel_with_header.bits.header.dst <= UInt<1>("h00")
    rel_with_header.valid <= io.client.release.valid
    io.client.release.ready <= rel_with_header.ready
    wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}
    prb_without_header is invalid
    prb_without_header.valid <= io.network.probe.valid
    prb_without_header.bits <- io.network.probe.bits.payload
    io.network.probe.ready <= prb_without_header.ready
    io.network.acquire.bits <- acq_with_header.bits
    node T_4978 = and(acq_with_header.valid, finisher.io.ready)
    io.network.acquire.valid <= T_4978
    node T_4979 = and(io.network.acquire.ready, finisher.io.ready)
    acq_with_header.ready <= T_4979
    io.network.release <- rel_with_header
    io.client.probe <- prb_without_header
    io.client.grant <- finisher.io.refill
    
  module FinishUnit_16 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>}
    
    io is invalid
    node T_1178 = and(io.grant.ready, io.grant.valid)
    wire T_1183 : UInt<3>[1]
    T_1183[0] <= UInt<3>("h05")
    node T_1186 = eq(T_1183[0], io.grant.bits.payload.g_type)
    node T_1188 = or(UInt<1>("h00"), T_1186)
    wire T_1190 : UInt<1>[2]
    T_1190[0] <= UInt<1>("h00")
    T_1190[1] <= UInt<1>("h01")
    node T_1194 = eq(T_1190[0], io.grant.bits.payload.g_type)
    node T_1195 = eq(T_1190[1], io.grant.bits.payload.g_type)
    node T_1197 = or(UInt<1>("h00"), T_1194)
    node T_1198 = or(T_1197, T_1195)
    node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198)
    node T_1200 = and(UInt<1>("h01"), T_1199)
    node T_1201 = and(T_1178, T_1200)
    reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_1201 :
      node T_1205 = eq(T_1203, UInt<2>("h03"))
      node T_1207 = and(UInt<1>("h00"), T_1205)
      node T_1210 = add(T_1203, UInt<1>("h01"))
      node T_1211 = tail(T_1210, 1)
      node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211)
      T_1203 <= T_1212
      skip
    node T_1213 = and(T_1201, T_1205)
    node T_1214 = mux(T_1200, T_1203, UInt<1>("h00"))
    node T_1215 = mux(T_1200, T_1213, T_1178)
    inst T_1312 of FinishQueue
    T_1312.io is invalid
    T_1312.clk <= clk
    T_1312.reset <= reset
    node T_1313 = and(io.grant.ready, io.grant.valid)
    node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318)
    node T_1321 = eq(T_1319, UInt<1>("h00"))
    node T_1322 = and(T_1316, T_1321)
    node T_1323 = and(T_1313, T_1322)
    wire T_1327 : UInt<3>[1]
    T_1327[0] <= UInt<3>("h05")
    node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type)
    node T_1332 = or(UInt<1>("h00"), T_1330)
    wire T_1334 : UInt<1>[2]
    T_1334[0] <= UInt<1>("h00")
    T_1334[1] <= UInt<1>("h01")
    node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type)
    node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type)
    node T_1341 = or(UInt<1>("h00"), T_1338)
    node T_1342 = or(T_1341, T_1339)
    node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342)
    node T_1344 = and(UInt<1>("h01"), T_1343)
    node T_1346 = eq(T_1344, UInt<1>("h00"))
    node T_1347 = or(T_1346, T_1215)
    node T_1348 = and(T_1323, T_1347)
    T_1312.io.enq.valid <= T_1348
    wire T_1374 : {manager_xact_id : UInt<4>}
    T_1374 is invalid
    T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id
    T_1312.io.enq.bits.fin <- T_1374
    T_1312.io.enq.bits.dst <= io.grant.bits.header.src
    io.finish.bits.header.src <= UInt<2>("h02")
    io.finish.bits.header.dst <= T_1312.io.deq.bits.dst
    io.finish.bits.payload <- T_1312.io.deq.bits.fin
    io.finish.valid <= T_1312.io.deq.valid
    T_1312.io.deq.ready <= io.finish.ready
    node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404)
    node T_1407 = eq(T_1405, UInt<1>("h00"))
    node T_1408 = and(T_1402, T_1407)
    node T_1410 = eq(T_1408, UInt<1>("h00"))
    node T_1411 = or(T_1312.io.enq.ready, T_1410)
    node T_1412 = and(T_1411, io.grant.valid)
    io.refill.valid <= T_1412
    io.refill.bits <- io.grant.bits.payload
    node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00"))
    node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417)
    node T_1420 = eq(T_1418, UInt<1>("h00"))
    node T_1421 = and(T_1415, T_1420)
    node T_1423 = eq(T_1421, UInt<1>("h00"))
    node T_1424 = or(T_1312.io.enq.ready, T_1423)
    node T_1425 = and(T_1424, io.refill.ready)
    io.grant.ready <= T_1425
    io.ready <= T_1312.io.enq.ready
    
  module ClientTileLinkNetworkPort_15 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}}
    
    io is invalid
    inst finisher of FinishUnit_16
    finisher.io is invalid
    finisher.clk <= clk
    finisher.reset <= reset
    finisher.io.grant <- io.network.grant
    io.network.finish <- finisher.io.finish
    wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}
    acq_with_header is invalid
    acq_with_header.bits.payload <- io.client.acquire.bits
    acq_with_header.bits.header.src <= UInt<2>("h02")
    acq_with_header.bits.header.dst <= UInt<1>("h00")
    acq_with_header.valid <= io.client.acquire.valid
    io.client.acquire.ready <= acq_with_header.ready
    wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}
    rel_with_header is invalid
    rel_with_header.bits.payload <- io.client.release.bits
    rel_with_header.bits.header.src <= UInt<2>("h02")
    rel_with_header.bits.header.dst <= UInt<1>("h00")
    rel_with_header.valid <= io.client.release.valid
    io.client.release.ready <= rel_with_header.ready
    wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}
    prb_without_header is invalid
    prb_without_header.valid <= io.network.probe.valid
    prb_without_header.bits <- io.network.probe.bits.payload
    io.network.probe.ready <= prb_without_header.ready
    io.network.acquire.bits <- acq_with_header.bits
    node T_4978 = and(acq_with_header.valid, finisher.io.ready)
    io.network.acquire.valid <= T_4978
    node T_4979 = and(io.network.acquire.ready, finisher.io.ready)
    acq_with_header.ready <= T_4979
    io.network.release <- rel_with_header
    io.client.probe <- prb_without_header
    io.client.grant <- finisher.io.refill
    
  module ManagerTileLinkNetworkPort : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}}
    
    io is invalid
    wire T_6833 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}}
    T_6833 is invalid
    T_6833.bits.payload <- io.manager.grant.bits
    T_6833.bits.header.src <= UInt<1>("h00")
    T_6833.bits.header.dst <= io.manager.grant.bits.client_id
    T_6833.valid <= io.manager.grant.valid
    io.manager.grant.ready <= T_6833.ready
    io.network.grant <- T_6833
    wire T_7463 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}}
    T_7463 is invalid
    T_7463.bits.payload <- io.manager.probe.bits
    T_7463.bits.header.src <= UInt<1>("h00")
    T_7463.bits.header.dst <= io.manager.probe.bits.client_id
    T_7463.valid <= io.manager.probe.valid
    io.manager.probe.ready <= T_7463.ready
    io.network.probe <- T_7463
    io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src
    wire T_7778 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}
    T_7778 is invalid
    T_7778.valid <= io.network.acquire.valid
    T_7778.bits <- io.network.acquire.bits.payload
    io.network.acquire.ready <= T_7778.ready
    io.manager.acquire <- T_7778
    io.manager.release.bits.client_id <= io.network.release.bits.header.src
    wire T_7906 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}
    T_7906 is invalid
    T_7906.valid <= io.network.release.valid
    T_7906.bits <- io.network.release.bits.payload
    io.network.release.ready <= T_7906.ready
    io.manager.release <- T_7906
    wire T_8022 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}
    T_8022 is invalid
    T_8022.valid <= io.network.finish.valid
    T_8022.bits <- io.network.finish.bits.payload
    io.network.finish.ready <= T_8022.ready
    io.manager.finish <- T_8022
    
  module Queue_25 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<1>}
    
    io is invalid
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[1]
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1156 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_1156)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_1162 = and(io.enq.ready, io.enq.valid)
    node T_1164 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_1162, T_1164)
    node T_1166 = and(io.deq.ready, io.deq.valid)
    node T_1168 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_1166, T_1168)
    when do_enq :
      infer mport T_1170 = ram[UInt<1>("h00")], clk
      T_1170 <- io.enq.bits
      skip
    when do_deq :
      skip
    node T_1298 = neq(do_enq, do_deq)
    when T_1298 :
      maybe_full <= do_enq
      skip
    node T_1300 = eq(empty, UInt<1>("h00"))
    node T_1302 = and(UInt<1>("h00"), io.enq.valid)
    node T_1303 = or(T_1300, T_1302)
    io.deq.valid <= T_1303
    node T_1305 = eq(full, UInt<1>("h00"))
    node T_1307 = and(UInt<1>("h00"), io.deq.ready)
    node T_1308 = or(T_1305, T_1307)
    io.enq.ready <= T_1308
    infer mport T_1309 = ram[UInt<1>("h00")], clk
    node T_1435 = mux(maybe_flow, io.enq.bits, T_1309)
    io.deq.bits <- T_1435
    node T_1561 = sub(UInt<1>("h00"), UInt<1>("h00"))
    node ptr_diff = tail(T_1561, 1)
    node T_1563 = and(maybe_full, ptr_match)
    node T_1564 = cat(T_1563, ptr_diff)
    io.count <= T_1564
    
  module TileLinkEnqueuer_24 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}}
    
    io is invalid
    io.manager.acquire <- io.client.acquire
    io.client.probe <- io.manager.probe
    inst T_7777 of Queue_25
    T_7777.io is invalid
    T_7777.clk <= clk
    T_7777.reset <= reset
    T_7777.io.enq.valid <= io.client.release.valid
    T_7777.io.enq.bits <- io.client.release.bits
    io.client.release.ready <= T_7777.io.enq.ready
    io.manager.release <- T_7777.io.deq
    io.client.grant <- io.manager.grant
    io.manager.finish <- io.client.finish
    
  module LockingRRArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, chosen : UInt<2>}
    
    io is invalid
    reg T_3348 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_3350 : UInt, clk with : (reset => (reset, UInt<2>("h02")))
    wire T_3352 : UInt<2>
    T_3352 is invalid
    io.out.valid <= io.in[T_3352].valid
    io.out.bits <- io.in[T_3352].bits
    io.chosen <= T_3352
    io.in[T_3352].ready <= UInt<1>("h00")
    reg last_grant : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_4128 = gt(UInt<1>("h00"), last_grant)
    node T_4129 = and(io.in[0].valid, T_4128)
    node T_4131 = gt(UInt<1>("h01"), last_grant)
    node T_4132 = and(io.in[1].valid, T_4131)
    node T_4134 = gt(UInt<2>("h02"), last_grant)
    node T_4135 = and(io.in[2].valid, T_4134)
    node T_4138 = or(UInt<1>("h00"), T_4129)
    node T_4140 = eq(T_4138, UInt<1>("h00"))
    node T_4142 = or(UInt<1>("h00"), T_4129)
    node T_4143 = or(T_4142, T_4132)
    node T_4145 = eq(T_4143, UInt<1>("h00"))
    node T_4147 = or(UInt<1>("h00"), T_4129)
    node T_4148 = or(T_4147, T_4132)
    node T_4149 = or(T_4148, T_4135)
    node T_4151 = eq(T_4149, UInt<1>("h00"))
    node T_4153 = or(UInt<1>("h00"), T_4129)
    node T_4154 = or(T_4153, T_4132)
    node T_4155 = or(T_4154, T_4135)
    node T_4156 = or(T_4155, io.in[0].valid)
    node T_4158 = eq(T_4156, UInt<1>("h00"))
    node T_4160 = or(UInt<1>("h00"), T_4129)
    node T_4161 = or(T_4160, T_4132)
    node T_4162 = or(T_4161, T_4135)
    node T_4163 = or(T_4162, io.in[0].valid)
    node T_4164 = or(T_4163, io.in[1].valid)
    node T_4166 = eq(T_4164, UInt<1>("h00"))
    node T_4168 = gt(UInt<1>("h00"), last_grant)
    node T_4169 = and(UInt<1>("h01"), T_4168)
    node T_4170 = or(T_4169, T_4151)
    node T_4172 = gt(UInt<1>("h01"), last_grant)
    node T_4173 = and(T_4140, T_4172)
    node T_4174 = or(T_4173, T_4158)
    node T_4176 = gt(UInt<2>("h02"), last_grant)
    node T_4177 = and(T_4145, T_4176)
    node T_4178 = or(T_4177, T_4166)
    node T_4180 = eq(T_3350, UInt<1>("h00"))
    node T_4181 = mux(T_3348, T_4180, T_4170)
    node T_4182 = and(T_4181, io.out.ready)
    io.in[0].ready <= T_4182
    node T_4184 = eq(T_3350, UInt<1>("h01"))
    node T_4185 = mux(T_3348, T_4184, T_4174)
    node T_4186 = and(T_4185, io.out.ready)
    io.in[1].ready <= T_4186
    node T_4188 = eq(T_3350, UInt<2>("h02"))
    node T_4189 = mux(T_3348, T_4188, T_4178)
    node T_4190 = and(T_4189, io.out.ready)
    io.in[2].ready <= T_4190
    reg T_4192 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_4194 = add(T_4192, UInt<1>("h01"))
    node T_4195 = tail(T_4194, 1)
    node T_4196 = and(io.out.ready, io.out.valid)
    when T_4196 :
      node T_4198 = and(UInt<1>("h01"), io.out.bits.payload.is_builtin_type)
      wire T_4201 : UInt<3>[1]
      T_4201[0] <= UInt<3>("h03")
      node T_4204 = eq(T_4201[0], io.out.bits.payload.a_type)
      node T_4206 = or(UInt<1>("h00"), T_4204)
      node T_4207 = and(T_4198, T_4206)
      when T_4207 :
        T_4192 <= T_4195
        node T_4209 = eq(T_3348, UInt<1>("h00"))
        when T_4209 :
          T_3348 <= UInt<1>("h01")
          node T_4211 = and(io.in[0].ready, io.in[0].valid)
          node T_4212 = and(io.in[1].ready, io.in[1].valid)
          node T_4213 = and(io.in[2].ready, io.in[2].valid)
          wire T_4215 : UInt<1>[3]
          T_4215[0] <= T_4211
          T_4215[1] <= T_4212
          T_4215[2] <= T_4213
          node T_4223 = mux(T_4215[1], UInt<1>("h01"), UInt<2>("h02"))
          node T_4224 = mux(T_4215[0], UInt<1>("h00"), T_4223)
          T_3350 <= T_4224
          skip
        skip
      node T_4226 = eq(T_4195, UInt<1>("h00"))
      when T_4226 :
        T_3348 <= UInt<1>("h00")
        skip
      skip
    node T_4230 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02"))
    node T_4232 = mux(io.in[0].valid, UInt<1>("h00"), T_4230)
    node T_4234 = gt(UInt<2>("h02"), last_grant)
    node T_4235 = and(io.in[2].valid, T_4234)
    node T_4237 = mux(T_4235, UInt<2>("h02"), T_4232)
    node T_4239 = gt(UInt<1>("h01"), last_grant)
    node T_4240 = and(io.in[1].valid, T_4239)
    node choose = mux(T_4240, UInt<1>("h01"), T_4237)
    node T_4243 = mux(T_3348, T_3350, choose)
    T_3352 <= T_4243
    node T_4244 = and(io.out.ready, io.out.valid)
    when T_4244 :
      last_grant <= T_3352
      skip
    
  module LockingRRArbiter_26 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, chosen : UInt<2>}
    
    io is invalid
    reg T_3322 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_3324 : UInt, clk with : (reset => (reset, UInt<2>("h02")))
    wire T_3326 : UInt<2>
    T_3326 is invalid
    io.out.valid <= io.in[T_3326].valid
    io.out.bits <- io.in[T_3326].bits
    io.chosen <= T_3326
    io.in[T_3326].ready <= UInt<1>("h00")
    reg last_grant : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_4096 = gt(UInt<1>("h00"), last_grant)
    node T_4097 = and(io.in[0].valid, T_4096)
    node T_4099 = gt(UInt<1>("h01"), last_grant)
    node T_4100 = and(io.in[1].valid, T_4099)
    node T_4102 = gt(UInt<2>("h02"), last_grant)
    node T_4103 = and(io.in[2].valid, T_4102)
    node T_4106 = or(UInt<1>("h00"), T_4097)
    node T_4108 = eq(T_4106, UInt<1>("h00"))
    node T_4110 = or(UInt<1>("h00"), T_4097)
    node T_4111 = or(T_4110, T_4100)
    node T_4113 = eq(T_4111, UInt<1>("h00"))
    node T_4115 = or(UInt<1>("h00"), T_4097)
    node T_4116 = or(T_4115, T_4100)
    node T_4117 = or(T_4116, T_4103)
    node T_4119 = eq(T_4117, UInt<1>("h00"))
    node T_4121 = or(UInt<1>("h00"), T_4097)
    node T_4122 = or(T_4121, T_4100)
    node T_4123 = or(T_4122, T_4103)
    node T_4124 = or(T_4123, io.in[0].valid)
    node T_4126 = eq(T_4124, UInt<1>("h00"))
    node T_4128 = or(UInt<1>("h00"), T_4097)
    node T_4129 = or(T_4128, T_4100)
    node T_4130 = or(T_4129, T_4103)
    node T_4131 = or(T_4130, io.in[0].valid)
    node T_4132 = or(T_4131, io.in[1].valid)
    node T_4134 = eq(T_4132, UInt<1>("h00"))
    node T_4136 = gt(UInt<1>("h00"), last_grant)
    node T_4137 = and(UInt<1>("h01"), T_4136)
    node T_4138 = or(T_4137, T_4119)
    node T_4140 = gt(UInt<1>("h01"), last_grant)
    node T_4141 = and(T_4108, T_4140)
    node T_4142 = or(T_4141, T_4126)
    node T_4144 = gt(UInt<2>("h02"), last_grant)
    node T_4145 = and(T_4113, T_4144)
    node T_4146 = or(T_4145, T_4134)
    node T_4148 = eq(T_3324, UInt<1>("h00"))
    node T_4149 = mux(T_3322, T_4148, T_4138)
    node T_4150 = and(T_4149, io.out.ready)
    io.in[0].ready <= T_4150
    node T_4152 = eq(T_3324, UInt<1>("h01"))
    node T_4153 = mux(T_3322, T_4152, T_4142)
    node T_4154 = and(T_4153, io.out.ready)
    io.in[1].ready <= T_4154
    node T_4156 = eq(T_3324, UInt<2>("h02"))
    node T_4157 = mux(T_3322, T_4156, T_4146)
    node T_4158 = and(T_4157, io.out.ready)
    io.in[2].ready <= T_4158
    reg T_4160 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_4162 = add(T_4160, UInt<1>("h01"))
    node T_4163 = tail(T_4162, 1)
    node T_4164 = and(io.out.ready, io.out.valid)
    when T_4164 :
      wire T_4167 : UInt<2>[3]
      T_4167[0] <= UInt<1>("h00")
      T_4167[1] <= UInt<1>("h01")
      T_4167[2] <= UInt<2>("h02")
      node T_4172 = eq(T_4167[0], io.out.bits.payload.r_type)
      node T_4173 = eq(T_4167[1], io.out.bits.payload.r_type)
      node T_4174 = eq(T_4167[2], io.out.bits.payload.r_type)
      node T_4176 = or(UInt<1>("h00"), T_4172)
      node T_4177 = or(T_4176, T_4173)
      node T_4178 = or(T_4177, T_4174)
      node T_4179 = and(UInt<1>("h01"), T_4178)
      when T_4179 :
        T_4160 <= T_4163
        node T_4181 = eq(T_3322, UInt<1>("h00"))
        when T_4181 :
          T_3322 <= UInt<1>("h01")
          node T_4183 = and(io.in[0].ready, io.in[0].valid)
          node T_4184 = and(io.in[1].ready, io.in[1].valid)
          node T_4185 = and(io.in[2].ready, io.in[2].valid)
          wire T_4187 : UInt<1>[3]
          T_4187[0] <= T_4183
          T_4187[1] <= T_4184
          T_4187[2] <= T_4185
          node T_4195 = mux(T_4187[1], UInt<1>("h01"), UInt<2>("h02"))
          node T_4196 = mux(T_4187[0], UInt<1>("h00"), T_4195)
          T_3324 <= T_4196
          skip
        skip
      node T_4198 = eq(T_4163, UInt<1>("h00"))
      when T_4198 :
        T_3322 <= UInt<1>("h00")
        skip
      skip
    node T_4202 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02"))
    node T_4204 = mux(io.in[0].valid, UInt<1>("h00"), T_4202)
    node T_4206 = gt(UInt<2>("h02"), last_grant)
    node T_4207 = and(io.in[2].valid, T_4206)
    node T_4209 = mux(T_4207, UInt<2>("h02"), T_4204)
    node T_4211 = gt(UInt<1>("h01"), last_grant)
    node T_4212 = and(io.in[1].valid, T_4211)
    node choose = mux(T_4212, UInt<1>("h01"), T_4209)
    node T_4215 = mux(T_3322, T_3324, choose)
    T_3326 <= T_4215
    node T_4216 = and(io.out.ready, io.out.valid)
    when T_4216 :
      last_grant <= T_3326
      skip
    
  module RRArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, chosen : UInt<2>}
    
    io is invalid
    wire T_3194 : UInt<2>
    T_3194 is invalid
    io.out.valid <= io.in[T_3194].valid
    io.out.bits <- io.in[T_3194].bits
    io.chosen <= T_3194
    io.in[T_3194].ready <= UInt<1>("h00")
    reg T_3933 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_3934 = gt(UInt<1>("h00"), T_3933)
    node T_3935 = and(io.in[0].valid, T_3934)
    node T_3937 = gt(UInt<1>("h01"), T_3933)
    node T_3938 = and(io.in[1].valid, T_3937)
    node T_3940 = gt(UInt<2>("h02"), T_3933)
    node T_3941 = and(io.in[2].valid, T_3940)
    node T_3944 = or(UInt<1>("h00"), T_3935)
    node T_3946 = eq(T_3944, UInt<1>("h00"))
    node T_3948 = or(UInt<1>("h00"), T_3935)
    node T_3949 = or(T_3948, T_3938)
    node T_3951 = eq(T_3949, UInt<1>("h00"))
    node T_3953 = or(UInt<1>("h00"), T_3935)
    node T_3954 = or(T_3953, T_3938)
    node T_3955 = or(T_3954, T_3941)
    node T_3957 = eq(T_3955, UInt<1>("h00"))
    node T_3959 = or(UInt<1>("h00"), T_3935)
    node T_3960 = or(T_3959, T_3938)
    node T_3961 = or(T_3960, T_3941)
    node T_3962 = or(T_3961, io.in[0].valid)
    node T_3964 = eq(T_3962, UInt<1>("h00"))
    node T_3966 = or(UInt<1>("h00"), T_3935)
    node T_3967 = or(T_3966, T_3938)
    node T_3968 = or(T_3967, T_3941)
    node T_3969 = or(T_3968, io.in[0].valid)
    node T_3970 = or(T_3969, io.in[1].valid)
    node T_3972 = eq(T_3970, UInt<1>("h00"))
    node T_3974 = gt(UInt<1>("h00"), T_3933)
    node T_3975 = and(UInt<1>("h01"), T_3974)
    node T_3976 = or(T_3975, T_3957)
    node T_3978 = gt(UInt<1>("h01"), T_3933)
    node T_3979 = and(T_3946, T_3978)
    node T_3980 = or(T_3979, T_3964)
    node T_3982 = gt(UInt<2>("h02"), T_3933)
    node T_3983 = and(T_3951, T_3982)
    node T_3984 = or(T_3983, T_3972)
    node T_3986 = eq(UInt<2>("h02"), UInt<1>("h00"))
    node T_3987 = mux(UInt<1>("h00"), T_3986, T_3976)
    node T_3988 = and(T_3987, io.out.ready)
    io.in[0].ready <= T_3988
    node T_3990 = eq(UInt<2>("h02"), UInt<1>("h01"))
    node T_3991 = mux(UInt<1>("h00"), T_3990, T_3980)
    node T_3992 = and(T_3991, io.out.ready)
    io.in[1].ready <= T_3992
    node T_3994 = eq(UInt<2>("h02"), UInt<2>("h02"))
    node T_3995 = mux(UInt<1>("h00"), T_3994, T_3984)
    node T_3996 = and(T_3995, io.out.ready)
    io.in[2].ready <= T_3996
    node T_3999 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02"))
    node T_4001 = mux(io.in[0].valid, UInt<1>("h00"), T_3999)
    node T_4003 = gt(UInt<2>("h02"), T_3933)
    node T_4004 = and(io.in[2].valid, T_4003)
    node T_4006 = mux(T_4004, UInt<2>("h02"), T_4001)
    node T_4008 = gt(UInt<1>("h01"), T_3933)
    node T_4009 = and(io.in[1].valid, T_4008)
    node T_4011 = mux(T_4009, UInt<1>("h01"), T_4006)
    node T_4012 = mux(UInt<1>("h00"), UInt<2>("h02"), T_4011)
    T_3194 <= T_4012
    node T_4013 = and(io.out.ready, io.out.valid)
    when T_4013 :
      T_3933 <= T_3194
      skip
    
  module RocketChipTileLinkArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], flip managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}[1]}
    
    io is invalid
    inst T_11386 of ClientTileLinkNetworkPort
    T_11386.io is invalid
    T_11386.clk <= clk
    T_11386.reset <= reset
    inst T_11387 of TileLinkEnqueuer
    T_11387.io is invalid
    T_11387.clk <= clk
    T_11387.reset <= reset
    T_11386.io.client <- io.clients[0]
    T_11387.io.client <- T_11386.io.network
    inst T_11388 of ClientTileLinkNetworkPort_6
    T_11388.io is invalid
    T_11388.clk <= clk
    T_11388.reset <= reset
    inst T_11389 of TileLinkEnqueuer
    T_11389.io is invalid
    T_11389.clk <= clk
    T_11389.reset <= reset
    T_11388.io.client <- io.clients[1]
    T_11389.io.client <- T_11388.io.network
    inst T_11390 of ClientTileLinkNetworkPort_15
    T_11390.io is invalid
    T_11390.clk <= clk
    T_11390.reset <= reset
    inst T_11391 of TileLinkEnqueuer
    T_11391.io is invalid
    T_11391.clk <= clk
    T_11391.reset <= reset
    T_11390.io.client <- io.clients[2]
    T_11391.io.client <- T_11390.io.network
    inst T_11392 of ManagerTileLinkNetworkPort
    T_11392.io is invalid
    T_11392.clk <= clk
    T_11392.reset <= reset
    inst T_11393 of TileLinkEnqueuer_24
    T_11393.io is invalid
    T_11393.clk <= clk
    T_11393.reset <= reset
    T_11392.io.manager <- io.managers[0]
    T_11392.io.network <- T_11393.io.manager
    inst T_11394 of LockingRRArbiter
    T_11394.io is invalid
    T_11394.clk <= clk
    T_11394.reset <= reset
    T_11394.io.in[0].valid <= T_11387.io.manager.acquire.valid
    T_11394.io.in[0].bits <- T_11387.io.manager.acquire.bits
    T_11394.io.in[0].bits.payload.client_xact_id <= T_11387.io.manager.acquire.bits.payload.client_xact_id
    T_11387.io.manager.acquire.ready <= T_11394.io.in[0].ready
    T_11394.io.in[1].valid <= T_11389.io.manager.acquire.valid
    T_11394.io.in[1].bits <- T_11389.io.manager.acquire.bits
    T_11394.io.in[1].bits.payload.client_xact_id <= T_11389.io.manager.acquire.bits.payload.client_xact_id
    T_11389.io.manager.acquire.ready <= T_11394.io.in[1].ready
    T_11394.io.in[2].valid <= T_11391.io.manager.acquire.valid
    T_11394.io.in[2].bits <- T_11391.io.manager.acquire.bits
    T_11394.io.in[2].bits.payload.client_xact_id <= T_11391.io.manager.acquire.bits.payload.client_xact_id
    T_11391.io.manager.acquire.ready <= T_11394.io.in[2].ready
    T_11393.io.client.acquire <- T_11394.io.out
    inst T_11395 of LockingRRArbiter_26
    T_11395.io is invalid
    T_11395.clk <= clk
    T_11395.reset <= reset
    T_11395.io.in[0].valid <= T_11387.io.manager.release.valid
    T_11395.io.in[0].bits <- T_11387.io.manager.release.bits
    T_11395.io.in[0].bits.payload.client_xact_id <= T_11387.io.manager.release.bits.payload.client_xact_id
    T_11387.io.manager.release.ready <= T_11395.io.in[0].ready
    T_11395.io.in[1].valid <= T_11389.io.manager.release.valid
    T_11395.io.in[1].bits <- T_11389.io.manager.release.bits
    T_11395.io.in[1].bits.payload.client_xact_id <= T_11389.io.manager.release.bits.payload.client_xact_id
    T_11389.io.manager.release.ready <= T_11395.io.in[1].ready
    T_11395.io.in[2].valid <= T_11391.io.manager.release.valid
    T_11395.io.in[2].bits <- T_11391.io.manager.release.bits
    T_11395.io.in[2].bits.payload.client_xact_id <= T_11391.io.manager.release.bits.payload.client_xact_id
    T_11391.io.manager.release.ready <= T_11395.io.in[2].ready
    T_11393.io.client.release <- T_11395.io.out
    inst T_11396 of RRArbiter
    T_11396.io is invalid
    T_11396.clk <= clk
    T_11396.reset <= reset
    T_11396.io.in[0] <- T_11387.io.manager.finish
    T_11396.io.in[1] <- T_11389.io.manager.finish
    T_11396.io.in[2] <- T_11391.io.manager.finish
    T_11393.io.client.finish <- T_11396.io.out
    T_11393.io.client.probe.ready <= UInt<1>("h00")
    T_11387.io.manager.probe.valid <= UInt<1>("h00")
    node T_11400 = eq(T_11393.io.client.probe.bits.header.dst, UInt<1>("h00"))
    when T_11400 :
      T_11387.io.manager.probe.valid <= T_11393.io.client.probe.valid
      T_11393.io.client.probe.ready <= T_11387.io.manager.probe.ready
      skip
    T_11387.io.manager.probe.bits <- T_11393.io.client.probe.bits
    T_11389.io.manager.probe.valid <= UInt<1>("h00")
    node T_11403 = eq(T_11393.io.client.probe.bits.header.dst, UInt<1>("h01"))
    when T_11403 :
      T_11389.io.manager.probe.valid <= T_11393.io.client.probe.valid
      T_11393.io.client.probe.ready <= T_11389.io.manager.probe.ready
      skip
    T_11389.io.manager.probe.bits <- T_11393.io.client.probe.bits
    T_11391.io.manager.probe.valid <= UInt<1>("h00")
    node T_11406 = eq(T_11393.io.client.probe.bits.header.dst, UInt<2>("h02"))
    when T_11406 :
      T_11391.io.manager.probe.valid <= T_11393.io.client.probe.valid
      T_11393.io.client.probe.ready <= T_11391.io.manager.probe.ready
      skip
    T_11391.io.manager.probe.bits <- T_11393.io.client.probe.bits
    T_11393.io.client.grant.ready <= UInt<1>("h00")
    T_11387.io.manager.grant.valid <= UInt<1>("h00")
    node T_11410 = eq(T_11393.io.client.grant.bits.header.dst, UInt<1>("h00"))
    when T_11410 :
      T_11387.io.manager.grant.valid <= T_11393.io.client.grant.valid
      T_11393.io.client.grant.ready <= T_11387.io.manager.grant.ready
      skip
    T_11387.io.manager.grant.bits <- T_11393.io.client.grant.bits
    T_11389.io.manager.grant.valid <= UInt<1>("h00")
    node T_11413 = eq(T_11393.io.client.grant.bits.header.dst, UInt<1>("h01"))
    when T_11413 :
      T_11389.io.manager.grant.valid <= T_11393.io.client.grant.valid
      T_11393.io.client.grant.ready <= T_11389.io.manager.grant.ready
      skip
    T_11389.io.manager.grant.bits <- T_11393.io.client.grant.bits
    T_11391.io.manager.grant.valid <= UInt<1>("h00")
    node T_11416 = eq(T_11393.io.client.grant.bits.header.dst, UInt<2>("h02"))
    when T_11416 :
      T_11391.io.manager.grant.valid <= T_11393.io.client.grant.valid
      T_11393.io.client.grant.ready <= T_11391.io.manager.grant.ready
      skip
    T_11391.io.manager.grant.bits <- T_11393.io.client.grant.bits
    
  module BroadcastVoluntaryReleaseTracker : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg xact : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
    wire coh : {sharers : UInt<1>}
    coh is invalid
    coh.sharers <= UInt<1>("h00")
    reg collect_irel_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg irel_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_302 = and(io.inner.release.ready, io.inner.release.valid)
    wire T_306 : UInt<2>[3]
    T_306[0] <= UInt<1>("h00")
    T_306[1] <= UInt<1>("h01")
    T_306[2] <= UInt<2>("h02")
    node T_311 = eq(T_306[0], io.inner.release.bits.r_type)
    node T_312 = eq(T_306[1], io.inner.release.bits.r_type)
    node T_313 = eq(T_306[2], io.inner.release.bits.r_type)
    node T_315 = or(UInt<1>("h00"), T_311)
    node T_316 = or(T_315, T_312)
    node T_317 = or(T_316, T_313)
    node T_318 = and(UInt<1>("h01"), T_317)
    node T_319 = and(T_302, T_318)
    reg T_321 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_319 :
      node T_323 = eq(T_321, UInt<2>("h03"))
      node T_325 = and(UInt<1>("h00"), T_323)
      node T_328 = add(T_321, UInt<1>("h01"))
      node T_329 = tail(T_328, 1)
      node T_330 = mux(T_325, UInt<1>("h00"), T_329)
      T_321 <= T_330
      skip
    node T_331 = and(T_319, T_323)
    node T_332 = mux(T_318, T_321, UInt<1>("h00"))
    node irel_data_done = mux(T_318, T_331, T_302)
    node T_335 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    node T_337 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type)
    wire T_340 : UInt<3>[1]
    T_340[0] <= UInt<3>("h03")
    node T_343 = eq(T_340[0], io.outer.acquire.bits.a_type)
    node T_345 = or(UInt<1>("h00"), T_343)
    node T_346 = and(T_337, T_345)
    node T_347 = and(T_335, T_346)
    reg T_349 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_347 :
      node T_351 = eq(T_349, UInt<2>("h03"))
      node T_353 = and(UInt<1>("h00"), T_351)
      node T_356 = add(T_349, UInt<1>("h01"))
      node T_357 = tail(T_356, 1)
      node T_358 = mux(T_353, UInt<1>("h00"), T_357)
      T_349 <= T_358
      skip
    node T_359 = and(T_347, T_351)
    node oacq_data_cnt = mux(T_346, T_349, UInt<1>("h00"))
    node oacq_data_done = mux(T_346, T_359, T_335)
    io.has_acquire_conflict <= UInt<1>("h00")
    io.has_release_match <= io.inner.release.bits.voluntary
    io.has_acquire_match <= UInt<1>("h00")
    io.outer.acquire.valid <= UInt<1>("h00")
    io.outer.grant.ready <= UInt<1>("h00")
    io.inner.acquire.ready <= UInt<1>("h00")
    io.inner.probe.valid <= UInt<1>("h00")
    io.inner.release.ready <= UInt<1>("h00")
    io.inner.grant.valid <= UInt<1>("h00")
    io.inner.finish.ready <= UInt<1>("h00")
    wire T_384 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_384 is invalid
    T_384.client_id <= xact.client_id
    T_384.is_builtin_type <= UInt<1>("h01")
    T_384.g_type <= UInt<3>("h00")
    T_384.client_xact_id <= xact.client_xact_id
    T_384.manager_xact_id <= UInt<1>("h00")
    T_384.addr_beat <= UInt<1>("h00")
    T_384.data <= UInt<1>("h00")
    io.inner.grant.bits <- T_384
    node T_397 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_403 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_404 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_405 = cat(T_403, T_404)
    node T_407 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_408 = cat(UInt<3>("h07"), T_407)
    node T_410 = cat(T_397, UInt<1>("h01"))
    node T_412 = cat(T_397, UInt<1>("h01"))
    node T_414 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_415 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_416 = cat(T_414, T_415)
    node T_418 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_420 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_421 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_422 = mux(T_421, T_420, UInt<1>("h00"))
    node T_423 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_424 = mux(T_423, T_418, T_422)
    node T_425 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_426 = mux(T_425, T_416, T_424)
    node T_427 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_428 = mux(T_427, T_412, T_426)
    node T_429 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_430 = mux(T_429, T_410, T_428)
    node T_431 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_432 = mux(T_431, T_408, T_430)
    node T_433 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_434 = mux(T_433, T_405, T_432)
    wire T_443 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    T_443 is invalid
    T_443.is_builtin_type <= UInt<1>("h01")
    T_443.a_type <= UInt<3>("h03")
    T_443.client_xact_id <= UInt<1>("h00")
    T_443.addr_block <= xact.addr_block
    T_443.addr_beat <= oacq_data_cnt
    T_443.data <= xact.data_buffer[oacq_data_cnt]
    T_443.union <= T_434
    io.outer.acquire.bits <- T_443
    when collect_irel_data :
      io.inner.release.ready <= UInt<1>("h01")
      when io.inner.release.valid :
        xact.data_buffer[io.inner.release.bits.addr_beat] <= io.inner.release.bits.data
        node T_455 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat)
        node T_456 = or(irel_data_valid, T_455)
        node T_457 = not(irel_data_valid)
        node T_458 = or(T_457, T_455)
        node T_459 = not(T_458)
        node T_460 = mux(UInt<1>("h01"), T_456, T_459)
        irel_data_valid <= T_460
        skip
      when irel_data_done :
        collect_irel_data <= UInt<1>("h00")
        skip
      skip
    node T_462 = eq(UInt<1>("h00"), state)
    when T_462 :
      io.inner.release.ready <= UInt<1>("h01")
      when io.inner.release.valid :
        xact <- io.inner.release.bits
        xact.data_buffer[UInt<1>("h00")] <= io.inner.release.bits.data
        wire T_468 : UInt<2>[3]
        T_468[0] <= UInt<1>("h00")
        T_468[1] <= UInt<1>("h01")
        T_468[2] <= UInt<2>("h02")
        node T_473 = eq(T_468[0], io.inner.release.bits.r_type)
        node T_474 = eq(T_468[1], io.inner.release.bits.r_type)
        node T_475 = eq(T_468[2], io.inner.release.bits.r_type)
        node T_477 = or(UInt<1>("h00"), T_473)
        node T_478 = or(T_477, T_474)
        node T_479 = or(T_478, T_475)
        node T_480 = and(UInt<1>("h01"), T_479)
        collect_irel_data <= T_480
        wire T_482 : UInt<2>[3]
        T_482[0] <= UInt<1>("h00")
        T_482[1] <= UInt<1>("h01")
        T_482[2] <= UInt<2>("h02")
        node T_487 = eq(T_482[0], io.inner.release.bits.r_type)
        node T_488 = eq(T_482[1], io.inner.release.bits.r_type)
        node T_489 = eq(T_482[2], io.inner.release.bits.r_type)
        node T_491 = or(UInt<1>("h00"), T_487)
        node T_492 = or(T_491, T_488)
        node T_493 = or(T_492, T_489)
        node T_494 = dshl(T_493, io.inner.release.bits.addr_beat)
        irel_data_valid <= T_494
        wire T_496 : UInt<2>[3]
        T_496[0] <= UInt<1>("h00")
        T_496[1] <= UInt<1>("h01")
        T_496[2] <= UInt<2>("h02")
        node T_501 = eq(T_496[0], io.inner.release.bits.r_type)
        node T_502 = eq(T_496[1], io.inner.release.bits.r_type)
        node T_503 = eq(T_496[2], io.inner.release.bits.r_type)
        node T_505 = or(UInt<1>("h00"), T_501)
        node T_506 = or(T_505, T_502)
        node T_507 = or(T_506, T_503)
        node T_510 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_511 = mux(T_510, UInt<2>("h03"), UInt<1>("h00"))
        node T_512 = mux(T_507, UInt<1>("h01"), T_511)
        state <= T_512
        skip
      skip
    node T_513 = eq(UInt<1>("h01"), state)
    when T_513 :
      node T_515 = eq(collect_irel_data, UInt<1>("h00"))
      node T_516 = dshr(irel_data_valid, oacq_data_cnt)
      node T_517 = bits(T_516, 0, 0)
      node T_518 = or(T_515, T_517)
      io.outer.acquire.valid <= T_518
      when oacq_data_done :
        state <= UInt<2>("h02")
        skip
      skip
    node T_519 = eq(UInt<2>("h02"), state)
    when T_519 :
      io.outer.grant.ready <= io.inner.grant.ready
      io.inner.grant.valid <= io.outer.grant.valid
      node T_520 = and(io.inner.grant.ready, io.inner.grant.valid)
      when T_520 :
        node T_523 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_525 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_526 = and(io.inner.grant.bits.is_builtin_type, T_525)
        node T_528 = eq(T_526, UInt<1>("h00"))
        node T_529 = and(T_523, T_528)
        node T_530 = mux(T_529, UInt<2>("h03"), UInt<1>("h00"))
        state <= T_530
        skip
      skip
    node T_531 = eq(UInt<2>("h03"), state)
    when T_531 :
      io.inner.finish.ready <= UInt<1>("h01")
      when io.inner.finish.valid :
        state <= UInt<1>("h00")
        skip
      skip
    
  module BroadcastAcquireTracker : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
    wire coh : {sharers : UInt<1>}
    coh is invalid
    coh.sharers <= UInt<1>("h00")
    node T_303 = neq(state, UInt<1>("h00"))
    node T_304 = and(T_303, xact.is_builtin_type)
    wire T_309 : UInt<3>[3]
    T_309[0] <= UInt<3>("h04")
    T_309[1] <= UInt<3>("h05")
    T_309[2] <= UInt<3>("h06")
    node T_314 = eq(T_309[0], xact.a_type)
    node T_315 = eq(T_309[1], xact.a_type)
    node T_316 = eq(T_309[2], xact.a_type)
    node T_318 = or(UInt<1>("h00"), T_314)
    node T_319 = or(T_318, T_315)
    node T_320 = or(T_319, T_316)
    node T_321 = and(T_304, T_320)
    node T_323 = eq(T_321, UInt<1>("h00"))
    node T_325 = eq(reset, UInt<1>("h00"))
    when T_325 :
      node T_327 = eq(T_323, UInt<1>("h00"))
      when T_327 :
        node T_329 = eq(reset, UInt<1>("h00"))
        when T_329 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_334 = bits(pending_probes, 0, 0)
    wire T_336 : UInt<1>[1]
    T_336[0] <= T_334
    node T_341 = asUInt(asSInt(UInt<1>("h01")))
    node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id)
    node T_345 = or(T_341, T_344)
    node T_346 = not(T_341)
    node T_347 = or(T_346, T_344)
    node T_348 = not(T_347)
    node mask_self = mux(UInt<1>("h00"), T_345, T_348)
    node T_350 = not(io.incoherent[0])
    node mask_incoherent = and(mask_self, T_350)
    reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_362 : UInt<3>[1]
    T_362[0] <= UInt<3>("h03")
    node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type)
    node T_367 = or(UInt<1>("h00"), T_365)
    node T_368 = and(T_359, T_367)
    node T_369 = and(T_356, T_368)
    reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_369 :
      node T_373 = eq(T_371, UInt<2>("h03"))
      node T_375 = and(UInt<1>("h00"), T_373)
      node T_378 = add(T_371, UInt<1>("h01"))
      node T_379 = tail(T_378, 1)
      node T_380 = mux(T_375, UInt<1>("h00"), T_379)
      T_371 <= T_380
      skip
    node T_381 = and(T_369, T_373)
    node T_382 = mux(T_368, T_371, UInt<1>("h00"))
    node iacq_data_done = mux(T_368, T_381, T_356)
    node T_384 = and(io.inner.release.ready, io.inner.release.valid)
    wire T_388 : UInt<2>[3]
    T_388[0] <= UInt<1>("h00")
    T_388[1] <= UInt<1>("h01")
    T_388[2] <= UInt<2>("h02")
    node T_393 = eq(T_388[0], io.inner.release.bits.r_type)
    node T_394 = eq(T_388[1], io.inner.release.bits.r_type)
    node T_395 = eq(T_388[2], io.inner.release.bits.r_type)
    node T_397 = or(UInt<1>("h00"), T_393)
    node T_398 = or(T_397, T_394)
    node T_399 = or(T_398, T_395)
    node T_400 = and(UInt<1>("h01"), T_399)
    node T_401 = and(T_384, T_400)
    reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_401 :
      node T_405 = eq(T_403, UInt<2>("h03"))
      node T_407 = and(UInt<1>("h00"), T_405)
      node T_410 = add(T_403, UInt<1>("h01"))
      node T_411 = tail(T_410, 1)
      node T_412 = mux(T_407, UInt<1>("h00"), T_411)
      T_403 <= T_412
      skip
    node T_413 = and(T_401, T_405)
    node T_414 = mux(T_400, T_403, UInt<1>("h00"))
    node irel_data_done = mux(T_400, T_413, T_384)
    node T_417 = and(io.inner.grant.ready, io.inner.grant.valid)
    wire T_421 : UInt<3>[1]
    T_421[0] <= UInt<3>("h05")
    node T_424 = eq(T_421[0], io.inner.grant.bits.g_type)
    node T_426 = or(UInt<1>("h00"), T_424)
    wire T_428 : UInt<1>[2]
    T_428[0] <= UInt<1>("h00")
    T_428[1] <= UInt<1>("h01")
    node T_432 = eq(T_428[0], io.inner.grant.bits.g_type)
    node T_433 = eq(T_428[1], io.inner.grant.bits.g_type)
    node T_435 = or(UInt<1>("h00"), T_432)
    node T_436 = or(T_435, T_433)
    node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436)
    node T_438 = and(UInt<1>("h01"), T_437)
    node T_439 = and(T_417, T_438)
    reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_439 :
      node T_443 = eq(T_441, UInt<2>("h03"))
      node T_445 = and(UInt<1>("h00"), T_443)
      node T_448 = add(T_441, UInt<1>("h01"))
      node T_449 = tail(T_448, 1)
      node T_450 = mux(T_445, UInt<1>("h00"), T_449)
      T_441 <= T_450
      skip
    node T_451 = and(T_439, T_443)
    node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00"))
    node ignt_data_done = mux(T_438, T_451, T_417)
    node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type)
    wire T_460 : UInt<3>[1]
    T_460[0] <= UInt<3>("h03")
    node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type)
    node T_465 = or(UInt<1>("h00"), T_463)
    node T_466 = and(T_457, T_465)
    node T_467 = and(T_455, T_466)
    reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_467 :
      node T_471 = eq(T_469, UInt<2>("h03"))
      node T_473 = and(UInt<1>("h00"), T_471)
      node T_476 = add(T_469, UInt<1>("h01"))
      node T_477 = tail(T_476, 1)
      node T_478 = mux(T_473, UInt<1>("h00"), T_477)
      T_469 <= T_478
      skip
    node T_479 = and(T_467, T_471)
    node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00"))
    node oacq_data_done = mux(T_466, T_479, T_455)
    node T_482 = and(io.outer.grant.ready, io.outer.grant.valid)
    wire T_487 : UInt<3>[1]
    T_487[0] <= UInt<3>("h05")
    node T_490 = eq(T_487[0], io.outer.grant.bits.g_type)
    node T_492 = or(UInt<1>("h00"), T_490)
    wire T_494 : UInt<1>[1]
    T_494[0] <= UInt<1>("h00")
    node T_497 = eq(T_494[0], io.outer.grant.bits.g_type)
    node T_499 = or(UInt<1>("h00"), T_497)
    node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499)
    node T_501 = and(UInt<1>("h01"), T_500)
    node T_502 = and(T_482, T_501)
    reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_502 :
      node T_506 = eq(T_504, UInt<2>("h03"))
      node T_508 = and(UInt<1>("h00"), T_506)
      node T_511 = add(T_504, UInt<1>("h01"))
      node T_512 = tail(T_511, 1)
      node T_513 = mux(T_508, UInt<1>("h00"), T_512)
      T_504 <= T_513
      skip
    node T_514 = and(T_502, T_506)
    node T_515 = mux(T_501, T_504, UInt<1>("h00"))
    node ognt_data_done = mux(T_501, T_514, T_482)
    reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_523 : UInt<3>[3]
    T_523[0] <= UInt<3>("h02")
    T_523[1] <= UInt<3>("h03")
    T_523[2] <= UInt<3>("h04")
    node T_528 = eq(T_523[0], xact.a_type)
    node T_529 = eq(T_523[1], xact.a_type)
    node T_530 = eq(T_523[2], xact.a_type)
    node T_532 = or(UInt<1>("h00"), T_528)
    node T_533 = or(T_532, T_529)
    node T_534 = or(T_533, T_530)
    node pending_outer_write = and(xact.is_builtin_type, T_534)
    wire T_540 : UInt<3>[3]
    T_540[0] <= UInt<3>("h02")
    T_540[1] <= UInt<3>("h03")
    T_540[2] <= UInt<3>("h04")
    node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type)
    node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type)
    node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type)
    node T_549 = or(UInt<1>("h00"), T_545)
    node T_550 = or(T_549, T_546)
    node T_551 = or(T_550, T_547)
    node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551)
    wire T_556 : UInt<3>[2]
    T_556[0] <= UInt<3>("h05")
    T_556[1] <= UInt<3>("h04")
    node T_560 = eq(T_556[0], io.inner.grant.bits.g_type)
    node T_561 = eq(T_556[1], io.inner.grant.bits.g_type)
    node T_563 = or(UInt<1>("h00"), T_560)
    node T_564 = or(T_563, T_561)
    wire T_566 : UInt<1>[2]
    T_566[0] <= UInt<1>("h00")
    T_566[1] <= UInt<1>("h01")
    node T_570 = eq(T_566[0], io.inner.grant.bits.g_type)
    node T_571 = eq(T_566[1], io.inner.grant.bits.g_type)
    node T_573 = or(UInt<1>("h00"), T_570)
    node T_574 = or(T_573, T_571)
    node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574)
    node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type)
    node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03"))
    node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type)
    node T_597 = mux(T_596, UInt<3>("h01"), T_595)
    node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type)
    node T_599 = mux(T_598, UInt<3>("h04"), T_597)
    node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type)
    node T_601 = mux(T_600, UInt<3>("h03"), T_599)
    node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type)
    node T_603 = mux(T_602, UInt<3>("h03"), T_601)
    node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type)
    node T_605 = mux(T_604, UInt<3>("h05"), T_603)
    node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type)
    node T_607 = mux(T_606, UInt<3>("h04"), T_605)
    node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00"))
    node T_611 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01"))
    node T_613 = mux(T_608, T_612, UInt<1>("h01"))
    node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613)
    wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_623 is invalid
    T_623.client_id <= io.inner.acquire.bits.client_id
    T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type
    T_623.g_type <= T_614
    T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id
    T_623.manager_xact_id <= UInt<1>("h01")
    T_623.addr_beat <= UInt<1>("h00")
    T_623.data <= UInt<1>("h00")
    wire T_634 : UInt<3>[2]
    T_634[0] <= UInt<3>("h05")
    T_634[1] <= UInt<3>("h04")
    node T_638 = eq(T_634[0], T_623.g_type)
    node T_639 = eq(T_634[1], T_623.g_type)
    node T_641 = or(UInt<1>("h00"), T_638)
    node T_642 = or(T_641, T_639)
    wire T_644 : UInt<1>[2]
    T_644[0] <= UInt<1>("h00")
    T_644[1] <= UInt<1>("h01")
    node T_648 = eq(T_644[0], T_623.g_type)
    node T_649 = eq(T_644[1], T_623.g_type)
    node T_651 = or(UInt<1>("h00"), T_648)
    node T_652 = or(T_651, T_649)
    node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652)
    wire T_658 : UInt<3>[3]
    T_658[0] <= UInt<3>("h02")
    T_658[1] <= UInt<3>("h00")
    T_658[2] <= UInt<3>("h04")
    node T_663 = eq(T_658[0], xact.a_type)
    node T_664 = eq(T_658[1], xact.a_type)
    node T_665 = eq(T_658[2], xact.a_type)
    node T_667 = or(UInt<1>("h00"), T_663)
    node T_668 = or(T_667, T_664)
    node T_669 = or(T_668, T_665)
    node subblock_type = and(xact.is_builtin_type, T_669)
    node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_672 = neq(state, UInt<1>("h00"))
    node T_673 = and(T_671, T_672)
    node T_675 = eq(collect_iacq_data, UInt<1>("h00"))
    node T_676 = and(T_673, T_675)
    io.has_acquire_conflict <= T_676
    node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_678 = and(T_677, collect_iacq_data)
    io.has_acquire_match <= T_678
    node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block)
    node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00"))
    node T_682 = and(T_679, T_681)
    node T_683 = eq(state, UInt<1>("h01"))
    node T_684 = and(T_682, T_683)
    io.has_release_match <= T_684
    node T_689 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_695 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_696 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_697 = cat(T_695, T_696)
    node T_699 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_700 = cat(UInt<3>("h07"), T_699)
    node T_702 = cat(T_689, UInt<1>("h01"))
    node T_704 = cat(T_689, UInt<1>("h01"))
    node T_706 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_707 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_708 = cat(T_706, T_707)
    node T_710 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_712 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_713 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_714 = mux(T_713, T_712, UInt<1>("h00"))
    node T_715 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_716 = mux(T_715, T_710, T_714)
    node T_717 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_718 = mux(T_717, T_708, T_716)
    node T_719 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_720 = mux(T_719, T_704, T_718)
    node T_721 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_722 = mux(T_721, T_702, T_720)
    node T_723 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_724 = mux(T_723, T_700, T_722)
    node T_725 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_726 = mux(T_725, T_697, T_724)
    wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_probe is invalid
    oacq_probe.is_builtin_type <= UInt<1>("h01")
    oacq_probe.a_type <= UInt<3>("h03")
    oacq_probe.client_xact_id <= UInt<1>("h01")
    oacq_probe.addr_block <= io.inner.release.bits.addr_block
    oacq_probe.addr_beat <= io.inner.release.bits.addr_beat
    oacq_probe.data <= io.inner.release.bits.data
    oacq_probe.union <= T_726
    node T_744 = bits(xact.union, 12, 9)
    node T_745 = bits(T_744, 3, 3)
    node T_747 = dshl(UInt<1>("h01"), T_745)
    node T_749 = eq(xact.a_type, UInt<3>("h04"))
    node T_750 = and(xact.is_builtin_type, T_749)
    node T_751 = bits(T_747, 0, 0)
    node T_752 = bits(T_747, 1, 1)
    wire T_754 : UInt<1>[2]
    T_754[0] <= T_751
    T_754[1] <= T_752
    node T_759 = sub(UInt<8>("h00"), T_754[0])
    node T_760 = tail(T_759, 1)
    node T_762 = sub(UInt<8>("h00"), T_754[1])
    node T_763 = tail(T_762, 1)
    wire T_765 : UInt<8>[2]
    T_765[0] <= T_760
    T_765[1] <= T_763
    node T_769 = cat(T_765[1], T_765[0])
    node T_771 = eq(xact.a_type, UInt<3>("h03"))
    node T_772 = and(xact.is_builtin_type, T_771)
    node T_774 = eq(xact.a_type, UInt<3>("h02"))
    node T_775 = and(xact.is_builtin_type, T_774)
    node T_776 = or(T_772, T_775)
    node T_777 = bits(xact.union, 16, 1)
    node T_779 = mux(T_776, T_777, UInt<16>("h00"))
    node T_780 = mux(T_750, T_769, T_779)
    node T_788 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_789 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_790 = cat(T_788, T_789)
    node T_792 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_793 = cat(UInt<3>("h07"), T_792)
    node T_795 = cat(T_780, UInt<1>("h01"))
    node T_797 = cat(T_780, UInt<1>("h01"))
    node T_799 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_800 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_801 = cat(T_799, T_800)
    node T_803 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_805 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_806 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_807 = mux(T_806, T_805, UInt<1>("h00"))
    node T_808 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_809 = mux(T_808, T_803, T_807)
    node T_810 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_811 = mux(T_810, T_801, T_809)
    node T_812 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_813 = mux(T_812, T_797, T_811)
    node T_814 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_815 = mux(T_814, T_795, T_813)
    node T_816 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_817 = mux(T_816, T_793, T_815)
    node T_818 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_819 = mux(T_818, T_790, T_817)
    wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_beat is invalid
    oacq_write_beat.is_builtin_type <= UInt<1>("h01")
    oacq_write_beat.a_type <= UInt<3>("h02")
    oacq_write_beat.client_xact_id <= UInt<1>("h01")
    oacq_write_beat.addr_block <= xact.addr_block
    oacq_write_beat.addr_beat <= xact.addr_beat
    oacq_write_beat.data <= xact.data_buffer[0]
    oacq_write_beat.union <= T_819
    node T_846 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_847 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_848 = cat(T_846, T_847)
    node T_850 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_851 = cat(UInt<3>("h07"), T_850)
    node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_857 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_858 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_859 = cat(T_857, T_858)
    node T_861 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_863 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_864 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_865 = mux(T_864, T_863, UInt<1>("h00"))
    node T_866 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_867 = mux(T_866, T_861, T_865)
    node T_868 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_869 = mux(T_868, T_859, T_867)
    node T_870 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_871 = mux(T_870, T_855, T_869)
    node T_872 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_873 = mux(T_872, T_853, T_871)
    node T_874 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_875 = mux(T_874, T_851, T_873)
    node T_876 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_877 = mux(T_876, T_848, T_875)
    wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_block is invalid
    oacq_write_block.is_builtin_type <= UInt<1>("h01")
    oacq_write_block.a_type <= UInt<3>("h03")
    oacq_write_block.client_xact_id <= UInt<1>("h01")
    oacq_write_block.addr_block <= xact.addr_block
    oacq_write_block.addr_beat <= oacq_data_cnt
    oacq_write_block.data <= xact.data_buffer[oacq_data_cnt]
    oacq_write_block.union <= T_877
    node T_895 = bits(xact.union, 12, 9)
    node T_896 = bits(xact.union, 8, 6)
    node T_904 = cat(T_895, T_896)
    node T_905 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_906 = cat(T_904, T_905)
    node T_908 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_909 = cat(T_896, T_908)
    node T_911 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_913 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_915 = cat(T_895, T_896)
    node T_916 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_917 = cat(T_915, T_916)
    node T_919 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_921 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_922 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_923 = mux(T_922, T_921, UInt<1>("h00"))
    node T_924 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_925 = mux(T_924, T_919, T_923)
    node T_926 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_927 = mux(T_926, T_917, T_925)
    node T_928 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_929 = mux(T_928, T_913, T_927)
    node T_930 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_931 = mux(T_930, T_911, T_929)
    node T_932 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_933 = mux(T_932, T_909, T_931)
    node T_934 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_935 = mux(T_934, T_906, T_933)
    wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_beat is invalid
    oacq_read_beat.is_builtin_type <= UInt<1>("h01")
    oacq_read_beat.a_type <= UInt<3>("h00")
    oacq_read_beat.client_xact_id <= UInt<1>("h01")
    oacq_read_beat.addr_block <= xact.addr_block
    oacq_read_beat.addr_beat <= xact.addr_beat
    oacq_read_beat.data <= UInt<1>("h00")
    oacq_read_beat.union <= T_935
    node T_962 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_963 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_964 = cat(T_962, T_963)
    node T_966 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_967 = cat(UInt<3>("h07"), T_966)
    node T_969 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_971 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_973 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_974 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_975 = cat(T_973, T_974)
    node T_977 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_979 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_980 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_981 = mux(T_980, T_979, UInt<1>("h00"))
    node T_982 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_983 = mux(T_982, T_977, T_981)
    node T_984 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_985 = mux(T_984, T_975, T_983)
    node T_986 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_987 = mux(T_986, T_971, T_985)
    node T_988 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_989 = mux(T_988, T_969, T_987)
    node T_990 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_991 = mux(T_990, T_967, T_989)
    node T_992 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_993 = mux(T_992, T_964, T_991)
    wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_block is invalid
    oacq_read_block.is_builtin_type <= UInt<1>("h01")
    oacq_read_block.a_type <= UInt<3>("h01")
    oacq_read_block.client_xact_id <= UInt<1>("h01")
    oacq_read_block.addr_block <= xact.addr_block
    oacq_read_block.addr_beat <= UInt<1>("h00")
    oacq_read_block.data <= UInt<1>("h00")
    oacq_read_block.union <= T_993
    io.outer.acquire.valid <= UInt<1>("h00")
    node T_1011 = eq(state, UInt<1>("h01"))
    node T_1012 = eq(state, UInt<2>("h03"))
    node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block)
    node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block)
    node T_1029 = mux(T_1012, T_1013, T_1021)
    node T_1037 = mux(T_1011, oacq_probe, T_1029)
    io.outer.acquire.bits <- T_1037
    io.outer.grant.ready <= UInt<1>("h00")
    io.inner.probe.valid <= UInt<1>("h00")
    node T_1054 = eq(UInt<3>("h04"), xact.a_type)
    node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02"))
    node T_1056 = eq(UInt<3>("h06"), xact.a_type)
    node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055)
    node T_1058 = eq(UInt<3>("h05"), xact.a_type)
    node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057)
    node T_1060 = eq(UInt<3>("h02"), xact.a_type)
    node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059)
    node T_1062 = eq(UInt<3>("h00"), xact.a_type)
    node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061)
    node T_1064 = eq(UInt<3>("h03"), xact.a_type)
    node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063)
    node T_1066 = eq(UInt<3>("h01"), xact.a_type)
    node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065)
    node T_1068 = eq(UInt<1>("h01"), xact.a_type)
    node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02"))
    node T_1070 = eq(UInt<1>("h00"), xact.a_type)
    node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069)
    node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071)
    wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_1077 is invalid
    T_1077.client_id <= UInt<1>("h00")
    T_1077.p_type <= T_1072
    T_1077.addr_block <= xact.addr_block
    io.inner.probe.bits <- T_1077
    io.inner.grant.valid <= UInt<1>("h00")
    node T_1100 = eq(UInt<3>("h06"), xact.a_type)
    node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03"))
    node T_1102 = eq(UInt<3>("h05"), xact.a_type)
    node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101)
    node T_1104 = eq(UInt<3>("h04"), xact.a_type)
    node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103)
    node T_1106 = eq(UInt<3>("h03"), xact.a_type)
    node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105)
    node T_1108 = eq(UInt<3>("h02"), xact.a_type)
    node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107)
    node T_1110 = eq(UInt<3>("h01"), xact.a_type)
    node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109)
    node T_1112 = eq(UInt<3>("h00"), xact.a_type)
    node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111)
    node T_1114 = eq(xact.a_type, UInt<1>("h00"))
    node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01"))
    node T_1119 = mux(T_1114, T_1118, UInt<1>("h01"))
    node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119)
    wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_1129 is invalid
    T_1129.client_id <= xact.client_id
    T_1129.is_builtin_type <= xact.is_builtin_type
    T_1129.g_type <= T_1120
    T_1129.client_xact_id <= xact.client_xact_id
    T_1129.manager_xact_id <= UInt<1>("h01")
    T_1129.addr_beat <= UInt<1>("h00")
    T_1129.data <= UInt<1>("h00")
    io.inner.grant.bits <- T_1129
    io.inner.acquire.ready <= UInt<1>("h00")
    io.inner.release.ready <= UInt<1>("h00")
    io.inner.finish.ready <= UInt<1>("h00")
    node T_1140 = neq(state, UInt<1>("h00"))
    node T_1141 = and(T_1140, collect_iacq_data)
    node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1143 = and(T_1141, T_1142)
    node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id)
    node T_1145 = and(T_1143, T_1144)
    node T_1147 = eq(T_1145, UInt<1>("h00"))
    node T_1149 = eq(reset, UInt<1>("h00"))
    when T_1149 :
      node T_1151 = eq(T_1147, UInt<1>("h00"))
      when T_1151 :
        node T_1153 = eq(reset, UInt<1>("h00"))
        when T_1153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1154 = neq(state, UInt<1>("h00"))
    node T_1155 = and(T_1154, collect_iacq_data)
    node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1157 = and(T_1155, T_1156)
    node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id)
    node T_1159 = and(T_1157, T_1158)
    node T_1161 = eq(T_1159, UInt<1>("h00"))
    node T_1163 = eq(reset, UInt<1>("h00"))
    when T_1163 :
      node T_1165 = eq(T_1161, UInt<1>("h00"))
      when T_1165 :
        node T_1167 = eq(reset, UInt<1>("h00"))
        when T_1167 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1168 = eq(state, UInt<1>("h00"))
    node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1170 = and(T_1168, T_1169)
    node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_1175 : UInt<3>[1]
    T_1175[0] <= UInt<3>("h03")
    node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type)
    node T_1180 = or(UInt<1>("h00"), T_1178)
    node T_1181 = and(T_1172, T_1180)
    node T_1182 = and(T_1170, T_1181)
    node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00"))
    node T_1185 = and(T_1182, T_1184)
    node T_1187 = eq(T_1185, UInt<1>("h00"))
    node T_1189 = eq(reset, UInt<1>("h00"))
    when T_1189 :
      node T_1191 = eq(T_1187, UInt<1>("h00"))
      when T_1191 :
        node T_1193 = eq(reset, UInt<1>("h00"))
        when T_1193 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    when collect_iacq_data :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data
        node T_1197 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1198 = bits(T_1197, 3, 3)
        node T_1200 = dshl(UInt<1>("h01"), T_1198)
        node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202)
        node T_1204 = bits(T_1200, 0, 0)
        node T_1205 = bits(T_1200, 1, 1)
        wire T_1207 : UInt<1>[2]
        T_1207[0] <= T_1204
        T_1207[1] <= T_1205
        node T_1212 = sub(UInt<8>("h00"), T_1207[0])
        node T_1213 = tail(T_1212, 1)
        node T_1215 = sub(UInt<8>("h00"), T_1207[1])
        node T_1216 = tail(T_1215, 1)
        wire T_1218 : UInt<8>[2]
        T_1218[0] <= T_1213
        T_1218[1] <= T_1216
        node T_1222 = cat(T_1218[1], T_1218[0])
        node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224)
        node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227)
        node T_1229 = or(T_1225, T_1228)
        node T_1230 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1232 = mux(T_1229, T_1230, UInt<16>("h00"))
        node T_1233 = mux(T_1203, T_1222, T_1232)
        xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233
        node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat)
        node T_1237 = or(iacq_data_valid, T_1236)
        node T_1238 = not(iacq_data_valid)
        node T_1239 = or(T_1238, T_1236)
        node T_1240 = not(T_1239)
        node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240)
        iacq_data_valid <= T_1241
        skip
      when iacq_data_done :
        collect_iacq_data <= UInt<1>("h00")
        skip
      skip
    when pending_ognt_ack :
      io.outer.grant.ready <= UInt<1>("h01")
      when io.outer.grant.valid :
        pending_ognt_ack <= UInt<1>("h00")
        skip
      skip
    node T_1245 = eq(UInt<1>("h00"), state)
    when T_1245 :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact <- io.inner.acquire.bits
        xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data
        node T_1251 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1252 = bits(T_1251, 3, 3)
        node T_1254 = dshl(UInt<1>("h01"), T_1252)
        node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256)
        node T_1258 = bits(T_1254, 0, 0)
        node T_1259 = bits(T_1254, 1, 1)
        wire T_1261 : UInt<1>[2]
        T_1261[0] <= T_1258
        T_1261[1] <= T_1259
        node T_1266 = sub(UInt<8>("h00"), T_1261[0])
        node T_1267 = tail(T_1266, 1)
        node T_1269 = sub(UInt<8>("h00"), T_1261[1])
        node T_1270 = tail(T_1269, 1)
        wire T_1272 : UInt<8>[2]
        T_1272[0] <= T_1267
        T_1272[1] <= T_1270
        node T_1276 = cat(T_1272[1], T_1272[0])
        node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278)
        node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281)
        node T_1283 = or(T_1279, T_1282)
        node T_1284 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1286 = mux(T_1283, T_1284, UInt<16>("h00"))
        node T_1287 = mux(T_1257, T_1276, T_1286)
        xact.wmask_buffer[UInt<1>("h00")] <= T_1287
        node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
        wire T_1292 : UInt<3>[1]
        T_1292[0] <= UInt<3>("h03")
        node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type)
        node T_1297 = or(UInt<1>("h00"), T_1295)
        node T_1298 = and(T_1289, T_1297)
        collect_iacq_data <= T_1298
        wire T_1303 : UInt<3>[3]
        T_1303[0] <= UInt<3>("h02")
        T_1303[1] <= UInt<3>("h03")
        T_1303[2] <= UInt<3>("h04")
        node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type)
        node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type)
        node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type)
        node T_1312 = or(UInt<1>("h00"), T_1308)
        node T_1313 = or(T_1312, T_1309)
        node T_1314 = or(T_1313, T_1310)
        node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314)
        node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat)
        iacq_data_valid <= T_1316
        node T_1318 = neq(mask_incoherent, UInt<1>("h00"))
        when T_1318 :
          pending_probes <= mask_incoherent
          node T_1319 = bits(mask_incoherent, 0, 0)
          node T_1320 = bits(mask_incoherent, 1, 1)
          node T_1321 = bits(mask_incoherent, 2, 2)
          node T_1322 = bits(mask_incoherent, 3, 3)
          node T_1324 = cat(UInt<1>("h00"), T_1320)
          node T_1325 = add(T_1319, T_1324)
          node T_1326 = tail(T_1325, 1)
          node T_1329 = cat(UInt<1>("h00"), T_1322)
          node T_1330 = add(T_1321, T_1329)
          node T_1331 = tail(T_1330, 1)
          node T_1332 = cat(UInt<1>("h00"), T_1331)
          node T_1333 = add(T_1326, T_1332)
          node T_1334 = tail(T_1333, 1)
          release_count <= T_1334
          skip
        node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04"))
        node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335)
        node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336)
        state <= T_1337
        skip
      skip
    node T_1338 = eq(UInt<1>("h01"), state)
    when T_1338 :
      node T_1340 = neq(pending_probes, UInt<1>("h00"))
      io.inner.probe.valid <= T_1340
      when io.inner.probe.ready :
        node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00"))
        node T_1343 = not(T_1342)
        node T_1344 = and(pending_probes, T_1343)
        pending_probes <= T_1344
        skip
      wire T_1346 : UInt<2>[3]
      T_1346[0] <= UInt<1>("h00")
      T_1346[1] <= UInt<1>("h01")
      T_1346[2] <= UInt<2>("h02")
      node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type)
      node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type)
      node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type)
      node T_1355 = or(UInt<1>("h00"), T_1351)
      node T_1356 = or(T_1355, T_1352)
      node T_1357 = or(T_1356, T_1353)
      node T_1359 = eq(T_1357, UInt<1>("h00"))
      node T_1360 = or(T_1359, io.outer.acquire.ready)
      io.inner.release.ready <= T_1360
      when io.inner.release.valid :
        wire T_1362 : UInt<2>[3]
        T_1362[0] <= UInt<1>("h00")
        T_1362[1] <= UInt<1>("h01")
        T_1362[2] <= UInt<2>("h02")
        node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type)
        node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type)
        node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type)
        node T_1371 = or(UInt<1>("h00"), T_1367)
        node T_1372 = or(T_1371, T_1368)
        node T_1373 = or(T_1372, T_1369)
        when T_1373 :
          io.outer.acquire.valid <= UInt<1>("h01")
          when io.outer.acquire.ready :
            when oacq_data_done :
              pending_ognt_ack <= UInt<1>("h01")
              node T_1377 = sub(release_count, UInt<1>("h01"))
              node T_1378 = tail(T_1377, 1)
              release_count <= T_1378
              node T_1380 = eq(release_count, UInt<1>("h01"))
              when T_1380 :
                node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
                node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381)
                state <= T_1382
                skip
              skip
            skip
          skip
        node T_1384 = eq(T_1373, UInt<1>("h00"))
        when T_1384 :
          node T_1386 = sub(release_count, UInt<1>("h01"))
          node T_1387 = tail(T_1386, 1)
          release_count <= T_1387
          node T_1389 = eq(release_count, UInt<1>("h01"))
          when T_1389 :
            node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
            node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390)
            state <= T_1391
            skip
          skip
        skip
      skip
    node T_1392 = eq(UInt<2>("h03"), state)
    when T_1392 :
      node T_1394 = eq(pending_ognt_ack, UInt<1>("h00"))
      node T_1396 = eq(collect_iacq_data, UInt<1>("h00"))
      node T_1397 = dshr(iacq_data_valid, oacq_data_cnt)
      node T_1398 = bits(T_1397, 0, 0)
      node T_1399 = or(T_1396, T_1398)
      node T_1400 = and(T_1394, T_1399)
      io.outer.acquire.valid <= T_1400
      when oacq_data_done :
        pending_ognt_ack <= UInt<1>("h01")
        node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05"))
        state <= T_1402
        skip
      skip
    node T_1403 = eq(UInt<2>("h02"), state)
    when T_1403 :
      node T_1405 = eq(pending_ognt_ack, UInt<1>("h00"))
      io.outer.acquire.valid <= T_1405
      node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid)
      when T_1406 :
        state <= UInt<3>("h05")
        skip
      skip
    node T_1407 = eq(UInt<3>("h05"), state)
    when T_1407 :
      io.outer.grant.ready <= io.inner.grant.ready
      io.inner.grant.valid <= io.outer.grant.valid
      when ignt_data_done :
        node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412)
        node T_1415 = eq(T_1413, UInt<1>("h00"))
        node T_1416 = and(T_1410, T_1415)
        node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1417
        skip
      skip
    node T_1418 = eq(UInt<3>("h04"), state)
    when T_1418 :
      io.inner.grant.valid <= UInt<1>("h01")
      when io.inner.grant.ready :
        node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424)
        node T_1427 = eq(T_1425, UInt<1>("h00"))
        node T_1428 = and(T_1422, T_1427)
        node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1429
        skip
      skip
    node T_1430 = eq(UInt<3>("h06"), state)
    when T_1430 :
      io.inner.finish.ready <= UInt<1>("h01")
      when io.inner.finish.valid :
        state <= UInt<1>("h00")
        skip
      skip
    
  module BroadcastAcquireTracker_27 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
    wire coh : {sharers : UInt<1>}
    coh is invalid
    coh.sharers <= UInt<1>("h00")
    node T_303 = neq(state, UInt<1>("h00"))
    node T_304 = and(T_303, xact.is_builtin_type)
    wire T_309 : UInt<3>[3]
    T_309[0] <= UInt<3>("h04")
    T_309[1] <= UInt<3>("h05")
    T_309[2] <= UInt<3>("h06")
    node T_314 = eq(T_309[0], xact.a_type)
    node T_315 = eq(T_309[1], xact.a_type)
    node T_316 = eq(T_309[2], xact.a_type)
    node T_318 = or(UInt<1>("h00"), T_314)
    node T_319 = or(T_318, T_315)
    node T_320 = or(T_319, T_316)
    node T_321 = and(T_304, T_320)
    node T_323 = eq(T_321, UInt<1>("h00"))
    node T_325 = eq(reset, UInt<1>("h00"))
    when T_325 :
      node T_327 = eq(T_323, UInt<1>("h00"))
      when T_327 :
        node T_329 = eq(reset, UInt<1>("h00"))
        when T_329 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_334 = bits(pending_probes, 0, 0)
    wire T_336 : UInt<1>[1]
    T_336[0] <= T_334
    node T_341 = asUInt(asSInt(UInt<1>("h01")))
    node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id)
    node T_345 = or(T_341, T_344)
    node T_346 = not(T_341)
    node T_347 = or(T_346, T_344)
    node T_348 = not(T_347)
    node mask_self = mux(UInt<1>("h00"), T_345, T_348)
    node T_350 = not(io.incoherent[0])
    node mask_incoherent = and(mask_self, T_350)
    reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_362 : UInt<3>[1]
    T_362[0] <= UInt<3>("h03")
    node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type)
    node T_367 = or(UInt<1>("h00"), T_365)
    node T_368 = and(T_359, T_367)
    node T_369 = and(T_356, T_368)
    reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_369 :
      node T_373 = eq(T_371, UInt<2>("h03"))
      node T_375 = and(UInt<1>("h00"), T_373)
      node T_378 = add(T_371, UInt<1>("h01"))
      node T_379 = tail(T_378, 1)
      node T_380 = mux(T_375, UInt<1>("h00"), T_379)
      T_371 <= T_380
      skip
    node T_381 = and(T_369, T_373)
    node T_382 = mux(T_368, T_371, UInt<1>("h00"))
    node iacq_data_done = mux(T_368, T_381, T_356)
    node T_384 = and(io.inner.release.ready, io.inner.release.valid)
    wire T_388 : UInt<2>[3]
    T_388[0] <= UInt<1>("h00")
    T_388[1] <= UInt<1>("h01")
    T_388[2] <= UInt<2>("h02")
    node T_393 = eq(T_388[0], io.inner.release.bits.r_type)
    node T_394 = eq(T_388[1], io.inner.release.bits.r_type)
    node T_395 = eq(T_388[2], io.inner.release.bits.r_type)
    node T_397 = or(UInt<1>("h00"), T_393)
    node T_398 = or(T_397, T_394)
    node T_399 = or(T_398, T_395)
    node T_400 = and(UInt<1>("h01"), T_399)
    node T_401 = and(T_384, T_400)
    reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_401 :
      node T_405 = eq(T_403, UInt<2>("h03"))
      node T_407 = and(UInt<1>("h00"), T_405)
      node T_410 = add(T_403, UInt<1>("h01"))
      node T_411 = tail(T_410, 1)
      node T_412 = mux(T_407, UInt<1>("h00"), T_411)
      T_403 <= T_412
      skip
    node T_413 = and(T_401, T_405)
    node T_414 = mux(T_400, T_403, UInt<1>("h00"))
    node irel_data_done = mux(T_400, T_413, T_384)
    node T_417 = and(io.inner.grant.ready, io.inner.grant.valid)
    wire T_421 : UInt<3>[1]
    T_421[0] <= UInt<3>("h05")
    node T_424 = eq(T_421[0], io.inner.grant.bits.g_type)
    node T_426 = or(UInt<1>("h00"), T_424)
    wire T_428 : UInt<1>[2]
    T_428[0] <= UInt<1>("h00")
    T_428[1] <= UInt<1>("h01")
    node T_432 = eq(T_428[0], io.inner.grant.bits.g_type)
    node T_433 = eq(T_428[1], io.inner.grant.bits.g_type)
    node T_435 = or(UInt<1>("h00"), T_432)
    node T_436 = or(T_435, T_433)
    node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436)
    node T_438 = and(UInt<1>("h01"), T_437)
    node T_439 = and(T_417, T_438)
    reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_439 :
      node T_443 = eq(T_441, UInt<2>("h03"))
      node T_445 = and(UInt<1>("h00"), T_443)
      node T_448 = add(T_441, UInt<1>("h01"))
      node T_449 = tail(T_448, 1)
      node T_450 = mux(T_445, UInt<1>("h00"), T_449)
      T_441 <= T_450
      skip
    node T_451 = and(T_439, T_443)
    node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00"))
    node ignt_data_done = mux(T_438, T_451, T_417)
    node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type)
    wire T_460 : UInt<3>[1]
    T_460[0] <= UInt<3>("h03")
    node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type)
    node T_465 = or(UInt<1>("h00"), T_463)
    node T_466 = and(T_457, T_465)
    node T_467 = and(T_455, T_466)
    reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_467 :
      node T_471 = eq(T_469, UInt<2>("h03"))
      node T_473 = and(UInt<1>("h00"), T_471)
      node T_476 = add(T_469, UInt<1>("h01"))
      node T_477 = tail(T_476, 1)
      node T_478 = mux(T_473, UInt<1>("h00"), T_477)
      T_469 <= T_478
      skip
    node T_479 = and(T_467, T_471)
    node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00"))
    node oacq_data_done = mux(T_466, T_479, T_455)
    node T_482 = and(io.outer.grant.ready, io.outer.grant.valid)
    wire T_487 : UInt<3>[1]
    T_487[0] <= UInt<3>("h05")
    node T_490 = eq(T_487[0], io.outer.grant.bits.g_type)
    node T_492 = or(UInt<1>("h00"), T_490)
    wire T_494 : UInt<1>[1]
    T_494[0] <= UInt<1>("h00")
    node T_497 = eq(T_494[0], io.outer.grant.bits.g_type)
    node T_499 = or(UInt<1>("h00"), T_497)
    node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499)
    node T_501 = and(UInt<1>("h01"), T_500)
    node T_502 = and(T_482, T_501)
    reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_502 :
      node T_506 = eq(T_504, UInt<2>("h03"))
      node T_508 = and(UInt<1>("h00"), T_506)
      node T_511 = add(T_504, UInt<1>("h01"))
      node T_512 = tail(T_511, 1)
      node T_513 = mux(T_508, UInt<1>("h00"), T_512)
      T_504 <= T_513
      skip
    node T_514 = and(T_502, T_506)
    node T_515 = mux(T_501, T_504, UInt<1>("h00"))
    node ognt_data_done = mux(T_501, T_514, T_482)
    reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_523 : UInt<3>[3]
    T_523[0] <= UInt<3>("h02")
    T_523[1] <= UInt<3>("h03")
    T_523[2] <= UInt<3>("h04")
    node T_528 = eq(T_523[0], xact.a_type)
    node T_529 = eq(T_523[1], xact.a_type)
    node T_530 = eq(T_523[2], xact.a_type)
    node T_532 = or(UInt<1>("h00"), T_528)
    node T_533 = or(T_532, T_529)
    node T_534 = or(T_533, T_530)
    node pending_outer_write = and(xact.is_builtin_type, T_534)
    wire T_540 : UInt<3>[3]
    T_540[0] <= UInt<3>("h02")
    T_540[1] <= UInt<3>("h03")
    T_540[2] <= UInt<3>("h04")
    node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type)
    node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type)
    node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type)
    node T_549 = or(UInt<1>("h00"), T_545)
    node T_550 = or(T_549, T_546)
    node T_551 = or(T_550, T_547)
    node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551)
    wire T_556 : UInt<3>[2]
    T_556[0] <= UInt<3>("h05")
    T_556[1] <= UInt<3>("h04")
    node T_560 = eq(T_556[0], io.inner.grant.bits.g_type)
    node T_561 = eq(T_556[1], io.inner.grant.bits.g_type)
    node T_563 = or(UInt<1>("h00"), T_560)
    node T_564 = or(T_563, T_561)
    wire T_566 : UInt<1>[2]
    T_566[0] <= UInt<1>("h00")
    T_566[1] <= UInt<1>("h01")
    node T_570 = eq(T_566[0], io.inner.grant.bits.g_type)
    node T_571 = eq(T_566[1], io.inner.grant.bits.g_type)
    node T_573 = or(UInt<1>("h00"), T_570)
    node T_574 = or(T_573, T_571)
    node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574)
    node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type)
    node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03"))
    node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type)
    node T_597 = mux(T_596, UInt<3>("h01"), T_595)
    node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type)
    node T_599 = mux(T_598, UInt<3>("h04"), T_597)
    node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type)
    node T_601 = mux(T_600, UInt<3>("h03"), T_599)
    node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type)
    node T_603 = mux(T_602, UInt<3>("h03"), T_601)
    node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type)
    node T_605 = mux(T_604, UInt<3>("h05"), T_603)
    node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type)
    node T_607 = mux(T_606, UInt<3>("h04"), T_605)
    node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00"))
    node T_611 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01"))
    node T_613 = mux(T_608, T_612, UInt<1>("h01"))
    node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613)
    wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_623 is invalid
    T_623.client_id <= io.inner.acquire.bits.client_id
    T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type
    T_623.g_type <= T_614
    T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id
    T_623.manager_xact_id <= UInt<2>("h02")
    T_623.addr_beat <= UInt<1>("h00")
    T_623.data <= UInt<1>("h00")
    wire T_634 : UInt<3>[2]
    T_634[0] <= UInt<3>("h05")
    T_634[1] <= UInt<3>("h04")
    node T_638 = eq(T_634[0], T_623.g_type)
    node T_639 = eq(T_634[1], T_623.g_type)
    node T_641 = or(UInt<1>("h00"), T_638)
    node T_642 = or(T_641, T_639)
    wire T_644 : UInt<1>[2]
    T_644[0] <= UInt<1>("h00")
    T_644[1] <= UInt<1>("h01")
    node T_648 = eq(T_644[0], T_623.g_type)
    node T_649 = eq(T_644[1], T_623.g_type)
    node T_651 = or(UInt<1>("h00"), T_648)
    node T_652 = or(T_651, T_649)
    node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652)
    wire T_658 : UInt<3>[3]
    T_658[0] <= UInt<3>("h02")
    T_658[1] <= UInt<3>("h00")
    T_658[2] <= UInt<3>("h04")
    node T_663 = eq(T_658[0], xact.a_type)
    node T_664 = eq(T_658[1], xact.a_type)
    node T_665 = eq(T_658[2], xact.a_type)
    node T_667 = or(UInt<1>("h00"), T_663)
    node T_668 = or(T_667, T_664)
    node T_669 = or(T_668, T_665)
    node subblock_type = and(xact.is_builtin_type, T_669)
    node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_672 = neq(state, UInt<1>("h00"))
    node T_673 = and(T_671, T_672)
    node T_675 = eq(collect_iacq_data, UInt<1>("h00"))
    node T_676 = and(T_673, T_675)
    io.has_acquire_conflict <= T_676
    node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_678 = and(T_677, collect_iacq_data)
    io.has_acquire_match <= T_678
    node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block)
    node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00"))
    node T_682 = and(T_679, T_681)
    node T_683 = eq(state, UInt<1>("h01"))
    node T_684 = and(T_682, T_683)
    io.has_release_match <= T_684
    node T_689 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_695 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_696 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_697 = cat(T_695, T_696)
    node T_699 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_700 = cat(UInt<3>("h07"), T_699)
    node T_702 = cat(T_689, UInt<1>("h01"))
    node T_704 = cat(T_689, UInt<1>("h01"))
    node T_706 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_707 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_708 = cat(T_706, T_707)
    node T_710 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_712 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_713 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_714 = mux(T_713, T_712, UInt<1>("h00"))
    node T_715 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_716 = mux(T_715, T_710, T_714)
    node T_717 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_718 = mux(T_717, T_708, T_716)
    node T_719 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_720 = mux(T_719, T_704, T_718)
    node T_721 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_722 = mux(T_721, T_702, T_720)
    node T_723 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_724 = mux(T_723, T_700, T_722)
    node T_725 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_726 = mux(T_725, T_697, T_724)
    wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_probe is invalid
    oacq_probe.is_builtin_type <= UInt<1>("h01")
    oacq_probe.a_type <= UInt<3>("h03")
    oacq_probe.client_xact_id <= UInt<2>("h02")
    oacq_probe.addr_block <= io.inner.release.bits.addr_block
    oacq_probe.addr_beat <= io.inner.release.bits.addr_beat
    oacq_probe.data <= io.inner.release.bits.data
    oacq_probe.union <= T_726
    node T_744 = bits(xact.union, 12, 9)
    node T_745 = bits(T_744, 3, 3)
    node T_747 = dshl(UInt<1>("h01"), T_745)
    node T_749 = eq(xact.a_type, UInt<3>("h04"))
    node T_750 = and(xact.is_builtin_type, T_749)
    node T_751 = bits(T_747, 0, 0)
    node T_752 = bits(T_747, 1, 1)
    wire T_754 : UInt<1>[2]
    T_754[0] <= T_751
    T_754[1] <= T_752
    node T_759 = sub(UInt<8>("h00"), T_754[0])
    node T_760 = tail(T_759, 1)
    node T_762 = sub(UInt<8>("h00"), T_754[1])
    node T_763 = tail(T_762, 1)
    wire T_765 : UInt<8>[2]
    T_765[0] <= T_760
    T_765[1] <= T_763
    node T_769 = cat(T_765[1], T_765[0])
    node T_771 = eq(xact.a_type, UInt<3>("h03"))
    node T_772 = and(xact.is_builtin_type, T_771)
    node T_774 = eq(xact.a_type, UInt<3>("h02"))
    node T_775 = and(xact.is_builtin_type, T_774)
    node T_776 = or(T_772, T_775)
    node T_777 = bits(xact.union, 16, 1)
    node T_779 = mux(T_776, T_777, UInt<16>("h00"))
    node T_780 = mux(T_750, T_769, T_779)
    node T_788 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_789 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_790 = cat(T_788, T_789)
    node T_792 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_793 = cat(UInt<3>("h07"), T_792)
    node T_795 = cat(T_780, UInt<1>("h01"))
    node T_797 = cat(T_780, UInt<1>("h01"))
    node T_799 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_800 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_801 = cat(T_799, T_800)
    node T_803 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_805 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_806 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_807 = mux(T_806, T_805, UInt<1>("h00"))
    node T_808 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_809 = mux(T_808, T_803, T_807)
    node T_810 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_811 = mux(T_810, T_801, T_809)
    node T_812 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_813 = mux(T_812, T_797, T_811)
    node T_814 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_815 = mux(T_814, T_795, T_813)
    node T_816 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_817 = mux(T_816, T_793, T_815)
    node T_818 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_819 = mux(T_818, T_790, T_817)
    wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_beat is invalid
    oacq_write_beat.is_builtin_type <= UInt<1>("h01")
    oacq_write_beat.a_type <= UInt<3>("h02")
    oacq_write_beat.client_xact_id <= UInt<2>("h02")
    oacq_write_beat.addr_block <= xact.addr_block
    oacq_write_beat.addr_beat <= xact.addr_beat
    oacq_write_beat.data <= xact.data_buffer[0]
    oacq_write_beat.union <= T_819
    node T_846 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_847 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_848 = cat(T_846, T_847)
    node T_850 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_851 = cat(UInt<3>("h07"), T_850)
    node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_857 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_858 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_859 = cat(T_857, T_858)
    node T_861 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_863 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_864 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_865 = mux(T_864, T_863, UInt<1>("h00"))
    node T_866 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_867 = mux(T_866, T_861, T_865)
    node T_868 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_869 = mux(T_868, T_859, T_867)
    node T_870 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_871 = mux(T_870, T_855, T_869)
    node T_872 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_873 = mux(T_872, T_853, T_871)
    node T_874 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_875 = mux(T_874, T_851, T_873)
    node T_876 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_877 = mux(T_876, T_848, T_875)
    wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_block is invalid
    oacq_write_block.is_builtin_type <= UInt<1>("h01")
    oacq_write_block.a_type <= UInt<3>("h03")
    oacq_write_block.client_xact_id <= UInt<2>("h02")
    oacq_write_block.addr_block <= xact.addr_block
    oacq_write_block.addr_beat <= oacq_data_cnt
    oacq_write_block.data <= xact.data_buffer[oacq_data_cnt]
    oacq_write_block.union <= T_877
    node T_895 = bits(xact.union, 12, 9)
    node T_896 = bits(xact.union, 8, 6)
    node T_904 = cat(T_895, T_896)
    node T_905 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_906 = cat(T_904, T_905)
    node T_908 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_909 = cat(T_896, T_908)
    node T_911 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_913 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_915 = cat(T_895, T_896)
    node T_916 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_917 = cat(T_915, T_916)
    node T_919 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_921 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_922 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_923 = mux(T_922, T_921, UInt<1>("h00"))
    node T_924 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_925 = mux(T_924, T_919, T_923)
    node T_926 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_927 = mux(T_926, T_917, T_925)
    node T_928 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_929 = mux(T_928, T_913, T_927)
    node T_930 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_931 = mux(T_930, T_911, T_929)
    node T_932 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_933 = mux(T_932, T_909, T_931)
    node T_934 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_935 = mux(T_934, T_906, T_933)
    wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_beat is invalid
    oacq_read_beat.is_builtin_type <= UInt<1>("h01")
    oacq_read_beat.a_type <= UInt<3>("h00")
    oacq_read_beat.client_xact_id <= UInt<2>("h02")
    oacq_read_beat.addr_block <= xact.addr_block
    oacq_read_beat.addr_beat <= xact.addr_beat
    oacq_read_beat.data <= UInt<1>("h00")
    oacq_read_beat.union <= T_935
    node T_962 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_963 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_964 = cat(T_962, T_963)
    node T_966 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_967 = cat(UInt<3>("h07"), T_966)
    node T_969 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_971 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_973 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_974 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_975 = cat(T_973, T_974)
    node T_977 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_979 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_980 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_981 = mux(T_980, T_979, UInt<1>("h00"))
    node T_982 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_983 = mux(T_982, T_977, T_981)
    node T_984 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_985 = mux(T_984, T_975, T_983)
    node T_986 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_987 = mux(T_986, T_971, T_985)
    node T_988 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_989 = mux(T_988, T_969, T_987)
    node T_990 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_991 = mux(T_990, T_967, T_989)
    node T_992 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_993 = mux(T_992, T_964, T_991)
    wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_block is invalid
    oacq_read_block.is_builtin_type <= UInt<1>("h01")
    oacq_read_block.a_type <= UInt<3>("h01")
    oacq_read_block.client_xact_id <= UInt<2>("h02")
    oacq_read_block.addr_block <= xact.addr_block
    oacq_read_block.addr_beat <= UInt<1>("h00")
    oacq_read_block.data <= UInt<1>("h00")
    oacq_read_block.union <= T_993
    io.outer.acquire.valid <= UInt<1>("h00")
    node T_1011 = eq(state, UInt<1>("h01"))
    node T_1012 = eq(state, UInt<2>("h03"))
    node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block)
    node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block)
    node T_1029 = mux(T_1012, T_1013, T_1021)
    node T_1037 = mux(T_1011, oacq_probe, T_1029)
    io.outer.acquire.bits <- T_1037
    io.outer.grant.ready <= UInt<1>("h00")
    io.inner.probe.valid <= UInt<1>("h00")
    node T_1054 = eq(UInt<3>("h04"), xact.a_type)
    node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02"))
    node T_1056 = eq(UInt<3>("h06"), xact.a_type)
    node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055)
    node T_1058 = eq(UInt<3>("h05"), xact.a_type)
    node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057)
    node T_1060 = eq(UInt<3>("h02"), xact.a_type)
    node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059)
    node T_1062 = eq(UInt<3>("h00"), xact.a_type)
    node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061)
    node T_1064 = eq(UInt<3>("h03"), xact.a_type)
    node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063)
    node T_1066 = eq(UInt<3>("h01"), xact.a_type)
    node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065)
    node T_1068 = eq(UInt<1>("h01"), xact.a_type)
    node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02"))
    node T_1070 = eq(UInt<1>("h00"), xact.a_type)
    node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069)
    node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071)
    wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_1077 is invalid
    T_1077.client_id <= UInt<1>("h00")
    T_1077.p_type <= T_1072
    T_1077.addr_block <= xact.addr_block
    io.inner.probe.bits <- T_1077
    io.inner.grant.valid <= UInt<1>("h00")
    node T_1100 = eq(UInt<3>("h06"), xact.a_type)
    node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03"))
    node T_1102 = eq(UInt<3>("h05"), xact.a_type)
    node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101)
    node T_1104 = eq(UInt<3>("h04"), xact.a_type)
    node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103)
    node T_1106 = eq(UInt<3>("h03"), xact.a_type)
    node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105)
    node T_1108 = eq(UInt<3>("h02"), xact.a_type)
    node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107)
    node T_1110 = eq(UInt<3>("h01"), xact.a_type)
    node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109)
    node T_1112 = eq(UInt<3>("h00"), xact.a_type)
    node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111)
    node T_1114 = eq(xact.a_type, UInt<1>("h00"))
    node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01"))
    node T_1119 = mux(T_1114, T_1118, UInt<1>("h01"))
    node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119)
    wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_1129 is invalid
    T_1129.client_id <= xact.client_id
    T_1129.is_builtin_type <= xact.is_builtin_type
    T_1129.g_type <= T_1120
    T_1129.client_xact_id <= xact.client_xact_id
    T_1129.manager_xact_id <= UInt<2>("h02")
    T_1129.addr_beat <= UInt<1>("h00")
    T_1129.data <= UInt<1>("h00")
    io.inner.grant.bits <- T_1129
    io.inner.acquire.ready <= UInt<1>("h00")
    io.inner.release.ready <= UInt<1>("h00")
    io.inner.finish.ready <= UInt<1>("h00")
    node T_1140 = neq(state, UInt<1>("h00"))
    node T_1141 = and(T_1140, collect_iacq_data)
    node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1143 = and(T_1141, T_1142)
    node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id)
    node T_1145 = and(T_1143, T_1144)
    node T_1147 = eq(T_1145, UInt<1>("h00"))
    node T_1149 = eq(reset, UInt<1>("h00"))
    when T_1149 :
      node T_1151 = eq(T_1147, UInt<1>("h00"))
      when T_1151 :
        node T_1153 = eq(reset, UInt<1>("h00"))
        when T_1153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1154 = neq(state, UInt<1>("h00"))
    node T_1155 = and(T_1154, collect_iacq_data)
    node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1157 = and(T_1155, T_1156)
    node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id)
    node T_1159 = and(T_1157, T_1158)
    node T_1161 = eq(T_1159, UInt<1>("h00"))
    node T_1163 = eq(reset, UInt<1>("h00"))
    when T_1163 :
      node T_1165 = eq(T_1161, UInt<1>("h00"))
      when T_1165 :
        node T_1167 = eq(reset, UInt<1>("h00"))
        when T_1167 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1168 = eq(state, UInt<1>("h00"))
    node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1170 = and(T_1168, T_1169)
    node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_1175 : UInt<3>[1]
    T_1175[0] <= UInt<3>("h03")
    node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type)
    node T_1180 = or(UInt<1>("h00"), T_1178)
    node T_1181 = and(T_1172, T_1180)
    node T_1182 = and(T_1170, T_1181)
    node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00"))
    node T_1185 = and(T_1182, T_1184)
    node T_1187 = eq(T_1185, UInt<1>("h00"))
    node T_1189 = eq(reset, UInt<1>("h00"))
    when T_1189 :
      node T_1191 = eq(T_1187, UInt<1>("h00"))
      when T_1191 :
        node T_1193 = eq(reset, UInt<1>("h00"))
        when T_1193 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    when collect_iacq_data :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data
        node T_1197 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1198 = bits(T_1197, 3, 3)
        node T_1200 = dshl(UInt<1>("h01"), T_1198)
        node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202)
        node T_1204 = bits(T_1200, 0, 0)
        node T_1205 = bits(T_1200, 1, 1)
        wire T_1207 : UInt<1>[2]
        T_1207[0] <= T_1204
        T_1207[1] <= T_1205
        node T_1212 = sub(UInt<8>("h00"), T_1207[0])
        node T_1213 = tail(T_1212, 1)
        node T_1215 = sub(UInt<8>("h00"), T_1207[1])
        node T_1216 = tail(T_1215, 1)
        wire T_1218 : UInt<8>[2]
        T_1218[0] <= T_1213
        T_1218[1] <= T_1216
        node T_1222 = cat(T_1218[1], T_1218[0])
        node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224)
        node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227)
        node T_1229 = or(T_1225, T_1228)
        node T_1230 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1232 = mux(T_1229, T_1230, UInt<16>("h00"))
        node T_1233 = mux(T_1203, T_1222, T_1232)
        xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233
        node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat)
        node T_1237 = or(iacq_data_valid, T_1236)
        node T_1238 = not(iacq_data_valid)
        node T_1239 = or(T_1238, T_1236)
        node T_1240 = not(T_1239)
        node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240)
        iacq_data_valid <= T_1241
        skip
      when iacq_data_done :
        collect_iacq_data <= UInt<1>("h00")
        skip
      skip
    when pending_ognt_ack :
      io.outer.grant.ready <= UInt<1>("h01")
      when io.outer.grant.valid :
        pending_ognt_ack <= UInt<1>("h00")
        skip
      skip
    node T_1245 = eq(UInt<1>("h00"), state)
    when T_1245 :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact <- io.inner.acquire.bits
        xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data
        node T_1251 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1252 = bits(T_1251, 3, 3)
        node T_1254 = dshl(UInt<1>("h01"), T_1252)
        node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256)
        node T_1258 = bits(T_1254, 0, 0)
        node T_1259 = bits(T_1254, 1, 1)
        wire T_1261 : UInt<1>[2]
        T_1261[0] <= T_1258
        T_1261[1] <= T_1259
        node T_1266 = sub(UInt<8>("h00"), T_1261[0])
        node T_1267 = tail(T_1266, 1)
        node T_1269 = sub(UInt<8>("h00"), T_1261[1])
        node T_1270 = tail(T_1269, 1)
        wire T_1272 : UInt<8>[2]
        T_1272[0] <= T_1267
        T_1272[1] <= T_1270
        node T_1276 = cat(T_1272[1], T_1272[0])
        node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278)
        node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281)
        node T_1283 = or(T_1279, T_1282)
        node T_1284 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1286 = mux(T_1283, T_1284, UInt<16>("h00"))
        node T_1287 = mux(T_1257, T_1276, T_1286)
        xact.wmask_buffer[UInt<1>("h00")] <= T_1287
        node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
        wire T_1292 : UInt<3>[1]
        T_1292[0] <= UInt<3>("h03")
        node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type)
        node T_1297 = or(UInt<1>("h00"), T_1295)
        node T_1298 = and(T_1289, T_1297)
        collect_iacq_data <= T_1298
        wire T_1303 : UInt<3>[3]
        T_1303[0] <= UInt<3>("h02")
        T_1303[1] <= UInt<3>("h03")
        T_1303[2] <= UInt<3>("h04")
        node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type)
        node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type)
        node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type)
        node T_1312 = or(UInt<1>("h00"), T_1308)
        node T_1313 = or(T_1312, T_1309)
        node T_1314 = or(T_1313, T_1310)
        node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314)
        node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat)
        iacq_data_valid <= T_1316
        node T_1318 = neq(mask_incoherent, UInt<1>("h00"))
        when T_1318 :
          pending_probes <= mask_incoherent
          node T_1319 = bits(mask_incoherent, 0, 0)
          node T_1320 = bits(mask_incoherent, 1, 1)
          node T_1321 = bits(mask_incoherent, 2, 2)
          node T_1322 = bits(mask_incoherent, 3, 3)
          node T_1324 = cat(UInt<1>("h00"), T_1320)
          node T_1325 = add(T_1319, T_1324)
          node T_1326 = tail(T_1325, 1)
          node T_1329 = cat(UInt<1>("h00"), T_1322)
          node T_1330 = add(T_1321, T_1329)
          node T_1331 = tail(T_1330, 1)
          node T_1332 = cat(UInt<1>("h00"), T_1331)
          node T_1333 = add(T_1326, T_1332)
          node T_1334 = tail(T_1333, 1)
          release_count <= T_1334
          skip
        node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04"))
        node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335)
        node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336)
        state <= T_1337
        skip
      skip
    node T_1338 = eq(UInt<1>("h01"), state)
    when T_1338 :
      node T_1340 = neq(pending_probes, UInt<1>("h00"))
      io.inner.probe.valid <= T_1340
      when io.inner.probe.ready :
        node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00"))
        node T_1343 = not(T_1342)
        node T_1344 = and(pending_probes, T_1343)
        pending_probes <= T_1344
        skip
      wire T_1346 : UInt<2>[3]
      T_1346[0] <= UInt<1>("h00")
      T_1346[1] <= UInt<1>("h01")
      T_1346[2] <= UInt<2>("h02")
      node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type)
      node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type)
      node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type)
      node T_1355 = or(UInt<1>("h00"), T_1351)
      node T_1356 = or(T_1355, T_1352)
      node T_1357 = or(T_1356, T_1353)
      node T_1359 = eq(T_1357, UInt<1>("h00"))
      node T_1360 = or(T_1359, io.outer.acquire.ready)
      io.inner.release.ready <= T_1360
      when io.inner.release.valid :
        wire T_1362 : UInt<2>[3]
        T_1362[0] <= UInt<1>("h00")
        T_1362[1] <= UInt<1>("h01")
        T_1362[2] <= UInt<2>("h02")
        node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type)
        node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type)
        node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type)
        node T_1371 = or(UInt<1>("h00"), T_1367)
        node T_1372 = or(T_1371, T_1368)
        node T_1373 = or(T_1372, T_1369)
        when T_1373 :
          io.outer.acquire.valid <= UInt<1>("h01")
          when io.outer.acquire.ready :
            when oacq_data_done :
              pending_ognt_ack <= UInt<1>("h01")
              node T_1377 = sub(release_count, UInt<1>("h01"))
              node T_1378 = tail(T_1377, 1)
              release_count <= T_1378
              node T_1380 = eq(release_count, UInt<1>("h01"))
              when T_1380 :
                node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
                node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381)
                state <= T_1382
                skip
              skip
            skip
          skip
        node T_1384 = eq(T_1373, UInt<1>("h00"))
        when T_1384 :
          node T_1386 = sub(release_count, UInt<1>("h01"))
          node T_1387 = tail(T_1386, 1)
          release_count <= T_1387
          node T_1389 = eq(release_count, UInt<1>("h01"))
          when T_1389 :
            node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
            node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390)
            state <= T_1391
            skip
          skip
        skip
      skip
    node T_1392 = eq(UInt<2>("h03"), state)
    when T_1392 :
      node T_1394 = eq(pending_ognt_ack, UInt<1>("h00"))
      node T_1396 = eq(collect_iacq_data, UInt<1>("h00"))
      node T_1397 = dshr(iacq_data_valid, oacq_data_cnt)
      node T_1398 = bits(T_1397, 0, 0)
      node T_1399 = or(T_1396, T_1398)
      node T_1400 = and(T_1394, T_1399)
      io.outer.acquire.valid <= T_1400
      when oacq_data_done :
        pending_ognt_ack <= UInt<1>("h01")
        node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05"))
        state <= T_1402
        skip
      skip
    node T_1403 = eq(UInt<2>("h02"), state)
    when T_1403 :
      node T_1405 = eq(pending_ognt_ack, UInt<1>("h00"))
      io.outer.acquire.valid <= T_1405
      node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid)
      when T_1406 :
        state <= UInt<3>("h05")
        skip
      skip
    node T_1407 = eq(UInt<3>("h05"), state)
    when T_1407 :
      io.outer.grant.ready <= io.inner.grant.ready
      io.inner.grant.valid <= io.outer.grant.valid
      when ignt_data_done :
        node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412)
        node T_1415 = eq(T_1413, UInt<1>("h00"))
        node T_1416 = and(T_1410, T_1415)
        node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1417
        skip
      skip
    node T_1418 = eq(UInt<3>("h04"), state)
    when T_1418 :
      io.inner.grant.valid <= UInt<1>("h01")
      when io.inner.grant.ready :
        node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424)
        node T_1427 = eq(T_1425, UInt<1>("h00"))
        node T_1428 = and(T_1422, T_1427)
        node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1429
        skip
      skip
    node T_1430 = eq(UInt<3>("h06"), state)
    when T_1430 :
      io.inner.finish.ready <= UInt<1>("h01")
      when io.inner.finish.valid :
        state <= UInt<1>("h00")
        skip
      skip
    
  module BroadcastAcquireTracker_28 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
    wire coh : {sharers : UInt<1>}
    coh is invalid
    coh.sharers <= UInt<1>("h00")
    node T_303 = neq(state, UInt<1>("h00"))
    node T_304 = and(T_303, xact.is_builtin_type)
    wire T_309 : UInt<3>[3]
    T_309[0] <= UInt<3>("h04")
    T_309[1] <= UInt<3>("h05")
    T_309[2] <= UInt<3>("h06")
    node T_314 = eq(T_309[0], xact.a_type)
    node T_315 = eq(T_309[1], xact.a_type)
    node T_316 = eq(T_309[2], xact.a_type)
    node T_318 = or(UInt<1>("h00"), T_314)
    node T_319 = or(T_318, T_315)
    node T_320 = or(T_319, T_316)
    node T_321 = and(T_304, T_320)
    node T_323 = eq(T_321, UInt<1>("h00"))
    node T_325 = eq(reset, UInt<1>("h00"))
    when T_325 :
      node T_327 = eq(T_323, UInt<1>("h00"))
      when T_327 :
        node T_329 = eq(reset, UInt<1>("h00"))
        when T_329 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_334 = bits(pending_probes, 0, 0)
    wire T_336 : UInt<1>[1]
    T_336[0] <= T_334
    node T_341 = asUInt(asSInt(UInt<1>("h01")))
    node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id)
    node T_345 = or(T_341, T_344)
    node T_346 = not(T_341)
    node T_347 = or(T_346, T_344)
    node T_348 = not(T_347)
    node mask_self = mux(UInt<1>("h00"), T_345, T_348)
    node T_350 = not(io.incoherent[0])
    node mask_incoherent = and(mask_self, T_350)
    reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_362 : UInt<3>[1]
    T_362[0] <= UInt<3>("h03")
    node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type)
    node T_367 = or(UInt<1>("h00"), T_365)
    node T_368 = and(T_359, T_367)
    node T_369 = and(T_356, T_368)
    reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_369 :
      node T_373 = eq(T_371, UInt<2>("h03"))
      node T_375 = and(UInt<1>("h00"), T_373)
      node T_378 = add(T_371, UInt<1>("h01"))
      node T_379 = tail(T_378, 1)
      node T_380 = mux(T_375, UInt<1>("h00"), T_379)
      T_371 <= T_380
      skip
    node T_381 = and(T_369, T_373)
    node T_382 = mux(T_368, T_371, UInt<1>("h00"))
    node iacq_data_done = mux(T_368, T_381, T_356)
    node T_384 = and(io.inner.release.ready, io.inner.release.valid)
    wire T_388 : UInt<2>[3]
    T_388[0] <= UInt<1>("h00")
    T_388[1] <= UInt<1>("h01")
    T_388[2] <= UInt<2>("h02")
    node T_393 = eq(T_388[0], io.inner.release.bits.r_type)
    node T_394 = eq(T_388[1], io.inner.release.bits.r_type)
    node T_395 = eq(T_388[2], io.inner.release.bits.r_type)
    node T_397 = or(UInt<1>("h00"), T_393)
    node T_398 = or(T_397, T_394)
    node T_399 = or(T_398, T_395)
    node T_400 = and(UInt<1>("h01"), T_399)
    node T_401 = and(T_384, T_400)
    reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_401 :
      node T_405 = eq(T_403, UInt<2>("h03"))
      node T_407 = and(UInt<1>("h00"), T_405)
      node T_410 = add(T_403, UInt<1>("h01"))
      node T_411 = tail(T_410, 1)
      node T_412 = mux(T_407, UInt<1>("h00"), T_411)
      T_403 <= T_412
      skip
    node T_413 = and(T_401, T_405)
    node T_414 = mux(T_400, T_403, UInt<1>("h00"))
    node irel_data_done = mux(T_400, T_413, T_384)
    node T_417 = and(io.inner.grant.ready, io.inner.grant.valid)
    wire T_421 : UInt<3>[1]
    T_421[0] <= UInt<3>("h05")
    node T_424 = eq(T_421[0], io.inner.grant.bits.g_type)
    node T_426 = or(UInt<1>("h00"), T_424)
    wire T_428 : UInt<1>[2]
    T_428[0] <= UInt<1>("h00")
    T_428[1] <= UInt<1>("h01")
    node T_432 = eq(T_428[0], io.inner.grant.bits.g_type)
    node T_433 = eq(T_428[1], io.inner.grant.bits.g_type)
    node T_435 = or(UInt<1>("h00"), T_432)
    node T_436 = or(T_435, T_433)
    node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436)
    node T_438 = and(UInt<1>("h01"), T_437)
    node T_439 = and(T_417, T_438)
    reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_439 :
      node T_443 = eq(T_441, UInt<2>("h03"))
      node T_445 = and(UInt<1>("h00"), T_443)
      node T_448 = add(T_441, UInt<1>("h01"))
      node T_449 = tail(T_448, 1)
      node T_450 = mux(T_445, UInt<1>("h00"), T_449)
      T_441 <= T_450
      skip
    node T_451 = and(T_439, T_443)
    node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00"))
    node ignt_data_done = mux(T_438, T_451, T_417)
    node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type)
    wire T_460 : UInt<3>[1]
    T_460[0] <= UInt<3>("h03")
    node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type)
    node T_465 = or(UInt<1>("h00"), T_463)
    node T_466 = and(T_457, T_465)
    node T_467 = and(T_455, T_466)
    reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_467 :
      node T_471 = eq(T_469, UInt<2>("h03"))
      node T_473 = and(UInt<1>("h00"), T_471)
      node T_476 = add(T_469, UInt<1>("h01"))
      node T_477 = tail(T_476, 1)
      node T_478 = mux(T_473, UInt<1>("h00"), T_477)
      T_469 <= T_478
      skip
    node T_479 = and(T_467, T_471)
    node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00"))
    node oacq_data_done = mux(T_466, T_479, T_455)
    node T_482 = and(io.outer.grant.ready, io.outer.grant.valid)
    wire T_487 : UInt<3>[1]
    T_487[0] <= UInt<3>("h05")
    node T_490 = eq(T_487[0], io.outer.grant.bits.g_type)
    node T_492 = or(UInt<1>("h00"), T_490)
    wire T_494 : UInt<1>[1]
    T_494[0] <= UInt<1>("h00")
    node T_497 = eq(T_494[0], io.outer.grant.bits.g_type)
    node T_499 = or(UInt<1>("h00"), T_497)
    node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499)
    node T_501 = and(UInt<1>("h01"), T_500)
    node T_502 = and(T_482, T_501)
    reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_502 :
      node T_506 = eq(T_504, UInt<2>("h03"))
      node T_508 = and(UInt<1>("h00"), T_506)
      node T_511 = add(T_504, UInt<1>("h01"))
      node T_512 = tail(T_511, 1)
      node T_513 = mux(T_508, UInt<1>("h00"), T_512)
      T_504 <= T_513
      skip
    node T_514 = and(T_502, T_506)
    node T_515 = mux(T_501, T_504, UInt<1>("h00"))
    node ognt_data_done = mux(T_501, T_514, T_482)
    reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_523 : UInt<3>[3]
    T_523[0] <= UInt<3>("h02")
    T_523[1] <= UInt<3>("h03")
    T_523[2] <= UInt<3>("h04")
    node T_528 = eq(T_523[0], xact.a_type)
    node T_529 = eq(T_523[1], xact.a_type)
    node T_530 = eq(T_523[2], xact.a_type)
    node T_532 = or(UInt<1>("h00"), T_528)
    node T_533 = or(T_532, T_529)
    node T_534 = or(T_533, T_530)
    node pending_outer_write = and(xact.is_builtin_type, T_534)
    wire T_540 : UInt<3>[3]
    T_540[0] <= UInt<3>("h02")
    T_540[1] <= UInt<3>("h03")
    T_540[2] <= UInt<3>("h04")
    node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type)
    node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type)
    node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type)
    node T_549 = or(UInt<1>("h00"), T_545)
    node T_550 = or(T_549, T_546)
    node T_551 = or(T_550, T_547)
    node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551)
    wire T_556 : UInt<3>[2]
    T_556[0] <= UInt<3>("h05")
    T_556[1] <= UInt<3>("h04")
    node T_560 = eq(T_556[0], io.inner.grant.bits.g_type)
    node T_561 = eq(T_556[1], io.inner.grant.bits.g_type)
    node T_563 = or(UInt<1>("h00"), T_560)
    node T_564 = or(T_563, T_561)
    wire T_566 : UInt<1>[2]
    T_566[0] <= UInt<1>("h00")
    T_566[1] <= UInt<1>("h01")
    node T_570 = eq(T_566[0], io.inner.grant.bits.g_type)
    node T_571 = eq(T_566[1], io.inner.grant.bits.g_type)
    node T_573 = or(UInt<1>("h00"), T_570)
    node T_574 = or(T_573, T_571)
    node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574)
    node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type)
    node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03"))
    node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type)
    node T_597 = mux(T_596, UInt<3>("h01"), T_595)
    node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type)
    node T_599 = mux(T_598, UInt<3>("h04"), T_597)
    node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type)
    node T_601 = mux(T_600, UInt<3>("h03"), T_599)
    node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type)
    node T_603 = mux(T_602, UInt<3>("h03"), T_601)
    node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type)
    node T_605 = mux(T_604, UInt<3>("h05"), T_603)
    node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type)
    node T_607 = mux(T_606, UInt<3>("h04"), T_605)
    node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00"))
    node T_611 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01"))
    node T_613 = mux(T_608, T_612, UInt<1>("h01"))
    node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613)
    wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_623 is invalid
    T_623.client_id <= io.inner.acquire.bits.client_id
    T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type
    T_623.g_type <= T_614
    T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id
    T_623.manager_xact_id <= UInt<2>("h03")
    T_623.addr_beat <= UInt<1>("h00")
    T_623.data <= UInt<1>("h00")
    wire T_634 : UInt<3>[2]
    T_634[0] <= UInt<3>("h05")
    T_634[1] <= UInt<3>("h04")
    node T_638 = eq(T_634[0], T_623.g_type)
    node T_639 = eq(T_634[1], T_623.g_type)
    node T_641 = or(UInt<1>("h00"), T_638)
    node T_642 = or(T_641, T_639)
    wire T_644 : UInt<1>[2]
    T_644[0] <= UInt<1>("h00")
    T_644[1] <= UInt<1>("h01")
    node T_648 = eq(T_644[0], T_623.g_type)
    node T_649 = eq(T_644[1], T_623.g_type)
    node T_651 = or(UInt<1>("h00"), T_648)
    node T_652 = or(T_651, T_649)
    node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652)
    wire T_658 : UInt<3>[3]
    T_658[0] <= UInt<3>("h02")
    T_658[1] <= UInt<3>("h00")
    T_658[2] <= UInt<3>("h04")
    node T_663 = eq(T_658[0], xact.a_type)
    node T_664 = eq(T_658[1], xact.a_type)
    node T_665 = eq(T_658[2], xact.a_type)
    node T_667 = or(UInt<1>("h00"), T_663)
    node T_668 = or(T_667, T_664)
    node T_669 = or(T_668, T_665)
    node subblock_type = and(xact.is_builtin_type, T_669)
    node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_672 = neq(state, UInt<1>("h00"))
    node T_673 = and(T_671, T_672)
    node T_675 = eq(collect_iacq_data, UInt<1>("h00"))
    node T_676 = and(T_673, T_675)
    io.has_acquire_conflict <= T_676
    node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_678 = and(T_677, collect_iacq_data)
    io.has_acquire_match <= T_678
    node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block)
    node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00"))
    node T_682 = and(T_679, T_681)
    node T_683 = eq(state, UInt<1>("h01"))
    node T_684 = and(T_682, T_683)
    io.has_release_match <= T_684
    node T_689 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_695 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_696 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_697 = cat(T_695, T_696)
    node T_699 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_700 = cat(UInt<3>("h07"), T_699)
    node T_702 = cat(T_689, UInt<1>("h01"))
    node T_704 = cat(T_689, UInt<1>("h01"))
    node T_706 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_707 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_708 = cat(T_706, T_707)
    node T_710 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_712 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_713 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_714 = mux(T_713, T_712, UInt<1>("h00"))
    node T_715 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_716 = mux(T_715, T_710, T_714)
    node T_717 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_718 = mux(T_717, T_708, T_716)
    node T_719 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_720 = mux(T_719, T_704, T_718)
    node T_721 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_722 = mux(T_721, T_702, T_720)
    node T_723 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_724 = mux(T_723, T_700, T_722)
    node T_725 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_726 = mux(T_725, T_697, T_724)
    wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_probe is invalid
    oacq_probe.is_builtin_type <= UInt<1>("h01")
    oacq_probe.a_type <= UInt<3>("h03")
    oacq_probe.client_xact_id <= UInt<2>("h03")
    oacq_probe.addr_block <= io.inner.release.bits.addr_block
    oacq_probe.addr_beat <= io.inner.release.bits.addr_beat
    oacq_probe.data <= io.inner.release.bits.data
    oacq_probe.union <= T_726
    node T_744 = bits(xact.union, 12, 9)
    node T_745 = bits(T_744, 3, 3)
    node T_747 = dshl(UInt<1>("h01"), T_745)
    node T_749 = eq(xact.a_type, UInt<3>("h04"))
    node T_750 = and(xact.is_builtin_type, T_749)
    node T_751 = bits(T_747, 0, 0)
    node T_752 = bits(T_747, 1, 1)
    wire T_754 : UInt<1>[2]
    T_754[0] <= T_751
    T_754[1] <= T_752
    node T_759 = sub(UInt<8>("h00"), T_754[0])
    node T_760 = tail(T_759, 1)
    node T_762 = sub(UInt<8>("h00"), T_754[1])
    node T_763 = tail(T_762, 1)
    wire T_765 : UInt<8>[2]
    T_765[0] <= T_760
    T_765[1] <= T_763
    node T_769 = cat(T_765[1], T_765[0])
    node T_771 = eq(xact.a_type, UInt<3>("h03"))
    node T_772 = and(xact.is_builtin_type, T_771)
    node T_774 = eq(xact.a_type, UInt<3>("h02"))
    node T_775 = and(xact.is_builtin_type, T_774)
    node T_776 = or(T_772, T_775)
    node T_777 = bits(xact.union, 16, 1)
    node T_779 = mux(T_776, T_777, UInt<16>("h00"))
    node T_780 = mux(T_750, T_769, T_779)
    node T_788 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_789 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_790 = cat(T_788, T_789)
    node T_792 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_793 = cat(UInt<3>("h07"), T_792)
    node T_795 = cat(T_780, UInt<1>("h01"))
    node T_797 = cat(T_780, UInt<1>("h01"))
    node T_799 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_800 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_801 = cat(T_799, T_800)
    node T_803 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_805 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_806 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_807 = mux(T_806, T_805, UInt<1>("h00"))
    node T_808 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_809 = mux(T_808, T_803, T_807)
    node T_810 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_811 = mux(T_810, T_801, T_809)
    node T_812 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_813 = mux(T_812, T_797, T_811)
    node T_814 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_815 = mux(T_814, T_795, T_813)
    node T_816 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_817 = mux(T_816, T_793, T_815)
    node T_818 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_819 = mux(T_818, T_790, T_817)
    wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_beat is invalid
    oacq_write_beat.is_builtin_type <= UInt<1>("h01")
    oacq_write_beat.a_type <= UInt<3>("h02")
    oacq_write_beat.client_xact_id <= UInt<2>("h03")
    oacq_write_beat.addr_block <= xact.addr_block
    oacq_write_beat.addr_beat <= xact.addr_beat
    oacq_write_beat.data <= xact.data_buffer[0]
    oacq_write_beat.union <= T_819
    node T_846 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_847 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_848 = cat(T_846, T_847)
    node T_850 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_851 = cat(UInt<3>("h07"), T_850)
    node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_857 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_858 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_859 = cat(T_857, T_858)
    node T_861 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_863 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_864 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_865 = mux(T_864, T_863, UInt<1>("h00"))
    node T_866 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_867 = mux(T_866, T_861, T_865)
    node T_868 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_869 = mux(T_868, T_859, T_867)
    node T_870 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_871 = mux(T_870, T_855, T_869)
    node T_872 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_873 = mux(T_872, T_853, T_871)
    node T_874 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_875 = mux(T_874, T_851, T_873)
    node T_876 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_877 = mux(T_876, T_848, T_875)
    wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_block is invalid
    oacq_write_block.is_builtin_type <= UInt<1>("h01")
    oacq_write_block.a_type <= UInt<3>("h03")
    oacq_write_block.client_xact_id <= UInt<2>("h03")
    oacq_write_block.addr_block <= xact.addr_block
    oacq_write_block.addr_beat <= oacq_data_cnt
    oacq_write_block.data <= xact.data_buffer[oacq_data_cnt]
    oacq_write_block.union <= T_877
    node T_895 = bits(xact.union, 12, 9)
    node T_896 = bits(xact.union, 8, 6)
    node T_904 = cat(T_895, T_896)
    node T_905 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_906 = cat(T_904, T_905)
    node T_908 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_909 = cat(T_896, T_908)
    node T_911 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_913 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_915 = cat(T_895, T_896)
    node T_916 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_917 = cat(T_915, T_916)
    node T_919 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_921 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_922 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_923 = mux(T_922, T_921, UInt<1>("h00"))
    node T_924 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_925 = mux(T_924, T_919, T_923)
    node T_926 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_927 = mux(T_926, T_917, T_925)
    node T_928 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_929 = mux(T_928, T_913, T_927)
    node T_930 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_931 = mux(T_930, T_911, T_929)
    node T_932 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_933 = mux(T_932, T_909, T_931)
    node T_934 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_935 = mux(T_934, T_906, T_933)
    wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_beat is invalid
    oacq_read_beat.is_builtin_type <= UInt<1>("h01")
    oacq_read_beat.a_type <= UInt<3>("h00")
    oacq_read_beat.client_xact_id <= UInt<2>("h03")
    oacq_read_beat.addr_block <= xact.addr_block
    oacq_read_beat.addr_beat <= xact.addr_beat
    oacq_read_beat.data <= UInt<1>("h00")
    oacq_read_beat.union <= T_935
    node T_962 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_963 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_964 = cat(T_962, T_963)
    node T_966 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_967 = cat(UInt<3>("h07"), T_966)
    node T_969 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_971 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_973 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_974 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_975 = cat(T_973, T_974)
    node T_977 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_979 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_980 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_981 = mux(T_980, T_979, UInt<1>("h00"))
    node T_982 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_983 = mux(T_982, T_977, T_981)
    node T_984 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_985 = mux(T_984, T_975, T_983)
    node T_986 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_987 = mux(T_986, T_971, T_985)
    node T_988 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_989 = mux(T_988, T_969, T_987)
    node T_990 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_991 = mux(T_990, T_967, T_989)
    node T_992 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_993 = mux(T_992, T_964, T_991)
    wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_block is invalid
    oacq_read_block.is_builtin_type <= UInt<1>("h01")
    oacq_read_block.a_type <= UInt<3>("h01")
    oacq_read_block.client_xact_id <= UInt<2>("h03")
    oacq_read_block.addr_block <= xact.addr_block
    oacq_read_block.addr_beat <= UInt<1>("h00")
    oacq_read_block.data <= UInt<1>("h00")
    oacq_read_block.union <= T_993
    io.outer.acquire.valid <= UInt<1>("h00")
    node T_1011 = eq(state, UInt<1>("h01"))
    node T_1012 = eq(state, UInt<2>("h03"))
    node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block)
    node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block)
    node T_1029 = mux(T_1012, T_1013, T_1021)
    node T_1037 = mux(T_1011, oacq_probe, T_1029)
    io.outer.acquire.bits <- T_1037
    io.outer.grant.ready <= UInt<1>("h00")
    io.inner.probe.valid <= UInt<1>("h00")
    node T_1054 = eq(UInt<3>("h04"), xact.a_type)
    node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02"))
    node T_1056 = eq(UInt<3>("h06"), xact.a_type)
    node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055)
    node T_1058 = eq(UInt<3>("h05"), xact.a_type)
    node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057)
    node T_1060 = eq(UInt<3>("h02"), xact.a_type)
    node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059)
    node T_1062 = eq(UInt<3>("h00"), xact.a_type)
    node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061)
    node T_1064 = eq(UInt<3>("h03"), xact.a_type)
    node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063)
    node T_1066 = eq(UInt<3>("h01"), xact.a_type)
    node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065)
    node T_1068 = eq(UInt<1>("h01"), xact.a_type)
    node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02"))
    node T_1070 = eq(UInt<1>("h00"), xact.a_type)
    node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069)
    node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071)
    wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_1077 is invalid
    T_1077.client_id <= UInt<1>("h00")
    T_1077.p_type <= T_1072
    T_1077.addr_block <= xact.addr_block
    io.inner.probe.bits <- T_1077
    io.inner.grant.valid <= UInt<1>("h00")
    node T_1100 = eq(UInt<3>("h06"), xact.a_type)
    node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03"))
    node T_1102 = eq(UInt<3>("h05"), xact.a_type)
    node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101)
    node T_1104 = eq(UInt<3>("h04"), xact.a_type)
    node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103)
    node T_1106 = eq(UInt<3>("h03"), xact.a_type)
    node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105)
    node T_1108 = eq(UInt<3>("h02"), xact.a_type)
    node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107)
    node T_1110 = eq(UInt<3>("h01"), xact.a_type)
    node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109)
    node T_1112 = eq(UInt<3>("h00"), xact.a_type)
    node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111)
    node T_1114 = eq(xact.a_type, UInt<1>("h00"))
    node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01"))
    node T_1119 = mux(T_1114, T_1118, UInt<1>("h01"))
    node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119)
    wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_1129 is invalid
    T_1129.client_id <= xact.client_id
    T_1129.is_builtin_type <= xact.is_builtin_type
    T_1129.g_type <= T_1120
    T_1129.client_xact_id <= xact.client_xact_id
    T_1129.manager_xact_id <= UInt<2>("h03")
    T_1129.addr_beat <= UInt<1>("h00")
    T_1129.data <= UInt<1>("h00")
    io.inner.grant.bits <- T_1129
    io.inner.acquire.ready <= UInt<1>("h00")
    io.inner.release.ready <= UInt<1>("h00")
    io.inner.finish.ready <= UInt<1>("h00")
    node T_1140 = neq(state, UInt<1>("h00"))
    node T_1141 = and(T_1140, collect_iacq_data)
    node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1143 = and(T_1141, T_1142)
    node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id)
    node T_1145 = and(T_1143, T_1144)
    node T_1147 = eq(T_1145, UInt<1>("h00"))
    node T_1149 = eq(reset, UInt<1>("h00"))
    when T_1149 :
      node T_1151 = eq(T_1147, UInt<1>("h00"))
      when T_1151 :
        node T_1153 = eq(reset, UInt<1>("h00"))
        when T_1153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1154 = neq(state, UInt<1>("h00"))
    node T_1155 = and(T_1154, collect_iacq_data)
    node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1157 = and(T_1155, T_1156)
    node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id)
    node T_1159 = and(T_1157, T_1158)
    node T_1161 = eq(T_1159, UInt<1>("h00"))
    node T_1163 = eq(reset, UInt<1>("h00"))
    when T_1163 :
      node T_1165 = eq(T_1161, UInt<1>("h00"))
      when T_1165 :
        node T_1167 = eq(reset, UInt<1>("h00"))
        when T_1167 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1168 = eq(state, UInt<1>("h00"))
    node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1170 = and(T_1168, T_1169)
    node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_1175 : UInt<3>[1]
    T_1175[0] <= UInt<3>("h03")
    node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type)
    node T_1180 = or(UInt<1>("h00"), T_1178)
    node T_1181 = and(T_1172, T_1180)
    node T_1182 = and(T_1170, T_1181)
    node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00"))
    node T_1185 = and(T_1182, T_1184)
    node T_1187 = eq(T_1185, UInt<1>("h00"))
    node T_1189 = eq(reset, UInt<1>("h00"))
    when T_1189 :
      node T_1191 = eq(T_1187, UInt<1>("h00"))
      when T_1191 :
        node T_1193 = eq(reset, UInt<1>("h00"))
        when T_1193 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    when collect_iacq_data :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data
        node T_1197 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1198 = bits(T_1197, 3, 3)
        node T_1200 = dshl(UInt<1>("h01"), T_1198)
        node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202)
        node T_1204 = bits(T_1200, 0, 0)
        node T_1205 = bits(T_1200, 1, 1)
        wire T_1207 : UInt<1>[2]
        T_1207[0] <= T_1204
        T_1207[1] <= T_1205
        node T_1212 = sub(UInt<8>("h00"), T_1207[0])
        node T_1213 = tail(T_1212, 1)
        node T_1215 = sub(UInt<8>("h00"), T_1207[1])
        node T_1216 = tail(T_1215, 1)
        wire T_1218 : UInt<8>[2]
        T_1218[0] <= T_1213
        T_1218[1] <= T_1216
        node T_1222 = cat(T_1218[1], T_1218[0])
        node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224)
        node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227)
        node T_1229 = or(T_1225, T_1228)
        node T_1230 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1232 = mux(T_1229, T_1230, UInt<16>("h00"))
        node T_1233 = mux(T_1203, T_1222, T_1232)
        xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233
        node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat)
        node T_1237 = or(iacq_data_valid, T_1236)
        node T_1238 = not(iacq_data_valid)
        node T_1239 = or(T_1238, T_1236)
        node T_1240 = not(T_1239)
        node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240)
        iacq_data_valid <= T_1241
        skip
      when iacq_data_done :
        collect_iacq_data <= UInt<1>("h00")
        skip
      skip
    when pending_ognt_ack :
      io.outer.grant.ready <= UInt<1>("h01")
      when io.outer.grant.valid :
        pending_ognt_ack <= UInt<1>("h00")
        skip
      skip
    node T_1245 = eq(UInt<1>("h00"), state)
    when T_1245 :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact <- io.inner.acquire.bits
        xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data
        node T_1251 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1252 = bits(T_1251, 3, 3)
        node T_1254 = dshl(UInt<1>("h01"), T_1252)
        node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256)
        node T_1258 = bits(T_1254, 0, 0)
        node T_1259 = bits(T_1254, 1, 1)
        wire T_1261 : UInt<1>[2]
        T_1261[0] <= T_1258
        T_1261[1] <= T_1259
        node T_1266 = sub(UInt<8>("h00"), T_1261[0])
        node T_1267 = tail(T_1266, 1)
        node T_1269 = sub(UInt<8>("h00"), T_1261[1])
        node T_1270 = tail(T_1269, 1)
        wire T_1272 : UInt<8>[2]
        T_1272[0] <= T_1267
        T_1272[1] <= T_1270
        node T_1276 = cat(T_1272[1], T_1272[0])
        node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278)
        node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281)
        node T_1283 = or(T_1279, T_1282)
        node T_1284 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1286 = mux(T_1283, T_1284, UInt<16>("h00"))
        node T_1287 = mux(T_1257, T_1276, T_1286)
        xact.wmask_buffer[UInt<1>("h00")] <= T_1287
        node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
        wire T_1292 : UInt<3>[1]
        T_1292[0] <= UInt<3>("h03")
        node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type)
        node T_1297 = or(UInt<1>("h00"), T_1295)
        node T_1298 = and(T_1289, T_1297)
        collect_iacq_data <= T_1298
        wire T_1303 : UInt<3>[3]
        T_1303[0] <= UInt<3>("h02")
        T_1303[1] <= UInt<3>("h03")
        T_1303[2] <= UInt<3>("h04")
        node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type)
        node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type)
        node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type)
        node T_1312 = or(UInt<1>("h00"), T_1308)
        node T_1313 = or(T_1312, T_1309)
        node T_1314 = or(T_1313, T_1310)
        node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314)
        node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat)
        iacq_data_valid <= T_1316
        node T_1318 = neq(mask_incoherent, UInt<1>("h00"))
        when T_1318 :
          pending_probes <= mask_incoherent
          node T_1319 = bits(mask_incoherent, 0, 0)
          node T_1320 = bits(mask_incoherent, 1, 1)
          node T_1321 = bits(mask_incoherent, 2, 2)
          node T_1322 = bits(mask_incoherent, 3, 3)
          node T_1324 = cat(UInt<1>("h00"), T_1320)
          node T_1325 = add(T_1319, T_1324)
          node T_1326 = tail(T_1325, 1)
          node T_1329 = cat(UInt<1>("h00"), T_1322)
          node T_1330 = add(T_1321, T_1329)
          node T_1331 = tail(T_1330, 1)
          node T_1332 = cat(UInt<1>("h00"), T_1331)
          node T_1333 = add(T_1326, T_1332)
          node T_1334 = tail(T_1333, 1)
          release_count <= T_1334
          skip
        node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04"))
        node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335)
        node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336)
        state <= T_1337
        skip
      skip
    node T_1338 = eq(UInt<1>("h01"), state)
    when T_1338 :
      node T_1340 = neq(pending_probes, UInt<1>("h00"))
      io.inner.probe.valid <= T_1340
      when io.inner.probe.ready :
        node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00"))
        node T_1343 = not(T_1342)
        node T_1344 = and(pending_probes, T_1343)
        pending_probes <= T_1344
        skip
      wire T_1346 : UInt<2>[3]
      T_1346[0] <= UInt<1>("h00")
      T_1346[1] <= UInt<1>("h01")
      T_1346[2] <= UInt<2>("h02")
      node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type)
      node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type)
      node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type)
      node T_1355 = or(UInt<1>("h00"), T_1351)
      node T_1356 = or(T_1355, T_1352)
      node T_1357 = or(T_1356, T_1353)
      node T_1359 = eq(T_1357, UInt<1>("h00"))
      node T_1360 = or(T_1359, io.outer.acquire.ready)
      io.inner.release.ready <= T_1360
      when io.inner.release.valid :
        wire T_1362 : UInt<2>[3]
        T_1362[0] <= UInt<1>("h00")
        T_1362[1] <= UInt<1>("h01")
        T_1362[2] <= UInt<2>("h02")
        node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type)
        node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type)
        node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type)
        node T_1371 = or(UInt<1>("h00"), T_1367)
        node T_1372 = or(T_1371, T_1368)
        node T_1373 = or(T_1372, T_1369)
        when T_1373 :
          io.outer.acquire.valid <= UInt<1>("h01")
          when io.outer.acquire.ready :
            when oacq_data_done :
              pending_ognt_ack <= UInt<1>("h01")
              node T_1377 = sub(release_count, UInt<1>("h01"))
              node T_1378 = tail(T_1377, 1)
              release_count <= T_1378
              node T_1380 = eq(release_count, UInt<1>("h01"))
              when T_1380 :
                node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
                node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381)
                state <= T_1382
                skip
              skip
            skip
          skip
        node T_1384 = eq(T_1373, UInt<1>("h00"))
        when T_1384 :
          node T_1386 = sub(release_count, UInt<1>("h01"))
          node T_1387 = tail(T_1386, 1)
          release_count <= T_1387
          node T_1389 = eq(release_count, UInt<1>("h01"))
          when T_1389 :
            node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
            node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390)
            state <= T_1391
            skip
          skip
        skip
      skip
    node T_1392 = eq(UInt<2>("h03"), state)
    when T_1392 :
      node T_1394 = eq(pending_ognt_ack, UInt<1>("h00"))
      node T_1396 = eq(collect_iacq_data, UInt<1>("h00"))
      node T_1397 = dshr(iacq_data_valid, oacq_data_cnt)
      node T_1398 = bits(T_1397, 0, 0)
      node T_1399 = or(T_1396, T_1398)
      node T_1400 = and(T_1394, T_1399)
      io.outer.acquire.valid <= T_1400
      when oacq_data_done :
        pending_ognt_ack <= UInt<1>("h01")
        node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05"))
        state <= T_1402
        skip
      skip
    node T_1403 = eq(UInt<2>("h02"), state)
    when T_1403 :
      node T_1405 = eq(pending_ognt_ack, UInt<1>("h00"))
      io.outer.acquire.valid <= T_1405
      node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid)
      when T_1406 :
        state <= UInt<3>("h05")
        skip
      skip
    node T_1407 = eq(UInt<3>("h05"), state)
    when T_1407 :
      io.outer.grant.ready <= io.inner.grant.ready
      io.inner.grant.valid <= io.outer.grant.valid
      when ignt_data_done :
        node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412)
        node T_1415 = eq(T_1413, UInt<1>("h00"))
        node T_1416 = and(T_1410, T_1415)
        node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1417
        skip
      skip
    node T_1418 = eq(UInt<3>("h04"), state)
    when T_1418 :
      io.inner.grant.valid <= UInt<1>("h01")
      when io.inner.grant.ready :
        node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424)
        node T_1427 = eq(T_1425, UInt<1>("h00"))
        node T_1428 = and(T_1422, T_1427)
        node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1429
        skip
      skip
    node T_1430 = eq(UInt<3>("h06"), state)
    when T_1430 :
      io.inner.finish.ready <= UInt<1>("h01")
      when io.inner.finish.valid :
        state <= UInt<1>("h00")
        skip
      skip
    
  module BroadcastAcquireTracker_29 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
    wire coh : {sharers : UInt<1>}
    coh is invalid
    coh.sharers <= UInt<1>("h00")
    node T_303 = neq(state, UInt<1>("h00"))
    node T_304 = and(T_303, xact.is_builtin_type)
    wire T_309 : UInt<3>[3]
    T_309[0] <= UInt<3>("h04")
    T_309[1] <= UInt<3>("h05")
    T_309[2] <= UInt<3>("h06")
    node T_314 = eq(T_309[0], xact.a_type)
    node T_315 = eq(T_309[1], xact.a_type)
    node T_316 = eq(T_309[2], xact.a_type)
    node T_318 = or(UInt<1>("h00"), T_314)
    node T_319 = or(T_318, T_315)
    node T_320 = or(T_319, T_316)
    node T_321 = and(T_304, T_320)
    node T_323 = eq(T_321, UInt<1>("h00"))
    node T_325 = eq(reset, UInt<1>("h00"))
    when T_325 :
      node T_327 = eq(T_323, UInt<1>("h00"))
      when T_327 :
        node T_329 = eq(reset, UInt<1>("h00"))
        when T_329 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_334 = bits(pending_probes, 0, 0)
    wire T_336 : UInt<1>[1]
    T_336[0] <= T_334
    node T_341 = asUInt(asSInt(UInt<1>("h01")))
    node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id)
    node T_345 = or(T_341, T_344)
    node T_346 = not(T_341)
    node T_347 = or(T_346, T_344)
    node T_348 = not(T_347)
    node mask_self = mux(UInt<1>("h00"), T_345, T_348)
    node T_350 = not(io.incoherent[0])
    node mask_incoherent = and(mask_self, T_350)
    reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_362 : UInt<3>[1]
    T_362[0] <= UInt<3>("h03")
    node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type)
    node T_367 = or(UInt<1>("h00"), T_365)
    node T_368 = and(T_359, T_367)
    node T_369 = and(T_356, T_368)
    reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_369 :
      node T_373 = eq(T_371, UInt<2>("h03"))
      node T_375 = and(UInt<1>("h00"), T_373)
      node T_378 = add(T_371, UInt<1>("h01"))
      node T_379 = tail(T_378, 1)
      node T_380 = mux(T_375, UInt<1>("h00"), T_379)
      T_371 <= T_380
      skip
    node T_381 = and(T_369, T_373)
    node T_382 = mux(T_368, T_371, UInt<1>("h00"))
    node iacq_data_done = mux(T_368, T_381, T_356)
    node T_384 = and(io.inner.release.ready, io.inner.release.valid)
    wire T_388 : UInt<2>[3]
    T_388[0] <= UInt<1>("h00")
    T_388[1] <= UInt<1>("h01")
    T_388[2] <= UInt<2>("h02")
    node T_393 = eq(T_388[0], io.inner.release.bits.r_type)
    node T_394 = eq(T_388[1], io.inner.release.bits.r_type)
    node T_395 = eq(T_388[2], io.inner.release.bits.r_type)
    node T_397 = or(UInt<1>("h00"), T_393)
    node T_398 = or(T_397, T_394)
    node T_399 = or(T_398, T_395)
    node T_400 = and(UInt<1>("h01"), T_399)
    node T_401 = and(T_384, T_400)
    reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_401 :
      node T_405 = eq(T_403, UInt<2>("h03"))
      node T_407 = and(UInt<1>("h00"), T_405)
      node T_410 = add(T_403, UInt<1>("h01"))
      node T_411 = tail(T_410, 1)
      node T_412 = mux(T_407, UInt<1>("h00"), T_411)
      T_403 <= T_412
      skip
    node T_413 = and(T_401, T_405)
    node T_414 = mux(T_400, T_403, UInt<1>("h00"))
    node irel_data_done = mux(T_400, T_413, T_384)
    node T_417 = and(io.inner.grant.ready, io.inner.grant.valid)
    wire T_421 : UInt<3>[1]
    T_421[0] <= UInt<3>("h05")
    node T_424 = eq(T_421[0], io.inner.grant.bits.g_type)
    node T_426 = or(UInt<1>("h00"), T_424)
    wire T_428 : UInt<1>[2]
    T_428[0] <= UInt<1>("h00")
    T_428[1] <= UInt<1>("h01")
    node T_432 = eq(T_428[0], io.inner.grant.bits.g_type)
    node T_433 = eq(T_428[1], io.inner.grant.bits.g_type)
    node T_435 = or(UInt<1>("h00"), T_432)
    node T_436 = or(T_435, T_433)
    node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436)
    node T_438 = and(UInt<1>("h01"), T_437)
    node T_439 = and(T_417, T_438)
    reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_439 :
      node T_443 = eq(T_441, UInt<2>("h03"))
      node T_445 = and(UInt<1>("h00"), T_443)
      node T_448 = add(T_441, UInt<1>("h01"))
      node T_449 = tail(T_448, 1)
      node T_450 = mux(T_445, UInt<1>("h00"), T_449)
      T_441 <= T_450
      skip
    node T_451 = and(T_439, T_443)
    node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00"))
    node ignt_data_done = mux(T_438, T_451, T_417)
    node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type)
    wire T_460 : UInt<3>[1]
    T_460[0] <= UInt<3>("h03")
    node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type)
    node T_465 = or(UInt<1>("h00"), T_463)
    node T_466 = and(T_457, T_465)
    node T_467 = and(T_455, T_466)
    reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_467 :
      node T_471 = eq(T_469, UInt<2>("h03"))
      node T_473 = and(UInt<1>("h00"), T_471)
      node T_476 = add(T_469, UInt<1>("h01"))
      node T_477 = tail(T_476, 1)
      node T_478 = mux(T_473, UInt<1>("h00"), T_477)
      T_469 <= T_478
      skip
    node T_479 = and(T_467, T_471)
    node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00"))
    node oacq_data_done = mux(T_466, T_479, T_455)
    node T_482 = and(io.outer.grant.ready, io.outer.grant.valid)
    wire T_487 : UInt<3>[1]
    T_487[0] <= UInt<3>("h05")
    node T_490 = eq(T_487[0], io.outer.grant.bits.g_type)
    node T_492 = or(UInt<1>("h00"), T_490)
    wire T_494 : UInt<1>[1]
    T_494[0] <= UInt<1>("h00")
    node T_497 = eq(T_494[0], io.outer.grant.bits.g_type)
    node T_499 = or(UInt<1>("h00"), T_497)
    node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499)
    node T_501 = and(UInt<1>("h01"), T_500)
    node T_502 = and(T_482, T_501)
    reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_502 :
      node T_506 = eq(T_504, UInt<2>("h03"))
      node T_508 = and(UInt<1>("h00"), T_506)
      node T_511 = add(T_504, UInt<1>("h01"))
      node T_512 = tail(T_511, 1)
      node T_513 = mux(T_508, UInt<1>("h00"), T_512)
      T_504 <= T_513
      skip
    node T_514 = and(T_502, T_506)
    node T_515 = mux(T_501, T_504, UInt<1>("h00"))
    node ognt_data_done = mux(T_501, T_514, T_482)
    reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_523 : UInt<3>[3]
    T_523[0] <= UInt<3>("h02")
    T_523[1] <= UInt<3>("h03")
    T_523[2] <= UInt<3>("h04")
    node T_528 = eq(T_523[0], xact.a_type)
    node T_529 = eq(T_523[1], xact.a_type)
    node T_530 = eq(T_523[2], xact.a_type)
    node T_532 = or(UInt<1>("h00"), T_528)
    node T_533 = or(T_532, T_529)
    node T_534 = or(T_533, T_530)
    node pending_outer_write = and(xact.is_builtin_type, T_534)
    wire T_540 : UInt<3>[3]
    T_540[0] <= UInt<3>("h02")
    T_540[1] <= UInt<3>("h03")
    T_540[2] <= UInt<3>("h04")
    node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type)
    node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type)
    node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type)
    node T_549 = or(UInt<1>("h00"), T_545)
    node T_550 = or(T_549, T_546)
    node T_551 = or(T_550, T_547)
    node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551)
    wire T_556 : UInt<3>[2]
    T_556[0] <= UInt<3>("h05")
    T_556[1] <= UInt<3>("h04")
    node T_560 = eq(T_556[0], io.inner.grant.bits.g_type)
    node T_561 = eq(T_556[1], io.inner.grant.bits.g_type)
    node T_563 = or(UInt<1>("h00"), T_560)
    node T_564 = or(T_563, T_561)
    wire T_566 : UInt<1>[2]
    T_566[0] <= UInt<1>("h00")
    T_566[1] <= UInt<1>("h01")
    node T_570 = eq(T_566[0], io.inner.grant.bits.g_type)
    node T_571 = eq(T_566[1], io.inner.grant.bits.g_type)
    node T_573 = or(UInt<1>("h00"), T_570)
    node T_574 = or(T_573, T_571)
    node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574)
    node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type)
    node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03"))
    node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type)
    node T_597 = mux(T_596, UInt<3>("h01"), T_595)
    node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type)
    node T_599 = mux(T_598, UInt<3>("h04"), T_597)
    node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type)
    node T_601 = mux(T_600, UInt<3>("h03"), T_599)
    node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type)
    node T_603 = mux(T_602, UInt<3>("h03"), T_601)
    node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type)
    node T_605 = mux(T_604, UInt<3>("h05"), T_603)
    node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type)
    node T_607 = mux(T_606, UInt<3>("h04"), T_605)
    node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00"))
    node T_611 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01"))
    node T_613 = mux(T_608, T_612, UInt<1>("h01"))
    node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613)
    wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_623 is invalid
    T_623.client_id <= io.inner.acquire.bits.client_id
    T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type
    T_623.g_type <= T_614
    T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id
    T_623.manager_xact_id <= UInt<3>("h04")
    T_623.addr_beat <= UInt<1>("h00")
    T_623.data <= UInt<1>("h00")
    wire T_634 : UInt<3>[2]
    T_634[0] <= UInt<3>("h05")
    T_634[1] <= UInt<3>("h04")
    node T_638 = eq(T_634[0], T_623.g_type)
    node T_639 = eq(T_634[1], T_623.g_type)
    node T_641 = or(UInt<1>("h00"), T_638)
    node T_642 = or(T_641, T_639)
    wire T_644 : UInt<1>[2]
    T_644[0] <= UInt<1>("h00")
    T_644[1] <= UInt<1>("h01")
    node T_648 = eq(T_644[0], T_623.g_type)
    node T_649 = eq(T_644[1], T_623.g_type)
    node T_651 = or(UInt<1>("h00"), T_648)
    node T_652 = or(T_651, T_649)
    node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652)
    wire T_658 : UInt<3>[3]
    T_658[0] <= UInt<3>("h02")
    T_658[1] <= UInt<3>("h00")
    T_658[2] <= UInt<3>("h04")
    node T_663 = eq(T_658[0], xact.a_type)
    node T_664 = eq(T_658[1], xact.a_type)
    node T_665 = eq(T_658[2], xact.a_type)
    node T_667 = or(UInt<1>("h00"), T_663)
    node T_668 = or(T_667, T_664)
    node T_669 = or(T_668, T_665)
    node subblock_type = and(xact.is_builtin_type, T_669)
    node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_672 = neq(state, UInt<1>("h00"))
    node T_673 = and(T_671, T_672)
    node T_675 = eq(collect_iacq_data, UInt<1>("h00"))
    node T_676 = and(T_673, T_675)
    io.has_acquire_conflict <= T_676
    node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_678 = and(T_677, collect_iacq_data)
    io.has_acquire_match <= T_678
    node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block)
    node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00"))
    node T_682 = and(T_679, T_681)
    node T_683 = eq(state, UInt<1>("h01"))
    node T_684 = and(T_682, T_683)
    io.has_release_match <= T_684
    node T_689 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_695 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_696 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_697 = cat(T_695, T_696)
    node T_699 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_700 = cat(UInt<3>("h07"), T_699)
    node T_702 = cat(T_689, UInt<1>("h01"))
    node T_704 = cat(T_689, UInt<1>("h01"))
    node T_706 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_707 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_708 = cat(T_706, T_707)
    node T_710 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_712 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_713 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_714 = mux(T_713, T_712, UInt<1>("h00"))
    node T_715 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_716 = mux(T_715, T_710, T_714)
    node T_717 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_718 = mux(T_717, T_708, T_716)
    node T_719 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_720 = mux(T_719, T_704, T_718)
    node T_721 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_722 = mux(T_721, T_702, T_720)
    node T_723 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_724 = mux(T_723, T_700, T_722)
    node T_725 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_726 = mux(T_725, T_697, T_724)
    wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_probe is invalid
    oacq_probe.is_builtin_type <= UInt<1>("h01")
    oacq_probe.a_type <= UInt<3>("h03")
    oacq_probe.client_xact_id <= UInt<3>("h04")
    oacq_probe.addr_block <= io.inner.release.bits.addr_block
    oacq_probe.addr_beat <= io.inner.release.bits.addr_beat
    oacq_probe.data <= io.inner.release.bits.data
    oacq_probe.union <= T_726
    node T_744 = bits(xact.union, 12, 9)
    node T_745 = bits(T_744, 3, 3)
    node T_747 = dshl(UInt<1>("h01"), T_745)
    node T_749 = eq(xact.a_type, UInt<3>("h04"))
    node T_750 = and(xact.is_builtin_type, T_749)
    node T_751 = bits(T_747, 0, 0)
    node T_752 = bits(T_747, 1, 1)
    wire T_754 : UInt<1>[2]
    T_754[0] <= T_751
    T_754[1] <= T_752
    node T_759 = sub(UInt<8>("h00"), T_754[0])
    node T_760 = tail(T_759, 1)
    node T_762 = sub(UInt<8>("h00"), T_754[1])
    node T_763 = tail(T_762, 1)
    wire T_765 : UInt<8>[2]
    T_765[0] <= T_760
    T_765[1] <= T_763
    node T_769 = cat(T_765[1], T_765[0])
    node T_771 = eq(xact.a_type, UInt<3>("h03"))
    node T_772 = and(xact.is_builtin_type, T_771)
    node T_774 = eq(xact.a_type, UInt<3>("h02"))
    node T_775 = and(xact.is_builtin_type, T_774)
    node T_776 = or(T_772, T_775)
    node T_777 = bits(xact.union, 16, 1)
    node T_779 = mux(T_776, T_777, UInt<16>("h00"))
    node T_780 = mux(T_750, T_769, T_779)
    node T_788 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_789 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_790 = cat(T_788, T_789)
    node T_792 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_793 = cat(UInt<3>("h07"), T_792)
    node T_795 = cat(T_780, UInt<1>("h01"))
    node T_797 = cat(T_780, UInt<1>("h01"))
    node T_799 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_800 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_801 = cat(T_799, T_800)
    node T_803 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_805 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_806 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_807 = mux(T_806, T_805, UInt<1>("h00"))
    node T_808 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_809 = mux(T_808, T_803, T_807)
    node T_810 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_811 = mux(T_810, T_801, T_809)
    node T_812 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_813 = mux(T_812, T_797, T_811)
    node T_814 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_815 = mux(T_814, T_795, T_813)
    node T_816 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_817 = mux(T_816, T_793, T_815)
    node T_818 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_819 = mux(T_818, T_790, T_817)
    wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_beat is invalid
    oacq_write_beat.is_builtin_type <= UInt<1>("h01")
    oacq_write_beat.a_type <= UInt<3>("h02")
    oacq_write_beat.client_xact_id <= UInt<3>("h04")
    oacq_write_beat.addr_block <= xact.addr_block
    oacq_write_beat.addr_beat <= xact.addr_beat
    oacq_write_beat.data <= xact.data_buffer[0]
    oacq_write_beat.union <= T_819
    node T_846 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_847 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_848 = cat(T_846, T_847)
    node T_850 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_851 = cat(UInt<3>("h07"), T_850)
    node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_857 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_858 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_859 = cat(T_857, T_858)
    node T_861 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_863 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_864 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_865 = mux(T_864, T_863, UInt<1>("h00"))
    node T_866 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_867 = mux(T_866, T_861, T_865)
    node T_868 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_869 = mux(T_868, T_859, T_867)
    node T_870 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_871 = mux(T_870, T_855, T_869)
    node T_872 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_873 = mux(T_872, T_853, T_871)
    node T_874 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_875 = mux(T_874, T_851, T_873)
    node T_876 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_877 = mux(T_876, T_848, T_875)
    wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_block is invalid
    oacq_write_block.is_builtin_type <= UInt<1>("h01")
    oacq_write_block.a_type <= UInt<3>("h03")
    oacq_write_block.client_xact_id <= UInt<3>("h04")
    oacq_write_block.addr_block <= xact.addr_block
    oacq_write_block.addr_beat <= oacq_data_cnt
    oacq_write_block.data <= xact.data_buffer[oacq_data_cnt]
    oacq_write_block.union <= T_877
    node T_895 = bits(xact.union, 12, 9)
    node T_896 = bits(xact.union, 8, 6)
    node T_904 = cat(T_895, T_896)
    node T_905 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_906 = cat(T_904, T_905)
    node T_908 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_909 = cat(T_896, T_908)
    node T_911 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_913 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_915 = cat(T_895, T_896)
    node T_916 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_917 = cat(T_915, T_916)
    node T_919 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_921 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_922 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_923 = mux(T_922, T_921, UInt<1>("h00"))
    node T_924 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_925 = mux(T_924, T_919, T_923)
    node T_926 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_927 = mux(T_926, T_917, T_925)
    node T_928 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_929 = mux(T_928, T_913, T_927)
    node T_930 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_931 = mux(T_930, T_911, T_929)
    node T_932 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_933 = mux(T_932, T_909, T_931)
    node T_934 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_935 = mux(T_934, T_906, T_933)
    wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_beat is invalid
    oacq_read_beat.is_builtin_type <= UInt<1>("h01")
    oacq_read_beat.a_type <= UInt<3>("h00")
    oacq_read_beat.client_xact_id <= UInt<3>("h04")
    oacq_read_beat.addr_block <= xact.addr_block
    oacq_read_beat.addr_beat <= xact.addr_beat
    oacq_read_beat.data <= UInt<1>("h00")
    oacq_read_beat.union <= T_935
    node T_962 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_963 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_964 = cat(T_962, T_963)
    node T_966 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_967 = cat(UInt<3>("h07"), T_966)
    node T_969 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_971 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_973 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_974 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_975 = cat(T_973, T_974)
    node T_977 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_979 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_980 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_981 = mux(T_980, T_979, UInt<1>("h00"))
    node T_982 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_983 = mux(T_982, T_977, T_981)
    node T_984 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_985 = mux(T_984, T_975, T_983)
    node T_986 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_987 = mux(T_986, T_971, T_985)
    node T_988 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_989 = mux(T_988, T_969, T_987)
    node T_990 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_991 = mux(T_990, T_967, T_989)
    node T_992 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_993 = mux(T_992, T_964, T_991)
    wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_block is invalid
    oacq_read_block.is_builtin_type <= UInt<1>("h01")
    oacq_read_block.a_type <= UInt<3>("h01")
    oacq_read_block.client_xact_id <= UInt<3>("h04")
    oacq_read_block.addr_block <= xact.addr_block
    oacq_read_block.addr_beat <= UInt<1>("h00")
    oacq_read_block.data <= UInt<1>("h00")
    oacq_read_block.union <= T_993
    io.outer.acquire.valid <= UInt<1>("h00")
    node T_1011 = eq(state, UInt<1>("h01"))
    node T_1012 = eq(state, UInt<2>("h03"))
    node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block)
    node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block)
    node T_1029 = mux(T_1012, T_1013, T_1021)
    node T_1037 = mux(T_1011, oacq_probe, T_1029)
    io.outer.acquire.bits <- T_1037
    io.outer.grant.ready <= UInt<1>("h00")
    io.inner.probe.valid <= UInt<1>("h00")
    node T_1054 = eq(UInt<3>("h04"), xact.a_type)
    node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02"))
    node T_1056 = eq(UInt<3>("h06"), xact.a_type)
    node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055)
    node T_1058 = eq(UInt<3>("h05"), xact.a_type)
    node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057)
    node T_1060 = eq(UInt<3>("h02"), xact.a_type)
    node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059)
    node T_1062 = eq(UInt<3>("h00"), xact.a_type)
    node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061)
    node T_1064 = eq(UInt<3>("h03"), xact.a_type)
    node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063)
    node T_1066 = eq(UInt<3>("h01"), xact.a_type)
    node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065)
    node T_1068 = eq(UInt<1>("h01"), xact.a_type)
    node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02"))
    node T_1070 = eq(UInt<1>("h00"), xact.a_type)
    node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069)
    node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071)
    wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_1077 is invalid
    T_1077.client_id <= UInt<1>("h00")
    T_1077.p_type <= T_1072
    T_1077.addr_block <= xact.addr_block
    io.inner.probe.bits <- T_1077
    io.inner.grant.valid <= UInt<1>("h00")
    node T_1100 = eq(UInt<3>("h06"), xact.a_type)
    node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03"))
    node T_1102 = eq(UInt<3>("h05"), xact.a_type)
    node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101)
    node T_1104 = eq(UInt<3>("h04"), xact.a_type)
    node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103)
    node T_1106 = eq(UInt<3>("h03"), xact.a_type)
    node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105)
    node T_1108 = eq(UInt<3>("h02"), xact.a_type)
    node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107)
    node T_1110 = eq(UInt<3>("h01"), xact.a_type)
    node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109)
    node T_1112 = eq(UInt<3>("h00"), xact.a_type)
    node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111)
    node T_1114 = eq(xact.a_type, UInt<1>("h00"))
    node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01"))
    node T_1119 = mux(T_1114, T_1118, UInt<1>("h01"))
    node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119)
    wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_1129 is invalid
    T_1129.client_id <= xact.client_id
    T_1129.is_builtin_type <= xact.is_builtin_type
    T_1129.g_type <= T_1120
    T_1129.client_xact_id <= xact.client_xact_id
    T_1129.manager_xact_id <= UInt<3>("h04")
    T_1129.addr_beat <= UInt<1>("h00")
    T_1129.data <= UInt<1>("h00")
    io.inner.grant.bits <- T_1129
    io.inner.acquire.ready <= UInt<1>("h00")
    io.inner.release.ready <= UInt<1>("h00")
    io.inner.finish.ready <= UInt<1>("h00")
    node T_1140 = neq(state, UInt<1>("h00"))
    node T_1141 = and(T_1140, collect_iacq_data)
    node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1143 = and(T_1141, T_1142)
    node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id)
    node T_1145 = and(T_1143, T_1144)
    node T_1147 = eq(T_1145, UInt<1>("h00"))
    node T_1149 = eq(reset, UInt<1>("h00"))
    when T_1149 :
      node T_1151 = eq(T_1147, UInt<1>("h00"))
      when T_1151 :
        node T_1153 = eq(reset, UInt<1>("h00"))
        when T_1153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1154 = neq(state, UInt<1>("h00"))
    node T_1155 = and(T_1154, collect_iacq_data)
    node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1157 = and(T_1155, T_1156)
    node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id)
    node T_1159 = and(T_1157, T_1158)
    node T_1161 = eq(T_1159, UInt<1>("h00"))
    node T_1163 = eq(reset, UInt<1>("h00"))
    when T_1163 :
      node T_1165 = eq(T_1161, UInt<1>("h00"))
      when T_1165 :
        node T_1167 = eq(reset, UInt<1>("h00"))
        when T_1167 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1168 = eq(state, UInt<1>("h00"))
    node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1170 = and(T_1168, T_1169)
    node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_1175 : UInt<3>[1]
    T_1175[0] <= UInt<3>("h03")
    node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type)
    node T_1180 = or(UInt<1>("h00"), T_1178)
    node T_1181 = and(T_1172, T_1180)
    node T_1182 = and(T_1170, T_1181)
    node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00"))
    node T_1185 = and(T_1182, T_1184)
    node T_1187 = eq(T_1185, UInt<1>("h00"))
    node T_1189 = eq(reset, UInt<1>("h00"))
    when T_1189 :
      node T_1191 = eq(T_1187, UInt<1>("h00"))
      when T_1191 :
        node T_1193 = eq(reset, UInt<1>("h00"))
        when T_1193 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    when collect_iacq_data :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data
        node T_1197 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1198 = bits(T_1197, 3, 3)
        node T_1200 = dshl(UInt<1>("h01"), T_1198)
        node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202)
        node T_1204 = bits(T_1200, 0, 0)
        node T_1205 = bits(T_1200, 1, 1)
        wire T_1207 : UInt<1>[2]
        T_1207[0] <= T_1204
        T_1207[1] <= T_1205
        node T_1212 = sub(UInt<8>("h00"), T_1207[0])
        node T_1213 = tail(T_1212, 1)
        node T_1215 = sub(UInt<8>("h00"), T_1207[1])
        node T_1216 = tail(T_1215, 1)
        wire T_1218 : UInt<8>[2]
        T_1218[0] <= T_1213
        T_1218[1] <= T_1216
        node T_1222 = cat(T_1218[1], T_1218[0])
        node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224)
        node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227)
        node T_1229 = or(T_1225, T_1228)
        node T_1230 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1232 = mux(T_1229, T_1230, UInt<16>("h00"))
        node T_1233 = mux(T_1203, T_1222, T_1232)
        xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233
        node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat)
        node T_1237 = or(iacq_data_valid, T_1236)
        node T_1238 = not(iacq_data_valid)
        node T_1239 = or(T_1238, T_1236)
        node T_1240 = not(T_1239)
        node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240)
        iacq_data_valid <= T_1241
        skip
      when iacq_data_done :
        collect_iacq_data <= UInt<1>("h00")
        skip
      skip
    when pending_ognt_ack :
      io.outer.grant.ready <= UInt<1>("h01")
      when io.outer.grant.valid :
        pending_ognt_ack <= UInt<1>("h00")
        skip
      skip
    node T_1245 = eq(UInt<1>("h00"), state)
    when T_1245 :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact <- io.inner.acquire.bits
        xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data
        node T_1251 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1252 = bits(T_1251, 3, 3)
        node T_1254 = dshl(UInt<1>("h01"), T_1252)
        node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256)
        node T_1258 = bits(T_1254, 0, 0)
        node T_1259 = bits(T_1254, 1, 1)
        wire T_1261 : UInt<1>[2]
        T_1261[0] <= T_1258
        T_1261[1] <= T_1259
        node T_1266 = sub(UInt<8>("h00"), T_1261[0])
        node T_1267 = tail(T_1266, 1)
        node T_1269 = sub(UInt<8>("h00"), T_1261[1])
        node T_1270 = tail(T_1269, 1)
        wire T_1272 : UInt<8>[2]
        T_1272[0] <= T_1267
        T_1272[1] <= T_1270
        node T_1276 = cat(T_1272[1], T_1272[0])
        node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278)
        node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281)
        node T_1283 = or(T_1279, T_1282)
        node T_1284 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1286 = mux(T_1283, T_1284, UInt<16>("h00"))
        node T_1287 = mux(T_1257, T_1276, T_1286)
        xact.wmask_buffer[UInt<1>("h00")] <= T_1287
        node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
        wire T_1292 : UInt<3>[1]
        T_1292[0] <= UInt<3>("h03")
        node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type)
        node T_1297 = or(UInt<1>("h00"), T_1295)
        node T_1298 = and(T_1289, T_1297)
        collect_iacq_data <= T_1298
        wire T_1303 : UInt<3>[3]
        T_1303[0] <= UInt<3>("h02")
        T_1303[1] <= UInt<3>("h03")
        T_1303[2] <= UInt<3>("h04")
        node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type)
        node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type)
        node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type)
        node T_1312 = or(UInt<1>("h00"), T_1308)
        node T_1313 = or(T_1312, T_1309)
        node T_1314 = or(T_1313, T_1310)
        node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314)
        node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat)
        iacq_data_valid <= T_1316
        node T_1318 = neq(mask_incoherent, UInt<1>("h00"))
        when T_1318 :
          pending_probes <= mask_incoherent
          node T_1319 = bits(mask_incoherent, 0, 0)
          node T_1320 = bits(mask_incoherent, 1, 1)
          node T_1321 = bits(mask_incoherent, 2, 2)
          node T_1322 = bits(mask_incoherent, 3, 3)
          node T_1324 = cat(UInt<1>("h00"), T_1320)
          node T_1325 = add(T_1319, T_1324)
          node T_1326 = tail(T_1325, 1)
          node T_1329 = cat(UInt<1>("h00"), T_1322)
          node T_1330 = add(T_1321, T_1329)
          node T_1331 = tail(T_1330, 1)
          node T_1332 = cat(UInt<1>("h00"), T_1331)
          node T_1333 = add(T_1326, T_1332)
          node T_1334 = tail(T_1333, 1)
          release_count <= T_1334
          skip
        node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04"))
        node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335)
        node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336)
        state <= T_1337
        skip
      skip
    node T_1338 = eq(UInt<1>("h01"), state)
    when T_1338 :
      node T_1340 = neq(pending_probes, UInt<1>("h00"))
      io.inner.probe.valid <= T_1340
      when io.inner.probe.ready :
        node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00"))
        node T_1343 = not(T_1342)
        node T_1344 = and(pending_probes, T_1343)
        pending_probes <= T_1344
        skip
      wire T_1346 : UInt<2>[3]
      T_1346[0] <= UInt<1>("h00")
      T_1346[1] <= UInt<1>("h01")
      T_1346[2] <= UInt<2>("h02")
      node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type)
      node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type)
      node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type)
      node T_1355 = or(UInt<1>("h00"), T_1351)
      node T_1356 = or(T_1355, T_1352)
      node T_1357 = or(T_1356, T_1353)
      node T_1359 = eq(T_1357, UInt<1>("h00"))
      node T_1360 = or(T_1359, io.outer.acquire.ready)
      io.inner.release.ready <= T_1360
      when io.inner.release.valid :
        wire T_1362 : UInt<2>[3]
        T_1362[0] <= UInt<1>("h00")
        T_1362[1] <= UInt<1>("h01")
        T_1362[2] <= UInt<2>("h02")
        node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type)
        node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type)
        node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type)
        node T_1371 = or(UInt<1>("h00"), T_1367)
        node T_1372 = or(T_1371, T_1368)
        node T_1373 = or(T_1372, T_1369)
        when T_1373 :
          io.outer.acquire.valid <= UInt<1>("h01")
          when io.outer.acquire.ready :
            when oacq_data_done :
              pending_ognt_ack <= UInt<1>("h01")
              node T_1377 = sub(release_count, UInt<1>("h01"))
              node T_1378 = tail(T_1377, 1)
              release_count <= T_1378
              node T_1380 = eq(release_count, UInt<1>("h01"))
              when T_1380 :
                node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
                node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381)
                state <= T_1382
                skip
              skip
            skip
          skip
        node T_1384 = eq(T_1373, UInt<1>("h00"))
        when T_1384 :
          node T_1386 = sub(release_count, UInt<1>("h01"))
          node T_1387 = tail(T_1386, 1)
          release_count <= T_1387
          node T_1389 = eq(release_count, UInt<1>("h01"))
          when T_1389 :
            node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
            node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390)
            state <= T_1391
            skip
          skip
        skip
      skip
    node T_1392 = eq(UInt<2>("h03"), state)
    when T_1392 :
      node T_1394 = eq(pending_ognt_ack, UInt<1>("h00"))
      node T_1396 = eq(collect_iacq_data, UInt<1>("h00"))
      node T_1397 = dshr(iacq_data_valid, oacq_data_cnt)
      node T_1398 = bits(T_1397, 0, 0)
      node T_1399 = or(T_1396, T_1398)
      node T_1400 = and(T_1394, T_1399)
      io.outer.acquire.valid <= T_1400
      when oacq_data_done :
        pending_ognt_ack <= UInt<1>("h01")
        node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05"))
        state <= T_1402
        skip
      skip
    node T_1403 = eq(UInt<2>("h02"), state)
    when T_1403 :
      node T_1405 = eq(pending_ognt_ack, UInt<1>("h00"))
      io.outer.acquire.valid <= T_1405
      node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid)
      when T_1406 :
        state <= UInt<3>("h05")
        skip
      skip
    node T_1407 = eq(UInt<3>("h05"), state)
    when T_1407 :
      io.outer.grant.ready <= io.inner.grant.ready
      io.inner.grant.valid <= io.outer.grant.valid
      when ignt_data_done :
        node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412)
        node T_1415 = eq(T_1413, UInt<1>("h00"))
        node T_1416 = and(T_1410, T_1415)
        node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1417
        skip
      skip
    node T_1418 = eq(UInt<3>("h04"), state)
    when T_1418 :
      io.inner.grant.valid <= UInt<1>("h01")
      when io.inner.grant.ready :
        node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424)
        node T_1427 = eq(T_1425, UInt<1>("h00"))
        node T_1428 = and(T_1422, T_1427)
        node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1429
        skip
      skip
    node T_1430 = eq(UInt<3>("h06"), state)
    when T_1430 :
      io.inner.finish.ready <= UInt<1>("h01")
      when io.inner.finish.valid :
        state <= UInt<1>("h00")
        skip
      skip
    
  module BroadcastAcquireTracker_30 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
    wire coh : {sharers : UInt<1>}
    coh is invalid
    coh.sharers <= UInt<1>("h00")
    node T_303 = neq(state, UInt<1>("h00"))
    node T_304 = and(T_303, xact.is_builtin_type)
    wire T_309 : UInt<3>[3]
    T_309[0] <= UInt<3>("h04")
    T_309[1] <= UInt<3>("h05")
    T_309[2] <= UInt<3>("h06")
    node T_314 = eq(T_309[0], xact.a_type)
    node T_315 = eq(T_309[1], xact.a_type)
    node T_316 = eq(T_309[2], xact.a_type)
    node T_318 = or(UInt<1>("h00"), T_314)
    node T_319 = or(T_318, T_315)
    node T_320 = or(T_319, T_316)
    node T_321 = and(T_304, T_320)
    node T_323 = eq(T_321, UInt<1>("h00"))
    node T_325 = eq(reset, UInt<1>("h00"))
    when T_325 :
      node T_327 = eq(T_323, UInt<1>("h00"))
      when T_327 :
        node T_329 = eq(reset, UInt<1>("h00"))
        when T_329 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_334 = bits(pending_probes, 0, 0)
    wire T_336 : UInt<1>[1]
    T_336[0] <= T_334
    node T_341 = asUInt(asSInt(UInt<1>("h01")))
    node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id)
    node T_345 = or(T_341, T_344)
    node T_346 = not(T_341)
    node T_347 = or(T_346, T_344)
    node T_348 = not(T_347)
    node mask_self = mux(UInt<1>("h00"), T_345, T_348)
    node T_350 = not(io.incoherent[0])
    node mask_incoherent = and(mask_self, T_350)
    reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_362 : UInt<3>[1]
    T_362[0] <= UInt<3>("h03")
    node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type)
    node T_367 = or(UInt<1>("h00"), T_365)
    node T_368 = and(T_359, T_367)
    node T_369 = and(T_356, T_368)
    reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_369 :
      node T_373 = eq(T_371, UInt<2>("h03"))
      node T_375 = and(UInt<1>("h00"), T_373)
      node T_378 = add(T_371, UInt<1>("h01"))
      node T_379 = tail(T_378, 1)
      node T_380 = mux(T_375, UInt<1>("h00"), T_379)
      T_371 <= T_380
      skip
    node T_381 = and(T_369, T_373)
    node T_382 = mux(T_368, T_371, UInt<1>("h00"))
    node iacq_data_done = mux(T_368, T_381, T_356)
    node T_384 = and(io.inner.release.ready, io.inner.release.valid)
    wire T_388 : UInt<2>[3]
    T_388[0] <= UInt<1>("h00")
    T_388[1] <= UInt<1>("h01")
    T_388[2] <= UInt<2>("h02")
    node T_393 = eq(T_388[0], io.inner.release.bits.r_type)
    node T_394 = eq(T_388[1], io.inner.release.bits.r_type)
    node T_395 = eq(T_388[2], io.inner.release.bits.r_type)
    node T_397 = or(UInt<1>("h00"), T_393)
    node T_398 = or(T_397, T_394)
    node T_399 = or(T_398, T_395)
    node T_400 = and(UInt<1>("h01"), T_399)
    node T_401 = and(T_384, T_400)
    reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_401 :
      node T_405 = eq(T_403, UInt<2>("h03"))
      node T_407 = and(UInt<1>("h00"), T_405)
      node T_410 = add(T_403, UInt<1>("h01"))
      node T_411 = tail(T_410, 1)
      node T_412 = mux(T_407, UInt<1>("h00"), T_411)
      T_403 <= T_412
      skip
    node T_413 = and(T_401, T_405)
    node T_414 = mux(T_400, T_403, UInt<1>("h00"))
    node irel_data_done = mux(T_400, T_413, T_384)
    node T_417 = and(io.inner.grant.ready, io.inner.grant.valid)
    wire T_421 : UInt<3>[1]
    T_421[0] <= UInt<3>("h05")
    node T_424 = eq(T_421[0], io.inner.grant.bits.g_type)
    node T_426 = or(UInt<1>("h00"), T_424)
    wire T_428 : UInt<1>[2]
    T_428[0] <= UInt<1>("h00")
    T_428[1] <= UInt<1>("h01")
    node T_432 = eq(T_428[0], io.inner.grant.bits.g_type)
    node T_433 = eq(T_428[1], io.inner.grant.bits.g_type)
    node T_435 = or(UInt<1>("h00"), T_432)
    node T_436 = or(T_435, T_433)
    node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436)
    node T_438 = and(UInt<1>("h01"), T_437)
    node T_439 = and(T_417, T_438)
    reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_439 :
      node T_443 = eq(T_441, UInt<2>("h03"))
      node T_445 = and(UInt<1>("h00"), T_443)
      node T_448 = add(T_441, UInt<1>("h01"))
      node T_449 = tail(T_448, 1)
      node T_450 = mux(T_445, UInt<1>("h00"), T_449)
      T_441 <= T_450
      skip
    node T_451 = and(T_439, T_443)
    node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00"))
    node ignt_data_done = mux(T_438, T_451, T_417)
    node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type)
    wire T_460 : UInt<3>[1]
    T_460[0] <= UInt<3>("h03")
    node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type)
    node T_465 = or(UInt<1>("h00"), T_463)
    node T_466 = and(T_457, T_465)
    node T_467 = and(T_455, T_466)
    reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_467 :
      node T_471 = eq(T_469, UInt<2>("h03"))
      node T_473 = and(UInt<1>("h00"), T_471)
      node T_476 = add(T_469, UInt<1>("h01"))
      node T_477 = tail(T_476, 1)
      node T_478 = mux(T_473, UInt<1>("h00"), T_477)
      T_469 <= T_478
      skip
    node T_479 = and(T_467, T_471)
    node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00"))
    node oacq_data_done = mux(T_466, T_479, T_455)
    node T_482 = and(io.outer.grant.ready, io.outer.grant.valid)
    wire T_487 : UInt<3>[1]
    T_487[0] <= UInt<3>("h05")
    node T_490 = eq(T_487[0], io.outer.grant.bits.g_type)
    node T_492 = or(UInt<1>("h00"), T_490)
    wire T_494 : UInt<1>[1]
    T_494[0] <= UInt<1>("h00")
    node T_497 = eq(T_494[0], io.outer.grant.bits.g_type)
    node T_499 = or(UInt<1>("h00"), T_497)
    node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499)
    node T_501 = and(UInt<1>("h01"), T_500)
    node T_502 = and(T_482, T_501)
    reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_502 :
      node T_506 = eq(T_504, UInt<2>("h03"))
      node T_508 = and(UInt<1>("h00"), T_506)
      node T_511 = add(T_504, UInt<1>("h01"))
      node T_512 = tail(T_511, 1)
      node T_513 = mux(T_508, UInt<1>("h00"), T_512)
      T_504 <= T_513
      skip
    node T_514 = and(T_502, T_506)
    node T_515 = mux(T_501, T_504, UInt<1>("h00"))
    node ognt_data_done = mux(T_501, T_514, T_482)
    reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_523 : UInt<3>[3]
    T_523[0] <= UInt<3>("h02")
    T_523[1] <= UInt<3>("h03")
    T_523[2] <= UInt<3>("h04")
    node T_528 = eq(T_523[0], xact.a_type)
    node T_529 = eq(T_523[1], xact.a_type)
    node T_530 = eq(T_523[2], xact.a_type)
    node T_532 = or(UInt<1>("h00"), T_528)
    node T_533 = or(T_532, T_529)
    node T_534 = or(T_533, T_530)
    node pending_outer_write = and(xact.is_builtin_type, T_534)
    wire T_540 : UInt<3>[3]
    T_540[0] <= UInt<3>("h02")
    T_540[1] <= UInt<3>("h03")
    T_540[2] <= UInt<3>("h04")
    node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type)
    node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type)
    node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type)
    node T_549 = or(UInt<1>("h00"), T_545)
    node T_550 = or(T_549, T_546)
    node T_551 = or(T_550, T_547)
    node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551)
    wire T_556 : UInt<3>[2]
    T_556[0] <= UInt<3>("h05")
    T_556[1] <= UInt<3>("h04")
    node T_560 = eq(T_556[0], io.inner.grant.bits.g_type)
    node T_561 = eq(T_556[1], io.inner.grant.bits.g_type)
    node T_563 = or(UInt<1>("h00"), T_560)
    node T_564 = or(T_563, T_561)
    wire T_566 : UInt<1>[2]
    T_566[0] <= UInt<1>("h00")
    T_566[1] <= UInt<1>("h01")
    node T_570 = eq(T_566[0], io.inner.grant.bits.g_type)
    node T_571 = eq(T_566[1], io.inner.grant.bits.g_type)
    node T_573 = or(UInt<1>("h00"), T_570)
    node T_574 = or(T_573, T_571)
    node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574)
    node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type)
    node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03"))
    node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type)
    node T_597 = mux(T_596, UInt<3>("h01"), T_595)
    node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type)
    node T_599 = mux(T_598, UInt<3>("h04"), T_597)
    node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type)
    node T_601 = mux(T_600, UInt<3>("h03"), T_599)
    node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type)
    node T_603 = mux(T_602, UInt<3>("h03"), T_601)
    node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type)
    node T_605 = mux(T_604, UInt<3>("h05"), T_603)
    node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type)
    node T_607 = mux(T_606, UInt<3>("h04"), T_605)
    node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00"))
    node T_611 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01"))
    node T_613 = mux(T_608, T_612, UInt<1>("h01"))
    node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613)
    wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_623 is invalid
    T_623.client_id <= io.inner.acquire.bits.client_id
    T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type
    T_623.g_type <= T_614
    T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id
    T_623.manager_xact_id <= UInt<3>("h05")
    T_623.addr_beat <= UInt<1>("h00")
    T_623.data <= UInt<1>("h00")
    wire T_634 : UInt<3>[2]
    T_634[0] <= UInt<3>("h05")
    T_634[1] <= UInt<3>("h04")
    node T_638 = eq(T_634[0], T_623.g_type)
    node T_639 = eq(T_634[1], T_623.g_type)
    node T_641 = or(UInt<1>("h00"), T_638)
    node T_642 = or(T_641, T_639)
    wire T_644 : UInt<1>[2]
    T_644[0] <= UInt<1>("h00")
    T_644[1] <= UInt<1>("h01")
    node T_648 = eq(T_644[0], T_623.g_type)
    node T_649 = eq(T_644[1], T_623.g_type)
    node T_651 = or(UInt<1>("h00"), T_648)
    node T_652 = or(T_651, T_649)
    node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652)
    wire T_658 : UInt<3>[3]
    T_658[0] <= UInt<3>("h02")
    T_658[1] <= UInt<3>("h00")
    T_658[2] <= UInt<3>("h04")
    node T_663 = eq(T_658[0], xact.a_type)
    node T_664 = eq(T_658[1], xact.a_type)
    node T_665 = eq(T_658[2], xact.a_type)
    node T_667 = or(UInt<1>("h00"), T_663)
    node T_668 = or(T_667, T_664)
    node T_669 = or(T_668, T_665)
    node subblock_type = and(xact.is_builtin_type, T_669)
    node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_672 = neq(state, UInt<1>("h00"))
    node T_673 = and(T_671, T_672)
    node T_675 = eq(collect_iacq_data, UInt<1>("h00"))
    node T_676 = and(T_673, T_675)
    io.has_acquire_conflict <= T_676
    node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_678 = and(T_677, collect_iacq_data)
    io.has_acquire_match <= T_678
    node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block)
    node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00"))
    node T_682 = and(T_679, T_681)
    node T_683 = eq(state, UInt<1>("h01"))
    node T_684 = and(T_682, T_683)
    io.has_release_match <= T_684
    node T_689 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_695 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_696 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_697 = cat(T_695, T_696)
    node T_699 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_700 = cat(UInt<3>("h07"), T_699)
    node T_702 = cat(T_689, UInt<1>("h01"))
    node T_704 = cat(T_689, UInt<1>("h01"))
    node T_706 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_707 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_708 = cat(T_706, T_707)
    node T_710 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_712 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_713 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_714 = mux(T_713, T_712, UInt<1>("h00"))
    node T_715 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_716 = mux(T_715, T_710, T_714)
    node T_717 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_718 = mux(T_717, T_708, T_716)
    node T_719 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_720 = mux(T_719, T_704, T_718)
    node T_721 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_722 = mux(T_721, T_702, T_720)
    node T_723 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_724 = mux(T_723, T_700, T_722)
    node T_725 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_726 = mux(T_725, T_697, T_724)
    wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_probe is invalid
    oacq_probe.is_builtin_type <= UInt<1>("h01")
    oacq_probe.a_type <= UInt<3>("h03")
    oacq_probe.client_xact_id <= UInt<3>("h05")
    oacq_probe.addr_block <= io.inner.release.bits.addr_block
    oacq_probe.addr_beat <= io.inner.release.bits.addr_beat
    oacq_probe.data <= io.inner.release.bits.data
    oacq_probe.union <= T_726
    node T_744 = bits(xact.union, 12, 9)
    node T_745 = bits(T_744, 3, 3)
    node T_747 = dshl(UInt<1>("h01"), T_745)
    node T_749 = eq(xact.a_type, UInt<3>("h04"))
    node T_750 = and(xact.is_builtin_type, T_749)
    node T_751 = bits(T_747, 0, 0)
    node T_752 = bits(T_747, 1, 1)
    wire T_754 : UInt<1>[2]
    T_754[0] <= T_751
    T_754[1] <= T_752
    node T_759 = sub(UInt<8>("h00"), T_754[0])
    node T_760 = tail(T_759, 1)
    node T_762 = sub(UInt<8>("h00"), T_754[1])
    node T_763 = tail(T_762, 1)
    wire T_765 : UInt<8>[2]
    T_765[0] <= T_760
    T_765[1] <= T_763
    node T_769 = cat(T_765[1], T_765[0])
    node T_771 = eq(xact.a_type, UInt<3>("h03"))
    node T_772 = and(xact.is_builtin_type, T_771)
    node T_774 = eq(xact.a_type, UInt<3>("h02"))
    node T_775 = and(xact.is_builtin_type, T_774)
    node T_776 = or(T_772, T_775)
    node T_777 = bits(xact.union, 16, 1)
    node T_779 = mux(T_776, T_777, UInt<16>("h00"))
    node T_780 = mux(T_750, T_769, T_779)
    node T_788 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_789 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_790 = cat(T_788, T_789)
    node T_792 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_793 = cat(UInt<3>("h07"), T_792)
    node T_795 = cat(T_780, UInt<1>("h01"))
    node T_797 = cat(T_780, UInt<1>("h01"))
    node T_799 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_800 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_801 = cat(T_799, T_800)
    node T_803 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_805 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_806 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_807 = mux(T_806, T_805, UInt<1>("h00"))
    node T_808 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_809 = mux(T_808, T_803, T_807)
    node T_810 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_811 = mux(T_810, T_801, T_809)
    node T_812 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_813 = mux(T_812, T_797, T_811)
    node T_814 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_815 = mux(T_814, T_795, T_813)
    node T_816 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_817 = mux(T_816, T_793, T_815)
    node T_818 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_819 = mux(T_818, T_790, T_817)
    wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_beat is invalid
    oacq_write_beat.is_builtin_type <= UInt<1>("h01")
    oacq_write_beat.a_type <= UInt<3>("h02")
    oacq_write_beat.client_xact_id <= UInt<3>("h05")
    oacq_write_beat.addr_block <= xact.addr_block
    oacq_write_beat.addr_beat <= xact.addr_beat
    oacq_write_beat.data <= xact.data_buffer[0]
    oacq_write_beat.union <= T_819
    node T_846 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_847 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_848 = cat(T_846, T_847)
    node T_850 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_851 = cat(UInt<3>("h07"), T_850)
    node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_857 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_858 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_859 = cat(T_857, T_858)
    node T_861 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_863 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_864 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_865 = mux(T_864, T_863, UInt<1>("h00"))
    node T_866 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_867 = mux(T_866, T_861, T_865)
    node T_868 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_869 = mux(T_868, T_859, T_867)
    node T_870 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_871 = mux(T_870, T_855, T_869)
    node T_872 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_873 = mux(T_872, T_853, T_871)
    node T_874 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_875 = mux(T_874, T_851, T_873)
    node T_876 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_877 = mux(T_876, T_848, T_875)
    wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_block is invalid
    oacq_write_block.is_builtin_type <= UInt<1>("h01")
    oacq_write_block.a_type <= UInt<3>("h03")
    oacq_write_block.client_xact_id <= UInt<3>("h05")
    oacq_write_block.addr_block <= xact.addr_block
    oacq_write_block.addr_beat <= oacq_data_cnt
    oacq_write_block.data <= xact.data_buffer[oacq_data_cnt]
    oacq_write_block.union <= T_877
    node T_895 = bits(xact.union, 12, 9)
    node T_896 = bits(xact.union, 8, 6)
    node T_904 = cat(T_895, T_896)
    node T_905 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_906 = cat(T_904, T_905)
    node T_908 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_909 = cat(T_896, T_908)
    node T_911 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_913 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_915 = cat(T_895, T_896)
    node T_916 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_917 = cat(T_915, T_916)
    node T_919 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_921 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_922 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_923 = mux(T_922, T_921, UInt<1>("h00"))
    node T_924 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_925 = mux(T_924, T_919, T_923)
    node T_926 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_927 = mux(T_926, T_917, T_925)
    node T_928 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_929 = mux(T_928, T_913, T_927)
    node T_930 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_931 = mux(T_930, T_911, T_929)
    node T_932 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_933 = mux(T_932, T_909, T_931)
    node T_934 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_935 = mux(T_934, T_906, T_933)
    wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_beat is invalid
    oacq_read_beat.is_builtin_type <= UInt<1>("h01")
    oacq_read_beat.a_type <= UInt<3>("h00")
    oacq_read_beat.client_xact_id <= UInt<3>("h05")
    oacq_read_beat.addr_block <= xact.addr_block
    oacq_read_beat.addr_beat <= xact.addr_beat
    oacq_read_beat.data <= UInt<1>("h00")
    oacq_read_beat.union <= T_935
    node T_962 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_963 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_964 = cat(T_962, T_963)
    node T_966 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_967 = cat(UInt<3>("h07"), T_966)
    node T_969 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_971 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_973 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_974 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_975 = cat(T_973, T_974)
    node T_977 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_979 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_980 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_981 = mux(T_980, T_979, UInt<1>("h00"))
    node T_982 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_983 = mux(T_982, T_977, T_981)
    node T_984 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_985 = mux(T_984, T_975, T_983)
    node T_986 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_987 = mux(T_986, T_971, T_985)
    node T_988 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_989 = mux(T_988, T_969, T_987)
    node T_990 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_991 = mux(T_990, T_967, T_989)
    node T_992 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_993 = mux(T_992, T_964, T_991)
    wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_block is invalid
    oacq_read_block.is_builtin_type <= UInt<1>("h01")
    oacq_read_block.a_type <= UInt<3>("h01")
    oacq_read_block.client_xact_id <= UInt<3>("h05")
    oacq_read_block.addr_block <= xact.addr_block
    oacq_read_block.addr_beat <= UInt<1>("h00")
    oacq_read_block.data <= UInt<1>("h00")
    oacq_read_block.union <= T_993
    io.outer.acquire.valid <= UInt<1>("h00")
    node T_1011 = eq(state, UInt<1>("h01"))
    node T_1012 = eq(state, UInt<2>("h03"))
    node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block)
    node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block)
    node T_1029 = mux(T_1012, T_1013, T_1021)
    node T_1037 = mux(T_1011, oacq_probe, T_1029)
    io.outer.acquire.bits <- T_1037
    io.outer.grant.ready <= UInt<1>("h00")
    io.inner.probe.valid <= UInt<1>("h00")
    node T_1054 = eq(UInt<3>("h04"), xact.a_type)
    node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02"))
    node T_1056 = eq(UInt<3>("h06"), xact.a_type)
    node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055)
    node T_1058 = eq(UInt<3>("h05"), xact.a_type)
    node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057)
    node T_1060 = eq(UInt<3>("h02"), xact.a_type)
    node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059)
    node T_1062 = eq(UInt<3>("h00"), xact.a_type)
    node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061)
    node T_1064 = eq(UInt<3>("h03"), xact.a_type)
    node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063)
    node T_1066 = eq(UInt<3>("h01"), xact.a_type)
    node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065)
    node T_1068 = eq(UInt<1>("h01"), xact.a_type)
    node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02"))
    node T_1070 = eq(UInt<1>("h00"), xact.a_type)
    node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069)
    node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071)
    wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_1077 is invalid
    T_1077.client_id <= UInt<1>("h00")
    T_1077.p_type <= T_1072
    T_1077.addr_block <= xact.addr_block
    io.inner.probe.bits <- T_1077
    io.inner.grant.valid <= UInt<1>("h00")
    node T_1100 = eq(UInt<3>("h06"), xact.a_type)
    node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03"))
    node T_1102 = eq(UInt<3>("h05"), xact.a_type)
    node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101)
    node T_1104 = eq(UInt<3>("h04"), xact.a_type)
    node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103)
    node T_1106 = eq(UInt<3>("h03"), xact.a_type)
    node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105)
    node T_1108 = eq(UInt<3>("h02"), xact.a_type)
    node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107)
    node T_1110 = eq(UInt<3>("h01"), xact.a_type)
    node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109)
    node T_1112 = eq(UInt<3>("h00"), xact.a_type)
    node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111)
    node T_1114 = eq(xact.a_type, UInt<1>("h00"))
    node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01"))
    node T_1119 = mux(T_1114, T_1118, UInt<1>("h01"))
    node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119)
    wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_1129 is invalid
    T_1129.client_id <= xact.client_id
    T_1129.is_builtin_type <= xact.is_builtin_type
    T_1129.g_type <= T_1120
    T_1129.client_xact_id <= xact.client_xact_id
    T_1129.manager_xact_id <= UInt<3>("h05")
    T_1129.addr_beat <= UInt<1>("h00")
    T_1129.data <= UInt<1>("h00")
    io.inner.grant.bits <- T_1129
    io.inner.acquire.ready <= UInt<1>("h00")
    io.inner.release.ready <= UInt<1>("h00")
    io.inner.finish.ready <= UInt<1>("h00")
    node T_1140 = neq(state, UInt<1>("h00"))
    node T_1141 = and(T_1140, collect_iacq_data)
    node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1143 = and(T_1141, T_1142)
    node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id)
    node T_1145 = and(T_1143, T_1144)
    node T_1147 = eq(T_1145, UInt<1>("h00"))
    node T_1149 = eq(reset, UInt<1>("h00"))
    when T_1149 :
      node T_1151 = eq(T_1147, UInt<1>("h00"))
      when T_1151 :
        node T_1153 = eq(reset, UInt<1>("h00"))
        when T_1153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1154 = neq(state, UInt<1>("h00"))
    node T_1155 = and(T_1154, collect_iacq_data)
    node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1157 = and(T_1155, T_1156)
    node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id)
    node T_1159 = and(T_1157, T_1158)
    node T_1161 = eq(T_1159, UInt<1>("h00"))
    node T_1163 = eq(reset, UInt<1>("h00"))
    when T_1163 :
      node T_1165 = eq(T_1161, UInt<1>("h00"))
      when T_1165 :
        node T_1167 = eq(reset, UInt<1>("h00"))
        when T_1167 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1168 = eq(state, UInt<1>("h00"))
    node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1170 = and(T_1168, T_1169)
    node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_1175 : UInt<3>[1]
    T_1175[0] <= UInt<3>("h03")
    node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type)
    node T_1180 = or(UInt<1>("h00"), T_1178)
    node T_1181 = and(T_1172, T_1180)
    node T_1182 = and(T_1170, T_1181)
    node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00"))
    node T_1185 = and(T_1182, T_1184)
    node T_1187 = eq(T_1185, UInt<1>("h00"))
    node T_1189 = eq(reset, UInt<1>("h00"))
    when T_1189 :
      node T_1191 = eq(T_1187, UInt<1>("h00"))
      when T_1191 :
        node T_1193 = eq(reset, UInt<1>("h00"))
        when T_1193 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    when collect_iacq_data :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data
        node T_1197 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1198 = bits(T_1197, 3, 3)
        node T_1200 = dshl(UInt<1>("h01"), T_1198)
        node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202)
        node T_1204 = bits(T_1200, 0, 0)
        node T_1205 = bits(T_1200, 1, 1)
        wire T_1207 : UInt<1>[2]
        T_1207[0] <= T_1204
        T_1207[1] <= T_1205
        node T_1212 = sub(UInt<8>("h00"), T_1207[0])
        node T_1213 = tail(T_1212, 1)
        node T_1215 = sub(UInt<8>("h00"), T_1207[1])
        node T_1216 = tail(T_1215, 1)
        wire T_1218 : UInt<8>[2]
        T_1218[0] <= T_1213
        T_1218[1] <= T_1216
        node T_1222 = cat(T_1218[1], T_1218[0])
        node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224)
        node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227)
        node T_1229 = or(T_1225, T_1228)
        node T_1230 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1232 = mux(T_1229, T_1230, UInt<16>("h00"))
        node T_1233 = mux(T_1203, T_1222, T_1232)
        xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233
        node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat)
        node T_1237 = or(iacq_data_valid, T_1236)
        node T_1238 = not(iacq_data_valid)
        node T_1239 = or(T_1238, T_1236)
        node T_1240 = not(T_1239)
        node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240)
        iacq_data_valid <= T_1241
        skip
      when iacq_data_done :
        collect_iacq_data <= UInt<1>("h00")
        skip
      skip
    when pending_ognt_ack :
      io.outer.grant.ready <= UInt<1>("h01")
      when io.outer.grant.valid :
        pending_ognt_ack <= UInt<1>("h00")
        skip
      skip
    node T_1245 = eq(UInt<1>("h00"), state)
    when T_1245 :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact <- io.inner.acquire.bits
        xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data
        node T_1251 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1252 = bits(T_1251, 3, 3)
        node T_1254 = dshl(UInt<1>("h01"), T_1252)
        node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256)
        node T_1258 = bits(T_1254, 0, 0)
        node T_1259 = bits(T_1254, 1, 1)
        wire T_1261 : UInt<1>[2]
        T_1261[0] <= T_1258
        T_1261[1] <= T_1259
        node T_1266 = sub(UInt<8>("h00"), T_1261[0])
        node T_1267 = tail(T_1266, 1)
        node T_1269 = sub(UInt<8>("h00"), T_1261[1])
        node T_1270 = tail(T_1269, 1)
        wire T_1272 : UInt<8>[2]
        T_1272[0] <= T_1267
        T_1272[1] <= T_1270
        node T_1276 = cat(T_1272[1], T_1272[0])
        node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278)
        node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281)
        node T_1283 = or(T_1279, T_1282)
        node T_1284 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1286 = mux(T_1283, T_1284, UInt<16>("h00"))
        node T_1287 = mux(T_1257, T_1276, T_1286)
        xact.wmask_buffer[UInt<1>("h00")] <= T_1287
        node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
        wire T_1292 : UInt<3>[1]
        T_1292[0] <= UInt<3>("h03")
        node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type)
        node T_1297 = or(UInt<1>("h00"), T_1295)
        node T_1298 = and(T_1289, T_1297)
        collect_iacq_data <= T_1298
        wire T_1303 : UInt<3>[3]
        T_1303[0] <= UInt<3>("h02")
        T_1303[1] <= UInt<3>("h03")
        T_1303[2] <= UInt<3>("h04")
        node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type)
        node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type)
        node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type)
        node T_1312 = or(UInt<1>("h00"), T_1308)
        node T_1313 = or(T_1312, T_1309)
        node T_1314 = or(T_1313, T_1310)
        node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314)
        node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat)
        iacq_data_valid <= T_1316
        node T_1318 = neq(mask_incoherent, UInt<1>("h00"))
        when T_1318 :
          pending_probes <= mask_incoherent
          node T_1319 = bits(mask_incoherent, 0, 0)
          node T_1320 = bits(mask_incoherent, 1, 1)
          node T_1321 = bits(mask_incoherent, 2, 2)
          node T_1322 = bits(mask_incoherent, 3, 3)
          node T_1324 = cat(UInt<1>("h00"), T_1320)
          node T_1325 = add(T_1319, T_1324)
          node T_1326 = tail(T_1325, 1)
          node T_1329 = cat(UInt<1>("h00"), T_1322)
          node T_1330 = add(T_1321, T_1329)
          node T_1331 = tail(T_1330, 1)
          node T_1332 = cat(UInt<1>("h00"), T_1331)
          node T_1333 = add(T_1326, T_1332)
          node T_1334 = tail(T_1333, 1)
          release_count <= T_1334
          skip
        node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04"))
        node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335)
        node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336)
        state <= T_1337
        skip
      skip
    node T_1338 = eq(UInt<1>("h01"), state)
    when T_1338 :
      node T_1340 = neq(pending_probes, UInt<1>("h00"))
      io.inner.probe.valid <= T_1340
      when io.inner.probe.ready :
        node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00"))
        node T_1343 = not(T_1342)
        node T_1344 = and(pending_probes, T_1343)
        pending_probes <= T_1344
        skip
      wire T_1346 : UInt<2>[3]
      T_1346[0] <= UInt<1>("h00")
      T_1346[1] <= UInt<1>("h01")
      T_1346[2] <= UInt<2>("h02")
      node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type)
      node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type)
      node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type)
      node T_1355 = or(UInt<1>("h00"), T_1351)
      node T_1356 = or(T_1355, T_1352)
      node T_1357 = or(T_1356, T_1353)
      node T_1359 = eq(T_1357, UInt<1>("h00"))
      node T_1360 = or(T_1359, io.outer.acquire.ready)
      io.inner.release.ready <= T_1360
      when io.inner.release.valid :
        wire T_1362 : UInt<2>[3]
        T_1362[0] <= UInt<1>("h00")
        T_1362[1] <= UInt<1>("h01")
        T_1362[2] <= UInt<2>("h02")
        node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type)
        node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type)
        node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type)
        node T_1371 = or(UInt<1>("h00"), T_1367)
        node T_1372 = or(T_1371, T_1368)
        node T_1373 = or(T_1372, T_1369)
        when T_1373 :
          io.outer.acquire.valid <= UInt<1>("h01")
          when io.outer.acquire.ready :
            when oacq_data_done :
              pending_ognt_ack <= UInt<1>("h01")
              node T_1377 = sub(release_count, UInt<1>("h01"))
              node T_1378 = tail(T_1377, 1)
              release_count <= T_1378
              node T_1380 = eq(release_count, UInt<1>("h01"))
              when T_1380 :
                node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
                node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381)
                state <= T_1382
                skip
              skip
            skip
          skip
        node T_1384 = eq(T_1373, UInt<1>("h00"))
        when T_1384 :
          node T_1386 = sub(release_count, UInt<1>("h01"))
          node T_1387 = tail(T_1386, 1)
          release_count <= T_1387
          node T_1389 = eq(release_count, UInt<1>("h01"))
          when T_1389 :
            node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
            node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390)
            state <= T_1391
            skip
          skip
        skip
      skip
    node T_1392 = eq(UInt<2>("h03"), state)
    when T_1392 :
      node T_1394 = eq(pending_ognt_ack, UInt<1>("h00"))
      node T_1396 = eq(collect_iacq_data, UInt<1>("h00"))
      node T_1397 = dshr(iacq_data_valid, oacq_data_cnt)
      node T_1398 = bits(T_1397, 0, 0)
      node T_1399 = or(T_1396, T_1398)
      node T_1400 = and(T_1394, T_1399)
      io.outer.acquire.valid <= T_1400
      when oacq_data_done :
        pending_ognt_ack <= UInt<1>("h01")
        node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05"))
        state <= T_1402
        skip
      skip
    node T_1403 = eq(UInt<2>("h02"), state)
    when T_1403 :
      node T_1405 = eq(pending_ognt_ack, UInt<1>("h00"))
      io.outer.acquire.valid <= T_1405
      node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid)
      when T_1406 :
        state <= UInt<3>("h05")
        skip
      skip
    node T_1407 = eq(UInt<3>("h05"), state)
    when T_1407 :
      io.outer.grant.ready <= io.inner.grant.ready
      io.inner.grant.valid <= io.outer.grant.valid
      when ignt_data_done :
        node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412)
        node T_1415 = eq(T_1413, UInt<1>("h00"))
        node T_1416 = and(T_1410, T_1415)
        node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1417
        skip
      skip
    node T_1418 = eq(UInt<3>("h04"), state)
    when T_1418 :
      io.inner.grant.valid <= UInt<1>("h01")
      when io.inner.grant.ready :
        node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424)
        node T_1427 = eq(T_1425, UInt<1>("h00"))
        node T_1428 = and(T_1422, T_1427)
        node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1429
        skip
      skip
    node T_1430 = eq(UInt<3>("h06"), state)
    when T_1430 :
      io.inner.finish.ready <= UInt<1>("h01")
      when io.inner.finish.valid :
        state <= UInt<1>("h00")
        skip
      skip
    
  module BroadcastAcquireTracker_31 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
    wire coh : {sharers : UInt<1>}
    coh is invalid
    coh.sharers <= UInt<1>("h00")
    node T_303 = neq(state, UInt<1>("h00"))
    node T_304 = and(T_303, xact.is_builtin_type)
    wire T_309 : UInt<3>[3]
    T_309[0] <= UInt<3>("h04")
    T_309[1] <= UInt<3>("h05")
    T_309[2] <= UInt<3>("h06")
    node T_314 = eq(T_309[0], xact.a_type)
    node T_315 = eq(T_309[1], xact.a_type)
    node T_316 = eq(T_309[2], xact.a_type)
    node T_318 = or(UInt<1>("h00"), T_314)
    node T_319 = or(T_318, T_315)
    node T_320 = or(T_319, T_316)
    node T_321 = and(T_304, T_320)
    node T_323 = eq(T_321, UInt<1>("h00"))
    node T_325 = eq(reset, UInt<1>("h00"))
    when T_325 :
      node T_327 = eq(T_323, UInt<1>("h00"))
      when T_327 :
        node T_329 = eq(reset, UInt<1>("h00"))
        when T_329 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_334 = bits(pending_probes, 0, 0)
    wire T_336 : UInt<1>[1]
    T_336[0] <= T_334
    node T_341 = asUInt(asSInt(UInt<1>("h01")))
    node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id)
    node T_345 = or(T_341, T_344)
    node T_346 = not(T_341)
    node T_347 = or(T_346, T_344)
    node T_348 = not(T_347)
    node mask_self = mux(UInt<1>("h00"), T_345, T_348)
    node T_350 = not(io.incoherent[0])
    node mask_incoherent = and(mask_self, T_350)
    reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_362 : UInt<3>[1]
    T_362[0] <= UInt<3>("h03")
    node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type)
    node T_367 = or(UInt<1>("h00"), T_365)
    node T_368 = and(T_359, T_367)
    node T_369 = and(T_356, T_368)
    reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_369 :
      node T_373 = eq(T_371, UInt<2>("h03"))
      node T_375 = and(UInt<1>("h00"), T_373)
      node T_378 = add(T_371, UInt<1>("h01"))
      node T_379 = tail(T_378, 1)
      node T_380 = mux(T_375, UInt<1>("h00"), T_379)
      T_371 <= T_380
      skip
    node T_381 = and(T_369, T_373)
    node T_382 = mux(T_368, T_371, UInt<1>("h00"))
    node iacq_data_done = mux(T_368, T_381, T_356)
    node T_384 = and(io.inner.release.ready, io.inner.release.valid)
    wire T_388 : UInt<2>[3]
    T_388[0] <= UInt<1>("h00")
    T_388[1] <= UInt<1>("h01")
    T_388[2] <= UInt<2>("h02")
    node T_393 = eq(T_388[0], io.inner.release.bits.r_type)
    node T_394 = eq(T_388[1], io.inner.release.bits.r_type)
    node T_395 = eq(T_388[2], io.inner.release.bits.r_type)
    node T_397 = or(UInt<1>("h00"), T_393)
    node T_398 = or(T_397, T_394)
    node T_399 = or(T_398, T_395)
    node T_400 = and(UInt<1>("h01"), T_399)
    node T_401 = and(T_384, T_400)
    reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_401 :
      node T_405 = eq(T_403, UInt<2>("h03"))
      node T_407 = and(UInt<1>("h00"), T_405)
      node T_410 = add(T_403, UInt<1>("h01"))
      node T_411 = tail(T_410, 1)
      node T_412 = mux(T_407, UInt<1>("h00"), T_411)
      T_403 <= T_412
      skip
    node T_413 = and(T_401, T_405)
    node T_414 = mux(T_400, T_403, UInt<1>("h00"))
    node irel_data_done = mux(T_400, T_413, T_384)
    node T_417 = and(io.inner.grant.ready, io.inner.grant.valid)
    wire T_421 : UInt<3>[1]
    T_421[0] <= UInt<3>("h05")
    node T_424 = eq(T_421[0], io.inner.grant.bits.g_type)
    node T_426 = or(UInt<1>("h00"), T_424)
    wire T_428 : UInt<1>[2]
    T_428[0] <= UInt<1>("h00")
    T_428[1] <= UInt<1>("h01")
    node T_432 = eq(T_428[0], io.inner.grant.bits.g_type)
    node T_433 = eq(T_428[1], io.inner.grant.bits.g_type)
    node T_435 = or(UInt<1>("h00"), T_432)
    node T_436 = or(T_435, T_433)
    node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436)
    node T_438 = and(UInt<1>("h01"), T_437)
    node T_439 = and(T_417, T_438)
    reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_439 :
      node T_443 = eq(T_441, UInt<2>("h03"))
      node T_445 = and(UInt<1>("h00"), T_443)
      node T_448 = add(T_441, UInt<1>("h01"))
      node T_449 = tail(T_448, 1)
      node T_450 = mux(T_445, UInt<1>("h00"), T_449)
      T_441 <= T_450
      skip
    node T_451 = and(T_439, T_443)
    node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00"))
    node ignt_data_done = mux(T_438, T_451, T_417)
    node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type)
    wire T_460 : UInt<3>[1]
    T_460[0] <= UInt<3>("h03")
    node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type)
    node T_465 = or(UInt<1>("h00"), T_463)
    node T_466 = and(T_457, T_465)
    node T_467 = and(T_455, T_466)
    reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_467 :
      node T_471 = eq(T_469, UInt<2>("h03"))
      node T_473 = and(UInt<1>("h00"), T_471)
      node T_476 = add(T_469, UInt<1>("h01"))
      node T_477 = tail(T_476, 1)
      node T_478 = mux(T_473, UInt<1>("h00"), T_477)
      T_469 <= T_478
      skip
    node T_479 = and(T_467, T_471)
    node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00"))
    node oacq_data_done = mux(T_466, T_479, T_455)
    node T_482 = and(io.outer.grant.ready, io.outer.grant.valid)
    wire T_487 : UInt<3>[1]
    T_487[0] <= UInt<3>("h05")
    node T_490 = eq(T_487[0], io.outer.grant.bits.g_type)
    node T_492 = or(UInt<1>("h00"), T_490)
    wire T_494 : UInt<1>[1]
    T_494[0] <= UInt<1>("h00")
    node T_497 = eq(T_494[0], io.outer.grant.bits.g_type)
    node T_499 = or(UInt<1>("h00"), T_497)
    node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499)
    node T_501 = and(UInt<1>("h01"), T_500)
    node T_502 = and(T_482, T_501)
    reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_502 :
      node T_506 = eq(T_504, UInt<2>("h03"))
      node T_508 = and(UInt<1>("h00"), T_506)
      node T_511 = add(T_504, UInt<1>("h01"))
      node T_512 = tail(T_511, 1)
      node T_513 = mux(T_508, UInt<1>("h00"), T_512)
      T_504 <= T_513
      skip
    node T_514 = and(T_502, T_506)
    node T_515 = mux(T_501, T_504, UInt<1>("h00"))
    node ognt_data_done = mux(T_501, T_514, T_482)
    reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_523 : UInt<3>[3]
    T_523[0] <= UInt<3>("h02")
    T_523[1] <= UInt<3>("h03")
    T_523[2] <= UInt<3>("h04")
    node T_528 = eq(T_523[0], xact.a_type)
    node T_529 = eq(T_523[1], xact.a_type)
    node T_530 = eq(T_523[2], xact.a_type)
    node T_532 = or(UInt<1>("h00"), T_528)
    node T_533 = or(T_532, T_529)
    node T_534 = or(T_533, T_530)
    node pending_outer_write = and(xact.is_builtin_type, T_534)
    wire T_540 : UInt<3>[3]
    T_540[0] <= UInt<3>("h02")
    T_540[1] <= UInt<3>("h03")
    T_540[2] <= UInt<3>("h04")
    node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type)
    node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type)
    node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type)
    node T_549 = or(UInt<1>("h00"), T_545)
    node T_550 = or(T_549, T_546)
    node T_551 = or(T_550, T_547)
    node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551)
    wire T_556 : UInt<3>[2]
    T_556[0] <= UInt<3>("h05")
    T_556[1] <= UInt<3>("h04")
    node T_560 = eq(T_556[0], io.inner.grant.bits.g_type)
    node T_561 = eq(T_556[1], io.inner.grant.bits.g_type)
    node T_563 = or(UInt<1>("h00"), T_560)
    node T_564 = or(T_563, T_561)
    wire T_566 : UInt<1>[2]
    T_566[0] <= UInt<1>("h00")
    T_566[1] <= UInt<1>("h01")
    node T_570 = eq(T_566[0], io.inner.grant.bits.g_type)
    node T_571 = eq(T_566[1], io.inner.grant.bits.g_type)
    node T_573 = or(UInt<1>("h00"), T_570)
    node T_574 = or(T_573, T_571)
    node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574)
    node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type)
    node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03"))
    node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type)
    node T_597 = mux(T_596, UInt<3>("h01"), T_595)
    node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type)
    node T_599 = mux(T_598, UInt<3>("h04"), T_597)
    node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type)
    node T_601 = mux(T_600, UInt<3>("h03"), T_599)
    node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type)
    node T_603 = mux(T_602, UInt<3>("h03"), T_601)
    node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type)
    node T_605 = mux(T_604, UInt<3>("h05"), T_603)
    node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type)
    node T_607 = mux(T_606, UInt<3>("h04"), T_605)
    node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00"))
    node T_611 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01"))
    node T_613 = mux(T_608, T_612, UInt<1>("h01"))
    node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613)
    wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_623 is invalid
    T_623.client_id <= io.inner.acquire.bits.client_id
    T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type
    T_623.g_type <= T_614
    T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id
    T_623.manager_xact_id <= UInt<3>("h06")
    T_623.addr_beat <= UInt<1>("h00")
    T_623.data <= UInt<1>("h00")
    wire T_634 : UInt<3>[2]
    T_634[0] <= UInt<3>("h05")
    T_634[1] <= UInt<3>("h04")
    node T_638 = eq(T_634[0], T_623.g_type)
    node T_639 = eq(T_634[1], T_623.g_type)
    node T_641 = or(UInt<1>("h00"), T_638)
    node T_642 = or(T_641, T_639)
    wire T_644 : UInt<1>[2]
    T_644[0] <= UInt<1>("h00")
    T_644[1] <= UInt<1>("h01")
    node T_648 = eq(T_644[0], T_623.g_type)
    node T_649 = eq(T_644[1], T_623.g_type)
    node T_651 = or(UInt<1>("h00"), T_648)
    node T_652 = or(T_651, T_649)
    node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652)
    wire T_658 : UInt<3>[3]
    T_658[0] <= UInt<3>("h02")
    T_658[1] <= UInt<3>("h00")
    T_658[2] <= UInt<3>("h04")
    node T_663 = eq(T_658[0], xact.a_type)
    node T_664 = eq(T_658[1], xact.a_type)
    node T_665 = eq(T_658[2], xact.a_type)
    node T_667 = or(UInt<1>("h00"), T_663)
    node T_668 = or(T_667, T_664)
    node T_669 = or(T_668, T_665)
    node subblock_type = and(xact.is_builtin_type, T_669)
    node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_672 = neq(state, UInt<1>("h00"))
    node T_673 = and(T_671, T_672)
    node T_675 = eq(collect_iacq_data, UInt<1>("h00"))
    node T_676 = and(T_673, T_675)
    io.has_acquire_conflict <= T_676
    node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_678 = and(T_677, collect_iacq_data)
    io.has_acquire_match <= T_678
    node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block)
    node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00"))
    node T_682 = and(T_679, T_681)
    node T_683 = eq(state, UInt<1>("h01"))
    node T_684 = and(T_682, T_683)
    io.has_release_match <= T_684
    node T_689 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_695 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_696 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_697 = cat(T_695, T_696)
    node T_699 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_700 = cat(UInt<3>("h07"), T_699)
    node T_702 = cat(T_689, UInt<1>("h01"))
    node T_704 = cat(T_689, UInt<1>("h01"))
    node T_706 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_707 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_708 = cat(T_706, T_707)
    node T_710 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_712 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_713 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_714 = mux(T_713, T_712, UInt<1>("h00"))
    node T_715 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_716 = mux(T_715, T_710, T_714)
    node T_717 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_718 = mux(T_717, T_708, T_716)
    node T_719 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_720 = mux(T_719, T_704, T_718)
    node T_721 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_722 = mux(T_721, T_702, T_720)
    node T_723 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_724 = mux(T_723, T_700, T_722)
    node T_725 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_726 = mux(T_725, T_697, T_724)
    wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_probe is invalid
    oacq_probe.is_builtin_type <= UInt<1>("h01")
    oacq_probe.a_type <= UInt<3>("h03")
    oacq_probe.client_xact_id <= UInt<3>("h06")
    oacq_probe.addr_block <= io.inner.release.bits.addr_block
    oacq_probe.addr_beat <= io.inner.release.bits.addr_beat
    oacq_probe.data <= io.inner.release.bits.data
    oacq_probe.union <= T_726
    node T_744 = bits(xact.union, 12, 9)
    node T_745 = bits(T_744, 3, 3)
    node T_747 = dshl(UInt<1>("h01"), T_745)
    node T_749 = eq(xact.a_type, UInt<3>("h04"))
    node T_750 = and(xact.is_builtin_type, T_749)
    node T_751 = bits(T_747, 0, 0)
    node T_752 = bits(T_747, 1, 1)
    wire T_754 : UInt<1>[2]
    T_754[0] <= T_751
    T_754[1] <= T_752
    node T_759 = sub(UInt<8>("h00"), T_754[0])
    node T_760 = tail(T_759, 1)
    node T_762 = sub(UInt<8>("h00"), T_754[1])
    node T_763 = tail(T_762, 1)
    wire T_765 : UInt<8>[2]
    T_765[0] <= T_760
    T_765[1] <= T_763
    node T_769 = cat(T_765[1], T_765[0])
    node T_771 = eq(xact.a_type, UInt<3>("h03"))
    node T_772 = and(xact.is_builtin_type, T_771)
    node T_774 = eq(xact.a_type, UInt<3>("h02"))
    node T_775 = and(xact.is_builtin_type, T_774)
    node T_776 = or(T_772, T_775)
    node T_777 = bits(xact.union, 16, 1)
    node T_779 = mux(T_776, T_777, UInt<16>("h00"))
    node T_780 = mux(T_750, T_769, T_779)
    node T_788 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_789 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_790 = cat(T_788, T_789)
    node T_792 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_793 = cat(UInt<3>("h07"), T_792)
    node T_795 = cat(T_780, UInt<1>("h01"))
    node T_797 = cat(T_780, UInt<1>("h01"))
    node T_799 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_800 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_801 = cat(T_799, T_800)
    node T_803 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_805 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_806 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_807 = mux(T_806, T_805, UInt<1>("h00"))
    node T_808 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_809 = mux(T_808, T_803, T_807)
    node T_810 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_811 = mux(T_810, T_801, T_809)
    node T_812 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_813 = mux(T_812, T_797, T_811)
    node T_814 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_815 = mux(T_814, T_795, T_813)
    node T_816 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_817 = mux(T_816, T_793, T_815)
    node T_818 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_819 = mux(T_818, T_790, T_817)
    wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_beat is invalid
    oacq_write_beat.is_builtin_type <= UInt<1>("h01")
    oacq_write_beat.a_type <= UInt<3>("h02")
    oacq_write_beat.client_xact_id <= UInt<3>("h06")
    oacq_write_beat.addr_block <= xact.addr_block
    oacq_write_beat.addr_beat <= xact.addr_beat
    oacq_write_beat.data <= xact.data_buffer[0]
    oacq_write_beat.union <= T_819
    node T_846 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_847 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_848 = cat(T_846, T_847)
    node T_850 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_851 = cat(UInt<3>("h07"), T_850)
    node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_857 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_858 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_859 = cat(T_857, T_858)
    node T_861 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_863 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_864 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_865 = mux(T_864, T_863, UInt<1>("h00"))
    node T_866 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_867 = mux(T_866, T_861, T_865)
    node T_868 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_869 = mux(T_868, T_859, T_867)
    node T_870 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_871 = mux(T_870, T_855, T_869)
    node T_872 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_873 = mux(T_872, T_853, T_871)
    node T_874 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_875 = mux(T_874, T_851, T_873)
    node T_876 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_877 = mux(T_876, T_848, T_875)
    wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_block is invalid
    oacq_write_block.is_builtin_type <= UInt<1>("h01")
    oacq_write_block.a_type <= UInt<3>("h03")
    oacq_write_block.client_xact_id <= UInt<3>("h06")
    oacq_write_block.addr_block <= xact.addr_block
    oacq_write_block.addr_beat <= oacq_data_cnt
    oacq_write_block.data <= xact.data_buffer[oacq_data_cnt]
    oacq_write_block.union <= T_877
    node T_895 = bits(xact.union, 12, 9)
    node T_896 = bits(xact.union, 8, 6)
    node T_904 = cat(T_895, T_896)
    node T_905 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_906 = cat(T_904, T_905)
    node T_908 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_909 = cat(T_896, T_908)
    node T_911 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_913 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_915 = cat(T_895, T_896)
    node T_916 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_917 = cat(T_915, T_916)
    node T_919 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_921 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_922 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_923 = mux(T_922, T_921, UInt<1>("h00"))
    node T_924 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_925 = mux(T_924, T_919, T_923)
    node T_926 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_927 = mux(T_926, T_917, T_925)
    node T_928 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_929 = mux(T_928, T_913, T_927)
    node T_930 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_931 = mux(T_930, T_911, T_929)
    node T_932 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_933 = mux(T_932, T_909, T_931)
    node T_934 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_935 = mux(T_934, T_906, T_933)
    wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_beat is invalid
    oacq_read_beat.is_builtin_type <= UInt<1>("h01")
    oacq_read_beat.a_type <= UInt<3>("h00")
    oacq_read_beat.client_xact_id <= UInt<3>("h06")
    oacq_read_beat.addr_block <= xact.addr_block
    oacq_read_beat.addr_beat <= xact.addr_beat
    oacq_read_beat.data <= UInt<1>("h00")
    oacq_read_beat.union <= T_935
    node T_962 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_963 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_964 = cat(T_962, T_963)
    node T_966 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_967 = cat(UInt<3>("h07"), T_966)
    node T_969 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_971 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_973 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_974 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_975 = cat(T_973, T_974)
    node T_977 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_979 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_980 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_981 = mux(T_980, T_979, UInt<1>("h00"))
    node T_982 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_983 = mux(T_982, T_977, T_981)
    node T_984 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_985 = mux(T_984, T_975, T_983)
    node T_986 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_987 = mux(T_986, T_971, T_985)
    node T_988 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_989 = mux(T_988, T_969, T_987)
    node T_990 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_991 = mux(T_990, T_967, T_989)
    node T_992 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_993 = mux(T_992, T_964, T_991)
    wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_block is invalid
    oacq_read_block.is_builtin_type <= UInt<1>("h01")
    oacq_read_block.a_type <= UInt<3>("h01")
    oacq_read_block.client_xact_id <= UInt<3>("h06")
    oacq_read_block.addr_block <= xact.addr_block
    oacq_read_block.addr_beat <= UInt<1>("h00")
    oacq_read_block.data <= UInt<1>("h00")
    oacq_read_block.union <= T_993
    io.outer.acquire.valid <= UInt<1>("h00")
    node T_1011 = eq(state, UInt<1>("h01"))
    node T_1012 = eq(state, UInt<2>("h03"))
    node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block)
    node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block)
    node T_1029 = mux(T_1012, T_1013, T_1021)
    node T_1037 = mux(T_1011, oacq_probe, T_1029)
    io.outer.acquire.bits <- T_1037
    io.outer.grant.ready <= UInt<1>("h00")
    io.inner.probe.valid <= UInt<1>("h00")
    node T_1054 = eq(UInt<3>("h04"), xact.a_type)
    node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02"))
    node T_1056 = eq(UInt<3>("h06"), xact.a_type)
    node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055)
    node T_1058 = eq(UInt<3>("h05"), xact.a_type)
    node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057)
    node T_1060 = eq(UInt<3>("h02"), xact.a_type)
    node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059)
    node T_1062 = eq(UInt<3>("h00"), xact.a_type)
    node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061)
    node T_1064 = eq(UInt<3>("h03"), xact.a_type)
    node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063)
    node T_1066 = eq(UInt<3>("h01"), xact.a_type)
    node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065)
    node T_1068 = eq(UInt<1>("h01"), xact.a_type)
    node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02"))
    node T_1070 = eq(UInt<1>("h00"), xact.a_type)
    node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069)
    node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071)
    wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_1077 is invalid
    T_1077.client_id <= UInt<1>("h00")
    T_1077.p_type <= T_1072
    T_1077.addr_block <= xact.addr_block
    io.inner.probe.bits <- T_1077
    io.inner.grant.valid <= UInt<1>("h00")
    node T_1100 = eq(UInt<3>("h06"), xact.a_type)
    node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03"))
    node T_1102 = eq(UInt<3>("h05"), xact.a_type)
    node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101)
    node T_1104 = eq(UInt<3>("h04"), xact.a_type)
    node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103)
    node T_1106 = eq(UInt<3>("h03"), xact.a_type)
    node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105)
    node T_1108 = eq(UInt<3>("h02"), xact.a_type)
    node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107)
    node T_1110 = eq(UInt<3>("h01"), xact.a_type)
    node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109)
    node T_1112 = eq(UInt<3>("h00"), xact.a_type)
    node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111)
    node T_1114 = eq(xact.a_type, UInt<1>("h00"))
    node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01"))
    node T_1119 = mux(T_1114, T_1118, UInt<1>("h01"))
    node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119)
    wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_1129 is invalid
    T_1129.client_id <= xact.client_id
    T_1129.is_builtin_type <= xact.is_builtin_type
    T_1129.g_type <= T_1120
    T_1129.client_xact_id <= xact.client_xact_id
    T_1129.manager_xact_id <= UInt<3>("h06")
    T_1129.addr_beat <= UInt<1>("h00")
    T_1129.data <= UInt<1>("h00")
    io.inner.grant.bits <- T_1129
    io.inner.acquire.ready <= UInt<1>("h00")
    io.inner.release.ready <= UInt<1>("h00")
    io.inner.finish.ready <= UInt<1>("h00")
    node T_1140 = neq(state, UInt<1>("h00"))
    node T_1141 = and(T_1140, collect_iacq_data)
    node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1143 = and(T_1141, T_1142)
    node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id)
    node T_1145 = and(T_1143, T_1144)
    node T_1147 = eq(T_1145, UInt<1>("h00"))
    node T_1149 = eq(reset, UInt<1>("h00"))
    when T_1149 :
      node T_1151 = eq(T_1147, UInt<1>("h00"))
      when T_1151 :
        node T_1153 = eq(reset, UInt<1>("h00"))
        when T_1153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1154 = neq(state, UInt<1>("h00"))
    node T_1155 = and(T_1154, collect_iacq_data)
    node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1157 = and(T_1155, T_1156)
    node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id)
    node T_1159 = and(T_1157, T_1158)
    node T_1161 = eq(T_1159, UInt<1>("h00"))
    node T_1163 = eq(reset, UInt<1>("h00"))
    when T_1163 :
      node T_1165 = eq(T_1161, UInt<1>("h00"))
      when T_1165 :
        node T_1167 = eq(reset, UInt<1>("h00"))
        when T_1167 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1168 = eq(state, UInt<1>("h00"))
    node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1170 = and(T_1168, T_1169)
    node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_1175 : UInt<3>[1]
    T_1175[0] <= UInt<3>("h03")
    node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type)
    node T_1180 = or(UInt<1>("h00"), T_1178)
    node T_1181 = and(T_1172, T_1180)
    node T_1182 = and(T_1170, T_1181)
    node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00"))
    node T_1185 = and(T_1182, T_1184)
    node T_1187 = eq(T_1185, UInt<1>("h00"))
    node T_1189 = eq(reset, UInt<1>("h00"))
    when T_1189 :
      node T_1191 = eq(T_1187, UInt<1>("h00"))
      when T_1191 :
        node T_1193 = eq(reset, UInt<1>("h00"))
        when T_1193 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    when collect_iacq_data :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data
        node T_1197 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1198 = bits(T_1197, 3, 3)
        node T_1200 = dshl(UInt<1>("h01"), T_1198)
        node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202)
        node T_1204 = bits(T_1200, 0, 0)
        node T_1205 = bits(T_1200, 1, 1)
        wire T_1207 : UInt<1>[2]
        T_1207[0] <= T_1204
        T_1207[1] <= T_1205
        node T_1212 = sub(UInt<8>("h00"), T_1207[0])
        node T_1213 = tail(T_1212, 1)
        node T_1215 = sub(UInt<8>("h00"), T_1207[1])
        node T_1216 = tail(T_1215, 1)
        wire T_1218 : UInt<8>[2]
        T_1218[0] <= T_1213
        T_1218[1] <= T_1216
        node T_1222 = cat(T_1218[1], T_1218[0])
        node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224)
        node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227)
        node T_1229 = or(T_1225, T_1228)
        node T_1230 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1232 = mux(T_1229, T_1230, UInt<16>("h00"))
        node T_1233 = mux(T_1203, T_1222, T_1232)
        xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233
        node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat)
        node T_1237 = or(iacq_data_valid, T_1236)
        node T_1238 = not(iacq_data_valid)
        node T_1239 = or(T_1238, T_1236)
        node T_1240 = not(T_1239)
        node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240)
        iacq_data_valid <= T_1241
        skip
      when iacq_data_done :
        collect_iacq_data <= UInt<1>("h00")
        skip
      skip
    when pending_ognt_ack :
      io.outer.grant.ready <= UInt<1>("h01")
      when io.outer.grant.valid :
        pending_ognt_ack <= UInt<1>("h00")
        skip
      skip
    node T_1245 = eq(UInt<1>("h00"), state)
    when T_1245 :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact <- io.inner.acquire.bits
        xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data
        node T_1251 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1252 = bits(T_1251, 3, 3)
        node T_1254 = dshl(UInt<1>("h01"), T_1252)
        node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256)
        node T_1258 = bits(T_1254, 0, 0)
        node T_1259 = bits(T_1254, 1, 1)
        wire T_1261 : UInt<1>[2]
        T_1261[0] <= T_1258
        T_1261[1] <= T_1259
        node T_1266 = sub(UInt<8>("h00"), T_1261[0])
        node T_1267 = tail(T_1266, 1)
        node T_1269 = sub(UInt<8>("h00"), T_1261[1])
        node T_1270 = tail(T_1269, 1)
        wire T_1272 : UInt<8>[2]
        T_1272[0] <= T_1267
        T_1272[1] <= T_1270
        node T_1276 = cat(T_1272[1], T_1272[0])
        node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278)
        node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281)
        node T_1283 = or(T_1279, T_1282)
        node T_1284 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1286 = mux(T_1283, T_1284, UInt<16>("h00"))
        node T_1287 = mux(T_1257, T_1276, T_1286)
        xact.wmask_buffer[UInt<1>("h00")] <= T_1287
        node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
        wire T_1292 : UInt<3>[1]
        T_1292[0] <= UInt<3>("h03")
        node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type)
        node T_1297 = or(UInt<1>("h00"), T_1295)
        node T_1298 = and(T_1289, T_1297)
        collect_iacq_data <= T_1298
        wire T_1303 : UInt<3>[3]
        T_1303[0] <= UInt<3>("h02")
        T_1303[1] <= UInt<3>("h03")
        T_1303[2] <= UInt<3>("h04")
        node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type)
        node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type)
        node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type)
        node T_1312 = or(UInt<1>("h00"), T_1308)
        node T_1313 = or(T_1312, T_1309)
        node T_1314 = or(T_1313, T_1310)
        node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314)
        node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat)
        iacq_data_valid <= T_1316
        node T_1318 = neq(mask_incoherent, UInt<1>("h00"))
        when T_1318 :
          pending_probes <= mask_incoherent
          node T_1319 = bits(mask_incoherent, 0, 0)
          node T_1320 = bits(mask_incoherent, 1, 1)
          node T_1321 = bits(mask_incoherent, 2, 2)
          node T_1322 = bits(mask_incoherent, 3, 3)
          node T_1324 = cat(UInt<1>("h00"), T_1320)
          node T_1325 = add(T_1319, T_1324)
          node T_1326 = tail(T_1325, 1)
          node T_1329 = cat(UInt<1>("h00"), T_1322)
          node T_1330 = add(T_1321, T_1329)
          node T_1331 = tail(T_1330, 1)
          node T_1332 = cat(UInt<1>("h00"), T_1331)
          node T_1333 = add(T_1326, T_1332)
          node T_1334 = tail(T_1333, 1)
          release_count <= T_1334
          skip
        node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04"))
        node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335)
        node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336)
        state <= T_1337
        skip
      skip
    node T_1338 = eq(UInt<1>("h01"), state)
    when T_1338 :
      node T_1340 = neq(pending_probes, UInt<1>("h00"))
      io.inner.probe.valid <= T_1340
      when io.inner.probe.ready :
        node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00"))
        node T_1343 = not(T_1342)
        node T_1344 = and(pending_probes, T_1343)
        pending_probes <= T_1344
        skip
      wire T_1346 : UInt<2>[3]
      T_1346[0] <= UInt<1>("h00")
      T_1346[1] <= UInt<1>("h01")
      T_1346[2] <= UInt<2>("h02")
      node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type)
      node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type)
      node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type)
      node T_1355 = or(UInt<1>("h00"), T_1351)
      node T_1356 = or(T_1355, T_1352)
      node T_1357 = or(T_1356, T_1353)
      node T_1359 = eq(T_1357, UInt<1>("h00"))
      node T_1360 = or(T_1359, io.outer.acquire.ready)
      io.inner.release.ready <= T_1360
      when io.inner.release.valid :
        wire T_1362 : UInt<2>[3]
        T_1362[0] <= UInt<1>("h00")
        T_1362[1] <= UInt<1>("h01")
        T_1362[2] <= UInt<2>("h02")
        node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type)
        node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type)
        node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type)
        node T_1371 = or(UInt<1>("h00"), T_1367)
        node T_1372 = or(T_1371, T_1368)
        node T_1373 = or(T_1372, T_1369)
        when T_1373 :
          io.outer.acquire.valid <= UInt<1>("h01")
          when io.outer.acquire.ready :
            when oacq_data_done :
              pending_ognt_ack <= UInt<1>("h01")
              node T_1377 = sub(release_count, UInt<1>("h01"))
              node T_1378 = tail(T_1377, 1)
              release_count <= T_1378
              node T_1380 = eq(release_count, UInt<1>("h01"))
              when T_1380 :
                node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
                node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381)
                state <= T_1382
                skip
              skip
            skip
          skip
        node T_1384 = eq(T_1373, UInt<1>("h00"))
        when T_1384 :
          node T_1386 = sub(release_count, UInt<1>("h01"))
          node T_1387 = tail(T_1386, 1)
          release_count <= T_1387
          node T_1389 = eq(release_count, UInt<1>("h01"))
          when T_1389 :
            node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
            node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390)
            state <= T_1391
            skip
          skip
        skip
      skip
    node T_1392 = eq(UInt<2>("h03"), state)
    when T_1392 :
      node T_1394 = eq(pending_ognt_ack, UInt<1>("h00"))
      node T_1396 = eq(collect_iacq_data, UInt<1>("h00"))
      node T_1397 = dshr(iacq_data_valid, oacq_data_cnt)
      node T_1398 = bits(T_1397, 0, 0)
      node T_1399 = or(T_1396, T_1398)
      node T_1400 = and(T_1394, T_1399)
      io.outer.acquire.valid <= T_1400
      when oacq_data_done :
        pending_ognt_ack <= UInt<1>("h01")
        node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05"))
        state <= T_1402
        skip
      skip
    node T_1403 = eq(UInt<2>("h02"), state)
    when T_1403 :
      node T_1405 = eq(pending_ognt_ack, UInt<1>("h00"))
      io.outer.acquire.valid <= T_1405
      node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid)
      when T_1406 :
        state <= UInt<3>("h05")
        skip
      skip
    node T_1407 = eq(UInt<3>("h05"), state)
    when T_1407 :
      io.outer.grant.ready <= io.inner.grant.ready
      io.inner.grant.valid <= io.outer.grant.valid
      when ignt_data_done :
        node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412)
        node T_1415 = eq(T_1413, UInt<1>("h00"))
        node T_1416 = and(T_1410, T_1415)
        node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1417
        skip
      skip
    node T_1418 = eq(UInt<3>("h04"), state)
    when T_1418 :
      io.inner.grant.valid <= UInt<1>("h01")
      when io.inner.grant.ready :
        node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424)
        node T_1427 = eq(T_1425, UInt<1>("h00"))
        node T_1428 = and(T_1422, T_1427)
        node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1429
        skip
      skip
    node T_1430 = eq(UInt<3>("h06"), state)
    when T_1430 :
      io.inner.finish.ready <= UInt<1>("h01")
      when io.inner.finish.valid :
        state <= UInt<1>("h00")
        skip
      skip
    
  module BroadcastAcquireTracker_32 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
    wire coh : {sharers : UInt<1>}
    coh is invalid
    coh.sharers <= UInt<1>("h00")
    node T_303 = neq(state, UInt<1>("h00"))
    node T_304 = and(T_303, xact.is_builtin_type)
    wire T_309 : UInt<3>[3]
    T_309[0] <= UInt<3>("h04")
    T_309[1] <= UInt<3>("h05")
    T_309[2] <= UInt<3>("h06")
    node T_314 = eq(T_309[0], xact.a_type)
    node T_315 = eq(T_309[1], xact.a_type)
    node T_316 = eq(T_309[2], xact.a_type)
    node T_318 = or(UInt<1>("h00"), T_314)
    node T_319 = or(T_318, T_315)
    node T_320 = or(T_319, T_316)
    node T_321 = and(T_304, T_320)
    node T_323 = eq(T_321, UInt<1>("h00"))
    node T_325 = eq(reset, UInt<1>("h00"))
    when T_325 :
      node T_327 = eq(T_323, UInt<1>("h00"))
      when T_327 :
        node T_329 = eq(reset, UInt<1>("h00"))
        when T_329 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_334 = bits(pending_probes, 0, 0)
    wire T_336 : UInt<1>[1]
    T_336[0] <= T_334
    node T_341 = asUInt(asSInt(UInt<1>("h01")))
    node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id)
    node T_345 = or(T_341, T_344)
    node T_346 = not(T_341)
    node T_347 = or(T_346, T_344)
    node T_348 = not(T_347)
    node mask_self = mux(UInt<1>("h00"), T_345, T_348)
    node T_350 = not(io.incoherent[0])
    node mask_incoherent = and(mask_self, T_350)
    reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_362 : UInt<3>[1]
    T_362[0] <= UInt<3>("h03")
    node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type)
    node T_367 = or(UInt<1>("h00"), T_365)
    node T_368 = and(T_359, T_367)
    node T_369 = and(T_356, T_368)
    reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_369 :
      node T_373 = eq(T_371, UInt<2>("h03"))
      node T_375 = and(UInt<1>("h00"), T_373)
      node T_378 = add(T_371, UInt<1>("h01"))
      node T_379 = tail(T_378, 1)
      node T_380 = mux(T_375, UInt<1>("h00"), T_379)
      T_371 <= T_380
      skip
    node T_381 = and(T_369, T_373)
    node T_382 = mux(T_368, T_371, UInt<1>("h00"))
    node iacq_data_done = mux(T_368, T_381, T_356)
    node T_384 = and(io.inner.release.ready, io.inner.release.valid)
    wire T_388 : UInt<2>[3]
    T_388[0] <= UInt<1>("h00")
    T_388[1] <= UInt<1>("h01")
    T_388[2] <= UInt<2>("h02")
    node T_393 = eq(T_388[0], io.inner.release.bits.r_type)
    node T_394 = eq(T_388[1], io.inner.release.bits.r_type)
    node T_395 = eq(T_388[2], io.inner.release.bits.r_type)
    node T_397 = or(UInt<1>("h00"), T_393)
    node T_398 = or(T_397, T_394)
    node T_399 = or(T_398, T_395)
    node T_400 = and(UInt<1>("h01"), T_399)
    node T_401 = and(T_384, T_400)
    reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_401 :
      node T_405 = eq(T_403, UInt<2>("h03"))
      node T_407 = and(UInt<1>("h00"), T_405)
      node T_410 = add(T_403, UInt<1>("h01"))
      node T_411 = tail(T_410, 1)
      node T_412 = mux(T_407, UInt<1>("h00"), T_411)
      T_403 <= T_412
      skip
    node T_413 = and(T_401, T_405)
    node T_414 = mux(T_400, T_403, UInt<1>("h00"))
    node irel_data_done = mux(T_400, T_413, T_384)
    node T_417 = and(io.inner.grant.ready, io.inner.grant.valid)
    wire T_421 : UInt<3>[1]
    T_421[0] <= UInt<3>("h05")
    node T_424 = eq(T_421[0], io.inner.grant.bits.g_type)
    node T_426 = or(UInt<1>("h00"), T_424)
    wire T_428 : UInt<1>[2]
    T_428[0] <= UInt<1>("h00")
    T_428[1] <= UInt<1>("h01")
    node T_432 = eq(T_428[0], io.inner.grant.bits.g_type)
    node T_433 = eq(T_428[1], io.inner.grant.bits.g_type)
    node T_435 = or(UInt<1>("h00"), T_432)
    node T_436 = or(T_435, T_433)
    node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436)
    node T_438 = and(UInt<1>("h01"), T_437)
    node T_439 = and(T_417, T_438)
    reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_439 :
      node T_443 = eq(T_441, UInt<2>("h03"))
      node T_445 = and(UInt<1>("h00"), T_443)
      node T_448 = add(T_441, UInt<1>("h01"))
      node T_449 = tail(T_448, 1)
      node T_450 = mux(T_445, UInt<1>("h00"), T_449)
      T_441 <= T_450
      skip
    node T_451 = and(T_439, T_443)
    node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00"))
    node ignt_data_done = mux(T_438, T_451, T_417)
    node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type)
    wire T_460 : UInt<3>[1]
    T_460[0] <= UInt<3>("h03")
    node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type)
    node T_465 = or(UInt<1>("h00"), T_463)
    node T_466 = and(T_457, T_465)
    node T_467 = and(T_455, T_466)
    reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_467 :
      node T_471 = eq(T_469, UInt<2>("h03"))
      node T_473 = and(UInt<1>("h00"), T_471)
      node T_476 = add(T_469, UInt<1>("h01"))
      node T_477 = tail(T_476, 1)
      node T_478 = mux(T_473, UInt<1>("h00"), T_477)
      T_469 <= T_478
      skip
    node T_479 = and(T_467, T_471)
    node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00"))
    node oacq_data_done = mux(T_466, T_479, T_455)
    node T_482 = and(io.outer.grant.ready, io.outer.grant.valid)
    wire T_487 : UInt<3>[1]
    T_487[0] <= UInt<3>("h05")
    node T_490 = eq(T_487[0], io.outer.grant.bits.g_type)
    node T_492 = or(UInt<1>("h00"), T_490)
    wire T_494 : UInt<1>[1]
    T_494[0] <= UInt<1>("h00")
    node T_497 = eq(T_494[0], io.outer.grant.bits.g_type)
    node T_499 = or(UInt<1>("h00"), T_497)
    node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499)
    node T_501 = and(UInt<1>("h01"), T_500)
    node T_502 = and(T_482, T_501)
    reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_502 :
      node T_506 = eq(T_504, UInt<2>("h03"))
      node T_508 = and(UInt<1>("h00"), T_506)
      node T_511 = add(T_504, UInt<1>("h01"))
      node T_512 = tail(T_511, 1)
      node T_513 = mux(T_508, UInt<1>("h00"), T_512)
      T_504 <= T_513
      skip
    node T_514 = and(T_502, T_506)
    node T_515 = mux(T_501, T_504, UInt<1>("h00"))
    node ognt_data_done = mux(T_501, T_514, T_482)
    reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_523 : UInt<3>[3]
    T_523[0] <= UInt<3>("h02")
    T_523[1] <= UInt<3>("h03")
    T_523[2] <= UInt<3>("h04")
    node T_528 = eq(T_523[0], xact.a_type)
    node T_529 = eq(T_523[1], xact.a_type)
    node T_530 = eq(T_523[2], xact.a_type)
    node T_532 = or(UInt<1>("h00"), T_528)
    node T_533 = or(T_532, T_529)
    node T_534 = or(T_533, T_530)
    node pending_outer_write = and(xact.is_builtin_type, T_534)
    wire T_540 : UInt<3>[3]
    T_540[0] <= UInt<3>("h02")
    T_540[1] <= UInt<3>("h03")
    T_540[2] <= UInt<3>("h04")
    node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type)
    node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type)
    node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type)
    node T_549 = or(UInt<1>("h00"), T_545)
    node T_550 = or(T_549, T_546)
    node T_551 = or(T_550, T_547)
    node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551)
    wire T_556 : UInt<3>[2]
    T_556[0] <= UInt<3>("h05")
    T_556[1] <= UInt<3>("h04")
    node T_560 = eq(T_556[0], io.inner.grant.bits.g_type)
    node T_561 = eq(T_556[1], io.inner.grant.bits.g_type)
    node T_563 = or(UInt<1>("h00"), T_560)
    node T_564 = or(T_563, T_561)
    wire T_566 : UInt<1>[2]
    T_566[0] <= UInt<1>("h00")
    T_566[1] <= UInt<1>("h01")
    node T_570 = eq(T_566[0], io.inner.grant.bits.g_type)
    node T_571 = eq(T_566[1], io.inner.grant.bits.g_type)
    node T_573 = or(UInt<1>("h00"), T_570)
    node T_574 = or(T_573, T_571)
    node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574)
    node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type)
    node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03"))
    node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type)
    node T_597 = mux(T_596, UInt<3>("h01"), T_595)
    node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type)
    node T_599 = mux(T_598, UInt<3>("h04"), T_597)
    node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type)
    node T_601 = mux(T_600, UInt<3>("h03"), T_599)
    node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type)
    node T_603 = mux(T_602, UInt<3>("h03"), T_601)
    node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type)
    node T_605 = mux(T_604, UInt<3>("h05"), T_603)
    node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type)
    node T_607 = mux(T_606, UInt<3>("h04"), T_605)
    node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00"))
    node T_611 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01"))
    node T_613 = mux(T_608, T_612, UInt<1>("h01"))
    node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613)
    wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_623 is invalid
    T_623.client_id <= io.inner.acquire.bits.client_id
    T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type
    T_623.g_type <= T_614
    T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id
    T_623.manager_xact_id <= UInt<3>("h07")
    T_623.addr_beat <= UInt<1>("h00")
    T_623.data <= UInt<1>("h00")
    wire T_634 : UInt<3>[2]
    T_634[0] <= UInt<3>("h05")
    T_634[1] <= UInt<3>("h04")
    node T_638 = eq(T_634[0], T_623.g_type)
    node T_639 = eq(T_634[1], T_623.g_type)
    node T_641 = or(UInt<1>("h00"), T_638)
    node T_642 = or(T_641, T_639)
    wire T_644 : UInt<1>[2]
    T_644[0] <= UInt<1>("h00")
    T_644[1] <= UInt<1>("h01")
    node T_648 = eq(T_644[0], T_623.g_type)
    node T_649 = eq(T_644[1], T_623.g_type)
    node T_651 = or(UInt<1>("h00"), T_648)
    node T_652 = or(T_651, T_649)
    node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652)
    wire T_658 : UInt<3>[3]
    T_658[0] <= UInt<3>("h02")
    T_658[1] <= UInt<3>("h00")
    T_658[2] <= UInt<3>("h04")
    node T_663 = eq(T_658[0], xact.a_type)
    node T_664 = eq(T_658[1], xact.a_type)
    node T_665 = eq(T_658[2], xact.a_type)
    node T_667 = or(UInt<1>("h00"), T_663)
    node T_668 = or(T_667, T_664)
    node T_669 = or(T_668, T_665)
    node subblock_type = and(xact.is_builtin_type, T_669)
    node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_672 = neq(state, UInt<1>("h00"))
    node T_673 = and(T_671, T_672)
    node T_675 = eq(collect_iacq_data, UInt<1>("h00"))
    node T_676 = and(T_673, T_675)
    io.has_acquire_conflict <= T_676
    node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block)
    node T_678 = and(T_677, collect_iacq_data)
    io.has_acquire_match <= T_678
    node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block)
    node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00"))
    node T_682 = and(T_679, T_681)
    node T_683 = eq(state, UInt<1>("h01"))
    node T_684 = and(T_682, T_683)
    io.has_release_match <= T_684
    node T_689 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_695 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_696 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_697 = cat(T_695, T_696)
    node T_699 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_700 = cat(UInt<3>("h07"), T_699)
    node T_702 = cat(T_689, UInt<1>("h01"))
    node T_704 = cat(T_689, UInt<1>("h01"))
    node T_706 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_707 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_708 = cat(T_706, T_707)
    node T_710 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_712 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_713 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_714 = mux(T_713, T_712, UInt<1>("h00"))
    node T_715 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_716 = mux(T_715, T_710, T_714)
    node T_717 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_718 = mux(T_717, T_708, T_716)
    node T_719 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_720 = mux(T_719, T_704, T_718)
    node T_721 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_722 = mux(T_721, T_702, T_720)
    node T_723 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_724 = mux(T_723, T_700, T_722)
    node T_725 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_726 = mux(T_725, T_697, T_724)
    wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_probe is invalid
    oacq_probe.is_builtin_type <= UInt<1>("h01")
    oacq_probe.a_type <= UInt<3>("h03")
    oacq_probe.client_xact_id <= UInt<3>("h07")
    oacq_probe.addr_block <= io.inner.release.bits.addr_block
    oacq_probe.addr_beat <= io.inner.release.bits.addr_beat
    oacq_probe.data <= io.inner.release.bits.data
    oacq_probe.union <= T_726
    node T_744 = bits(xact.union, 12, 9)
    node T_745 = bits(T_744, 3, 3)
    node T_747 = dshl(UInt<1>("h01"), T_745)
    node T_749 = eq(xact.a_type, UInt<3>("h04"))
    node T_750 = and(xact.is_builtin_type, T_749)
    node T_751 = bits(T_747, 0, 0)
    node T_752 = bits(T_747, 1, 1)
    wire T_754 : UInt<1>[2]
    T_754[0] <= T_751
    T_754[1] <= T_752
    node T_759 = sub(UInt<8>("h00"), T_754[0])
    node T_760 = tail(T_759, 1)
    node T_762 = sub(UInt<8>("h00"), T_754[1])
    node T_763 = tail(T_762, 1)
    wire T_765 : UInt<8>[2]
    T_765[0] <= T_760
    T_765[1] <= T_763
    node T_769 = cat(T_765[1], T_765[0])
    node T_771 = eq(xact.a_type, UInt<3>("h03"))
    node T_772 = and(xact.is_builtin_type, T_771)
    node T_774 = eq(xact.a_type, UInt<3>("h02"))
    node T_775 = and(xact.is_builtin_type, T_774)
    node T_776 = or(T_772, T_775)
    node T_777 = bits(xact.union, 16, 1)
    node T_779 = mux(T_776, T_777, UInt<16>("h00"))
    node T_780 = mux(T_750, T_769, T_779)
    node T_788 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_789 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_790 = cat(T_788, T_789)
    node T_792 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_793 = cat(UInt<3>("h07"), T_792)
    node T_795 = cat(T_780, UInt<1>("h01"))
    node T_797 = cat(T_780, UInt<1>("h01"))
    node T_799 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_800 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_801 = cat(T_799, T_800)
    node T_803 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_805 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_806 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_807 = mux(T_806, T_805, UInt<1>("h00"))
    node T_808 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_809 = mux(T_808, T_803, T_807)
    node T_810 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_811 = mux(T_810, T_801, T_809)
    node T_812 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_813 = mux(T_812, T_797, T_811)
    node T_814 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_815 = mux(T_814, T_795, T_813)
    node T_816 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_817 = mux(T_816, T_793, T_815)
    node T_818 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_819 = mux(T_818, T_790, T_817)
    wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_beat is invalid
    oacq_write_beat.is_builtin_type <= UInt<1>("h01")
    oacq_write_beat.a_type <= UInt<3>("h02")
    oacq_write_beat.client_xact_id <= UInt<3>("h07")
    oacq_write_beat.addr_block <= xact.addr_block
    oacq_write_beat.addr_beat <= xact.addr_beat
    oacq_write_beat.data <= xact.data_buffer[0]
    oacq_write_beat.union <= T_819
    node T_846 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_847 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_848 = cat(T_846, T_847)
    node T_850 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_851 = cat(UInt<3>("h07"), T_850)
    node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01"))
    node T_857 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_858 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_859 = cat(T_857, T_858)
    node T_861 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_863 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_864 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_865 = mux(T_864, T_863, UInt<1>("h00"))
    node T_866 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_867 = mux(T_866, T_861, T_865)
    node T_868 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_869 = mux(T_868, T_859, T_867)
    node T_870 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_871 = mux(T_870, T_855, T_869)
    node T_872 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_873 = mux(T_872, T_853, T_871)
    node T_874 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_875 = mux(T_874, T_851, T_873)
    node T_876 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_877 = mux(T_876, T_848, T_875)
    wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_write_block is invalid
    oacq_write_block.is_builtin_type <= UInt<1>("h01")
    oacq_write_block.a_type <= UInt<3>("h03")
    oacq_write_block.client_xact_id <= UInt<3>("h07")
    oacq_write_block.addr_block <= xact.addr_block
    oacq_write_block.addr_beat <= oacq_data_cnt
    oacq_write_block.data <= xact.data_buffer[oacq_data_cnt]
    oacq_write_block.union <= T_877
    node T_895 = bits(xact.union, 12, 9)
    node T_896 = bits(xact.union, 8, 6)
    node T_904 = cat(T_895, T_896)
    node T_905 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_906 = cat(T_904, T_905)
    node T_908 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_909 = cat(T_896, T_908)
    node T_911 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_913 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_915 = cat(T_895, T_896)
    node T_916 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_917 = cat(T_915, T_916)
    node T_919 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_921 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_922 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_923 = mux(T_922, T_921, UInt<1>("h00"))
    node T_924 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_925 = mux(T_924, T_919, T_923)
    node T_926 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_927 = mux(T_926, T_917, T_925)
    node T_928 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_929 = mux(T_928, T_913, T_927)
    node T_930 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_931 = mux(T_930, T_911, T_929)
    node T_932 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_933 = mux(T_932, T_909, T_931)
    node T_934 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_935 = mux(T_934, T_906, T_933)
    wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_beat is invalid
    oacq_read_beat.is_builtin_type <= UInt<1>("h01")
    oacq_read_beat.a_type <= UInt<3>("h00")
    oacq_read_beat.client_xact_id <= UInt<3>("h07")
    oacq_read_beat.addr_block <= xact.addr_block
    oacq_read_beat.addr_beat <= xact.addr_beat
    oacq_read_beat.data <= UInt<1>("h00")
    oacq_read_beat.union <= T_935
    node T_962 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_963 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_964 = cat(T_962, T_963)
    node T_966 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_967 = cat(UInt<3>("h07"), T_966)
    node T_969 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_971 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_973 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_974 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_975 = cat(T_973, T_974)
    node T_977 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_979 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_980 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_981 = mux(T_980, T_979, UInt<1>("h00"))
    node T_982 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_983 = mux(T_982, T_977, T_981)
    node T_984 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_985 = mux(T_984, T_975, T_983)
    node T_986 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_987 = mux(T_986, T_971, T_985)
    node T_988 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_989 = mux(T_988, T_969, T_987)
    node T_990 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_991 = mux(T_990, T_967, T_989)
    node T_992 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_993 = mux(T_992, T_964, T_991)
    wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}
    oacq_read_block is invalid
    oacq_read_block.is_builtin_type <= UInt<1>("h01")
    oacq_read_block.a_type <= UInt<3>("h01")
    oacq_read_block.client_xact_id <= UInt<3>("h07")
    oacq_read_block.addr_block <= xact.addr_block
    oacq_read_block.addr_beat <= UInt<1>("h00")
    oacq_read_block.data <= UInt<1>("h00")
    oacq_read_block.union <= T_993
    io.outer.acquire.valid <= UInt<1>("h00")
    node T_1011 = eq(state, UInt<1>("h01"))
    node T_1012 = eq(state, UInt<2>("h03"))
    node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block)
    node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block)
    node T_1029 = mux(T_1012, T_1013, T_1021)
    node T_1037 = mux(T_1011, oacq_probe, T_1029)
    io.outer.acquire.bits <- T_1037
    io.outer.grant.ready <= UInt<1>("h00")
    io.inner.probe.valid <= UInt<1>("h00")
    node T_1054 = eq(UInt<3>("h04"), xact.a_type)
    node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02"))
    node T_1056 = eq(UInt<3>("h06"), xact.a_type)
    node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055)
    node T_1058 = eq(UInt<3>("h05"), xact.a_type)
    node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057)
    node T_1060 = eq(UInt<3>("h02"), xact.a_type)
    node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059)
    node T_1062 = eq(UInt<3>("h00"), xact.a_type)
    node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061)
    node T_1064 = eq(UInt<3>("h03"), xact.a_type)
    node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063)
    node T_1066 = eq(UInt<3>("h01"), xact.a_type)
    node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065)
    node T_1068 = eq(UInt<1>("h01"), xact.a_type)
    node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02"))
    node T_1070 = eq(UInt<1>("h00"), xact.a_type)
    node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069)
    node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071)
    wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_1077 is invalid
    T_1077.client_id <= UInt<1>("h00")
    T_1077.p_type <= T_1072
    T_1077.addr_block <= xact.addr_block
    io.inner.probe.bits <- T_1077
    io.inner.grant.valid <= UInt<1>("h00")
    node T_1100 = eq(UInt<3>("h06"), xact.a_type)
    node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03"))
    node T_1102 = eq(UInt<3>("h05"), xact.a_type)
    node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101)
    node T_1104 = eq(UInt<3>("h04"), xact.a_type)
    node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103)
    node T_1106 = eq(UInt<3>("h03"), xact.a_type)
    node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105)
    node T_1108 = eq(UInt<3>("h02"), xact.a_type)
    node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107)
    node T_1110 = eq(UInt<3>("h01"), xact.a_type)
    node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109)
    node T_1112 = eq(UInt<3>("h00"), xact.a_type)
    node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111)
    node T_1114 = eq(xact.a_type, UInt<1>("h00"))
    node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01"))
    node T_1119 = mux(T_1114, T_1118, UInt<1>("h01"))
    node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119)
    wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}
    T_1129 is invalid
    T_1129.client_id <= xact.client_id
    T_1129.is_builtin_type <= xact.is_builtin_type
    T_1129.g_type <= T_1120
    T_1129.client_xact_id <= xact.client_xact_id
    T_1129.manager_xact_id <= UInt<3>("h07")
    T_1129.addr_beat <= UInt<1>("h00")
    T_1129.data <= UInt<1>("h00")
    io.inner.grant.bits <- T_1129
    io.inner.acquire.ready <= UInt<1>("h00")
    io.inner.release.ready <= UInt<1>("h00")
    io.inner.finish.ready <= UInt<1>("h00")
    node T_1140 = neq(state, UInt<1>("h00"))
    node T_1141 = and(T_1140, collect_iacq_data)
    node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1143 = and(T_1141, T_1142)
    node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id)
    node T_1145 = and(T_1143, T_1144)
    node T_1147 = eq(T_1145, UInt<1>("h00"))
    node T_1149 = eq(reset, UInt<1>("h00"))
    when T_1149 :
      node T_1151 = eq(T_1147, UInt<1>("h00"))
      when T_1151 :
        node T_1153 = eq(reset, UInt<1>("h00"))
        when T_1153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1154 = neq(state, UInt<1>("h00"))
    node T_1155 = and(T_1154, collect_iacq_data)
    node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1157 = and(T_1155, T_1156)
    node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id)
    node T_1159 = and(T_1157, T_1158)
    node T_1161 = eq(T_1159, UInt<1>("h00"))
    node T_1163 = eq(reset, UInt<1>("h00"))
    when T_1163 :
      node T_1165 = eq(T_1161, UInt<1>("h00"))
      when T_1165 :
        node T_1167 = eq(reset, UInt<1>("h00"))
        when T_1167 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1168 = eq(state, UInt<1>("h00"))
    node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    node T_1170 = and(T_1168, T_1169)
    node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
    wire T_1175 : UInt<3>[1]
    T_1175[0] <= UInt<3>("h03")
    node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type)
    node T_1180 = or(UInt<1>("h00"), T_1178)
    node T_1181 = and(T_1172, T_1180)
    node T_1182 = and(T_1170, T_1181)
    node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00"))
    node T_1185 = and(T_1182, T_1184)
    node T_1187 = eq(T_1185, UInt<1>("h00"))
    node T_1189 = eq(reset, UInt<1>("h00"))
    when T_1189 :
      node T_1191 = eq(T_1187, UInt<1>("h00"))
      when T_1191 :
        node T_1193 = eq(reset, UInt<1>("h00"))
        when T_1193 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    when collect_iacq_data :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data
        node T_1197 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1198 = bits(T_1197, 3, 3)
        node T_1200 = dshl(UInt<1>("h01"), T_1198)
        node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202)
        node T_1204 = bits(T_1200, 0, 0)
        node T_1205 = bits(T_1200, 1, 1)
        wire T_1207 : UInt<1>[2]
        T_1207[0] <= T_1204
        T_1207[1] <= T_1205
        node T_1212 = sub(UInt<8>("h00"), T_1207[0])
        node T_1213 = tail(T_1212, 1)
        node T_1215 = sub(UInt<8>("h00"), T_1207[1])
        node T_1216 = tail(T_1215, 1)
        wire T_1218 : UInt<8>[2]
        T_1218[0] <= T_1213
        T_1218[1] <= T_1216
        node T_1222 = cat(T_1218[1], T_1218[0])
        node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224)
        node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227)
        node T_1229 = or(T_1225, T_1228)
        node T_1230 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1232 = mux(T_1229, T_1230, UInt<16>("h00"))
        node T_1233 = mux(T_1203, T_1222, T_1232)
        xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233
        node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat)
        node T_1237 = or(iacq_data_valid, T_1236)
        node T_1238 = not(iacq_data_valid)
        node T_1239 = or(T_1238, T_1236)
        node T_1240 = not(T_1239)
        node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240)
        iacq_data_valid <= T_1241
        skip
      when iacq_data_done :
        collect_iacq_data <= UInt<1>("h00")
        skip
      skip
    when pending_ognt_ack :
      io.outer.grant.ready <= UInt<1>("h01")
      when io.outer.grant.valid :
        pending_ognt_ack <= UInt<1>("h00")
        skip
      skip
    node T_1245 = eq(UInt<1>("h00"), state)
    when T_1245 :
      io.inner.acquire.ready <= UInt<1>("h01")
      when io.inner.acquire.valid :
        xact <- io.inner.acquire.bits
        xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data
        node T_1251 = bits(io.inner.acquire.bits.union, 12, 9)
        node T_1252 = bits(T_1251, 3, 3)
        node T_1254 = dshl(UInt<1>("h01"), T_1252)
        node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04"))
        node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256)
        node T_1258 = bits(T_1254, 0, 0)
        node T_1259 = bits(T_1254, 1, 1)
        wire T_1261 : UInt<1>[2]
        T_1261[0] <= T_1258
        T_1261[1] <= T_1259
        node T_1266 = sub(UInt<8>("h00"), T_1261[0])
        node T_1267 = tail(T_1266, 1)
        node T_1269 = sub(UInt<8>("h00"), T_1261[1])
        node T_1270 = tail(T_1269, 1)
        wire T_1272 : UInt<8>[2]
        T_1272[0] <= T_1267
        T_1272[1] <= T_1270
        node T_1276 = cat(T_1272[1], T_1272[0])
        node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03"))
        node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278)
        node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02"))
        node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281)
        node T_1283 = or(T_1279, T_1282)
        node T_1284 = bits(io.inner.acquire.bits.union, 16, 1)
        node T_1286 = mux(T_1283, T_1284, UInt<16>("h00"))
        node T_1287 = mux(T_1257, T_1276, T_1286)
        xact.wmask_buffer[UInt<1>("h00")] <= T_1287
        node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type)
        wire T_1292 : UInt<3>[1]
        T_1292[0] <= UInt<3>("h03")
        node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type)
        node T_1297 = or(UInt<1>("h00"), T_1295)
        node T_1298 = and(T_1289, T_1297)
        collect_iacq_data <= T_1298
        wire T_1303 : UInt<3>[3]
        T_1303[0] <= UInt<3>("h02")
        T_1303[1] <= UInt<3>("h03")
        T_1303[2] <= UInt<3>("h04")
        node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type)
        node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type)
        node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type)
        node T_1312 = or(UInt<1>("h00"), T_1308)
        node T_1313 = or(T_1312, T_1309)
        node T_1314 = or(T_1313, T_1310)
        node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314)
        node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat)
        iacq_data_valid <= T_1316
        node T_1318 = neq(mask_incoherent, UInt<1>("h00"))
        when T_1318 :
          pending_probes <= mask_incoherent
          node T_1319 = bits(mask_incoherent, 0, 0)
          node T_1320 = bits(mask_incoherent, 1, 1)
          node T_1321 = bits(mask_incoherent, 2, 2)
          node T_1322 = bits(mask_incoherent, 3, 3)
          node T_1324 = cat(UInt<1>("h00"), T_1320)
          node T_1325 = add(T_1319, T_1324)
          node T_1326 = tail(T_1325, 1)
          node T_1329 = cat(UInt<1>("h00"), T_1322)
          node T_1330 = add(T_1321, T_1329)
          node T_1331 = tail(T_1330, 1)
          node T_1332 = cat(UInt<1>("h00"), T_1331)
          node T_1333 = add(T_1326, T_1332)
          node T_1334 = tail(T_1333, 1)
          release_count <= T_1334
          skip
        node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04"))
        node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335)
        node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336)
        state <= T_1337
        skip
      skip
    node T_1338 = eq(UInt<1>("h01"), state)
    when T_1338 :
      node T_1340 = neq(pending_probes, UInt<1>("h00"))
      io.inner.probe.valid <= T_1340
      when io.inner.probe.ready :
        node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00"))
        node T_1343 = not(T_1342)
        node T_1344 = and(pending_probes, T_1343)
        pending_probes <= T_1344
        skip
      wire T_1346 : UInt<2>[3]
      T_1346[0] <= UInt<1>("h00")
      T_1346[1] <= UInt<1>("h01")
      T_1346[2] <= UInt<2>("h02")
      node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type)
      node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type)
      node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type)
      node T_1355 = or(UInt<1>("h00"), T_1351)
      node T_1356 = or(T_1355, T_1352)
      node T_1357 = or(T_1356, T_1353)
      node T_1359 = eq(T_1357, UInt<1>("h00"))
      node T_1360 = or(T_1359, io.outer.acquire.ready)
      io.inner.release.ready <= T_1360
      when io.inner.release.valid :
        wire T_1362 : UInt<2>[3]
        T_1362[0] <= UInt<1>("h00")
        T_1362[1] <= UInt<1>("h01")
        T_1362[2] <= UInt<2>("h02")
        node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type)
        node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type)
        node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type)
        node T_1371 = or(UInt<1>("h00"), T_1367)
        node T_1372 = or(T_1371, T_1368)
        node T_1373 = or(T_1372, T_1369)
        when T_1373 :
          io.outer.acquire.valid <= UInt<1>("h01")
          when io.outer.acquire.ready :
            when oacq_data_done :
              pending_ognt_ack <= UInt<1>("h01")
              node T_1377 = sub(release_count, UInt<1>("h01"))
              node T_1378 = tail(T_1377, 1)
              release_count <= T_1378
              node T_1380 = eq(release_count, UInt<1>("h01"))
              when T_1380 :
                node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
                node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381)
                state <= T_1382
                skip
              skip
            skip
          skip
        node T_1384 = eq(T_1373, UInt<1>("h00"))
        when T_1384 :
          node T_1386 = sub(release_count, UInt<1>("h01"))
          node T_1387 = tail(T_1386, 1)
          release_count <= T_1387
          node T_1389 = eq(release_count, UInt<1>("h01"))
          when T_1389 :
            node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04"))
            node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390)
            state <= T_1391
            skip
          skip
        skip
      skip
    node T_1392 = eq(UInt<2>("h03"), state)
    when T_1392 :
      node T_1394 = eq(pending_ognt_ack, UInt<1>("h00"))
      node T_1396 = eq(collect_iacq_data, UInt<1>("h00"))
      node T_1397 = dshr(iacq_data_valid, oacq_data_cnt)
      node T_1398 = bits(T_1397, 0, 0)
      node T_1399 = or(T_1396, T_1398)
      node T_1400 = and(T_1394, T_1399)
      io.outer.acquire.valid <= T_1400
      when oacq_data_done :
        pending_ognt_ack <= UInt<1>("h01")
        node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05"))
        state <= T_1402
        skip
      skip
    node T_1403 = eq(UInt<2>("h02"), state)
    when T_1403 :
      node T_1405 = eq(pending_ognt_ack, UInt<1>("h00"))
      io.outer.acquire.valid <= T_1405
      node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid)
      when T_1406 :
        state <= UInt<3>("h05")
        skip
      skip
    node T_1407 = eq(UInt<3>("h05"), state)
    when T_1407 :
      io.outer.grant.ready <= io.inner.grant.ready
      io.inner.grant.valid <= io.outer.grant.valid
      when ignt_data_done :
        node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412)
        node T_1415 = eq(T_1413, UInt<1>("h00"))
        node T_1416 = and(T_1410, T_1415)
        node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1417
        skip
      skip
    node T_1418 = eq(UInt<3>("h04"), state)
    when T_1418 :
      io.inner.grant.valid <= UInt<1>("h01")
      when io.inner.grant.ready :
        node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00"))
        node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00"))
        node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424)
        node T_1427 = eq(T_1425, UInt<1>("h00"))
        node T_1428 = and(T_1422, T_1427)
        node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00"))
        state <= T_1429
        skip
      skip
    node T_1430 = eq(UInt<3>("h06"), state)
    when T_1430 :
      io.inner.finish.ready <= UInt<1>("h01")
      when io.inner.finish.valid :
        state <= UInt<1>("h00")
        skip
      skip
    
  module LockingRRArbiter_33 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, chosen : UInt<3>}
    
    io is invalid
    reg T_1502 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_1504 : UInt, clk with : (reset => (reset, UInt<3>("h07")))
    wire T_1506 : UInt<3>
    T_1506 is invalid
    io.out.valid <= io.in[T_1506].valid
    io.out.bits <- io.in[T_1506].bits
    io.chosen <= T_1506
    io.in[T_1506].ready <= UInt<1>("h00")
    reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    node T_1706 = gt(UInt<1>("h00"), last_grant)
    node T_1707 = and(io.in[0].valid, T_1706)
    node T_1709 = gt(UInt<1>("h01"), last_grant)
    node T_1710 = and(io.in[1].valid, T_1709)
    node T_1712 = gt(UInt<2>("h02"), last_grant)
    node T_1713 = and(io.in[2].valid, T_1712)
    node T_1715 = gt(UInt<2>("h03"), last_grant)
    node T_1716 = and(io.in[3].valid, T_1715)
    node T_1718 = gt(UInt<3>("h04"), last_grant)
    node T_1719 = and(io.in[4].valid, T_1718)
    node T_1721 = gt(UInt<3>("h05"), last_grant)
    node T_1722 = and(io.in[5].valid, T_1721)
    node T_1724 = gt(UInt<3>("h06"), last_grant)
    node T_1725 = and(io.in[6].valid, T_1724)
    node T_1727 = gt(UInt<3>("h07"), last_grant)
    node T_1728 = and(io.in[7].valid, T_1727)
    node T_1731 = or(UInt<1>("h00"), T_1707)
    node T_1733 = eq(T_1731, UInt<1>("h00"))
    node T_1735 = or(UInt<1>("h00"), T_1707)
    node T_1736 = or(T_1735, T_1710)
    node T_1738 = eq(T_1736, UInt<1>("h00"))
    node T_1740 = or(UInt<1>("h00"), T_1707)
    node T_1741 = or(T_1740, T_1710)
    node T_1742 = or(T_1741, T_1713)
    node T_1744 = eq(T_1742, UInt<1>("h00"))
    node T_1746 = or(UInt<1>("h00"), T_1707)
    node T_1747 = or(T_1746, T_1710)
    node T_1748 = or(T_1747, T_1713)
    node T_1749 = or(T_1748, T_1716)
    node T_1751 = eq(T_1749, UInt<1>("h00"))
    node T_1753 = or(UInt<1>("h00"), T_1707)
    node T_1754 = or(T_1753, T_1710)
    node T_1755 = or(T_1754, T_1713)
    node T_1756 = or(T_1755, T_1716)
    node T_1757 = or(T_1756, T_1719)
    node T_1759 = eq(T_1757, UInt<1>("h00"))
    node T_1761 = or(UInt<1>("h00"), T_1707)
    node T_1762 = or(T_1761, T_1710)
    node T_1763 = or(T_1762, T_1713)
    node T_1764 = or(T_1763, T_1716)
    node T_1765 = or(T_1764, T_1719)
    node T_1766 = or(T_1765, T_1722)
    node T_1768 = eq(T_1766, UInt<1>("h00"))
    node T_1770 = or(UInt<1>("h00"), T_1707)
    node T_1771 = or(T_1770, T_1710)
    node T_1772 = or(T_1771, T_1713)
    node T_1773 = or(T_1772, T_1716)
    node T_1774 = or(T_1773, T_1719)
    node T_1775 = or(T_1774, T_1722)
    node T_1776 = or(T_1775, T_1725)
    node T_1778 = eq(T_1776, UInt<1>("h00"))
    node T_1780 = or(UInt<1>("h00"), T_1707)
    node T_1781 = or(T_1780, T_1710)
    node T_1782 = or(T_1781, T_1713)
    node T_1783 = or(T_1782, T_1716)
    node T_1784 = or(T_1783, T_1719)
    node T_1785 = or(T_1784, T_1722)
    node T_1786 = or(T_1785, T_1725)
    node T_1787 = or(T_1786, T_1728)
    node T_1789 = eq(T_1787, UInt<1>("h00"))
    node T_1791 = or(UInt<1>("h00"), T_1707)
    node T_1792 = or(T_1791, T_1710)
    node T_1793 = or(T_1792, T_1713)
    node T_1794 = or(T_1793, T_1716)
    node T_1795 = or(T_1794, T_1719)
    node T_1796 = or(T_1795, T_1722)
    node T_1797 = or(T_1796, T_1725)
    node T_1798 = or(T_1797, T_1728)
    node T_1799 = or(T_1798, io.in[0].valid)
    node T_1801 = eq(T_1799, UInt<1>("h00"))
    node T_1803 = or(UInt<1>("h00"), T_1707)
    node T_1804 = or(T_1803, T_1710)
    node T_1805 = or(T_1804, T_1713)
    node T_1806 = or(T_1805, T_1716)
    node T_1807 = or(T_1806, T_1719)
    node T_1808 = or(T_1807, T_1722)
    node T_1809 = or(T_1808, T_1725)
    node T_1810 = or(T_1809, T_1728)
    node T_1811 = or(T_1810, io.in[0].valid)
    node T_1812 = or(T_1811, io.in[1].valid)
    node T_1814 = eq(T_1812, UInt<1>("h00"))
    node T_1816 = or(UInt<1>("h00"), T_1707)
    node T_1817 = or(T_1816, T_1710)
    node T_1818 = or(T_1817, T_1713)
    node T_1819 = or(T_1818, T_1716)
    node T_1820 = or(T_1819, T_1719)
    node T_1821 = or(T_1820, T_1722)
    node T_1822 = or(T_1821, T_1725)
    node T_1823 = or(T_1822, T_1728)
    node T_1824 = or(T_1823, io.in[0].valid)
    node T_1825 = or(T_1824, io.in[1].valid)
    node T_1826 = or(T_1825, io.in[2].valid)
    node T_1828 = eq(T_1826, UInt<1>("h00"))
    node T_1830 = or(UInt<1>("h00"), T_1707)
    node T_1831 = or(T_1830, T_1710)
    node T_1832 = or(T_1831, T_1713)
    node T_1833 = or(T_1832, T_1716)
    node T_1834 = or(T_1833, T_1719)
    node T_1835 = or(T_1834, T_1722)
    node T_1836 = or(T_1835, T_1725)
    node T_1837 = or(T_1836, T_1728)
    node T_1838 = or(T_1837, io.in[0].valid)
    node T_1839 = or(T_1838, io.in[1].valid)
    node T_1840 = or(T_1839, io.in[2].valid)
    node T_1841 = or(T_1840, io.in[3].valid)
    node T_1843 = eq(T_1841, UInt<1>("h00"))
    node T_1845 = or(UInt<1>("h00"), T_1707)
    node T_1846 = or(T_1845, T_1710)
    node T_1847 = or(T_1846, T_1713)
    node T_1848 = or(T_1847, T_1716)
    node T_1849 = or(T_1848, T_1719)
    node T_1850 = or(T_1849, T_1722)
    node T_1851 = or(T_1850, T_1725)
    node T_1852 = or(T_1851, T_1728)
    node T_1853 = or(T_1852, io.in[0].valid)
    node T_1854 = or(T_1853, io.in[1].valid)
    node T_1855 = or(T_1854, io.in[2].valid)
    node T_1856 = or(T_1855, io.in[3].valid)
    node T_1857 = or(T_1856, io.in[4].valid)
    node T_1859 = eq(T_1857, UInt<1>("h00"))
    node T_1861 = or(UInt<1>("h00"), T_1707)
    node T_1862 = or(T_1861, T_1710)
    node T_1863 = or(T_1862, T_1713)
    node T_1864 = or(T_1863, T_1716)
    node T_1865 = or(T_1864, T_1719)
    node T_1866 = or(T_1865, T_1722)
    node T_1867 = or(T_1866, T_1725)
    node T_1868 = or(T_1867, T_1728)
    node T_1869 = or(T_1868, io.in[0].valid)
    node T_1870 = or(T_1869, io.in[1].valid)
    node T_1871 = or(T_1870, io.in[2].valid)
    node T_1872 = or(T_1871, io.in[3].valid)
    node T_1873 = or(T_1872, io.in[4].valid)
    node T_1874 = or(T_1873, io.in[5].valid)
    node T_1876 = eq(T_1874, UInt<1>("h00"))
    node T_1878 = or(UInt<1>("h00"), T_1707)
    node T_1879 = or(T_1878, T_1710)
    node T_1880 = or(T_1879, T_1713)
    node T_1881 = or(T_1880, T_1716)
    node T_1882 = or(T_1881, T_1719)
    node T_1883 = or(T_1882, T_1722)
    node T_1884 = or(T_1883, T_1725)
    node T_1885 = or(T_1884, T_1728)
    node T_1886 = or(T_1885, io.in[0].valid)
    node T_1887 = or(T_1886, io.in[1].valid)
    node T_1888 = or(T_1887, io.in[2].valid)
    node T_1889 = or(T_1888, io.in[3].valid)
    node T_1890 = or(T_1889, io.in[4].valid)
    node T_1891 = or(T_1890, io.in[5].valid)
    node T_1892 = or(T_1891, io.in[6].valid)
    node T_1894 = eq(T_1892, UInt<1>("h00"))
    node T_1896 = gt(UInt<1>("h00"), last_grant)
    node T_1897 = and(UInt<1>("h01"), T_1896)
    node T_1898 = or(T_1897, T_1789)
    node T_1900 = gt(UInt<1>("h01"), last_grant)
    node T_1901 = and(T_1733, T_1900)
    node T_1902 = or(T_1901, T_1801)
    node T_1904 = gt(UInt<2>("h02"), last_grant)
    node T_1905 = and(T_1738, T_1904)
    node T_1906 = or(T_1905, T_1814)
    node T_1908 = gt(UInt<2>("h03"), last_grant)
    node T_1909 = and(T_1744, T_1908)
    node T_1910 = or(T_1909, T_1828)
    node T_1912 = gt(UInt<3>("h04"), last_grant)
    node T_1913 = and(T_1751, T_1912)
    node T_1914 = or(T_1913, T_1843)
    node T_1916 = gt(UInt<3>("h05"), last_grant)
    node T_1917 = and(T_1759, T_1916)
    node T_1918 = or(T_1917, T_1859)
    node T_1920 = gt(UInt<3>("h06"), last_grant)
    node T_1921 = and(T_1768, T_1920)
    node T_1922 = or(T_1921, T_1876)
    node T_1924 = gt(UInt<3>("h07"), last_grant)
    node T_1925 = and(T_1778, T_1924)
    node T_1926 = or(T_1925, T_1894)
    node T_1928 = eq(T_1504, UInt<1>("h00"))
    node T_1929 = mux(T_1502, T_1928, T_1898)
    node T_1930 = and(T_1929, io.out.ready)
    io.in[0].ready <= T_1930
    node T_1932 = eq(T_1504, UInt<1>("h01"))
    node T_1933 = mux(T_1502, T_1932, T_1902)
    node T_1934 = and(T_1933, io.out.ready)
    io.in[1].ready <= T_1934
    node T_1936 = eq(T_1504, UInt<2>("h02"))
    node T_1937 = mux(T_1502, T_1936, T_1906)
    node T_1938 = and(T_1937, io.out.ready)
    io.in[2].ready <= T_1938
    node T_1940 = eq(T_1504, UInt<2>("h03"))
    node T_1941 = mux(T_1502, T_1940, T_1910)
    node T_1942 = and(T_1941, io.out.ready)
    io.in[3].ready <= T_1942
    node T_1944 = eq(T_1504, UInt<3>("h04"))
    node T_1945 = mux(T_1502, T_1944, T_1914)
    node T_1946 = and(T_1945, io.out.ready)
    io.in[4].ready <= T_1946
    node T_1948 = eq(T_1504, UInt<3>("h05"))
    node T_1949 = mux(T_1502, T_1948, T_1918)
    node T_1950 = and(T_1949, io.out.ready)
    io.in[5].ready <= T_1950
    node T_1952 = eq(T_1504, UInt<3>("h06"))
    node T_1953 = mux(T_1502, T_1952, T_1922)
    node T_1954 = and(T_1953, io.out.ready)
    io.in[6].ready <= T_1954
    node T_1956 = eq(T_1504, UInt<3>("h07"))
    node T_1957 = mux(T_1502, T_1956, T_1926)
    node T_1958 = and(T_1957, io.out.ready)
    io.in[7].ready <= T_1958
    reg T_1960 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_1962 = add(T_1960, UInt<1>("h01"))
    node T_1963 = tail(T_1962, 1)
    node T_1964 = and(io.out.ready, io.out.valid)
    when T_1964 :
      wire T_1968 : UInt<3>[1]
      T_1968[0] <= UInt<3>("h05")
      node T_1971 = eq(T_1968[0], io.out.bits.g_type)
      node T_1973 = or(UInt<1>("h00"), T_1971)
      wire T_1975 : UInt<1>[2]
      T_1975[0] <= UInt<1>("h00")
      T_1975[1] <= UInt<1>("h01")
      node T_1979 = eq(T_1975[0], io.out.bits.g_type)
      node T_1980 = eq(T_1975[1], io.out.bits.g_type)
      node T_1982 = or(UInt<1>("h00"), T_1979)
      node T_1983 = or(T_1982, T_1980)
      node T_1984 = mux(io.out.bits.is_builtin_type, T_1973, T_1983)
      node T_1985 = and(UInt<1>("h01"), T_1984)
      when T_1985 :
        T_1960 <= T_1963
        node T_1987 = eq(T_1502, UInt<1>("h00"))
        when T_1987 :
          T_1502 <= UInt<1>("h01")
          node T_1989 = and(io.in[0].ready, io.in[0].valid)
          node T_1990 = and(io.in[1].ready, io.in[1].valid)
          node T_1991 = and(io.in[2].ready, io.in[2].valid)
          node T_1992 = and(io.in[3].ready, io.in[3].valid)
          node T_1993 = and(io.in[4].ready, io.in[4].valid)
          node T_1994 = and(io.in[5].ready, io.in[5].valid)
          node T_1995 = and(io.in[6].ready, io.in[6].valid)
          node T_1996 = and(io.in[7].ready, io.in[7].valid)
          wire T_1998 : UInt<1>[8]
          T_1998[0] <= T_1989
          T_1998[1] <= T_1990
          T_1998[2] <= T_1991
          T_1998[3] <= T_1992
          T_1998[4] <= T_1993
          T_1998[5] <= T_1994
          T_1998[6] <= T_1995
          T_1998[7] <= T_1996
          node T_2016 = mux(T_1998[6], UInt<3>("h06"), UInt<3>("h07"))
          node T_2017 = mux(T_1998[5], UInt<3>("h05"), T_2016)
          node T_2018 = mux(T_1998[4], UInt<3>("h04"), T_2017)
          node T_2019 = mux(T_1998[3], UInt<2>("h03"), T_2018)
          node T_2020 = mux(T_1998[2], UInt<2>("h02"), T_2019)
          node T_2021 = mux(T_1998[1], UInt<1>("h01"), T_2020)
          node T_2022 = mux(T_1998[0], UInt<1>("h00"), T_2021)
          T_1504 <= T_2022
          skip
        skip
      node T_2024 = eq(T_1963, UInt<1>("h00"))
      when T_2024 :
        T_1502 <= UInt<1>("h00")
        skip
      skip
    node T_2028 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07"))
    node T_2030 = mux(io.in[5].valid, UInt<3>("h05"), T_2028)
    node T_2032 = mux(io.in[4].valid, UInt<3>("h04"), T_2030)
    node T_2034 = mux(io.in[3].valid, UInt<2>("h03"), T_2032)
    node T_2036 = mux(io.in[2].valid, UInt<2>("h02"), T_2034)
    node T_2038 = mux(io.in[1].valid, UInt<1>("h01"), T_2036)
    node T_2040 = mux(io.in[0].valid, UInt<1>("h00"), T_2038)
    node T_2042 = gt(UInt<3>("h07"), last_grant)
    node T_2043 = and(io.in[7].valid, T_2042)
    node T_2045 = mux(T_2043, UInt<3>("h07"), T_2040)
    node T_2047 = gt(UInt<3>("h06"), last_grant)
    node T_2048 = and(io.in[6].valid, T_2047)
    node T_2050 = mux(T_2048, UInt<3>("h06"), T_2045)
    node T_2052 = gt(UInt<3>("h05"), last_grant)
    node T_2053 = and(io.in[5].valid, T_2052)
    node T_2055 = mux(T_2053, UInt<3>("h05"), T_2050)
    node T_2057 = gt(UInt<3>("h04"), last_grant)
    node T_2058 = and(io.in[4].valid, T_2057)
    node T_2060 = mux(T_2058, UInt<3>("h04"), T_2055)
    node T_2062 = gt(UInt<2>("h03"), last_grant)
    node T_2063 = and(io.in[3].valid, T_2062)
    node T_2065 = mux(T_2063, UInt<2>("h03"), T_2060)
    node T_2067 = gt(UInt<2>("h02"), last_grant)
    node T_2068 = and(io.in[2].valid, T_2067)
    node T_2070 = mux(T_2068, UInt<2>("h02"), T_2065)
    node T_2072 = gt(UInt<1>("h01"), last_grant)
    node T_2073 = and(io.in[1].valid, T_2072)
    node choose = mux(T_2073, UInt<1>("h01"), T_2070)
    node T_2076 = mux(T_1502, T_1504, choose)
    T_1506 <= T_2076
    node T_2077 = and(io.out.ready, io.out.valid)
    when T_2077 :
      last_grant <= T_1506
      skip
    
  module LockingRRArbiter_34 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, chosen : UInt<3>}
    
    io is invalid
    reg T_1318 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_1320 : UInt, clk with : (reset => (reset, UInt<3>("h07")))
    wire T_1322 : UInt<3>
    T_1322 is invalid
    io.out.valid <= io.in[T_1322].valid
    io.out.bits <- io.in[T_1322].bits
    io.chosen <= T_1322
    io.in[T_1322].ready <= UInt<1>("h00")
    reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    node T_1498 = gt(UInt<1>("h00"), last_grant)
    node T_1499 = and(io.in[0].valid, T_1498)
    node T_1501 = gt(UInt<1>("h01"), last_grant)
    node T_1502 = and(io.in[1].valid, T_1501)
    node T_1504 = gt(UInt<2>("h02"), last_grant)
    node T_1505 = and(io.in[2].valid, T_1504)
    node T_1507 = gt(UInt<2>("h03"), last_grant)
    node T_1508 = and(io.in[3].valid, T_1507)
    node T_1510 = gt(UInt<3>("h04"), last_grant)
    node T_1511 = and(io.in[4].valid, T_1510)
    node T_1513 = gt(UInt<3>("h05"), last_grant)
    node T_1514 = and(io.in[5].valid, T_1513)
    node T_1516 = gt(UInt<3>("h06"), last_grant)
    node T_1517 = and(io.in[6].valid, T_1516)
    node T_1519 = gt(UInt<3>("h07"), last_grant)
    node T_1520 = and(io.in[7].valid, T_1519)
    node T_1523 = or(UInt<1>("h00"), T_1499)
    node T_1525 = eq(T_1523, UInt<1>("h00"))
    node T_1527 = or(UInt<1>("h00"), T_1499)
    node T_1528 = or(T_1527, T_1502)
    node T_1530 = eq(T_1528, UInt<1>("h00"))
    node T_1532 = or(UInt<1>("h00"), T_1499)
    node T_1533 = or(T_1532, T_1502)
    node T_1534 = or(T_1533, T_1505)
    node T_1536 = eq(T_1534, UInt<1>("h00"))
    node T_1538 = or(UInt<1>("h00"), T_1499)
    node T_1539 = or(T_1538, T_1502)
    node T_1540 = or(T_1539, T_1505)
    node T_1541 = or(T_1540, T_1508)
    node T_1543 = eq(T_1541, UInt<1>("h00"))
    node T_1545 = or(UInt<1>("h00"), T_1499)
    node T_1546 = or(T_1545, T_1502)
    node T_1547 = or(T_1546, T_1505)
    node T_1548 = or(T_1547, T_1508)
    node T_1549 = or(T_1548, T_1511)
    node T_1551 = eq(T_1549, UInt<1>("h00"))
    node T_1553 = or(UInt<1>("h00"), T_1499)
    node T_1554 = or(T_1553, T_1502)
    node T_1555 = or(T_1554, T_1505)
    node T_1556 = or(T_1555, T_1508)
    node T_1557 = or(T_1556, T_1511)
    node T_1558 = or(T_1557, T_1514)
    node T_1560 = eq(T_1558, UInt<1>("h00"))
    node T_1562 = or(UInt<1>("h00"), T_1499)
    node T_1563 = or(T_1562, T_1502)
    node T_1564 = or(T_1563, T_1505)
    node T_1565 = or(T_1564, T_1508)
    node T_1566 = or(T_1565, T_1511)
    node T_1567 = or(T_1566, T_1514)
    node T_1568 = or(T_1567, T_1517)
    node T_1570 = eq(T_1568, UInt<1>("h00"))
    node T_1572 = or(UInt<1>("h00"), T_1499)
    node T_1573 = or(T_1572, T_1502)
    node T_1574 = or(T_1573, T_1505)
    node T_1575 = or(T_1574, T_1508)
    node T_1576 = or(T_1575, T_1511)
    node T_1577 = or(T_1576, T_1514)
    node T_1578 = or(T_1577, T_1517)
    node T_1579 = or(T_1578, T_1520)
    node T_1581 = eq(T_1579, UInt<1>("h00"))
    node T_1583 = or(UInt<1>("h00"), T_1499)
    node T_1584 = or(T_1583, T_1502)
    node T_1585 = or(T_1584, T_1505)
    node T_1586 = or(T_1585, T_1508)
    node T_1587 = or(T_1586, T_1511)
    node T_1588 = or(T_1587, T_1514)
    node T_1589 = or(T_1588, T_1517)
    node T_1590 = or(T_1589, T_1520)
    node T_1591 = or(T_1590, io.in[0].valid)
    node T_1593 = eq(T_1591, UInt<1>("h00"))
    node T_1595 = or(UInt<1>("h00"), T_1499)
    node T_1596 = or(T_1595, T_1502)
    node T_1597 = or(T_1596, T_1505)
    node T_1598 = or(T_1597, T_1508)
    node T_1599 = or(T_1598, T_1511)
    node T_1600 = or(T_1599, T_1514)
    node T_1601 = or(T_1600, T_1517)
    node T_1602 = or(T_1601, T_1520)
    node T_1603 = or(T_1602, io.in[0].valid)
    node T_1604 = or(T_1603, io.in[1].valid)
    node T_1606 = eq(T_1604, UInt<1>("h00"))
    node T_1608 = or(UInt<1>("h00"), T_1499)
    node T_1609 = or(T_1608, T_1502)
    node T_1610 = or(T_1609, T_1505)
    node T_1611 = or(T_1610, T_1508)
    node T_1612 = or(T_1611, T_1511)
    node T_1613 = or(T_1612, T_1514)
    node T_1614 = or(T_1613, T_1517)
    node T_1615 = or(T_1614, T_1520)
    node T_1616 = or(T_1615, io.in[0].valid)
    node T_1617 = or(T_1616, io.in[1].valid)
    node T_1618 = or(T_1617, io.in[2].valid)
    node T_1620 = eq(T_1618, UInt<1>("h00"))
    node T_1622 = or(UInt<1>("h00"), T_1499)
    node T_1623 = or(T_1622, T_1502)
    node T_1624 = or(T_1623, T_1505)
    node T_1625 = or(T_1624, T_1508)
    node T_1626 = or(T_1625, T_1511)
    node T_1627 = or(T_1626, T_1514)
    node T_1628 = or(T_1627, T_1517)
    node T_1629 = or(T_1628, T_1520)
    node T_1630 = or(T_1629, io.in[0].valid)
    node T_1631 = or(T_1630, io.in[1].valid)
    node T_1632 = or(T_1631, io.in[2].valid)
    node T_1633 = or(T_1632, io.in[3].valid)
    node T_1635 = eq(T_1633, UInt<1>("h00"))
    node T_1637 = or(UInt<1>("h00"), T_1499)
    node T_1638 = or(T_1637, T_1502)
    node T_1639 = or(T_1638, T_1505)
    node T_1640 = or(T_1639, T_1508)
    node T_1641 = or(T_1640, T_1511)
    node T_1642 = or(T_1641, T_1514)
    node T_1643 = or(T_1642, T_1517)
    node T_1644 = or(T_1643, T_1520)
    node T_1645 = or(T_1644, io.in[0].valid)
    node T_1646 = or(T_1645, io.in[1].valid)
    node T_1647 = or(T_1646, io.in[2].valid)
    node T_1648 = or(T_1647, io.in[3].valid)
    node T_1649 = or(T_1648, io.in[4].valid)
    node T_1651 = eq(T_1649, UInt<1>("h00"))
    node T_1653 = or(UInt<1>("h00"), T_1499)
    node T_1654 = or(T_1653, T_1502)
    node T_1655 = or(T_1654, T_1505)
    node T_1656 = or(T_1655, T_1508)
    node T_1657 = or(T_1656, T_1511)
    node T_1658 = or(T_1657, T_1514)
    node T_1659 = or(T_1658, T_1517)
    node T_1660 = or(T_1659, T_1520)
    node T_1661 = or(T_1660, io.in[0].valid)
    node T_1662 = or(T_1661, io.in[1].valid)
    node T_1663 = or(T_1662, io.in[2].valid)
    node T_1664 = or(T_1663, io.in[3].valid)
    node T_1665 = or(T_1664, io.in[4].valid)
    node T_1666 = or(T_1665, io.in[5].valid)
    node T_1668 = eq(T_1666, UInt<1>("h00"))
    node T_1670 = or(UInt<1>("h00"), T_1499)
    node T_1671 = or(T_1670, T_1502)
    node T_1672 = or(T_1671, T_1505)
    node T_1673 = or(T_1672, T_1508)
    node T_1674 = or(T_1673, T_1511)
    node T_1675 = or(T_1674, T_1514)
    node T_1676 = or(T_1675, T_1517)
    node T_1677 = or(T_1676, T_1520)
    node T_1678 = or(T_1677, io.in[0].valid)
    node T_1679 = or(T_1678, io.in[1].valid)
    node T_1680 = or(T_1679, io.in[2].valid)
    node T_1681 = or(T_1680, io.in[3].valid)
    node T_1682 = or(T_1681, io.in[4].valid)
    node T_1683 = or(T_1682, io.in[5].valid)
    node T_1684 = or(T_1683, io.in[6].valid)
    node T_1686 = eq(T_1684, UInt<1>("h00"))
    node T_1688 = gt(UInt<1>("h00"), last_grant)
    node T_1689 = and(UInt<1>("h01"), T_1688)
    node T_1690 = or(T_1689, T_1581)
    node T_1692 = gt(UInt<1>("h01"), last_grant)
    node T_1693 = and(T_1525, T_1692)
    node T_1694 = or(T_1693, T_1593)
    node T_1696 = gt(UInt<2>("h02"), last_grant)
    node T_1697 = and(T_1530, T_1696)
    node T_1698 = or(T_1697, T_1606)
    node T_1700 = gt(UInt<2>("h03"), last_grant)
    node T_1701 = and(T_1536, T_1700)
    node T_1702 = or(T_1701, T_1620)
    node T_1704 = gt(UInt<3>("h04"), last_grant)
    node T_1705 = and(T_1543, T_1704)
    node T_1706 = or(T_1705, T_1635)
    node T_1708 = gt(UInt<3>("h05"), last_grant)
    node T_1709 = and(T_1551, T_1708)
    node T_1710 = or(T_1709, T_1651)
    node T_1712 = gt(UInt<3>("h06"), last_grant)
    node T_1713 = and(T_1560, T_1712)
    node T_1714 = or(T_1713, T_1668)
    node T_1716 = gt(UInt<3>("h07"), last_grant)
    node T_1717 = and(T_1570, T_1716)
    node T_1718 = or(T_1717, T_1686)
    node T_1720 = eq(T_1320, UInt<1>("h00"))
    node T_1721 = mux(T_1318, T_1720, T_1690)
    node T_1722 = and(T_1721, io.out.ready)
    io.in[0].ready <= T_1722
    node T_1724 = eq(T_1320, UInt<1>("h01"))
    node T_1725 = mux(T_1318, T_1724, T_1694)
    node T_1726 = and(T_1725, io.out.ready)
    io.in[1].ready <= T_1726
    node T_1728 = eq(T_1320, UInt<2>("h02"))
    node T_1729 = mux(T_1318, T_1728, T_1698)
    node T_1730 = and(T_1729, io.out.ready)
    io.in[2].ready <= T_1730
    node T_1732 = eq(T_1320, UInt<2>("h03"))
    node T_1733 = mux(T_1318, T_1732, T_1702)
    node T_1734 = and(T_1733, io.out.ready)
    io.in[3].ready <= T_1734
    node T_1736 = eq(T_1320, UInt<3>("h04"))
    node T_1737 = mux(T_1318, T_1736, T_1706)
    node T_1738 = and(T_1737, io.out.ready)
    io.in[4].ready <= T_1738
    node T_1740 = eq(T_1320, UInt<3>("h05"))
    node T_1741 = mux(T_1318, T_1740, T_1710)
    node T_1742 = and(T_1741, io.out.ready)
    io.in[5].ready <= T_1742
    node T_1744 = eq(T_1320, UInt<3>("h06"))
    node T_1745 = mux(T_1318, T_1744, T_1714)
    node T_1746 = and(T_1745, io.out.ready)
    io.in[6].ready <= T_1746
    node T_1748 = eq(T_1320, UInt<3>("h07"))
    node T_1749 = mux(T_1318, T_1748, T_1718)
    node T_1750 = and(T_1749, io.out.ready)
    io.in[7].ready <= T_1750
    reg T_1752 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_1754 = add(T_1752, UInt<1>("h01"))
    node T_1755 = tail(T_1754, 1)
    node T_1756 = and(io.out.ready, io.out.valid)
    when T_1756 :
      when UInt<1>("h00") :
        T_1752 <= T_1755
        node T_1759 = eq(T_1318, UInt<1>("h00"))
        when T_1759 :
          T_1318 <= UInt<1>("h01")
          node T_1761 = and(io.in[0].ready, io.in[0].valid)
          node T_1762 = and(io.in[1].ready, io.in[1].valid)
          node T_1763 = and(io.in[2].ready, io.in[2].valid)
          node T_1764 = and(io.in[3].ready, io.in[3].valid)
          node T_1765 = and(io.in[4].ready, io.in[4].valid)
          node T_1766 = and(io.in[5].ready, io.in[5].valid)
          node T_1767 = and(io.in[6].ready, io.in[6].valid)
          node T_1768 = and(io.in[7].ready, io.in[7].valid)
          wire T_1770 : UInt<1>[8]
          T_1770[0] <= T_1761
          T_1770[1] <= T_1762
          T_1770[2] <= T_1763
          T_1770[3] <= T_1764
          T_1770[4] <= T_1765
          T_1770[5] <= T_1766
          T_1770[6] <= T_1767
          T_1770[7] <= T_1768
          node T_1788 = mux(T_1770[6], UInt<3>("h06"), UInt<3>("h07"))
          node T_1789 = mux(T_1770[5], UInt<3>("h05"), T_1788)
          node T_1790 = mux(T_1770[4], UInt<3>("h04"), T_1789)
          node T_1791 = mux(T_1770[3], UInt<2>("h03"), T_1790)
          node T_1792 = mux(T_1770[2], UInt<2>("h02"), T_1791)
          node T_1793 = mux(T_1770[1], UInt<1>("h01"), T_1792)
          node T_1794 = mux(T_1770[0], UInt<1>("h00"), T_1793)
          T_1320 <= T_1794
          skip
        skip
      node T_1796 = eq(T_1755, UInt<1>("h00"))
      when T_1796 :
        T_1318 <= UInt<1>("h00")
        skip
      skip
    node T_1800 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07"))
    node T_1802 = mux(io.in[5].valid, UInt<3>("h05"), T_1800)
    node T_1804 = mux(io.in[4].valid, UInt<3>("h04"), T_1802)
    node T_1806 = mux(io.in[3].valid, UInt<2>("h03"), T_1804)
    node T_1808 = mux(io.in[2].valid, UInt<2>("h02"), T_1806)
    node T_1810 = mux(io.in[1].valid, UInt<1>("h01"), T_1808)
    node T_1812 = mux(io.in[0].valid, UInt<1>("h00"), T_1810)
    node T_1814 = gt(UInt<3>("h07"), last_grant)
    node T_1815 = and(io.in[7].valid, T_1814)
    node T_1817 = mux(T_1815, UInt<3>("h07"), T_1812)
    node T_1819 = gt(UInt<3>("h06"), last_grant)
    node T_1820 = and(io.in[6].valid, T_1819)
    node T_1822 = mux(T_1820, UInt<3>("h06"), T_1817)
    node T_1824 = gt(UInt<3>("h05"), last_grant)
    node T_1825 = and(io.in[5].valid, T_1824)
    node T_1827 = mux(T_1825, UInt<3>("h05"), T_1822)
    node T_1829 = gt(UInt<3>("h04"), last_grant)
    node T_1830 = and(io.in[4].valid, T_1829)
    node T_1832 = mux(T_1830, UInt<3>("h04"), T_1827)
    node T_1834 = gt(UInt<2>("h03"), last_grant)
    node T_1835 = and(io.in[3].valid, T_1834)
    node T_1837 = mux(T_1835, UInt<2>("h03"), T_1832)
    node T_1839 = gt(UInt<2>("h02"), last_grant)
    node T_1840 = and(io.in[2].valid, T_1839)
    node T_1842 = mux(T_1840, UInt<2>("h02"), T_1837)
    node T_1844 = gt(UInt<1>("h01"), last_grant)
    node T_1845 = and(io.in[1].valid, T_1844)
    node choose = mux(T_1845, UInt<1>("h01"), T_1842)
    node T_1848 = mux(T_1318, T_1320, choose)
    T_1322 <= T_1848
    node T_1849 = and(io.out.ready, io.out.valid)
    when T_1849 :
      last_grant <= T_1322
      skip
    
  module LockingRRArbiter_35 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, chosen : UInt<3>}
    
    io is invalid
    reg T_444 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_446 : UInt, clk with : (reset => (reset, UInt<3>("h07")))
    wire T_448 : UInt<3>
    T_448 is invalid
    io.out.valid <= io.in[T_448].valid
    io.out.bits <- io.in[T_448].bits
    io.chosen <= T_448
    io.in[T_448].ready <= UInt<1>("h00")
    reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    node T_510 = gt(UInt<1>("h00"), last_grant)
    node T_511 = and(io.in[0].valid, T_510)
    node T_513 = gt(UInt<1>("h01"), last_grant)
    node T_514 = and(io.in[1].valid, T_513)
    node T_516 = gt(UInt<2>("h02"), last_grant)
    node T_517 = and(io.in[2].valid, T_516)
    node T_519 = gt(UInt<2>("h03"), last_grant)
    node T_520 = and(io.in[3].valid, T_519)
    node T_522 = gt(UInt<3>("h04"), last_grant)
    node T_523 = and(io.in[4].valid, T_522)
    node T_525 = gt(UInt<3>("h05"), last_grant)
    node T_526 = and(io.in[5].valid, T_525)
    node T_528 = gt(UInt<3>("h06"), last_grant)
    node T_529 = and(io.in[6].valid, T_528)
    node T_531 = gt(UInt<3>("h07"), last_grant)
    node T_532 = and(io.in[7].valid, T_531)
    node T_535 = or(UInt<1>("h00"), T_511)
    node T_537 = eq(T_535, UInt<1>("h00"))
    node T_539 = or(UInt<1>("h00"), T_511)
    node T_540 = or(T_539, T_514)
    node T_542 = eq(T_540, UInt<1>("h00"))
    node T_544 = or(UInt<1>("h00"), T_511)
    node T_545 = or(T_544, T_514)
    node T_546 = or(T_545, T_517)
    node T_548 = eq(T_546, UInt<1>("h00"))
    node T_550 = or(UInt<1>("h00"), T_511)
    node T_551 = or(T_550, T_514)
    node T_552 = or(T_551, T_517)
    node T_553 = or(T_552, T_520)
    node T_555 = eq(T_553, UInt<1>("h00"))
    node T_557 = or(UInt<1>("h00"), T_511)
    node T_558 = or(T_557, T_514)
    node T_559 = or(T_558, T_517)
    node T_560 = or(T_559, T_520)
    node T_561 = or(T_560, T_523)
    node T_563 = eq(T_561, UInt<1>("h00"))
    node T_565 = or(UInt<1>("h00"), T_511)
    node T_566 = or(T_565, T_514)
    node T_567 = or(T_566, T_517)
    node T_568 = or(T_567, T_520)
    node T_569 = or(T_568, T_523)
    node T_570 = or(T_569, T_526)
    node T_572 = eq(T_570, UInt<1>("h00"))
    node T_574 = or(UInt<1>("h00"), T_511)
    node T_575 = or(T_574, T_514)
    node T_576 = or(T_575, T_517)
    node T_577 = or(T_576, T_520)
    node T_578 = or(T_577, T_523)
    node T_579 = or(T_578, T_526)
    node T_580 = or(T_579, T_529)
    node T_582 = eq(T_580, UInt<1>("h00"))
    node T_584 = or(UInt<1>("h00"), T_511)
    node T_585 = or(T_584, T_514)
    node T_586 = or(T_585, T_517)
    node T_587 = or(T_586, T_520)
    node T_588 = or(T_587, T_523)
    node T_589 = or(T_588, T_526)
    node T_590 = or(T_589, T_529)
    node T_591 = or(T_590, T_532)
    node T_593 = eq(T_591, UInt<1>("h00"))
    node T_595 = or(UInt<1>("h00"), T_511)
    node T_596 = or(T_595, T_514)
    node T_597 = or(T_596, T_517)
    node T_598 = or(T_597, T_520)
    node T_599 = or(T_598, T_523)
    node T_600 = or(T_599, T_526)
    node T_601 = or(T_600, T_529)
    node T_602 = or(T_601, T_532)
    node T_603 = or(T_602, io.in[0].valid)
    node T_605 = eq(T_603, UInt<1>("h00"))
    node T_607 = or(UInt<1>("h00"), T_511)
    node T_608 = or(T_607, T_514)
    node T_609 = or(T_608, T_517)
    node T_610 = or(T_609, T_520)
    node T_611 = or(T_610, T_523)
    node T_612 = or(T_611, T_526)
    node T_613 = or(T_612, T_529)
    node T_614 = or(T_613, T_532)
    node T_615 = or(T_614, io.in[0].valid)
    node T_616 = or(T_615, io.in[1].valid)
    node T_618 = eq(T_616, UInt<1>("h00"))
    node T_620 = or(UInt<1>("h00"), T_511)
    node T_621 = or(T_620, T_514)
    node T_622 = or(T_621, T_517)
    node T_623 = or(T_622, T_520)
    node T_624 = or(T_623, T_523)
    node T_625 = or(T_624, T_526)
    node T_626 = or(T_625, T_529)
    node T_627 = or(T_626, T_532)
    node T_628 = or(T_627, io.in[0].valid)
    node T_629 = or(T_628, io.in[1].valid)
    node T_630 = or(T_629, io.in[2].valid)
    node T_632 = eq(T_630, UInt<1>("h00"))
    node T_634 = or(UInt<1>("h00"), T_511)
    node T_635 = or(T_634, T_514)
    node T_636 = or(T_635, T_517)
    node T_637 = or(T_636, T_520)
    node T_638 = or(T_637, T_523)
    node T_639 = or(T_638, T_526)
    node T_640 = or(T_639, T_529)
    node T_641 = or(T_640, T_532)
    node T_642 = or(T_641, io.in[0].valid)
    node T_643 = or(T_642, io.in[1].valid)
    node T_644 = or(T_643, io.in[2].valid)
    node T_645 = or(T_644, io.in[3].valid)
    node T_647 = eq(T_645, UInt<1>("h00"))
    node T_649 = or(UInt<1>("h00"), T_511)
    node T_650 = or(T_649, T_514)
    node T_651 = or(T_650, T_517)
    node T_652 = or(T_651, T_520)
    node T_653 = or(T_652, T_523)
    node T_654 = or(T_653, T_526)
    node T_655 = or(T_654, T_529)
    node T_656 = or(T_655, T_532)
    node T_657 = or(T_656, io.in[0].valid)
    node T_658 = or(T_657, io.in[1].valid)
    node T_659 = or(T_658, io.in[2].valid)
    node T_660 = or(T_659, io.in[3].valid)
    node T_661 = or(T_660, io.in[4].valid)
    node T_663 = eq(T_661, UInt<1>("h00"))
    node T_665 = or(UInt<1>("h00"), T_511)
    node T_666 = or(T_665, T_514)
    node T_667 = or(T_666, T_517)
    node T_668 = or(T_667, T_520)
    node T_669 = or(T_668, T_523)
    node T_670 = or(T_669, T_526)
    node T_671 = or(T_670, T_529)
    node T_672 = or(T_671, T_532)
    node T_673 = or(T_672, io.in[0].valid)
    node T_674 = or(T_673, io.in[1].valid)
    node T_675 = or(T_674, io.in[2].valid)
    node T_676 = or(T_675, io.in[3].valid)
    node T_677 = or(T_676, io.in[4].valid)
    node T_678 = or(T_677, io.in[5].valid)
    node T_680 = eq(T_678, UInt<1>("h00"))
    node T_682 = or(UInt<1>("h00"), T_511)
    node T_683 = or(T_682, T_514)
    node T_684 = or(T_683, T_517)
    node T_685 = or(T_684, T_520)
    node T_686 = or(T_685, T_523)
    node T_687 = or(T_686, T_526)
    node T_688 = or(T_687, T_529)
    node T_689 = or(T_688, T_532)
    node T_690 = or(T_689, io.in[0].valid)
    node T_691 = or(T_690, io.in[1].valid)
    node T_692 = or(T_691, io.in[2].valid)
    node T_693 = or(T_692, io.in[3].valid)
    node T_694 = or(T_693, io.in[4].valid)
    node T_695 = or(T_694, io.in[5].valid)
    node T_696 = or(T_695, io.in[6].valid)
    node T_698 = eq(T_696, UInt<1>("h00"))
    node T_700 = gt(UInt<1>("h00"), last_grant)
    node T_701 = and(UInt<1>("h01"), T_700)
    node T_702 = or(T_701, T_593)
    node T_704 = gt(UInt<1>("h01"), last_grant)
    node T_705 = and(T_537, T_704)
    node T_706 = or(T_705, T_605)
    node T_708 = gt(UInt<2>("h02"), last_grant)
    node T_709 = and(T_542, T_708)
    node T_710 = or(T_709, T_618)
    node T_712 = gt(UInt<2>("h03"), last_grant)
    node T_713 = and(T_548, T_712)
    node T_714 = or(T_713, T_632)
    node T_716 = gt(UInt<3>("h04"), last_grant)
    node T_717 = and(T_555, T_716)
    node T_718 = or(T_717, T_647)
    node T_720 = gt(UInt<3>("h05"), last_grant)
    node T_721 = and(T_563, T_720)
    node T_722 = or(T_721, T_663)
    node T_724 = gt(UInt<3>("h06"), last_grant)
    node T_725 = and(T_572, T_724)
    node T_726 = or(T_725, T_680)
    node T_728 = gt(UInt<3>("h07"), last_grant)
    node T_729 = and(T_582, T_728)
    node T_730 = or(T_729, T_698)
    node T_732 = eq(T_446, UInt<1>("h00"))
    node T_733 = mux(T_444, T_732, T_702)
    node T_734 = and(T_733, io.out.ready)
    io.in[0].ready <= T_734
    node T_736 = eq(T_446, UInt<1>("h01"))
    node T_737 = mux(T_444, T_736, T_706)
    node T_738 = and(T_737, io.out.ready)
    io.in[1].ready <= T_738
    node T_740 = eq(T_446, UInt<2>("h02"))
    node T_741 = mux(T_444, T_740, T_710)
    node T_742 = and(T_741, io.out.ready)
    io.in[2].ready <= T_742
    node T_744 = eq(T_446, UInt<2>("h03"))
    node T_745 = mux(T_444, T_744, T_714)
    node T_746 = and(T_745, io.out.ready)
    io.in[3].ready <= T_746
    node T_748 = eq(T_446, UInt<3>("h04"))
    node T_749 = mux(T_444, T_748, T_718)
    node T_750 = and(T_749, io.out.ready)
    io.in[4].ready <= T_750
    node T_752 = eq(T_446, UInt<3>("h05"))
    node T_753 = mux(T_444, T_752, T_722)
    node T_754 = and(T_753, io.out.ready)
    io.in[5].ready <= T_754
    node T_756 = eq(T_446, UInt<3>("h06"))
    node T_757 = mux(T_444, T_756, T_726)
    node T_758 = and(T_757, io.out.ready)
    io.in[6].ready <= T_758
    node T_760 = eq(T_446, UInt<3>("h07"))
    node T_761 = mux(T_444, T_760, T_730)
    node T_762 = and(T_761, io.out.ready)
    io.in[7].ready <= T_762
    reg T_764 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_766 = add(T_764, UInt<1>("h01"))
    node T_767 = tail(T_766, 1)
    node T_768 = and(io.out.ready, io.out.valid)
    when T_768 :
      node T_770 = and(UInt<1>("h01"), io.out.bits.is_builtin_type)
      wire T_773 : UInt<3>[1]
      T_773[0] <= UInt<3>("h03")
      node T_776 = eq(T_773[0], io.out.bits.a_type)
      node T_778 = or(UInt<1>("h00"), T_776)
      node T_779 = and(T_770, T_778)
      when T_779 :
        T_764 <= T_767
        node T_781 = eq(T_444, UInt<1>("h00"))
        when T_781 :
          T_444 <= UInt<1>("h01")
          node T_783 = and(io.in[0].ready, io.in[0].valid)
          node T_784 = and(io.in[1].ready, io.in[1].valid)
          node T_785 = and(io.in[2].ready, io.in[2].valid)
          node T_786 = and(io.in[3].ready, io.in[3].valid)
          node T_787 = and(io.in[4].ready, io.in[4].valid)
          node T_788 = and(io.in[5].ready, io.in[5].valid)
          node T_789 = and(io.in[6].ready, io.in[6].valid)
          node T_790 = and(io.in[7].ready, io.in[7].valid)
          wire T_792 : UInt<1>[8]
          T_792[0] <= T_783
          T_792[1] <= T_784
          T_792[2] <= T_785
          T_792[3] <= T_786
          T_792[4] <= T_787
          T_792[5] <= T_788
          T_792[6] <= T_789
          T_792[7] <= T_790
          node T_810 = mux(T_792[6], UInt<3>("h06"), UInt<3>("h07"))
          node T_811 = mux(T_792[5], UInt<3>("h05"), T_810)
          node T_812 = mux(T_792[4], UInt<3>("h04"), T_811)
          node T_813 = mux(T_792[3], UInt<2>("h03"), T_812)
          node T_814 = mux(T_792[2], UInt<2>("h02"), T_813)
          node T_815 = mux(T_792[1], UInt<1>("h01"), T_814)
          node T_816 = mux(T_792[0], UInt<1>("h00"), T_815)
          T_446 <= T_816
          skip
        skip
      node T_818 = eq(T_767, UInt<1>("h00"))
      when T_818 :
        T_444 <= UInt<1>("h00")
        skip
      skip
    node T_822 = mux(io.in[6].valid, UInt<3>("h06"), UInt<3>("h07"))
    node T_824 = mux(io.in[5].valid, UInt<3>("h05"), T_822)
    node T_826 = mux(io.in[4].valid, UInt<3>("h04"), T_824)
    node T_828 = mux(io.in[3].valid, UInt<2>("h03"), T_826)
    node T_830 = mux(io.in[2].valid, UInt<2>("h02"), T_828)
    node T_832 = mux(io.in[1].valid, UInt<1>("h01"), T_830)
    node T_834 = mux(io.in[0].valid, UInt<1>("h00"), T_832)
    node T_836 = gt(UInt<3>("h07"), last_grant)
    node T_837 = and(io.in[7].valid, T_836)
    node T_839 = mux(T_837, UInt<3>("h07"), T_834)
    node T_841 = gt(UInt<3>("h06"), last_grant)
    node T_842 = and(io.in[6].valid, T_841)
    node T_844 = mux(T_842, UInt<3>("h06"), T_839)
    node T_846 = gt(UInt<3>("h05"), last_grant)
    node T_847 = and(io.in[5].valid, T_846)
    node T_849 = mux(T_847, UInt<3>("h05"), T_844)
    node T_851 = gt(UInt<3>("h04"), last_grant)
    node T_852 = and(io.in[4].valid, T_851)
    node T_854 = mux(T_852, UInt<3>("h04"), T_849)
    node T_856 = gt(UInt<2>("h03"), last_grant)
    node T_857 = and(io.in[3].valid, T_856)
    node T_859 = mux(T_857, UInt<2>("h03"), T_854)
    node T_861 = gt(UInt<2>("h02"), last_grant)
    node T_862 = and(io.in[2].valid, T_861)
    node T_864 = mux(T_862, UInt<2>("h02"), T_859)
    node T_866 = gt(UInt<1>("h01"), last_grant)
    node T_867 = and(io.in[1].valid, T_866)
    node choose = mux(T_867, UInt<1>("h01"), T_864)
    node T_870 = mux(T_444, T_446, choose)
    T_448 <= T_870
    node T_871 = and(io.out.ready, io.out.valid)
    when T_871 :
      last_grant <= T_448
      skip
    
  module ClientUncachedTileLinkIOArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}[8], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}}
    
    io is invalid
    inst T_1593 of LockingRRArbiter_35
    T_1593.io is invalid
    T_1593.clk <= clk
    T_1593.reset <= reset
    T_1593.io.in[0].valid <= io.in[0].acquire.valid
    T_1593.io.in[0].bits <- io.in[0].acquire.bits
    node T_1595 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h00"))
    T_1593.io.in[0].bits.client_xact_id <= T_1595
    io.in[0].acquire.ready <= T_1593.io.in[0].ready
    T_1593.io.in[1].valid <= io.in[1].acquire.valid
    T_1593.io.in[1].bits <- io.in[1].acquire.bits
    node T_1597 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h01"))
    T_1593.io.in[1].bits.client_xact_id <= T_1597
    io.in[1].acquire.ready <= T_1593.io.in[1].ready
    T_1593.io.in[2].valid <= io.in[2].acquire.valid
    T_1593.io.in[2].bits <- io.in[2].acquire.bits
    node T_1599 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h02"))
    T_1593.io.in[2].bits.client_xact_id <= T_1599
    io.in[2].acquire.ready <= T_1593.io.in[2].ready
    T_1593.io.in[3].valid <= io.in[3].acquire.valid
    T_1593.io.in[3].bits <- io.in[3].acquire.bits
    node T_1601 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h03"))
    T_1593.io.in[3].bits.client_xact_id <= T_1601
    io.in[3].acquire.ready <= T_1593.io.in[3].ready
    T_1593.io.in[4].valid <= io.in[4].acquire.valid
    T_1593.io.in[4].bits <- io.in[4].acquire.bits
    node T_1603 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h04"))
    T_1593.io.in[4].bits.client_xact_id <= T_1603
    io.in[4].acquire.ready <= T_1593.io.in[4].ready
    T_1593.io.in[5].valid <= io.in[5].acquire.valid
    T_1593.io.in[5].bits <- io.in[5].acquire.bits
    node T_1605 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h05"))
    T_1593.io.in[5].bits.client_xact_id <= T_1605
    io.in[5].acquire.ready <= T_1593.io.in[5].ready
    T_1593.io.in[6].valid <= io.in[6].acquire.valid
    T_1593.io.in[6].bits <- io.in[6].acquire.bits
    node T_1607 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h06"))
    T_1593.io.in[6].bits.client_xact_id <= T_1607
    io.in[6].acquire.ready <= T_1593.io.in[6].ready
    T_1593.io.in[7].valid <= io.in[7].acquire.valid
    T_1593.io.in[7].bits <- io.in[7].acquire.bits
    node T_1609 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h07"))
    T_1593.io.in[7].bits.client_xact_id <= T_1609
    io.in[7].acquire.ready <= T_1593.io.in[7].ready
    io.out.acquire <- T_1593.io.out
    io.out.grant.ready <= UInt<1>("h00")
    io.in[0].grant.valid <= UInt<1>("h00")
    node T_1612 = bits(io.out.grant.bits.client_xact_id, 2, 0)
    node T_1614 = eq(T_1612, UInt<1>("h00"))
    when T_1614 :
      io.in[0].grant.valid <= io.out.grant.valid
      io.out.grant.ready <= io.in[0].grant.ready
      skip
    io.in[0].grant.bits <- io.out.grant.bits
    node T_1615 = shr(io.out.grant.bits.client_xact_id, 3)
    io.in[0].grant.bits.client_xact_id <= T_1615
    io.in[1].grant.valid <= UInt<1>("h00")
    node T_1617 = bits(io.out.grant.bits.client_xact_id, 2, 0)
    node T_1619 = eq(T_1617, UInt<1>("h01"))
    when T_1619 :
      io.in[1].grant.valid <= io.out.grant.valid
      io.out.grant.ready <= io.in[1].grant.ready
      skip
    io.in[1].grant.bits <- io.out.grant.bits
    node T_1620 = shr(io.out.grant.bits.client_xact_id, 3)
    io.in[1].grant.bits.client_xact_id <= T_1620
    io.in[2].grant.valid <= UInt<1>("h00")
    node T_1622 = bits(io.out.grant.bits.client_xact_id, 2, 0)
    node T_1624 = eq(T_1622, UInt<2>("h02"))
    when T_1624 :
      io.in[2].grant.valid <= io.out.grant.valid
      io.out.grant.ready <= io.in[2].grant.ready
      skip
    io.in[2].grant.bits <- io.out.grant.bits
    node T_1625 = shr(io.out.grant.bits.client_xact_id, 3)
    io.in[2].grant.bits.client_xact_id <= T_1625
    io.in[3].grant.valid <= UInt<1>("h00")
    node T_1627 = bits(io.out.grant.bits.client_xact_id, 2, 0)
    node T_1629 = eq(T_1627, UInt<2>("h03"))
    when T_1629 :
      io.in[3].grant.valid <= io.out.grant.valid
      io.out.grant.ready <= io.in[3].grant.ready
      skip
    io.in[3].grant.bits <- io.out.grant.bits
    node T_1630 = shr(io.out.grant.bits.client_xact_id, 3)
    io.in[3].grant.bits.client_xact_id <= T_1630
    io.in[4].grant.valid <= UInt<1>("h00")
    node T_1632 = bits(io.out.grant.bits.client_xact_id, 2, 0)
    node T_1634 = eq(T_1632, UInt<3>("h04"))
    when T_1634 :
      io.in[4].grant.valid <= io.out.grant.valid
      io.out.grant.ready <= io.in[4].grant.ready
      skip
    io.in[4].grant.bits <- io.out.grant.bits
    node T_1635 = shr(io.out.grant.bits.client_xact_id, 3)
    io.in[4].grant.bits.client_xact_id <= T_1635
    io.in[5].grant.valid <= UInt<1>("h00")
    node T_1637 = bits(io.out.grant.bits.client_xact_id, 2, 0)
    node T_1639 = eq(T_1637, UInt<3>("h05"))
    when T_1639 :
      io.in[5].grant.valid <= io.out.grant.valid
      io.out.grant.ready <= io.in[5].grant.ready
      skip
    io.in[5].grant.bits <- io.out.grant.bits
    node T_1640 = shr(io.out.grant.bits.client_xact_id, 3)
    io.in[5].grant.bits.client_xact_id <= T_1640
    io.in[6].grant.valid <= UInt<1>("h00")
    node T_1642 = bits(io.out.grant.bits.client_xact_id, 2, 0)
    node T_1644 = eq(T_1642, UInt<3>("h06"))
    when T_1644 :
      io.in[6].grant.valid <= io.out.grant.valid
      io.out.grant.ready <= io.in[6].grant.ready
      skip
    io.in[6].grant.bits <- io.out.grant.bits
    node T_1645 = shr(io.out.grant.bits.client_xact_id, 3)
    io.in[6].grant.bits.client_xact_id <= T_1645
    io.in[7].grant.valid <= UInt<1>("h00")
    node T_1647 = bits(io.out.grant.bits.client_xact_id, 2, 0)
    node T_1649 = eq(T_1647, UInt<3>("h07"))
    when T_1649 :
      io.in[7].grant.valid <= io.out.grant.valid
      io.out.grant.ready <= io.in[7].grant.ready
      skip
    io.in[7].grant.bits <- io.out.grant.bits
    node T_1650 = shr(io.out.grant.bits.client_xact_id, 3)
    io.in[7].grant.bits.client_xact_id <= T_1650
    
  module L2BroadcastHub : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}}
    
    io is invalid
    inst T_1060 of BroadcastVoluntaryReleaseTracker
    T_1060.io is invalid
    T_1060.clk <= clk
    T_1060.reset <= reset
    inst T_1061 of BroadcastAcquireTracker
    T_1061.io is invalid
    T_1061.clk <= clk
    T_1061.reset <= reset
    inst T_1062 of BroadcastAcquireTracker_27
    T_1062.io is invalid
    T_1062.clk <= clk
    T_1062.reset <= reset
    inst T_1063 of BroadcastAcquireTracker_28
    T_1063.io is invalid
    T_1063.clk <= clk
    T_1063.reset <= reset
    inst T_1064 of BroadcastAcquireTracker_29
    T_1064.io is invalid
    T_1064.clk <= clk
    T_1064.reset <= reset
    inst T_1065 of BroadcastAcquireTracker_30
    T_1065.io is invalid
    T_1065.clk <= clk
    T_1065.reset <= reset
    inst T_1066 of BroadcastAcquireTracker_31
    T_1066.io is invalid
    T_1066.clk <= clk
    T_1066.reset <= reset
    inst T_1067 of BroadcastAcquireTracker_32
    T_1067.io is invalid
    T_1067.clk <= clk
    T_1067.reset <= reset
    T_1060.io.incoherent <= io.incoherent
    T_1061.io.incoherent <= io.incoherent
    T_1062.io.incoherent <= io.incoherent
    T_1063.io.incoherent <= io.incoherent
    T_1064.io.incoherent <= io.incoherent
    T_1065.io.incoherent <= io.incoherent
    T_1066.io.incoherent <= io.incoherent
    T_1067.io.incoherent <= io.incoherent
    reg sdq : UInt<128>[4], clk
    reg sdq_val : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    node T_1085 = not(sdq_val)
    node T_1086 = bits(T_1085, 0, 0)
    node T_1087 = bits(T_1085, 1, 1)
    node T_1088 = bits(T_1085, 2, 2)
    node T_1089 = bits(T_1085, 3, 3)
    wire T_1091 : UInt<1>[4]
    T_1091[0] <= T_1086
    T_1091[1] <= T_1087
    T_1091[2] <= T_1088
    T_1091[3] <= T_1089
    node T_1101 = mux(T_1091[2], UInt<2>("h02"), UInt<2>("h03"))
    node T_1102 = mux(T_1091[1], UInt<1>("h01"), T_1101)
    node sdq_alloc_id = mux(T_1091[0], UInt<1>("h00"), T_1102)
    node T_1104 = not(sdq_val)
    node T_1106 = eq(T_1104, UInt<1>("h00"))
    node sdq_rdy = eq(T_1106, UInt<1>("h00"))
    node T_1109 = and(io.inner.acquire.ready, io.inner.acquire.valid)
    wire T_1114 : UInt<3>[3]
    T_1114[0] <= UInt<3>("h02")
    T_1114[1] <= UInt<3>("h03")
    T_1114[2] <= UInt<3>("h04")
    node T_1119 = eq(T_1114[0], io.inner.acquire.bits.a_type)
    node T_1120 = eq(T_1114[1], io.inner.acquire.bits.a_type)
    node T_1121 = eq(T_1114[2], io.inner.acquire.bits.a_type)
    node T_1123 = or(UInt<1>("h00"), T_1119)
    node T_1124 = or(T_1123, T_1120)
    node T_1125 = or(T_1124, T_1121)
    node T_1126 = and(io.inner.acquire.bits.is_builtin_type, T_1125)
    node sdq_enq = and(T_1109, T_1126)
    when sdq_enq :
      sdq[sdq_alloc_id] <= io.inner.acquire.bits.data
      skip
    wire T_1130 : UInt<1>[8]
    T_1130[0] <= T_1060.io.has_acquire_conflict
    T_1130[1] <= T_1061.io.has_acquire_conflict
    T_1130[2] <= T_1062.io.has_acquire_conflict
    T_1130[3] <= T_1063.io.has_acquire_conflict
    T_1130[4] <= T_1064.io.has_acquire_conflict
    T_1130[5] <= T_1065.io.has_acquire_conflict
    T_1130[6] <= T_1066.io.has_acquire_conflict
    T_1130[7] <= T_1067.io.has_acquire_conflict
    node T_1140 = cat(T_1130[7], T_1130[6])
    node T_1141 = cat(T_1130[5], T_1130[4])
    node T_1142 = cat(T_1140, T_1141)
    node T_1143 = cat(T_1130[3], T_1130[2])
    node T_1144 = cat(T_1130[1], T_1130[0])
    node T_1145 = cat(T_1143, T_1144)
    node acquireConflicts = cat(T_1142, T_1145)
    wire T_1148 : UInt<1>[8]
    T_1148[0] <= T_1060.io.has_acquire_match
    T_1148[1] <= T_1061.io.has_acquire_match
    T_1148[2] <= T_1062.io.has_acquire_match
    T_1148[3] <= T_1063.io.has_acquire_match
    T_1148[4] <= T_1064.io.has_acquire_match
    T_1148[5] <= T_1065.io.has_acquire_match
    T_1148[6] <= T_1066.io.has_acquire_match
    T_1148[7] <= T_1067.io.has_acquire_match
    node T_1158 = cat(T_1148[7], T_1148[6])
    node T_1159 = cat(T_1148[5], T_1148[4])
    node T_1160 = cat(T_1158, T_1159)
    node T_1161 = cat(T_1148[3], T_1148[2])
    node T_1162 = cat(T_1148[1], T_1148[0])
    node T_1163 = cat(T_1161, T_1162)
    node acquireMatches = cat(T_1160, T_1163)
    wire T_1166 : UInt<1>[8]
    T_1166[0] <= T_1060.io.inner.acquire.ready
    T_1166[1] <= T_1061.io.inner.acquire.ready
    T_1166[2] <= T_1062.io.inner.acquire.ready
    T_1166[3] <= T_1063.io.inner.acquire.ready
    T_1166[4] <= T_1064.io.inner.acquire.ready
    T_1166[5] <= T_1065.io.inner.acquire.ready
    T_1166[6] <= T_1066.io.inner.acquire.ready
    T_1166[7] <= T_1067.io.inner.acquire.ready
    node T_1176 = cat(T_1166[7], T_1166[6])
    node T_1177 = cat(T_1166[5], T_1166[4])
    node T_1178 = cat(T_1176, T_1177)
    node T_1179 = cat(T_1166[3], T_1166[2])
    node T_1180 = cat(T_1166[1], T_1166[0])
    node T_1181 = cat(T_1179, T_1180)
    node acquireReadys = cat(T_1178, T_1181)
    node T_1184 = neq(acquireMatches, UInt<1>("h00"))
    node T_1185 = bits(acquireMatches, 0, 0)
    node T_1186 = bits(acquireMatches, 1, 1)
    node T_1187 = bits(acquireMatches, 2, 2)
    node T_1188 = bits(acquireMatches, 3, 3)
    node T_1189 = bits(acquireMatches, 4, 4)
    node T_1190 = bits(acquireMatches, 5, 5)
    node T_1191 = bits(acquireMatches, 6, 6)
    node T_1192 = bits(acquireMatches, 7, 7)
    wire T_1194 : UInt<1>[8]
    T_1194[0] <= T_1185
    T_1194[1] <= T_1186
    T_1194[2] <= T_1187
    T_1194[3] <= T_1188
    T_1194[4] <= T_1189
    T_1194[5] <= T_1190
    T_1194[6] <= T_1191
    T_1194[7] <= T_1192
    node T_1212 = mux(T_1194[6], UInt<3>("h06"), UInt<3>("h07"))
    node T_1213 = mux(T_1194[5], UInt<3>("h05"), T_1212)
    node T_1214 = mux(T_1194[4], UInt<3>("h04"), T_1213)
    node T_1215 = mux(T_1194[3], UInt<2>("h03"), T_1214)
    node T_1216 = mux(T_1194[2], UInt<2>("h02"), T_1215)
    node T_1217 = mux(T_1194[1], UInt<1>("h01"), T_1216)
    node T_1218 = mux(T_1194[0], UInt<1>("h00"), T_1217)
    node T_1219 = bits(acquireReadys, 0, 0)
    node T_1220 = bits(acquireReadys, 1, 1)
    node T_1221 = bits(acquireReadys, 2, 2)
    node T_1222 = bits(acquireReadys, 3, 3)
    node T_1223 = bits(acquireReadys, 4, 4)
    node T_1224 = bits(acquireReadys, 5, 5)
    node T_1225 = bits(acquireReadys, 6, 6)
    node T_1226 = bits(acquireReadys, 7, 7)
    wire T_1228 : UInt<1>[8]
    T_1228[0] <= T_1219
    T_1228[1] <= T_1220
    T_1228[2] <= T_1221
    T_1228[3] <= T_1222
    T_1228[4] <= T_1223
    T_1228[5] <= T_1224
    T_1228[6] <= T_1225
    T_1228[7] <= T_1226
    node T_1246 = mux(T_1228[6], UInt<3>("h06"), UInt<3>("h07"))
    node T_1247 = mux(T_1228[5], UInt<3>("h05"), T_1246)
    node T_1248 = mux(T_1228[4], UInt<3>("h04"), T_1247)
    node T_1249 = mux(T_1228[3], UInt<2>("h03"), T_1248)
    node T_1250 = mux(T_1228[2], UInt<2>("h02"), T_1249)
    node T_1251 = mux(T_1228[1], UInt<1>("h01"), T_1250)
    node T_1252 = mux(T_1228[0], UInt<1>("h00"), T_1251)
    node acquire_idx = mux(T_1184, T_1218, T_1252)
    node T_1255 = neq(acquireConflicts, UInt<1>("h00"))
    node T_1257 = eq(sdq_rdy, UInt<1>("h00"))
    node block_acquires = or(T_1255, T_1257)
    node T_1260 = neq(acquireReadys, UInt<1>("h00"))
    node T_1262 = eq(block_acquires, UInt<1>("h00"))
    node T_1263 = and(T_1260, T_1262)
    io.inner.acquire.ready <= T_1263
    T_1060.io.inner.acquire.bits <- io.inner.acquire.bits
    wire T_1310 : {idx : UInt<2>, loc : UInt<2>}
    T_1310 is invalid
    T_1310.idx <= sdq_alloc_id
    T_1310.loc <= UInt<1>("h00")
    node T_1356 = cat(T_1310.idx, T_1310.loc)
    T_1060.io.inner.acquire.bits.data <= T_1356
    node T_1358 = eq(block_acquires, UInt<1>("h00"))
    node T_1359 = and(io.inner.acquire.valid, T_1358)
    node T_1361 = eq(acquire_idx, UInt<1>("h00"))
    node T_1362 = and(T_1359, T_1361)
    T_1060.io.inner.acquire.valid <= T_1362
    T_1061.io.inner.acquire.bits <- io.inner.acquire.bits
    wire T_1409 : {idx : UInt<2>, loc : UInt<2>}
    T_1409 is invalid
    T_1409.idx <= sdq_alloc_id
    T_1409.loc <= UInt<1>("h00")
    node T_1455 = cat(T_1409.idx, T_1409.loc)
    T_1061.io.inner.acquire.bits.data <= T_1455
    node T_1457 = eq(block_acquires, UInt<1>("h00"))
    node T_1458 = and(io.inner.acquire.valid, T_1457)
    node T_1460 = eq(acquire_idx, UInt<1>("h01"))
    node T_1461 = and(T_1458, T_1460)
    T_1061.io.inner.acquire.valid <= T_1461
    T_1062.io.inner.acquire.bits <- io.inner.acquire.bits
    wire T_1508 : {idx : UInt<2>, loc : UInt<2>}
    T_1508 is invalid
    T_1508.idx <= sdq_alloc_id
    T_1508.loc <= UInt<1>("h00")
    node T_1554 = cat(T_1508.idx, T_1508.loc)
    T_1062.io.inner.acquire.bits.data <= T_1554
    node T_1556 = eq(block_acquires, UInt<1>("h00"))
    node T_1557 = and(io.inner.acquire.valid, T_1556)
    node T_1559 = eq(acquire_idx, UInt<2>("h02"))
    node T_1560 = and(T_1557, T_1559)
    T_1062.io.inner.acquire.valid <= T_1560
    T_1063.io.inner.acquire.bits <- io.inner.acquire.bits
    wire T_1607 : {idx : UInt<2>, loc : UInt<2>}
    T_1607 is invalid
    T_1607.idx <= sdq_alloc_id
    T_1607.loc <= UInt<1>("h00")
    node T_1653 = cat(T_1607.idx, T_1607.loc)
    T_1063.io.inner.acquire.bits.data <= T_1653
    node T_1655 = eq(block_acquires, UInt<1>("h00"))
    node T_1656 = and(io.inner.acquire.valid, T_1655)
    node T_1658 = eq(acquire_idx, UInt<2>("h03"))
    node T_1659 = and(T_1656, T_1658)
    T_1063.io.inner.acquire.valid <= T_1659
    T_1064.io.inner.acquire.bits <- io.inner.acquire.bits
    wire T_1706 : {idx : UInt<2>, loc : UInt<2>}
    T_1706 is invalid
    T_1706.idx <= sdq_alloc_id
    T_1706.loc <= UInt<1>("h00")
    node T_1752 = cat(T_1706.idx, T_1706.loc)
    T_1064.io.inner.acquire.bits.data <= T_1752
    node T_1754 = eq(block_acquires, UInt<1>("h00"))
    node T_1755 = and(io.inner.acquire.valid, T_1754)
    node T_1757 = eq(acquire_idx, UInt<3>("h04"))
    node T_1758 = and(T_1755, T_1757)
    T_1064.io.inner.acquire.valid <= T_1758
    T_1065.io.inner.acquire.bits <- io.inner.acquire.bits
    wire T_1805 : {idx : UInt<2>, loc : UInt<2>}
    T_1805 is invalid
    T_1805.idx <= sdq_alloc_id
    T_1805.loc <= UInt<1>("h00")
    node T_1851 = cat(T_1805.idx, T_1805.loc)
    T_1065.io.inner.acquire.bits.data <= T_1851
    node T_1853 = eq(block_acquires, UInt<1>("h00"))
    node T_1854 = and(io.inner.acquire.valid, T_1853)
    node T_1856 = eq(acquire_idx, UInt<3>("h05"))
    node T_1857 = and(T_1854, T_1856)
    T_1065.io.inner.acquire.valid <= T_1857
    T_1066.io.inner.acquire.bits <- io.inner.acquire.bits
    wire T_1904 : {idx : UInt<2>, loc : UInt<2>}
    T_1904 is invalid
    T_1904.idx <= sdq_alloc_id
    T_1904.loc <= UInt<1>("h00")
    node T_1950 = cat(T_1904.idx, T_1904.loc)
    T_1066.io.inner.acquire.bits.data <= T_1950
    node T_1952 = eq(block_acquires, UInt<1>("h00"))
    node T_1953 = and(io.inner.acquire.valid, T_1952)
    node T_1955 = eq(acquire_idx, UInt<3>("h06"))
    node T_1956 = and(T_1953, T_1955)
    T_1066.io.inner.acquire.valid <= T_1956
    T_1067.io.inner.acquire.bits <- io.inner.acquire.bits
    wire T_2003 : {idx : UInt<2>, loc : UInt<2>}
    T_2003 is invalid
    T_2003.idx <= sdq_alloc_id
    T_2003.loc <= UInt<1>("h00")
    node T_2049 = cat(T_2003.idx, T_2003.loc)
    T_1067.io.inner.acquire.bits.data <= T_2049
    node T_2051 = eq(block_acquires, UInt<1>("h00"))
    node T_2052 = and(io.inner.acquire.valid, T_2051)
    node T_2054 = eq(acquire_idx, UInt<3>("h07"))
    node T_2055 = and(T_2052, T_2054)
    T_1067.io.inner.acquire.valid <= T_2055
    node T_2056 = and(io.inner.release.ready, io.inner.release.valid)
    node T_2057 = and(T_2056, io.inner.release.bits.voluntary)
    wire T_2059 : UInt<2>[3]
    T_2059[0] <= UInt<1>("h00")
    T_2059[1] <= UInt<1>("h01")
    T_2059[2] <= UInt<2>("h02")
    node T_2064 = eq(T_2059[0], io.inner.release.bits.r_type)
    node T_2065 = eq(T_2059[1], io.inner.release.bits.r_type)
    node T_2066 = eq(T_2059[2], io.inner.release.bits.r_type)
    node T_2068 = or(UInt<1>("h00"), T_2064)
    node T_2069 = or(T_2068, T_2065)
    node T_2070 = or(T_2069, T_2066)
    node vwbdq_enq = and(T_2057, T_2070)
    reg rel_data_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when vwbdq_enq :
      node T_2075 = eq(rel_data_cnt, UInt<2>("h03"))
      node T_2077 = and(UInt<1>("h00"), T_2075)
      node T_2080 = add(rel_data_cnt, UInt<1>("h01"))
      node T_2081 = tail(T_2080, 1)
      node T_2082 = mux(T_2077, UInt<1>("h00"), T_2081)
      rel_data_cnt <= T_2082
      skip
    node rel_data_done = and(vwbdq_enq, T_2075)
    reg vwbdq : UInt<128>[4], clk
    when vwbdq_enq :
      vwbdq[rel_data_cnt] <= io.inner.release.bits.data
      skip
    wire T_2101 : UInt<1>[8]
    T_2101[0] <= T_1060.io.inner.release.ready
    T_2101[1] <= T_1061.io.inner.release.ready
    T_2101[2] <= T_1062.io.inner.release.ready
    T_2101[3] <= T_1063.io.inner.release.ready
    T_2101[4] <= T_1064.io.inner.release.ready
    T_2101[5] <= T_1065.io.inner.release.ready
    T_2101[6] <= T_1066.io.inner.release.ready
    T_2101[7] <= T_1067.io.inner.release.ready
    node T_2111 = cat(T_2101[7], T_2101[6])
    node T_2112 = cat(T_2101[5], T_2101[4])
    node T_2113 = cat(T_2111, T_2112)
    node T_2114 = cat(T_2101[3], T_2101[2])
    node T_2115 = cat(T_2101[1], T_2101[0])
    node T_2116 = cat(T_2114, T_2115)
    node releaseReadys = cat(T_2113, T_2116)
    wire T_2119 : UInt<1>[8]
    T_2119[0] <= T_1060.io.has_release_match
    T_2119[1] <= T_1061.io.has_release_match
    T_2119[2] <= T_1062.io.has_release_match
    T_2119[3] <= T_1063.io.has_release_match
    T_2119[4] <= T_1064.io.has_release_match
    T_2119[5] <= T_1065.io.has_release_match
    T_2119[6] <= T_1066.io.has_release_match
    T_2119[7] <= T_1067.io.has_release_match
    node T_2129 = cat(T_2119[7], T_2119[6])
    node T_2130 = cat(T_2119[5], T_2119[4])
    node T_2131 = cat(T_2129, T_2130)
    node T_2132 = cat(T_2119[3], T_2119[2])
    node T_2133 = cat(T_2119[1], T_2119[0])
    node T_2134 = cat(T_2132, T_2133)
    node releaseMatches = cat(T_2131, T_2134)
    node T_2136 = bits(releaseMatches, 0, 0)
    node T_2137 = bits(releaseMatches, 1, 1)
    node T_2138 = bits(releaseMatches, 2, 2)
    node T_2139 = bits(releaseMatches, 3, 3)
    node T_2140 = bits(releaseMatches, 4, 4)
    node T_2141 = bits(releaseMatches, 5, 5)
    node T_2142 = bits(releaseMatches, 6, 6)
    node T_2143 = bits(releaseMatches, 7, 7)
    wire T_2145 : UInt<1>[8]
    T_2145[0] <= T_2136
    T_2145[1] <= T_2137
    T_2145[2] <= T_2138
    T_2145[3] <= T_2139
    T_2145[4] <= T_2140
    T_2145[5] <= T_2141
    T_2145[6] <= T_2142
    T_2145[7] <= T_2143
    node T_2163 = mux(T_2145[6], UInt<3>("h06"), UInt<3>("h07"))
    node T_2164 = mux(T_2145[5], UInt<3>("h05"), T_2163)
    node T_2165 = mux(T_2145[4], UInt<3>("h04"), T_2164)
    node T_2166 = mux(T_2145[3], UInt<2>("h03"), T_2165)
    node T_2167 = mux(T_2145[2], UInt<2>("h02"), T_2166)
    node T_2168 = mux(T_2145[1], UInt<1>("h01"), T_2167)
    node release_idx = mux(T_2145[0], UInt<1>("h00"), T_2168)
    node T_2170 = dshr(releaseReadys, release_idx)
    node T_2171 = bits(T_2170, 0, 0)
    io.inner.release.ready <= T_2171
    node T_2173 = eq(release_idx, UInt<1>("h00"))
    node T_2174 = and(io.inner.release.valid, T_2173)
    T_1060.io.inner.release.valid <= T_2174
    T_1060.io.inner.release.bits <- io.inner.release.bits
    wire T_2221 : {idx : UInt<2>, loc : UInt<2>}
    T_2221 is invalid
    T_2221.idx <= rel_data_cnt
    T_2221.loc <= UInt<1>("h01")
    node T_2267 = cat(T_2221.idx, T_2221.loc)
    T_1060.io.inner.release.bits.data <= T_2267
    node T_2269 = eq(release_idx, UInt<1>("h01"))
    node T_2270 = and(io.inner.release.valid, T_2269)
    T_1061.io.inner.release.valid <= T_2270
    T_1061.io.inner.release.bits <- io.inner.release.bits
    wire T_2317 : {idx : UInt<2>, loc : UInt<2>}
    T_2317 is invalid
    T_2317.idx <= rel_data_cnt
    T_2317.loc <= UInt<2>("h02")
    node T_2363 = cat(T_2317.idx, T_2317.loc)
    T_1061.io.inner.release.bits.data <= T_2363
    node T_2365 = eq(release_idx, UInt<2>("h02"))
    node T_2366 = and(io.inner.release.valid, T_2365)
    T_1062.io.inner.release.valid <= T_2366
    T_1062.io.inner.release.bits <- io.inner.release.bits
    wire T_2413 : {idx : UInt<2>, loc : UInt<2>}
    T_2413 is invalid
    T_2413.idx <= rel_data_cnt
    T_2413.loc <= UInt<2>("h02")
    node T_2459 = cat(T_2413.idx, T_2413.loc)
    T_1062.io.inner.release.bits.data <= T_2459
    node T_2461 = eq(release_idx, UInt<2>("h03"))
    node T_2462 = and(io.inner.release.valid, T_2461)
    T_1063.io.inner.release.valid <= T_2462
    T_1063.io.inner.release.bits <- io.inner.release.bits
    wire T_2509 : {idx : UInt<2>, loc : UInt<2>}
    T_2509 is invalid
    T_2509.idx <= rel_data_cnt
    T_2509.loc <= UInt<2>("h02")
    node T_2555 = cat(T_2509.idx, T_2509.loc)
    T_1063.io.inner.release.bits.data <= T_2555
    node T_2557 = eq(release_idx, UInt<3>("h04"))
    node T_2558 = and(io.inner.release.valid, T_2557)
    T_1064.io.inner.release.valid <= T_2558
    T_1064.io.inner.release.bits <- io.inner.release.bits
    wire T_2605 : {idx : UInt<2>, loc : UInt<2>}
    T_2605 is invalid
    T_2605.idx <= rel_data_cnt
    T_2605.loc <= UInt<2>("h02")
    node T_2651 = cat(T_2605.idx, T_2605.loc)
    T_1064.io.inner.release.bits.data <= T_2651
    node T_2653 = eq(release_idx, UInt<3>("h05"))
    node T_2654 = and(io.inner.release.valid, T_2653)
    T_1065.io.inner.release.valid <= T_2654
    T_1065.io.inner.release.bits <- io.inner.release.bits
    wire T_2701 : {idx : UInt<2>, loc : UInt<2>}
    T_2701 is invalid
    T_2701.idx <= rel_data_cnt
    T_2701.loc <= UInt<2>("h02")
    node T_2747 = cat(T_2701.idx, T_2701.loc)
    T_1065.io.inner.release.bits.data <= T_2747
    node T_2749 = eq(release_idx, UInt<3>("h06"))
    node T_2750 = and(io.inner.release.valid, T_2749)
    T_1066.io.inner.release.valid <= T_2750
    T_1066.io.inner.release.bits <- io.inner.release.bits
    wire T_2797 : {idx : UInt<2>, loc : UInt<2>}
    T_2797 is invalid
    T_2797.idx <= rel_data_cnt
    T_2797.loc <= UInt<2>("h02")
    node T_2843 = cat(T_2797.idx, T_2797.loc)
    T_1066.io.inner.release.bits.data <= T_2843
    node T_2845 = eq(release_idx, UInt<3>("h07"))
    node T_2846 = and(io.inner.release.valid, T_2845)
    T_1067.io.inner.release.valid <= T_2846
    T_1067.io.inner.release.bits <- io.inner.release.bits
    wire T_2893 : {idx : UInt<2>, loc : UInt<2>}
    T_2893 is invalid
    T_2893.idx <= rel_data_cnt
    T_2893.loc <= UInt<2>("h02")
    node T_2939 = cat(T_2893.idx, T_2893.loc)
    T_1067.io.inner.release.bits.data <= T_2939
    node T_2941 = neq(releaseMatches, UInt<1>("h00"))
    node T_2943 = eq(T_2941, UInt<1>("h00"))
    node T_2944 = and(io.inner.release.valid, T_2943)
    node T_2946 = eq(T_2944, UInt<1>("h00"))
    node T_2948 = eq(reset, UInt<1>("h00"))
    when T_2948 :
      node T_2950 = eq(T_2946, UInt<1>("h00"))
      when T_2950 :
        node T_2952 = eq(reset, UInt<1>("h00"))
        when T_2952 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Non-voluntary release should always have a Tracker waiting for it.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    inst T_2953 of LockingRRArbiter_33
    T_2953.io is invalid
    T_2953.clk <= clk
    T_2953.reset <= reset
    io.inner.grant <- T_2953.io.out
    T_2953.io.in[0] <- T_1060.io.inner.grant
    T_2953.io.in[1] <- T_1061.io.inner.grant
    T_2953.io.in[2] <- T_1062.io.inner.grant
    T_2953.io.in[3] <- T_1063.io.inner.grant
    T_2953.io.in[4] <- T_1064.io.inner.grant
    T_2953.io.in[5] <- T_1065.io.inner.grant
    T_2953.io.in[6] <- T_1066.io.inner.grant
    T_2953.io.in[7] <- T_1067.io.inner.grant
    io.inner.grant.bits.data <= io.outer.grant.bits.data
    io.inner.grant.bits.addr_beat <= io.outer.grant.bits.addr_beat
    inst T_2954 of LockingRRArbiter_34
    T_2954.io is invalid
    T_2954.clk <= clk
    T_2954.reset <= reset
    io.inner.probe <- T_2954.io.out
    T_2954.io.in[0] <- T_1060.io.inner.probe
    T_2954.io.in[1] <- T_1061.io.inner.probe
    T_2954.io.in[2] <- T_1062.io.inner.probe
    T_2954.io.in[3] <- T_1063.io.inner.probe
    T_2954.io.in[4] <- T_1064.io.inner.probe
    T_2954.io.in[5] <- T_1065.io.inner.probe
    T_2954.io.in[6] <- T_1066.io.inner.probe
    T_2954.io.in[7] <- T_1067.io.inner.probe
    T_1060.io.inner.finish.bits <- io.inner.finish.bits
    T_1061.io.inner.finish.bits <- io.inner.finish.bits
    T_1062.io.inner.finish.bits <- io.inner.finish.bits
    T_1063.io.inner.finish.bits <- io.inner.finish.bits
    T_1064.io.inner.finish.bits <- io.inner.finish.bits
    T_1065.io.inner.finish.bits <- io.inner.finish.bits
    T_1066.io.inner.finish.bits <- io.inner.finish.bits
    T_1067.io.inner.finish.bits <- io.inner.finish.bits
    node T_2956 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h00"))
    node T_2957 = and(io.inner.finish.valid, T_2956)
    T_1060.io.inner.finish.valid <= T_2957
    node T_2959 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h01"))
    node T_2960 = and(io.inner.finish.valid, T_2959)
    T_1061.io.inner.finish.valid <= T_2960
    node T_2962 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h02"))
    node T_2963 = and(io.inner.finish.valid, T_2962)
    T_1062.io.inner.finish.valid <= T_2963
    node T_2965 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h03"))
    node T_2966 = and(io.inner.finish.valid, T_2965)
    T_1063.io.inner.finish.valid <= T_2966
    node T_2968 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h04"))
    node T_2969 = and(io.inner.finish.valid, T_2968)
    T_1064.io.inner.finish.valid <= T_2969
    node T_2971 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h05"))
    node T_2972 = and(io.inner.finish.valid, T_2971)
    T_1065.io.inner.finish.valid <= T_2972
    node T_2974 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h06"))
    node T_2975 = and(io.inner.finish.valid, T_2974)
    T_1066.io.inner.finish.valid <= T_2975
    node T_2977 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h07"))
    node T_2978 = and(io.inner.finish.valid, T_2977)
    T_1067.io.inner.finish.valid <= T_2978
    wire T_2980 : UInt<1>[8]
    T_2980[0] <= T_1060.io.inner.finish.ready
    T_2980[1] <= T_1061.io.inner.finish.ready
    T_2980[2] <= T_1062.io.inner.finish.ready
    T_2980[3] <= T_1063.io.inner.finish.ready
    T_2980[4] <= T_1064.io.inner.finish.ready
    T_2980[5] <= T_1065.io.inner.finish.ready
    T_2980[6] <= T_1066.io.inner.finish.ready
    T_2980[7] <= T_1067.io.inner.finish.ready
    io.inner.finish.ready <= T_2980[io.inner.finish.bits.manager_xact_id]
    inst outer_arb of ClientUncachedTileLinkIOArbiter
    outer_arb.io is invalid
    outer_arb.clk <= clk
    outer_arb.reset <= reset
    outer_arb.io.in[0] <- T_1060.io.outer
    outer_arb.io.in[1] <- T_1061.io.outer
    outer_arb.io.in[2] <- T_1062.io.outer
    outer_arb.io.in[3] <- T_1063.io.outer
    outer_arb.io.in[4] <- T_1064.io.outer
    outer_arb.io.in[5] <- T_1065.io.outer
    outer_arb.io.in[6] <- T_1066.io.outer
    outer_arb.io.in[7] <- T_1067.io.outer
    wire outer_data_ptr : {idx : UInt<2>, loc : UInt<2>}
    outer_data_ptr is invalid
    node T_3130 = bits(outer_arb.io.out.acquire.bits.data, 1, 0)
    outer_data_ptr.loc <= T_3130
    node T_3131 = bits(outer_arb.io.out.acquire.bits.data, 3, 2)
    outer_data_ptr.idx <= T_3131
    node is_in_sdq = eq(outer_data_ptr.loc, UInt<1>("h00"))
    node T_3133 = and(io.outer.acquire.ready, io.outer.acquire.valid)
    wire T_3138 : UInt<3>[3]
    T_3138[0] <= UInt<3>("h02")
    T_3138[1] <= UInt<3>("h03")
    T_3138[2] <= UInt<3>("h04")
    node T_3143 = eq(T_3138[0], io.outer.acquire.bits.a_type)
    node T_3144 = eq(T_3138[1], io.outer.acquire.bits.a_type)
    node T_3145 = eq(T_3138[2], io.outer.acquire.bits.a_type)
    node T_3147 = or(UInt<1>("h00"), T_3143)
    node T_3148 = or(T_3147, T_3144)
    node T_3149 = or(T_3148, T_3145)
    node T_3150 = and(io.outer.acquire.bits.is_builtin_type, T_3149)
    node T_3151 = and(T_3133, T_3150)
    node T_3152 = eq(outer_data_ptr.loc, UInt<1>("h00"))
    node free_sdq = and(T_3151, T_3152)
    io.outer <- outer_arb.io.out
    node T_3156 = eq(UInt<1>("h01"), outer_data_ptr.loc)
    node T_3157 = mux(T_3156, vwbdq[outer_data_ptr.idx], io.inner.release.bits.data)
    node T_3158 = eq(UInt<1>("h00"), outer_data_ptr.loc)
    node T_3159 = mux(T_3158, sdq[outer_data_ptr.idx], T_3157)
    io.outer.acquire.bits.data <= T_3159
    node T_3160 = or(io.outer.acquire.valid, sdq_enq)
    when T_3160 :
      node T_3162 = dshl(UInt<1>("h01"), outer_data_ptr.idx)
      node T_3164 = sub(UInt<4>("h00"), free_sdq)
      node T_3165 = tail(T_3164, 1)
      node T_3166 = and(T_3162, T_3165)
      node T_3167 = not(T_3166)
      node T_3168 = and(sdq_val, T_3167)
      node T_3169 = bits(sdq_val, 3, 0)
      node T_3170 = not(T_3169)
      node T_3171 = bits(T_3170, 0, 0)
      node T_3172 = bits(T_3170, 1, 1)
      node T_3173 = bits(T_3170, 2, 2)
      node T_3174 = bits(T_3170, 3, 3)
      wire T_3180 : UInt<4>[4]
      T_3180[0] <= UInt<4>("h01")
      T_3180[1] <= UInt<4>("h02")
      T_3180[2] <= UInt<4>("h04")
      T_3180[3] <= UInt<4>("h08")
      node T_3188 = mux(T_3174, T_3180[3], UInt<4>("h00"))
      node T_3189 = mux(T_3173, T_3180[2], T_3188)
      node T_3190 = mux(T_3172, T_3180[1], T_3189)
      node T_3191 = mux(T_3171, T_3180[0], T_3190)
      node T_3193 = sub(UInt<4>("h00"), sdq_enq)
      node T_3194 = tail(T_3193, 1)
      node T_3195 = and(T_3191, T_3194)
      node T_3196 = or(T_3168, T_3195)
      sdq_val <= T_3196
      skip
    
  module Queue_36 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>}
    
    io is invalid
    cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[2]
    reg T_125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_127 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_125, T_127)
    node T_132 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_132)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_138 = and(io.enq.ready, io.enq.valid)
    node T_140 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_138, T_140)
    node T_142 = and(io.deq.ready, io.deq.valid)
    node T_144 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_142, T_144)
    when do_enq :
      infer mport T_146 = ram[T_125], clk
      T_146 <- io.enq.bits
      node T_159 = eq(T_125, UInt<1>("h01"))
      node T_161 = and(UInt<1>("h00"), T_159)
      node T_164 = add(T_125, UInt<1>("h01"))
      node T_165 = tail(T_164, 1)
      node T_166 = mux(T_161, UInt<1>("h00"), T_165)
      T_125 <= T_166
      skip
    when do_deq :
      node T_168 = eq(T_127, UInt<1>("h01"))
      node T_170 = and(UInt<1>("h00"), T_168)
      node T_173 = add(T_127, UInt<1>("h01"))
      node T_174 = tail(T_173, 1)
      node T_175 = mux(T_170, UInt<1>("h00"), T_174)
      T_127 <= T_175
      skip
    node T_176 = neq(do_enq, do_deq)
    when T_176 :
      maybe_full <= do_enq
      skip
    node T_178 = eq(empty, UInt<1>("h00"))
    node T_180 = and(UInt<1>("h00"), io.enq.valid)
    node T_181 = or(T_178, T_180)
    io.deq.valid <= T_181
    node T_183 = eq(full, UInt<1>("h00"))
    node T_185 = and(UInt<1>("h00"), io.deq.ready)
    node T_186 = or(T_183, T_185)
    io.enq.ready <= T_186
    infer mport T_187 = ram[T_127], clk
    node T_199 = mux(maybe_flow, io.enq.bits, T_187)
    io.deq.bits <- T_199
    node T_211 = sub(T_125, T_127)
    node ptr_diff = tail(T_211, 1)
    node T_213 = and(maybe_full, ptr_match)
    node T_214 = cat(T_213, ptr_diff)
    io.count <= T_214
    
  module Queue_37 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, count : UInt<2>}
    
    io is invalid
    cmem ram : UInt<5>[2]
    reg T_26 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_28 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_26, T_28)
    node T_33 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_33)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_39 = and(io.enq.ready, io.enq.valid)
    node T_41 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_39, T_41)
    node T_43 = and(io.deq.ready, io.deq.valid)
    node T_45 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_43, T_45)
    when do_enq :
      infer mport T_47 = ram[T_26], clk
      T_47 <= io.enq.bits
      node T_49 = eq(T_26, UInt<1>("h01"))
      node T_51 = and(UInt<1>("h00"), T_49)
      node T_54 = add(T_26, UInt<1>("h01"))
      node T_55 = tail(T_54, 1)
      node T_56 = mux(T_51, UInt<1>("h00"), T_55)
      T_26 <= T_56
      skip
    when do_deq :
      node T_58 = eq(T_28, UInt<1>("h01"))
      node T_60 = and(UInt<1>("h00"), T_58)
      node T_63 = add(T_28, UInt<1>("h01"))
      node T_64 = tail(T_63, 1)
      node T_65 = mux(T_60, UInt<1>("h00"), T_64)
      T_28 <= T_65
      skip
    node T_66 = neq(do_enq, do_deq)
    when T_66 :
      maybe_full <= do_enq
      skip
    node T_68 = eq(empty, UInt<1>("h00"))
    node T_70 = and(UInt<1>("h00"), io.enq.valid)
    node T_71 = or(T_68, T_70)
    io.deq.valid <= T_71
    node T_73 = eq(full, UInt<1>("h00"))
    node T_75 = and(UInt<1>("h00"), io.deq.ready)
    node T_76 = or(T_73, T_75)
    io.enq.ready <= T_76
    infer mport T_77 = ram[T_28], clk
    node T_78 = mux(maybe_flow, io.enq.bits, T_77)
    io.deq.bits <= T_78
    node T_79 = sub(T_26, T_28)
    node ptr_diff = tail(T_79, 1)
    node T_81 = and(maybe_full, ptr_match)
    node T_82 = cat(T_81, ptr_diff)
    io.count <= T_82
    
  module NastiErrorSlave : 
    input clk : Clock
    input reset : UInt<1>
    input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}
    
    io is invalid
    node T_322 = and(io.ar.ready, io.ar.valid)
    when T_322 :
      node T_324 = eq(reset, UInt<1>("h00"))
      when T_324 :
        printf(clk, UInt<1>(1), "Invalid read address %x\n", io.ar.bits.addr)
        skip
      skip
    node T_325 = and(io.aw.ready, io.aw.valid)
    when T_325 :
      node T_327 = eq(reset, UInt<1>("h00"))
      when T_327 :
        printf(clk, UInt<1>(1), "Invalid write address %x\n", io.aw.bits.addr)
        skip
      skip
    inst r_queue of Queue_36
    r_queue.io is invalid
    r_queue.clk <= clk
    r_queue.reset <= reset
    r_queue.io.enq <- io.ar
    reg responding : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg beats_left : UInt<8>, clk with : (reset => (reset, UInt<8>("h00")))
    node T_346 = eq(responding, UInt<1>("h00"))
    node T_347 = and(T_346, r_queue.io.deq.valid)
    when T_347 :
      responding <= UInt<1>("h01")
      beats_left <= r_queue.io.deq.bits.len
      skip
    node T_349 = and(r_queue.io.deq.valid, responding)
    io.r.valid <= T_349
    io.r.bits.id <= r_queue.io.deq.bits.id
    io.r.bits.data <= UInt<1>("h00")
    io.r.bits.resp <= UInt<2>("h03")
    node T_359 = eq(beats_left, UInt<1>("h00"))
    io.r.bits.last <= T_359
    node T_360 = and(io.r.ready, io.r.valid)
    node T_361 = and(T_360, io.r.bits.last)
    r_queue.io.deq.ready <= T_361
    node T_362 = and(io.r.ready, io.r.valid)
    when T_362 :
      node T_364 = eq(beats_left, UInt<1>("h00"))
      when T_364 :
        responding <= UInt<1>("h00")
        skip
      node T_367 = eq(T_364, UInt<1>("h00"))
      when T_367 :
        node T_369 = sub(beats_left, UInt<1>("h01"))
        node T_370 = tail(T_369, 1)
        beats_left <= T_370
        skip
      skip
    reg draining : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    io.w.ready <= draining
    node T_373 = and(io.aw.ready, io.aw.valid)
    when T_373 :
      draining <= UInt<1>("h01")
      skip
    node T_375 = and(io.w.ready, io.w.valid)
    node T_376 = and(T_375, io.w.bits.last)
    when T_376 :
      draining <= UInt<1>("h00")
      skip
    inst b_queue of Queue_37
    b_queue.io is invalid
    b_queue.clk <= clk
    b_queue.reset <= reset
    node T_381 = eq(draining, UInt<1>("h00"))
    node T_382 = and(io.aw.valid, T_381)
    b_queue.io.enq.valid <= T_382
    b_queue.io.enq.bits <= io.aw.bits.id
    node T_384 = eq(draining, UInt<1>("h00"))
    node T_385 = and(b_queue.io.enq.ready, T_384)
    io.aw.ready <= T_385
    node T_387 = eq(draining, UInt<1>("h00"))
    node T_388 = and(b_queue.io.deq.valid, T_387)
    io.b.valid <= T_388
    io.b.bits.id <= b_queue.io.deq.bits
    io.b.bits.resp <= UInt<2>("h03")
    node T_391 = eq(draining, UInt<1>("h00"))
    node T_392 = and(io.b.ready, T_391)
    b_queue.io.deq.ready <= T_392
    
  module RRArbiter_38 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<3>}
    
    io is invalid
    wire T_196 : UInt<3>
    T_196 is invalid
    io.out.valid <= io.in[T_196].valid
    io.out.bits <- io.in[T_196].bits
    io.chosen <= T_196
    io.in[T_196].ready <= UInt<1>("h00")
    reg T_233 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    node T_234 = gt(UInt<1>("h00"), T_233)
    node T_235 = and(io.in[0].valid, T_234)
    node T_237 = gt(UInt<1>("h01"), T_233)
    node T_238 = and(io.in[1].valid, T_237)
    node T_240 = gt(UInt<2>("h02"), T_233)
    node T_241 = and(io.in[2].valid, T_240)
    node T_243 = gt(UInt<2>("h03"), T_233)
    node T_244 = and(io.in[3].valid, T_243)
    node T_246 = gt(UInt<3>("h04"), T_233)
    node T_247 = and(io.in[4].valid, T_246)
    node T_250 = or(UInt<1>("h00"), T_235)
    node T_252 = eq(T_250, UInt<1>("h00"))
    node T_254 = or(UInt<1>("h00"), T_235)
    node T_255 = or(T_254, T_238)
    node T_257 = eq(T_255, UInt<1>("h00"))
    node T_259 = or(UInt<1>("h00"), T_235)
    node T_260 = or(T_259, T_238)
    node T_261 = or(T_260, T_241)
    node T_263 = eq(T_261, UInt<1>("h00"))
    node T_265 = or(UInt<1>("h00"), T_235)
    node T_266 = or(T_265, T_238)
    node T_267 = or(T_266, T_241)
    node T_268 = or(T_267, T_244)
    node T_270 = eq(T_268, UInt<1>("h00"))
    node T_272 = or(UInt<1>("h00"), T_235)
    node T_273 = or(T_272, T_238)
    node T_274 = or(T_273, T_241)
    node T_275 = or(T_274, T_244)
    node T_276 = or(T_275, T_247)
    node T_278 = eq(T_276, UInt<1>("h00"))
    node T_280 = or(UInt<1>("h00"), T_235)
    node T_281 = or(T_280, T_238)
    node T_282 = or(T_281, T_241)
    node T_283 = or(T_282, T_244)
    node T_284 = or(T_283, T_247)
    node T_285 = or(T_284, io.in[0].valid)
    node T_287 = eq(T_285, UInt<1>("h00"))
    node T_289 = or(UInt<1>("h00"), T_235)
    node T_290 = or(T_289, T_238)
    node T_291 = or(T_290, T_241)
    node T_292 = or(T_291, T_244)
    node T_293 = or(T_292, T_247)
    node T_294 = or(T_293, io.in[0].valid)
    node T_295 = or(T_294, io.in[1].valid)
    node T_297 = eq(T_295, UInt<1>("h00"))
    node T_299 = or(UInt<1>("h00"), T_235)
    node T_300 = or(T_299, T_238)
    node T_301 = or(T_300, T_241)
    node T_302 = or(T_301, T_244)
    node T_303 = or(T_302, T_247)
    node T_304 = or(T_303, io.in[0].valid)
    node T_305 = or(T_304, io.in[1].valid)
    node T_306 = or(T_305, io.in[2].valid)
    node T_308 = eq(T_306, UInt<1>("h00"))
    node T_310 = or(UInt<1>("h00"), T_235)
    node T_311 = or(T_310, T_238)
    node T_312 = or(T_311, T_241)
    node T_313 = or(T_312, T_244)
    node T_314 = or(T_313, T_247)
    node T_315 = or(T_314, io.in[0].valid)
    node T_316 = or(T_315, io.in[1].valid)
    node T_317 = or(T_316, io.in[2].valid)
    node T_318 = or(T_317, io.in[3].valid)
    node T_320 = eq(T_318, UInt<1>("h00"))
    node T_322 = gt(UInt<1>("h00"), T_233)
    node T_323 = and(UInt<1>("h01"), T_322)
    node T_324 = or(T_323, T_278)
    node T_326 = gt(UInt<1>("h01"), T_233)
    node T_327 = and(T_252, T_326)
    node T_328 = or(T_327, T_287)
    node T_330 = gt(UInt<2>("h02"), T_233)
    node T_331 = and(T_257, T_330)
    node T_332 = or(T_331, T_297)
    node T_334 = gt(UInt<2>("h03"), T_233)
    node T_335 = and(T_263, T_334)
    node T_336 = or(T_335, T_308)
    node T_338 = gt(UInt<3>("h04"), T_233)
    node T_339 = and(T_270, T_338)
    node T_340 = or(T_339, T_320)
    node T_342 = eq(UInt<3>("h04"), UInt<1>("h00"))
    node T_343 = mux(UInt<1>("h00"), T_342, T_324)
    node T_344 = and(T_343, io.out.ready)
    io.in[0].ready <= T_344
    node T_346 = eq(UInt<3>("h04"), UInt<1>("h01"))
    node T_347 = mux(UInt<1>("h00"), T_346, T_328)
    node T_348 = and(T_347, io.out.ready)
    io.in[1].ready <= T_348
    node T_350 = eq(UInt<3>("h04"), UInt<2>("h02"))
    node T_351 = mux(UInt<1>("h00"), T_350, T_332)
    node T_352 = and(T_351, io.out.ready)
    io.in[2].ready <= T_352
    node T_354 = eq(UInt<3>("h04"), UInt<2>("h03"))
    node T_355 = mux(UInt<1>("h00"), T_354, T_336)
    node T_356 = and(T_355, io.out.ready)
    io.in[3].ready <= T_356
    node T_358 = eq(UInt<3>("h04"), UInt<3>("h04"))
    node T_359 = mux(UInt<1>("h00"), T_358, T_340)
    node T_360 = and(T_359, io.out.ready)
    io.in[4].ready <= T_360
    node T_363 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04"))
    node T_365 = mux(io.in[2].valid, UInt<2>("h02"), T_363)
    node T_367 = mux(io.in[1].valid, UInt<1>("h01"), T_365)
    node T_369 = mux(io.in[0].valid, UInt<1>("h00"), T_367)
    node T_371 = gt(UInt<3>("h04"), T_233)
    node T_372 = and(io.in[4].valid, T_371)
    node T_374 = mux(T_372, UInt<3>("h04"), T_369)
    node T_376 = gt(UInt<2>("h03"), T_233)
    node T_377 = and(io.in[3].valid, T_376)
    node T_379 = mux(T_377, UInt<2>("h03"), T_374)
    node T_381 = gt(UInt<2>("h02"), T_233)
    node T_382 = and(io.in[2].valid, T_381)
    node T_384 = mux(T_382, UInt<2>("h02"), T_379)
    node T_386 = gt(UInt<1>("h01"), T_233)
    node T_387 = and(io.in[1].valid, T_386)
    node T_389 = mux(T_387, UInt<1>("h01"), T_384)
    node T_390 = mux(UInt<1>("h00"), UInt<3>("h04"), T_389)
    T_196 <= T_390
    node T_391 = and(io.out.ready, io.out.valid)
    when T_391 :
      T_233 <= T_196
      skip
    
  module JunctionsPeekingArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}
    
    io is invalid
    reg T_273 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg T_275 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_277 : UInt<1>[5]
    T_277[0] <= io.in[0].valid
    T_277[1] <= io.in[1].valid
    T_277[2] <= io.in[2].valid
    T_277[3] <= io.in[3].valid
    T_277[4] <= io.in[4].valid
    node T_285 = add(T_273, UInt<1>("h01"))
    node T_286 = tail(T_285, 1)
    node T_288 = lt(T_286, UInt<3>("h05"))
    node T_290 = add(UInt<1>("h00"), T_286)
    node T_291 = tail(T_290, 1)
    node T_294 = sub(T_286, UInt<3>("h05"))
    node T_295 = tail(T_294, 1)
    node T_297 = mux(T_288, T_277[T_291], T_277[T_295])
    node T_299 = lt(T_286, UInt<3>("h04"))
    node T_301 = add(UInt<1>("h01"), T_286)
    node T_302 = tail(T_301, 1)
    node T_305 = sub(T_286, UInt<3>("h04"))
    node T_306 = tail(T_305, 1)
    node T_308 = mux(T_299, T_277[T_302], T_277[T_306])
    node T_310 = lt(T_286, UInt<2>("h03"))
    node T_312 = add(UInt<2>("h02"), T_286)
    node T_313 = tail(T_312, 1)
    node T_316 = sub(T_286, UInt<2>("h03"))
    node T_317 = tail(T_316, 1)
    node T_319 = mux(T_310, T_277[T_313], T_277[T_317])
    node T_321 = lt(T_286, UInt<2>("h02"))
    node T_323 = add(UInt<2>("h03"), T_286)
    node T_324 = tail(T_323, 1)
    node T_327 = sub(T_286, UInt<2>("h02"))
    node T_328 = tail(T_327, 1)
    node T_330 = mux(T_321, T_277[T_324], T_277[T_328])
    node T_332 = lt(T_286, UInt<1>("h01"))
    node T_334 = add(UInt<3>("h04"), T_286)
    node T_335 = tail(T_334, 1)
    node T_338 = sub(T_286, UInt<1>("h01"))
    node T_339 = tail(T_338, 1)
    node T_341 = mux(T_332, T_277[T_335], T_277[T_339])
    wire T_343 : UInt<1>[5]
    T_343[0] <= T_297
    T_343[1] <= T_308
    T_343[2] <= T_319
    T_343[3] <= T_330
    T_343[4] <= T_341
    wire T_356 : UInt<3>[5]
    T_356[0] <= UInt<1>("h00")
    T_356[1] <= UInt<1>("h01")
    T_356[2] <= UInt<2>("h02")
    T_356[3] <= UInt<2>("h03")
    T_356[4] <= UInt<3>("h04")
    node T_364 = add(T_273, UInt<1>("h01"))
    node T_365 = tail(T_364, 1)
    node T_367 = lt(T_365, UInt<3>("h05"))
    node T_369 = add(UInt<1>("h00"), T_365)
    node T_370 = tail(T_369, 1)
    node T_373 = sub(T_365, UInt<3>("h05"))
    node T_374 = tail(T_373, 1)
    node T_376 = mux(T_367, T_356[T_370], T_356[T_374])
    node T_378 = lt(T_365, UInt<3>("h04"))
    node T_380 = add(UInt<1>("h01"), T_365)
    node T_381 = tail(T_380, 1)
    node T_384 = sub(T_365, UInt<3>("h04"))
    node T_385 = tail(T_384, 1)
    node T_387 = mux(T_378, T_356[T_381], T_356[T_385])
    node T_389 = lt(T_365, UInt<2>("h03"))
    node T_391 = add(UInt<2>("h02"), T_365)
    node T_392 = tail(T_391, 1)
    node T_395 = sub(T_365, UInt<2>("h03"))
    node T_396 = tail(T_395, 1)
    node T_398 = mux(T_389, T_356[T_392], T_356[T_396])
    node T_400 = lt(T_365, UInt<2>("h02"))
    node T_402 = add(UInt<2>("h03"), T_365)
    node T_403 = tail(T_402, 1)
    node T_406 = sub(T_365, UInt<2>("h02"))
    node T_407 = tail(T_406, 1)
    node T_409 = mux(T_400, T_356[T_403], T_356[T_407])
    node T_411 = lt(T_365, UInt<1>("h01"))
    node T_413 = add(UInt<3>("h04"), T_365)
    node T_414 = tail(T_413, 1)
    node T_417 = sub(T_365, UInt<1>("h01"))
    node T_418 = tail(T_417, 1)
    node T_420 = mux(T_411, T_356[T_414], T_356[T_418])
    wire T_422 : UInt<3>[5]
    T_422[0] <= T_376
    T_422[1] <= T_387
    T_422[2] <= T_398
    T_422[3] <= T_409
    T_422[4] <= T_420
    node T_429 = mux(T_343[3], T_422[3], T_422[4])
    node T_430 = mux(T_343[2], T_422[2], T_429)
    node T_431 = mux(T_343[1], T_422[1], T_430)
    node T_432 = mux(T_343[0], T_422[0], T_431)
    node T_433 = mux(T_275, T_273, T_432)
    node T_435 = eq(T_433, UInt<1>("h00"))
    node T_436 = and(io.out.ready, T_435)
    io.in[0].ready <= T_436
    node T_438 = eq(T_433, UInt<1>("h01"))
    node T_439 = and(io.out.ready, T_438)
    io.in[1].ready <= T_439
    node T_441 = eq(T_433, UInt<2>("h02"))
    node T_442 = and(io.out.ready, T_441)
    io.in[2].ready <= T_442
    node T_444 = eq(T_433, UInt<2>("h03"))
    node T_445 = and(io.out.ready, T_444)
    io.in[3].ready <= T_445
    node T_447 = eq(T_433, UInt<3>("h04"))
    node T_448 = and(io.out.ready, T_447)
    io.in[4].ready <= T_448
    io.out.valid <= io.in[T_433].valid
    io.out.bits <- io.in[T_433].bits
    node T_479 = and(io.out.ready, io.out.valid)
    when T_479 :
      node T_481 = eq(T_275, UInt<1>("h00"))
      node T_483 = and(T_481, UInt<1>("h01"))
      when T_483 :
        T_273 <= T_432
        T_275 <= UInt<1>("h01")
        skip
      when io.out.bits.last :
        T_275 <= UInt<1>("h00")
        skip
      skip
    
  module NastiRouter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}
    
    io is invalid
    node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h00"))
    node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h040000000"))
    node T_1440 = and(T_1437, T_1439)
    node T_1442 = geq(io.master.ar.bits.addr, UInt<31>("h040000000"))
    node T_1444 = lt(io.master.ar.bits.addr, UInt<31>("h060000000"))
    node T_1445 = and(T_1442, T_1444)
    node T_1447 = geq(io.master.ar.bits.addr, UInt<31>("h060000000"))
    node T_1449 = lt(io.master.ar.bits.addr, UInt<32>("h080000000"))
    node T_1450 = and(T_1447, T_1449)
    node T_1452 = geq(io.master.ar.bits.addr, UInt<32>("h080000000"))
    node T_1454 = lt(io.master.ar.bits.addr, UInt<33>("h0100000000"))
    node T_1455 = and(T_1452, T_1454)
    wire T_1457 : UInt<1>[4]
    T_1457[0] <= T_1440
    T_1457[1] <= T_1445
    T_1457[2] <= T_1450
    T_1457[3] <= T_1455
    node T_1463 = cat(T_1457[3], T_1457[2])
    node T_1464 = cat(T_1457[1], T_1457[0])
    node ar_route = cat(T_1463, T_1464)
    node T_1467 = geq(io.master.aw.bits.addr, UInt<1>("h00"))
    node T_1469 = lt(io.master.aw.bits.addr, UInt<31>("h040000000"))
    node T_1470 = and(T_1467, T_1469)
    node T_1472 = geq(io.master.aw.bits.addr, UInt<31>("h040000000"))
    node T_1474 = lt(io.master.aw.bits.addr, UInt<31>("h060000000"))
    node T_1475 = and(T_1472, T_1474)
    node T_1477 = geq(io.master.aw.bits.addr, UInt<31>("h060000000"))
    node T_1479 = lt(io.master.aw.bits.addr, UInt<32>("h080000000"))
    node T_1480 = and(T_1477, T_1479)
    node T_1482 = geq(io.master.aw.bits.addr, UInt<32>("h080000000"))
    node T_1484 = lt(io.master.aw.bits.addr, UInt<33>("h0100000000"))
    node T_1485 = and(T_1482, T_1484)
    wire T_1487 : UInt<1>[4]
    T_1487[0] <= T_1470
    T_1487[1] <= T_1475
    T_1487[2] <= T_1480
    T_1487[3] <= T_1485
    node T_1493 = cat(T_1487[3], T_1487[2])
    node T_1494 = cat(T_1487[1], T_1487[0])
    node aw_route = cat(T_1493, T_1494)
    node T_1499 = bits(ar_route, 0, 0)
    node T_1500 = and(io.master.ar.valid, T_1499)
    io.slave[0].ar.valid <= T_1500
    io.slave[0].ar.bits <- io.master.ar.bits
    node T_1501 = bits(ar_route, 0, 0)
    node T_1502 = and(io.slave[0].ar.ready, T_1501)
    node T_1503 = or(UInt<1>("h00"), T_1502)
    node T_1504 = bits(aw_route, 0, 0)
    node T_1505 = and(io.master.aw.valid, T_1504)
    io.slave[0].aw.valid <= T_1505
    io.slave[0].aw.bits <- io.master.aw.bits
    node T_1506 = bits(aw_route, 0, 0)
    node T_1507 = and(io.slave[0].aw.ready, T_1506)
    node T_1508 = or(UInt<1>("h00"), T_1507)
    reg T_1510 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid)
    when T_1511 :
      T_1510 <= UInt<1>("h01")
      skip
    node T_1513 = and(io.slave[0].w.ready, io.slave[0].w.valid)
    node T_1514 = and(T_1513, io.slave[0].w.bits.last)
    when T_1514 :
      T_1510 <= UInt<1>("h00")
      skip
    node T_1516 = and(io.master.w.valid, T_1510)
    io.slave[0].w.valid <= T_1516
    io.slave[0].w.bits <- io.master.w.bits
    node T_1517 = and(io.slave[0].w.ready, T_1510)
    node T_1518 = or(UInt<1>("h00"), T_1517)
    node T_1519 = bits(ar_route, 1, 1)
    node T_1520 = and(io.master.ar.valid, T_1519)
    io.slave[1].ar.valid <= T_1520
    io.slave[1].ar.bits <- io.master.ar.bits
    node T_1521 = bits(ar_route, 1, 1)
    node T_1522 = and(io.slave[1].ar.ready, T_1521)
    node T_1523 = or(T_1503, T_1522)
    node T_1524 = bits(aw_route, 1, 1)
    node T_1525 = and(io.master.aw.valid, T_1524)
    io.slave[1].aw.valid <= T_1525
    io.slave[1].aw.bits <- io.master.aw.bits
    node T_1526 = bits(aw_route, 1, 1)
    node T_1527 = and(io.slave[1].aw.ready, T_1526)
    node T_1528 = or(T_1508, T_1527)
    reg T_1530 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid)
    when T_1531 :
      T_1530 <= UInt<1>("h01")
      skip
    node T_1533 = and(io.slave[1].w.ready, io.slave[1].w.valid)
    node T_1534 = and(T_1533, io.slave[1].w.bits.last)
    when T_1534 :
      T_1530 <= UInt<1>("h00")
      skip
    node T_1536 = and(io.master.w.valid, T_1530)
    io.slave[1].w.valid <= T_1536
    io.slave[1].w.bits <- io.master.w.bits
    node T_1537 = and(io.slave[1].w.ready, T_1530)
    node T_1538 = or(T_1518, T_1537)
    node T_1539 = bits(ar_route, 2, 2)
    node T_1540 = and(io.master.ar.valid, T_1539)
    io.slave[2].ar.valid <= T_1540
    io.slave[2].ar.bits <- io.master.ar.bits
    node T_1541 = bits(ar_route, 2, 2)
    node T_1542 = and(io.slave[2].ar.ready, T_1541)
    node T_1543 = or(T_1523, T_1542)
    node T_1544 = bits(aw_route, 2, 2)
    node T_1545 = and(io.master.aw.valid, T_1544)
    io.slave[2].aw.valid <= T_1545
    io.slave[2].aw.bits <- io.master.aw.bits
    node T_1546 = bits(aw_route, 2, 2)
    node T_1547 = and(io.slave[2].aw.ready, T_1546)
    node T_1548 = or(T_1528, T_1547)
    reg T_1550 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid)
    when T_1551 :
      T_1550 <= UInt<1>("h01")
      skip
    node T_1553 = and(io.slave[2].w.ready, io.slave[2].w.valid)
    node T_1554 = and(T_1553, io.slave[2].w.bits.last)
    when T_1554 :
      T_1550 <= UInt<1>("h00")
      skip
    node T_1556 = and(io.master.w.valid, T_1550)
    io.slave[2].w.valid <= T_1556
    io.slave[2].w.bits <- io.master.w.bits
    node T_1557 = and(io.slave[2].w.ready, T_1550)
    node T_1558 = or(T_1538, T_1557)
    node T_1559 = bits(ar_route, 3, 3)
    node T_1560 = and(io.master.ar.valid, T_1559)
    io.slave[3].ar.valid <= T_1560
    io.slave[3].ar.bits <- io.master.ar.bits
    node T_1561 = bits(ar_route, 3, 3)
    node T_1562 = and(io.slave[3].ar.ready, T_1561)
    node ar_ready = or(T_1543, T_1562)
    node T_1564 = bits(aw_route, 3, 3)
    node T_1565 = and(io.master.aw.valid, T_1564)
    io.slave[3].aw.valid <= T_1565
    io.slave[3].aw.bits <- io.master.aw.bits
    node T_1566 = bits(aw_route, 3, 3)
    node T_1567 = and(io.slave[3].aw.ready, T_1566)
    node aw_ready = or(T_1548, T_1567)
    reg T_1570 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid)
    when T_1571 :
      T_1570 <= UInt<1>("h01")
      skip
    node T_1573 = and(io.slave[3].w.ready, io.slave[3].w.valid)
    node T_1574 = and(T_1573, io.slave[3].w.bits.last)
    when T_1574 :
      T_1570 <= UInt<1>("h00")
      skip
    node T_1576 = and(io.master.w.valid, T_1570)
    io.slave[3].w.valid <= T_1576
    io.slave[3].w.bits <- io.master.w.bits
    node T_1577 = and(io.slave[3].w.ready, T_1570)
    node w_ready = or(T_1558, T_1577)
    node T_1580 = neq(ar_route, UInt<1>("h00"))
    node r_invalid = eq(T_1580, UInt<1>("h00"))
    node T_1584 = neq(aw_route, UInt<1>("h00"))
    node w_invalid = eq(T_1584, UInt<1>("h00"))
    inst err_slave of NastiErrorSlave
    err_slave.io is invalid
    err_slave.clk <= clk
    err_slave.reset <= reset
    node T_1588 = and(r_invalid, io.master.ar.valid)
    err_slave.io.ar.valid <= T_1588
    err_slave.io.ar.bits <- io.master.ar.bits
    node T_1589 = and(w_invalid, io.master.aw.valid)
    err_slave.io.aw.valid <= T_1589
    err_slave.io.aw.bits <- io.master.aw.bits
    err_slave.io.w.valid <= io.master.w.valid
    err_slave.io.w.bits <- io.master.w.bits
    node T_1590 = and(r_invalid, err_slave.io.ar.ready)
    node T_1591 = or(ar_ready, T_1590)
    io.master.ar.ready <= T_1591
    node T_1592 = and(w_invalid, err_slave.io.aw.ready)
    node T_1593 = or(aw_ready, T_1592)
    io.master.aw.ready <= T_1593
    node T_1594 = or(w_ready, err_slave.io.w.ready)
    io.master.w.ready <= T_1594
    inst b_arb of RRArbiter_38
    b_arb.io is invalid
    b_arb.clk <= clk
    b_arb.reset <= reset
    inst r_arb of JunctionsPeekingArbiter
    r_arb.io is invalid
    r_arb.clk <= clk
    r_arb.reset <= reset
    b_arb.io.in[0] <- io.slave[0].b
    r_arb.io.in[0] <- io.slave[0].r
    b_arb.io.in[1] <- io.slave[1].b
    r_arb.io.in[1] <- io.slave[1].r
    b_arb.io.in[2] <- io.slave[2].b
    r_arb.io.in[2] <- io.slave[2].r
    b_arb.io.in[3] <- io.slave[3].b
    r_arb.io.in[3] <- io.slave[3].r
    b_arb.io.in[4] <- err_slave.io.b
    r_arb.io.in[4] <- err_slave.io.r
    io.master.b <- b_arb.io.out
    io.master.r <- r_arb.io.out
    
  module NastiErrorSlave_40 : 
    input clk : Clock
    input reset : UInt<1>
    input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}
    
    io is invalid
    node T_322 = and(io.ar.ready, io.ar.valid)
    when T_322 :
      node T_324 = eq(reset, UInt<1>("h00"))
      when T_324 :
        printf(clk, UInt<1>(1), "Invalid read address %x\n", io.ar.bits.addr)
        skip
      skip
    node T_325 = and(io.aw.ready, io.aw.valid)
    when T_325 :
      node T_327 = eq(reset, UInt<1>("h00"))
      when T_327 :
        printf(clk, UInt<1>(1), "Invalid write address %x\n", io.aw.bits.addr)
        skip
      skip
    inst r_queue of Queue_36
    r_queue.io is invalid
    r_queue.clk <= clk
    r_queue.reset <= reset
    r_queue.io.enq <- io.ar
    reg responding : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg beats_left : UInt<8>, clk with : (reset => (reset, UInt<8>("h00")))
    node T_346 = eq(responding, UInt<1>("h00"))
    node T_347 = and(T_346, r_queue.io.deq.valid)
    when T_347 :
      responding <= UInt<1>("h01")
      beats_left <= r_queue.io.deq.bits.len
      skip
    node T_349 = and(r_queue.io.deq.valid, responding)
    io.r.valid <= T_349
    io.r.bits.id <= r_queue.io.deq.bits.id
    io.r.bits.data <= UInt<1>("h00")
    io.r.bits.resp <= UInt<2>("h03")
    node T_352 = eq(beats_left, UInt<1>("h00"))
    io.r.bits.last <= T_352
    node T_353 = and(io.r.ready, io.r.valid)
    node T_354 = and(T_353, io.r.bits.last)
    r_queue.io.deq.ready <= T_354
    node T_355 = and(io.r.ready, io.r.valid)
    when T_355 :
      node T_357 = eq(beats_left, UInt<1>("h00"))
      when T_357 :
        responding <= UInt<1>("h00")
        skip
      node T_360 = eq(T_357, UInt<1>("h00"))
      when T_360 :
        node T_362 = sub(beats_left, UInt<1>("h01"))
        node T_363 = tail(T_362, 1)
        beats_left <= T_363
        skip
      skip
    reg draining : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    io.w.ready <= draining
    node T_366 = and(io.aw.ready, io.aw.valid)
    when T_366 :
      draining <= UInt<1>("h01")
      skip
    node T_368 = and(io.w.ready, io.w.valid)
    node T_369 = and(T_368, io.w.bits.last)
    when T_369 :
      draining <= UInt<1>("h00")
      skip
    inst b_queue of Queue_37
    b_queue.io is invalid
    b_queue.clk <= clk
    b_queue.reset <= reset
    node T_374 = eq(draining, UInt<1>("h00"))
    node T_375 = and(io.aw.valid, T_374)
    b_queue.io.enq.valid <= T_375
    b_queue.io.enq.bits <= io.aw.bits.id
    node T_377 = eq(draining, UInt<1>("h00"))
    node T_378 = and(b_queue.io.enq.ready, T_377)
    io.aw.ready <= T_378
    node T_380 = eq(draining, UInt<1>("h00"))
    node T_381 = and(b_queue.io.deq.valid, T_380)
    io.b.valid <= T_381
    io.b.bits.id <= b_queue.io.deq.bits
    io.b.bits.resp <= UInt<2>("h03")
    node T_384 = eq(draining, UInt<1>("h00"))
    node T_385 = and(io.b.ready, T_384)
    b_queue.io.deq.ready <= T_385
    
  module NastiRouter_39 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}
    
    io is invalid
    node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h00"))
    node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h040000000"))
    node T_1440 = and(T_1437, T_1439)
    node T_1442 = geq(io.master.ar.bits.addr, UInt<31>("h040000000"))
    node T_1444 = lt(io.master.ar.bits.addr, UInt<31>("h060000000"))
    node T_1445 = and(T_1442, T_1444)
    node T_1447 = geq(io.master.ar.bits.addr, UInt<31>("h060000000"))
    node T_1449 = lt(io.master.ar.bits.addr, UInt<32>("h080000000"))
    node T_1450 = and(T_1447, T_1449)
    node T_1452 = geq(io.master.ar.bits.addr, UInt<32>("h080000000"))
    node T_1454 = lt(io.master.ar.bits.addr, UInt<33>("h0100000000"))
    node T_1455 = and(T_1452, T_1454)
    wire T_1457 : UInt<1>[4]
    T_1457[0] <= T_1440
    T_1457[1] <= T_1445
    T_1457[2] <= T_1450
    T_1457[3] <= T_1455
    node T_1463 = cat(T_1457[3], T_1457[2])
    node T_1464 = cat(T_1457[1], T_1457[0])
    node ar_route = cat(T_1463, T_1464)
    node T_1467 = geq(io.master.aw.bits.addr, UInt<1>("h00"))
    node T_1469 = lt(io.master.aw.bits.addr, UInt<31>("h040000000"))
    node T_1470 = and(T_1467, T_1469)
    node T_1472 = geq(io.master.aw.bits.addr, UInt<31>("h040000000"))
    node T_1474 = lt(io.master.aw.bits.addr, UInt<31>("h060000000"))
    node T_1475 = and(T_1472, T_1474)
    node T_1477 = geq(io.master.aw.bits.addr, UInt<31>("h060000000"))
    node T_1479 = lt(io.master.aw.bits.addr, UInt<32>("h080000000"))
    node T_1480 = and(T_1477, T_1479)
    node T_1482 = geq(io.master.aw.bits.addr, UInt<32>("h080000000"))
    node T_1484 = lt(io.master.aw.bits.addr, UInt<33>("h0100000000"))
    node T_1485 = and(T_1482, T_1484)
    wire T_1487 : UInt<1>[4]
    T_1487[0] <= T_1470
    T_1487[1] <= T_1475
    T_1487[2] <= T_1480
    T_1487[3] <= T_1485
    node T_1493 = cat(T_1487[3], T_1487[2])
    node T_1494 = cat(T_1487[1], T_1487[0])
    node aw_route = cat(T_1493, T_1494)
    node T_1499 = bits(ar_route, 0, 0)
    node T_1500 = and(io.master.ar.valid, T_1499)
    io.slave[0].ar.valid <= T_1500
    io.slave[0].ar.bits <- io.master.ar.bits
    node T_1501 = bits(ar_route, 0, 0)
    node T_1502 = and(io.slave[0].ar.ready, T_1501)
    node T_1503 = or(UInt<1>("h00"), T_1502)
    node T_1504 = bits(aw_route, 0, 0)
    node T_1505 = and(io.master.aw.valid, T_1504)
    io.slave[0].aw.valid <= T_1505
    io.slave[0].aw.bits <- io.master.aw.bits
    node T_1506 = bits(aw_route, 0, 0)
    node T_1507 = and(io.slave[0].aw.ready, T_1506)
    node T_1508 = or(UInt<1>("h00"), T_1507)
    reg T_1510 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid)
    when T_1511 :
      T_1510 <= UInt<1>("h01")
      skip
    node T_1513 = and(io.slave[0].w.ready, io.slave[0].w.valid)
    node T_1514 = and(T_1513, io.slave[0].w.bits.last)
    when T_1514 :
      T_1510 <= UInt<1>("h00")
      skip
    node T_1516 = and(io.master.w.valid, T_1510)
    io.slave[0].w.valid <= T_1516
    io.slave[0].w.bits <- io.master.w.bits
    node T_1517 = and(io.slave[0].w.ready, T_1510)
    node T_1518 = or(UInt<1>("h00"), T_1517)
    node T_1519 = bits(ar_route, 1, 1)
    node T_1520 = and(io.master.ar.valid, T_1519)
    io.slave[1].ar.valid <= T_1520
    io.slave[1].ar.bits <- io.master.ar.bits
    node T_1521 = bits(ar_route, 1, 1)
    node T_1522 = and(io.slave[1].ar.ready, T_1521)
    node T_1523 = or(T_1503, T_1522)
    node T_1524 = bits(aw_route, 1, 1)
    node T_1525 = and(io.master.aw.valid, T_1524)
    io.slave[1].aw.valid <= T_1525
    io.slave[1].aw.bits <- io.master.aw.bits
    node T_1526 = bits(aw_route, 1, 1)
    node T_1527 = and(io.slave[1].aw.ready, T_1526)
    node T_1528 = or(T_1508, T_1527)
    reg T_1530 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid)
    when T_1531 :
      T_1530 <= UInt<1>("h01")
      skip
    node T_1533 = and(io.slave[1].w.ready, io.slave[1].w.valid)
    node T_1534 = and(T_1533, io.slave[1].w.bits.last)
    when T_1534 :
      T_1530 <= UInt<1>("h00")
      skip
    node T_1536 = and(io.master.w.valid, T_1530)
    io.slave[1].w.valid <= T_1536
    io.slave[1].w.bits <- io.master.w.bits
    node T_1537 = and(io.slave[1].w.ready, T_1530)
    node T_1538 = or(T_1518, T_1537)
    node T_1539 = bits(ar_route, 2, 2)
    node T_1540 = and(io.master.ar.valid, T_1539)
    io.slave[2].ar.valid <= T_1540
    io.slave[2].ar.bits <- io.master.ar.bits
    node T_1541 = bits(ar_route, 2, 2)
    node T_1542 = and(io.slave[2].ar.ready, T_1541)
    node T_1543 = or(T_1523, T_1542)
    node T_1544 = bits(aw_route, 2, 2)
    node T_1545 = and(io.master.aw.valid, T_1544)
    io.slave[2].aw.valid <= T_1545
    io.slave[2].aw.bits <- io.master.aw.bits
    node T_1546 = bits(aw_route, 2, 2)
    node T_1547 = and(io.slave[2].aw.ready, T_1546)
    node T_1548 = or(T_1528, T_1547)
    reg T_1550 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid)
    when T_1551 :
      T_1550 <= UInt<1>("h01")
      skip
    node T_1553 = and(io.slave[2].w.ready, io.slave[2].w.valid)
    node T_1554 = and(T_1553, io.slave[2].w.bits.last)
    when T_1554 :
      T_1550 <= UInt<1>("h00")
      skip
    node T_1556 = and(io.master.w.valid, T_1550)
    io.slave[2].w.valid <= T_1556
    io.slave[2].w.bits <- io.master.w.bits
    node T_1557 = and(io.slave[2].w.ready, T_1550)
    node T_1558 = or(T_1538, T_1557)
    node T_1559 = bits(ar_route, 3, 3)
    node T_1560 = and(io.master.ar.valid, T_1559)
    io.slave[3].ar.valid <= T_1560
    io.slave[3].ar.bits <- io.master.ar.bits
    node T_1561 = bits(ar_route, 3, 3)
    node T_1562 = and(io.slave[3].ar.ready, T_1561)
    node ar_ready = or(T_1543, T_1562)
    node T_1564 = bits(aw_route, 3, 3)
    node T_1565 = and(io.master.aw.valid, T_1564)
    io.slave[3].aw.valid <= T_1565
    io.slave[3].aw.bits <- io.master.aw.bits
    node T_1566 = bits(aw_route, 3, 3)
    node T_1567 = and(io.slave[3].aw.ready, T_1566)
    node aw_ready = or(T_1548, T_1567)
    reg T_1570 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid)
    when T_1571 :
      T_1570 <= UInt<1>("h01")
      skip
    node T_1573 = and(io.slave[3].w.ready, io.slave[3].w.valid)
    node T_1574 = and(T_1573, io.slave[3].w.bits.last)
    when T_1574 :
      T_1570 <= UInt<1>("h00")
      skip
    node T_1576 = and(io.master.w.valid, T_1570)
    io.slave[3].w.valid <= T_1576
    io.slave[3].w.bits <- io.master.w.bits
    node T_1577 = and(io.slave[3].w.ready, T_1570)
    node w_ready = or(T_1558, T_1577)
    node T_1580 = neq(ar_route, UInt<1>("h00"))
    node r_invalid = eq(T_1580, UInt<1>("h00"))
    node T_1584 = neq(aw_route, UInt<1>("h00"))
    node w_invalid = eq(T_1584, UInt<1>("h00"))
    inst err_slave of NastiErrorSlave_40
    err_slave.io is invalid
    err_slave.clk <= clk
    err_slave.reset <= reset
    node T_1588 = and(r_invalid, io.master.ar.valid)
    err_slave.io.ar.valid <= T_1588
    err_slave.io.ar.bits <- io.master.ar.bits
    node T_1589 = and(w_invalid, io.master.aw.valid)
    err_slave.io.aw.valid <= T_1589
    err_slave.io.aw.bits <- io.master.aw.bits
    err_slave.io.w.valid <= io.master.w.valid
    err_slave.io.w.bits <- io.master.w.bits
    node T_1590 = and(r_invalid, err_slave.io.ar.ready)
    node T_1591 = or(ar_ready, T_1590)
    io.master.ar.ready <= T_1591
    node T_1592 = and(w_invalid, err_slave.io.aw.ready)
    node T_1593 = or(aw_ready, T_1592)
    io.master.aw.ready <= T_1593
    node T_1594 = or(w_ready, err_slave.io.w.ready)
    io.master.w.ready <= T_1594
    inst b_arb of RRArbiter_38
    b_arb.io is invalid
    b_arb.clk <= clk
    b_arb.reset <= reset
    inst r_arb of JunctionsPeekingArbiter
    r_arb.io is invalid
    r_arb.clk <= clk
    r_arb.reset <= reset
    b_arb.io.in[0] <- io.slave[0].b
    r_arb.io.in[0] <- io.slave[0].r
    b_arb.io.in[1] <- io.slave[1].b
    r_arb.io.in[1] <- io.slave[1].r
    b_arb.io.in[2] <- io.slave[2].b
    r_arb.io.in[2] <- io.slave[2].r
    b_arb.io.in[3] <- io.slave[3].b
    r_arb.io.in[3] <- io.slave[3].r
    b_arb.io.in[4] <- err_slave.io.b
    r_arb.io.in[4] <- err_slave.io.r
    io.master.b <- b_arb.io.out
    io.master.r <- r_arb.io.out
    
  module RRArbiter_45 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_306 : UInt<1>
    T_306 is invalid
    io.out.valid <= io.in[T_306].valid
    io.out.bits <- io.in[T_306].bits
    io.chosen <= T_306
    io.in[T_306].ready <= UInt<1>("h00")
    reg T_391 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_392 = gt(UInt<1>("h00"), T_391)
    node T_393 = and(io.in[0].valid, T_392)
    node T_395 = gt(UInt<1>("h01"), T_391)
    node T_396 = and(io.in[1].valid, T_395)
    node T_399 = or(UInt<1>("h00"), T_393)
    node T_401 = eq(T_399, UInt<1>("h00"))
    node T_403 = or(UInt<1>("h00"), T_393)
    node T_404 = or(T_403, T_396)
    node T_406 = eq(T_404, UInt<1>("h00"))
    node T_408 = or(UInt<1>("h00"), T_393)
    node T_409 = or(T_408, T_396)
    node T_410 = or(T_409, io.in[0].valid)
    node T_412 = eq(T_410, UInt<1>("h00"))
    node T_414 = gt(UInt<1>("h00"), T_391)
    node T_415 = and(UInt<1>("h01"), T_414)
    node T_416 = or(T_415, T_406)
    node T_418 = gt(UInt<1>("h01"), T_391)
    node T_419 = and(T_401, T_418)
    node T_420 = or(T_419, T_412)
    node T_422 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_423 = mux(UInt<1>("h00"), T_422, T_416)
    node T_424 = and(T_423, io.out.ready)
    io.in[0].ready <= T_424
    node T_426 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_427 = mux(UInt<1>("h00"), T_426, T_420)
    node T_428 = and(T_427, io.out.ready)
    io.in[1].ready <= T_428
    node T_431 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_433 = gt(UInt<1>("h01"), T_391)
    node T_434 = and(io.in[1].valid, T_433)
    node T_436 = mux(T_434, UInt<1>("h01"), T_431)
    node T_437 = mux(UInt<1>("h00"), UInt<1>("h01"), T_436)
    T_306 <= T_437
    node T_438 = and(io.out.ready, io.out.valid)
    when T_438 :
      T_391 <= T_306
      skip
    
  module NastiArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}
    
    io is invalid
    inst T_1767 of RRArbiter_45
    T_1767.io is invalid
    T_1767.clk <= clk
    T_1767.reset <= reset
    inst T_1780 of RRArbiter_45
    T_1780.io is invalid
    T_1780.clk <= clk
    T_1780.reset <= reset
    node T_1781 = bits(io.slave.r.bits.id, 0, 0)
    node T_1782 = bits(io.slave.b.bits.id, 0, 0)
    reg T_1784 : UInt<1>, clk
    reg T_1786 : UInt<1>, clk with : (reset => (reset, UInt<1>("h01")))
    node T_1787 = and(T_1780.io.out.ready, T_1780.io.out.valid)
    when T_1787 :
      T_1784 <= T_1780.io.chosen
      T_1786 <= UInt<1>("h00")
      skip
    node T_1789 = and(io.slave.w.ready, io.slave.w.valid)
    node T_1790 = and(T_1789, io.slave.w.bits.last)
    when T_1790 :
      T_1786 <= UInt<1>("h01")
      skip
    T_1767.io.in[0] <- io.master[0].ar
    node T_1793 = cat(io.master[0].ar.bits.id, UInt<1>("h00"))
    T_1767.io.in[0].bits.id <= T_1793
    T_1780.io.in[0] <- io.master[0].aw
    node T_1795 = cat(io.master[0].aw.bits.id, UInt<1>("h00"))
    T_1780.io.in[0].bits.id <= T_1795
    node T_1797 = eq(T_1781, UInt<1>("h00"))
    node T_1798 = and(io.slave.r.valid, T_1797)
    io.master[0].r.valid <= T_1798
    io.master[0].r.bits <- io.slave.r.bits
    node T_1800 = dshr(io.slave.r.bits.id, UInt<1>("h01"))
    io.master[0].r.bits.id <= T_1800
    node T_1802 = eq(T_1782, UInt<1>("h00"))
    node T_1803 = and(io.slave.b.valid, T_1802)
    io.master[0].b.valid <= T_1803
    io.master[0].b.bits <- io.slave.b.bits
    node T_1805 = dshr(io.slave.b.bits.id, UInt<1>("h01"))
    io.master[0].b.bits.id <= T_1805
    node T_1807 = eq(T_1784, UInt<1>("h00"))
    node T_1808 = and(io.slave.w.ready, T_1807)
    node T_1810 = eq(T_1786, UInt<1>("h00"))
    node T_1811 = and(T_1808, T_1810)
    io.master[0].w.ready <= T_1811
    T_1767.io.in[1] <- io.master[1].ar
    node T_1813 = cat(io.master[1].ar.bits.id, UInt<1>("h01"))
    T_1767.io.in[1].bits.id <= T_1813
    T_1780.io.in[1] <- io.master[1].aw
    node T_1815 = cat(io.master[1].aw.bits.id, UInt<1>("h01"))
    T_1780.io.in[1].bits.id <= T_1815
    node T_1817 = eq(T_1781, UInt<1>("h01"))
    node T_1818 = and(io.slave.r.valid, T_1817)
    io.master[1].r.valid <= T_1818
    io.master[1].r.bits <- io.slave.r.bits
    node T_1820 = dshr(io.slave.r.bits.id, UInt<1>("h01"))
    io.master[1].r.bits.id <= T_1820
    node T_1822 = eq(T_1782, UInt<1>("h01"))
    node T_1823 = and(io.slave.b.valid, T_1822)
    io.master[1].b.valid <= T_1823
    io.master[1].b.bits <- io.slave.b.bits
    node T_1825 = dshr(io.slave.b.bits.id, UInt<1>("h01"))
    io.master[1].b.bits.id <= T_1825
    node T_1827 = eq(T_1784, UInt<1>("h01"))
    node T_1828 = and(io.slave.w.ready, T_1827)
    node T_1830 = eq(T_1786, UInt<1>("h00"))
    node T_1831 = and(T_1828, T_1830)
    io.master[1].w.ready <= T_1831
    io.slave.r.ready <= io.master[T_1781].r.ready
    io.slave.b.ready <= io.master[T_1782].b.ready
    io.slave.w.bits <- io.master[T_1784].w.bits
    node T_2469 = eq(T_1786, UInt<1>("h00"))
    node T_2470 = and(io.master[T_1784].w.valid, T_2469)
    io.slave.w.valid <= T_2470
    io.slave.ar <- T_1767.io.out
    io.slave.aw.bits <- T_1780.io.out.bits
    node T_2471 = and(T_1780.io.out.valid, T_1786)
    io.slave.aw.valid <= T_2471
    node T_2472 = and(io.slave.aw.ready, T_1786)
    T_1780.io.out.ready <= T_2472
    
  module NastiCrossbar : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}
    
    io is invalid
    inst T_2710 of NastiRouter
    T_2710.io is invalid
    T_2710.clk <= clk
    T_2710.reset <= reset
    inst T_2711 of NastiRouter_39
    T_2711.io is invalid
    T_2711.clk <= clk
    T_2711.reset <= reset
    wire T_4146 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}[2]
    T_4146[0] <- T_2710.io
    T_4146[1] <- T_2711.io
    inst T_8449 of NastiArbiter
    T_8449.io is invalid
    T_8449.clk <= clk
    T_8449.reset <= reset
    inst T_8450 of NastiArbiter
    T_8450.io is invalid
    T_8450.clk <= clk
    T_8450.reset <= reset
    inst T_8451 of NastiArbiter
    T_8451.io is invalid
    T_8451.clk <= clk
    T_8451.reset <= reset
    inst T_8452 of NastiArbiter
    T_8452.io is invalid
    T_8452.clk <= clk
    T_8452.reset <= reset
    wire T_10206 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}[4]
    T_10206[0] <- T_8449.io
    T_10206[1] <- T_8450.io
    T_10206[2] <- T_8451.io
    T_10206[3] <- T_8452.io
    T_4146[0].master <- io.masters[0]
    T_4146[1].master <- io.masters[1]
    wire T_19131 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2]
    T_19131[0] <- T_4146[0].slave[0]
    T_19131[1] <- T_4146[1].slave[0]
    T_10206[0].master <= T_19131
    io.slaves[0] <- T_10206[0].slave
    wire T_19768 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2]
    T_19768[0] <- T_4146[0].slave[1]
    T_19768[1] <- T_4146[1].slave[1]
    T_10206[1].master <= T_19768
    io.slaves[1] <- T_10206[1].slave
    wire T_20405 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2]
    T_20405[0] <- T_4146[0].slave[2]
    T_20405[1] <- T_4146[1].slave[2]
    T_10206[2].master <= T_20405
    io.slaves[2] <- T_10206[2].slave
    wire T_21042 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2]
    T_21042[0] <- T_4146[0].slave[3]
    T_21042[1] <- T_4146[1].slave[3]
    T_10206[3].master <= T_21042
    io.slaves[3] <- T_10206[3].slave
    
  module RRArbiter_62 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<2>}
    
    io is invalid
    wire T_174 : UInt<2>
    T_174 is invalid
    io.out.valid <= io.in[T_174].valid
    io.out.bits <- io.in[T_174].bits
    io.chosen <= T_174
    io.in[T_174].ready <= UInt<1>("h00")
    reg T_211 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_212 = gt(UInt<1>("h00"), T_211)
    node T_213 = and(io.in[0].valid, T_212)
    node T_215 = gt(UInt<1>("h01"), T_211)
    node T_216 = and(io.in[1].valid, T_215)
    node T_218 = gt(UInt<2>("h02"), T_211)
    node T_219 = and(io.in[2].valid, T_218)
    node T_221 = gt(UInt<2>("h03"), T_211)
    node T_222 = and(io.in[3].valid, T_221)
    node T_225 = or(UInt<1>("h00"), T_213)
    node T_227 = eq(T_225, UInt<1>("h00"))
    node T_229 = or(UInt<1>("h00"), T_213)
    node T_230 = or(T_229, T_216)
    node T_232 = eq(T_230, UInt<1>("h00"))
    node T_234 = or(UInt<1>("h00"), T_213)
    node T_235 = or(T_234, T_216)
    node T_236 = or(T_235, T_219)
    node T_238 = eq(T_236, UInt<1>("h00"))
    node T_240 = or(UInt<1>("h00"), T_213)
    node T_241 = or(T_240, T_216)
    node T_242 = or(T_241, T_219)
    node T_243 = or(T_242, T_222)
    node T_245 = eq(T_243, UInt<1>("h00"))
    node T_247 = or(UInt<1>("h00"), T_213)
    node T_248 = or(T_247, T_216)
    node T_249 = or(T_248, T_219)
    node T_250 = or(T_249, T_222)
    node T_251 = or(T_250, io.in[0].valid)
    node T_253 = eq(T_251, UInt<1>("h00"))
    node T_255 = or(UInt<1>("h00"), T_213)
    node T_256 = or(T_255, T_216)
    node T_257 = or(T_256, T_219)
    node T_258 = or(T_257, T_222)
    node T_259 = or(T_258, io.in[0].valid)
    node T_260 = or(T_259, io.in[1].valid)
    node T_262 = eq(T_260, UInt<1>("h00"))
    node T_264 = or(UInt<1>("h00"), T_213)
    node T_265 = or(T_264, T_216)
    node T_266 = or(T_265, T_219)
    node T_267 = or(T_266, T_222)
    node T_268 = or(T_267, io.in[0].valid)
    node T_269 = or(T_268, io.in[1].valid)
    node T_270 = or(T_269, io.in[2].valid)
    node T_272 = eq(T_270, UInt<1>("h00"))
    node T_274 = gt(UInt<1>("h00"), T_211)
    node T_275 = and(UInt<1>("h01"), T_274)
    node T_276 = or(T_275, T_245)
    node T_278 = gt(UInt<1>("h01"), T_211)
    node T_279 = and(T_227, T_278)
    node T_280 = or(T_279, T_253)
    node T_282 = gt(UInt<2>("h02"), T_211)
    node T_283 = and(T_232, T_282)
    node T_284 = or(T_283, T_262)
    node T_286 = gt(UInt<2>("h03"), T_211)
    node T_287 = and(T_238, T_286)
    node T_288 = or(T_287, T_272)
    node T_290 = eq(UInt<2>("h03"), UInt<1>("h00"))
    node T_291 = mux(UInt<1>("h00"), T_290, T_276)
    node T_292 = and(T_291, io.out.ready)
    io.in[0].ready <= T_292
    node T_294 = eq(UInt<2>("h03"), UInt<1>("h01"))
    node T_295 = mux(UInt<1>("h00"), T_294, T_280)
    node T_296 = and(T_295, io.out.ready)
    io.in[1].ready <= T_296
    node T_298 = eq(UInt<2>("h03"), UInt<2>("h02"))
    node T_299 = mux(UInt<1>("h00"), T_298, T_284)
    node T_300 = and(T_299, io.out.ready)
    io.in[2].ready <= T_300
    node T_302 = eq(UInt<2>("h03"), UInt<2>("h03"))
    node T_303 = mux(UInt<1>("h00"), T_302, T_288)
    node T_304 = and(T_303, io.out.ready)
    io.in[3].ready <= T_304
    node T_307 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03"))
    node T_309 = mux(io.in[1].valid, UInt<1>("h01"), T_307)
    node T_311 = mux(io.in[0].valid, UInt<1>("h00"), T_309)
    node T_313 = gt(UInt<2>("h03"), T_211)
    node T_314 = and(io.in[3].valid, T_313)
    node T_316 = mux(T_314, UInt<2>("h03"), T_311)
    node T_318 = gt(UInt<2>("h02"), T_211)
    node T_319 = and(io.in[2].valid, T_318)
    node T_321 = mux(T_319, UInt<2>("h02"), T_316)
    node T_323 = gt(UInt<1>("h01"), T_211)
    node T_324 = and(io.in[1].valid, T_323)
    node T_326 = mux(T_324, UInt<1>("h01"), T_321)
    node T_327 = mux(UInt<1>("h00"), UInt<2>("h03"), T_326)
    T_174 <= T_327
    node T_328 = and(io.out.ready, io.out.valid)
    when T_328 :
      T_211 <= T_174
      skip
    
  module JunctionsPeekingArbiter_63 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}
    
    io is invalid
    reg T_243 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    reg T_245 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_247 : UInt<1>[4]
    T_247[0] <= io.in[0].valid
    T_247[1] <= io.in[1].valid
    T_247[2] <= io.in[2].valid
    T_247[3] <= io.in[3].valid
    node T_254 = add(T_243, UInt<1>("h01"))
    node T_255 = tail(T_254, 1)
    node T_257 = lt(T_255, UInt<3>("h04"))
    node T_259 = add(UInt<1>("h00"), T_255)
    node T_260 = tail(T_259, 1)
    node T_263 = sub(T_255, UInt<3>("h04"))
    node T_264 = tail(T_263, 1)
    node T_266 = mux(T_257, T_247[T_260], T_247[T_264])
    node T_268 = lt(T_255, UInt<2>("h03"))
    node T_270 = add(UInt<1>("h01"), T_255)
    node T_271 = tail(T_270, 1)
    node T_274 = sub(T_255, UInt<2>("h03"))
    node T_275 = tail(T_274, 1)
    node T_277 = mux(T_268, T_247[T_271], T_247[T_275])
    node T_279 = lt(T_255, UInt<2>("h02"))
    node T_281 = add(UInt<2>("h02"), T_255)
    node T_282 = tail(T_281, 1)
    node T_285 = sub(T_255, UInt<2>("h02"))
    node T_286 = tail(T_285, 1)
    node T_288 = mux(T_279, T_247[T_282], T_247[T_286])
    node T_290 = lt(T_255, UInt<1>("h01"))
    node T_292 = add(UInt<2>("h03"), T_255)
    node T_293 = tail(T_292, 1)
    node T_296 = sub(T_255, UInt<1>("h01"))
    node T_297 = tail(T_296, 1)
    node T_299 = mux(T_290, T_247[T_293], T_247[T_297])
    wire T_301 : UInt<1>[4]
    T_301[0] <= T_266
    T_301[1] <= T_277
    T_301[2] <= T_288
    T_301[3] <= T_299
    wire T_312 : UInt<2>[4]
    T_312[0] <= UInt<1>("h00")
    T_312[1] <= UInt<1>("h01")
    T_312[2] <= UInt<2>("h02")
    T_312[3] <= UInt<2>("h03")
    node T_319 = add(T_243, UInt<1>("h01"))
    node T_320 = tail(T_319, 1)
    node T_322 = lt(T_320, UInt<3>("h04"))
    node T_324 = add(UInt<1>("h00"), T_320)
    node T_325 = tail(T_324, 1)
    node T_328 = sub(T_320, UInt<3>("h04"))
    node T_329 = tail(T_328, 1)
    node T_331 = mux(T_322, T_312[T_325], T_312[T_329])
    node T_333 = lt(T_320, UInt<2>("h03"))
    node T_335 = add(UInt<1>("h01"), T_320)
    node T_336 = tail(T_335, 1)
    node T_339 = sub(T_320, UInt<2>("h03"))
    node T_340 = tail(T_339, 1)
    node T_342 = mux(T_333, T_312[T_336], T_312[T_340])
    node T_344 = lt(T_320, UInt<2>("h02"))
    node T_346 = add(UInt<2>("h02"), T_320)
    node T_347 = tail(T_346, 1)
    node T_350 = sub(T_320, UInt<2>("h02"))
    node T_351 = tail(T_350, 1)
    node T_353 = mux(T_344, T_312[T_347], T_312[T_351])
    node T_355 = lt(T_320, UInt<1>("h01"))
    node T_357 = add(UInt<2>("h03"), T_320)
    node T_358 = tail(T_357, 1)
    node T_361 = sub(T_320, UInt<1>("h01"))
    node T_362 = tail(T_361, 1)
    node T_364 = mux(T_355, T_312[T_358], T_312[T_362])
    wire T_366 : UInt<2>[4]
    T_366[0] <= T_331
    T_366[1] <= T_342
    T_366[2] <= T_353
    T_366[3] <= T_364
    node T_372 = mux(T_301[2], T_366[2], T_366[3])
    node T_373 = mux(T_301[1], T_366[1], T_372)
    node T_374 = mux(T_301[0], T_366[0], T_373)
    node T_375 = mux(T_245, T_243, T_374)
    node T_377 = eq(T_375, UInt<1>("h00"))
    node T_378 = and(io.out.ready, T_377)
    io.in[0].ready <= T_378
    node T_380 = eq(T_375, UInt<1>("h01"))
    node T_381 = and(io.out.ready, T_380)
    io.in[1].ready <= T_381
    node T_383 = eq(T_375, UInt<2>("h02"))
    node T_384 = and(io.out.ready, T_383)
    io.in[2].ready <= T_384
    node T_386 = eq(T_375, UInt<2>("h03"))
    node T_387 = and(io.out.ready, T_386)
    io.in[3].ready <= T_387
    io.out.valid <= io.in[T_375].valid
    io.out.bits <- io.in[T_375].bits
    node T_418 = and(io.out.ready, io.out.valid)
    when T_418 :
      node T_420 = eq(T_245, UInt<1>("h00"))
      node T_422 = and(T_420, UInt<1>("h01"))
      when T_422 :
        T_243 <= T_374
        T_245 <= UInt<1>("h01")
        skip
      when io.out.bits.last :
        T_245 <= UInt<1>("h00")
        skip
      skip
    
  module NastiRouter_58 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]}
    
    io is invalid
    node T_1278 = geq(io.master.ar.bits.addr, UInt<31>("h040000000"))
    node T_1280 = lt(io.master.ar.bits.addr, UInt<31>("h040008000"))
    node T_1281 = and(T_1278, T_1280)
    node T_1283 = geq(io.master.ar.bits.addr, UInt<31>("h040008000"))
    node T_1285 = lt(io.master.ar.bits.addr, UInt<31>("h040010000"))
    node T_1286 = and(T_1283, T_1285)
    node T_1288 = geq(io.master.ar.bits.addr, UInt<31>("h040010000"))
    node T_1290 = lt(io.master.ar.bits.addr, UInt<31>("h040010200"))
    node T_1291 = and(T_1288, T_1290)
    wire T_1293 : UInt<1>[3]
    T_1293[0] <= T_1281
    T_1293[1] <= T_1286
    T_1293[2] <= T_1291
    node T_1298 = cat(T_1293[1], T_1293[0])
    node ar_route = cat(T_1293[2], T_1298)
    node T_1301 = geq(io.master.aw.bits.addr, UInt<31>("h040000000"))
    node T_1303 = lt(io.master.aw.bits.addr, UInt<31>("h040008000"))
    node T_1304 = and(T_1301, T_1303)
    node T_1306 = geq(io.master.aw.bits.addr, UInt<31>("h040008000"))
    node T_1308 = lt(io.master.aw.bits.addr, UInt<31>("h040010000"))
    node T_1309 = and(T_1306, T_1308)
    node T_1311 = geq(io.master.aw.bits.addr, UInt<31>("h040010000"))
    node T_1313 = lt(io.master.aw.bits.addr, UInt<31>("h040010200"))
    node T_1314 = and(T_1311, T_1313)
    wire T_1316 : UInt<1>[3]
    T_1316[0] <= T_1304
    T_1316[1] <= T_1309
    T_1316[2] <= T_1314
    node T_1321 = cat(T_1316[1], T_1316[0])
    node aw_route = cat(T_1316[2], T_1321)
    node T_1326 = bits(ar_route, 0, 0)
    node T_1327 = and(io.master.ar.valid, T_1326)
    io.slave[0].ar.valid <= T_1327
    io.slave[0].ar.bits <- io.master.ar.bits
    node T_1328 = bits(ar_route, 0, 0)
    node T_1329 = and(io.slave[0].ar.ready, T_1328)
    node T_1330 = or(UInt<1>("h00"), T_1329)
    node T_1331 = bits(aw_route, 0, 0)
    node T_1332 = and(io.master.aw.valid, T_1331)
    io.slave[0].aw.valid <= T_1332
    io.slave[0].aw.bits <- io.master.aw.bits
    node T_1333 = bits(aw_route, 0, 0)
    node T_1334 = and(io.slave[0].aw.ready, T_1333)
    node T_1335 = or(UInt<1>("h00"), T_1334)
    reg T_1337 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1338 = and(io.slave[0].aw.ready, io.slave[0].aw.valid)
    when T_1338 :
      T_1337 <= UInt<1>("h01")
      skip
    node T_1340 = and(io.slave[0].w.ready, io.slave[0].w.valid)
    node T_1341 = and(T_1340, io.slave[0].w.bits.last)
    when T_1341 :
      T_1337 <= UInt<1>("h00")
      skip
    node T_1343 = and(io.master.w.valid, T_1337)
    io.slave[0].w.valid <= T_1343
    io.slave[0].w.bits <- io.master.w.bits
    node T_1344 = and(io.slave[0].w.ready, T_1337)
    node T_1345 = or(UInt<1>("h00"), T_1344)
    node T_1346 = bits(ar_route, 1, 1)
    node T_1347 = and(io.master.ar.valid, T_1346)
    io.slave[1].ar.valid <= T_1347
    io.slave[1].ar.bits <- io.master.ar.bits
    node T_1348 = bits(ar_route, 1, 1)
    node T_1349 = and(io.slave[1].ar.ready, T_1348)
    node T_1350 = or(T_1330, T_1349)
    node T_1351 = bits(aw_route, 1, 1)
    node T_1352 = and(io.master.aw.valid, T_1351)
    io.slave[1].aw.valid <= T_1352
    io.slave[1].aw.bits <- io.master.aw.bits
    node T_1353 = bits(aw_route, 1, 1)
    node T_1354 = and(io.slave[1].aw.ready, T_1353)
    node T_1355 = or(T_1335, T_1354)
    reg T_1357 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1358 = and(io.slave[1].aw.ready, io.slave[1].aw.valid)
    when T_1358 :
      T_1357 <= UInt<1>("h01")
      skip
    node T_1360 = and(io.slave[1].w.ready, io.slave[1].w.valid)
    node T_1361 = and(T_1360, io.slave[1].w.bits.last)
    when T_1361 :
      T_1357 <= UInt<1>("h00")
      skip
    node T_1363 = and(io.master.w.valid, T_1357)
    io.slave[1].w.valid <= T_1363
    io.slave[1].w.bits <- io.master.w.bits
    node T_1364 = and(io.slave[1].w.ready, T_1357)
    node T_1365 = or(T_1345, T_1364)
    node T_1366 = bits(ar_route, 2, 2)
    node T_1367 = and(io.master.ar.valid, T_1366)
    io.slave[2].ar.valid <= T_1367
    io.slave[2].ar.bits <- io.master.ar.bits
    node T_1368 = bits(ar_route, 2, 2)
    node T_1369 = and(io.slave[2].ar.ready, T_1368)
    node ar_ready = or(T_1350, T_1369)
    node T_1371 = bits(aw_route, 2, 2)
    node T_1372 = and(io.master.aw.valid, T_1371)
    io.slave[2].aw.valid <= T_1372
    io.slave[2].aw.bits <- io.master.aw.bits
    node T_1373 = bits(aw_route, 2, 2)
    node T_1374 = and(io.slave[2].aw.ready, T_1373)
    node aw_ready = or(T_1355, T_1374)
    reg T_1377 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1378 = and(io.slave[2].aw.ready, io.slave[2].aw.valid)
    when T_1378 :
      T_1377 <= UInt<1>("h01")
      skip
    node T_1380 = and(io.slave[2].w.ready, io.slave[2].w.valid)
    node T_1381 = and(T_1380, io.slave[2].w.bits.last)
    when T_1381 :
      T_1377 <= UInt<1>("h00")
      skip
    node T_1383 = and(io.master.w.valid, T_1377)
    io.slave[2].w.valid <= T_1383
    io.slave[2].w.bits <- io.master.w.bits
    node T_1384 = and(io.slave[2].w.ready, T_1377)
    node w_ready = or(T_1365, T_1384)
    node T_1387 = neq(ar_route, UInt<1>("h00"))
    node r_invalid = eq(T_1387, UInt<1>("h00"))
    node T_1391 = neq(aw_route, UInt<1>("h00"))
    node w_invalid = eq(T_1391, UInt<1>("h00"))
    inst err_slave of NastiErrorSlave_40
    err_slave.io is invalid
    err_slave.clk <= clk
    err_slave.reset <= reset
    node T_1395 = and(r_invalid, io.master.ar.valid)
    err_slave.io.ar.valid <= T_1395
    err_slave.io.ar.bits <- io.master.ar.bits
    node T_1396 = and(w_invalid, io.master.aw.valid)
    err_slave.io.aw.valid <= T_1396
    err_slave.io.aw.bits <- io.master.aw.bits
    err_slave.io.w.valid <= io.master.w.valid
    err_slave.io.w.bits <- io.master.w.bits
    node T_1397 = and(r_invalid, err_slave.io.ar.ready)
    node T_1398 = or(ar_ready, T_1397)
    io.master.ar.ready <= T_1398
    node T_1399 = and(w_invalid, err_slave.io.aw.ready)
    node T_1400 = or(aw_ready, T_1399)
    io.master.aw.ready <= T_1400
    node T_1401 = or(w_ready, err_slave.io.w.ready)
    io.master.w.ready <= T_1401
    inst b_arb of RRArbiter_62
    b_arb.io is invalid
    b_arb.clk <= clk
    b_arb.reset <= reset
    inst r_arb of JunctionsPeekingArbiter_63
    r_arb.io is invalid
    r_arb.clk <= clk
    r_arb.reset <= reset
    b_arb.io.in[0] <- io.slave[0].b
    r_arb.io.in[0] <- io.slave[0].r
    b_arb.io.in[1] <- io.slave[1].b
    r_arb.io.in[1] <- io.slave[1].r
    b_arb.io.in[2] <- io.slave[2].b
    r_arb.io.in[2] <- io.slave[2].r
    b_arb.io.in[3] <- err_slave.io.b
    r_arb.io.in[3] <- err_slave.io.r
    io.master.b <- b_arb.io.out
    io.master.r <- r_arb.io.out
    
  module NastiCrossbar_57 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]}
    
    io is invalid
    inst T_2233 of NastiRouter_58
    T_2233.io is invalid
    T_2233.clk <= clk
    T_2233.reset <= reset
    T_2233.io.master <- io.masters[0]
    io.slaves <= T_2233.io.slave
    
  module NastiRecursiveInterconnect_56 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]}
    
    io is invalid
    inst xbar of NastiCrossbar_57
    xbar.io is invalid
    xbar.clk <= clk
    xbar.reset <= reset
    xbar.io.masters <= io.masters
    io.slaves[0] <- xbar.io.slaves[0]
    io.slaves[1] <- xbar.io.slaves[1]
    io.slaves[2] <- xbar.io.slaves[2]
    
  module NastiRecursiveInterconnect : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[5]}
    
    io is invalid
    inst xbar of NastiCrossbar
    xbar.io is invalid
    xbar.clk <= clk
    xbar.reset <= reset
    xbar.io.masters <= io.masters
    io.slaves[0] <- xbar.io.slaves[0]
    inst T_2869 of NastiRecursiveInterconnect_56
    T_2869.io is invalid
    T_2869.clk <= clk
    T_2869.reset <= reset
    T_2869.io.masters[0] <- xbar.io.slaves[1]
    io.slaves[1] <- T_2869.io.slaves[0]
    io.slaves[2] <- T_2869.io.slaves[1]
    io.slaves[3] <- T_2869.io.slaves[2]
    inst T_2870 of NastiErrorSlave_40
    T_2870.io is invalid
    T_2870.clk <= clk
    T_2870.reset <= reset
    T_2870.io <- xbar.io.slaves[2]
    io.slaves[4] <- xbar.io.slaves[3]
    
  module LockingRRArbiter_67 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<1>}
    
    io is invalid
    reg T_656 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_658 : UInt, clk with : (reset => (reset, UInt<1>("h01")))
    wire T_660 : UInt<1>
    T_660 is invalid
    io.out.valid <= io.in[T_660].valid
    io.out.bits <- io.in[T_660].bits
    io.chosen <= T_660
    io.in[T_660].ready <= UInt<1>("h00")
    reg last_grant : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_842 = gt(UInt<1>("h00"), last_grant)
    node T_843 = and(io.in[0].valid, T_842)
    node T_845 = gt(UInt<1>("h01"), last_grant)
    node T_846 = and(io.in[1].valid, T_845)
    node T_849 = or(UInt<1>("h00"), T_843)
    node T_851 = eq(T_849, UInt<1>("h00"))
    node T_853 = or(UInt<1>("h00"), T_843)
    node T_854 = or(T_853, T_846)
    node T_856 = eq(T_854, UInt<1>("h00"))
    node T_858 = or(UInt<1>("h00"), T_843)
    node T_859 = or(T_858, T_846)
    node T_860 = or(T_859, io.in[0].valid)
    node T_862 = eq(T_860, UInt<1>("h00"))
    node T_864 = gt(UInt<1>("h00"), last_grant)
    node T_865 = and(UInt<1>("h01"), T_864)
    node T_866 = or(T_865, T_856)
    node T_868 = gt(UInt<1>("h01"), last_grant)
    node T_869 = and(T_851, T_868)
    node T_870 = or(T_869, T_862)
    node T_872 = eq(T_658, UInt<1>("h00"))
    node T_873 = mux(T_656, T_872, T_866)
    node T_874 = and(T_873, io.out.ready)
    io.in[0].ready <= T_874
    node T_876 = eq(T_658, UInt<1>("h01"))
    node T_877 = mux(T_656, T_876, T_870)
    node T_878 = and(T_877, io.out.ready)
    io.in[1].ready <= T_878
    reg T_880 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_882 = add(T_880, UInt<1>("h01"))
    node T_883 = tail(T_882, 1)
    node T_884 = and(io.out.ready, io.out.valid)
    when T_884 :
      node T_886 = and(UInt<1>("h01"), io.out.bits.is_builtin_type)
      wire T_889 : UInt<3>[1]
      T_889[0] <= UInt<3>("h03")
      node T_892 = eq(T_889[0], io.out.bits.a_type)
      node T_894 = or(UInt<1>("h00"), T_892)
      node T_895 = and(T_886, T_894)
      when T_895 :
        T_880 <= T_883
        node T_897 = eq(T_656, UInt<1>("h00"))
        when T_897 :
          T_656 <= UInt<1>("h01")
          node T_899 = and(io.in[0].ready, io.in[0].valid)
          node T_900 = and(io.in[1].ready, io.in[1].valid)
          wire T_902 : UInt<1>[2]
          T_902[0] <= T_899
          T_902[1] <= T_900
          node T_908 = mux(T_902[0], UInt<1>("h00"), UInt<1>("h01"))
          T_658 <= T_908
          skip
        skip
      node T_910 = eq(T_883, UInt<1>("h00"))
      when T_910 :
        T_656 <= UInt<1>("h00")
        skip
      skip
    node T_914 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_916 = gt(UInt<1>("h01"), last_grant)
    node T_917 = and(io.in[1].valid, T_916)
    node choose = mux(T_917, UInt<1>("h01"), T_914)
    node T_920 = mux(T_656, T_658, choose)
    T_660 <= T_920
    node T_921 = and(io.out.ready, io.out.valid)
    when T_921 :
      last_grant <= T_660
      skip
    
  module ReorderQueue : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<1>, tag : UInt<4>}}, deq : {flip valid : UInt<1>, flip tag : UInt<4>, data : UInt<1>, matches : UInt<1>}}
    
    io is invalid
    reg roq_data : UInt<1>[9], clk
    reg roq_tags : UInt<4>[9], clk
    wire T_96 : UInt<1>[9]
    T_96[0] <= UInt<1>("h01")
    T_96[1] <= UInt<1>("h01")
    T_96[2] <= UInt<1>("h01")
    T_96[3] <= UInt<1>("h01")
    T_96[4] <= UInt<1>("h01")
    T_96[5] <= UInt<1>("h01")
    T_96[6] <= UInt<1>("h01")
    T_96[7] <= UInt<1>("h01")
    T_96[8] <= UInt<1>("h01")
    reg roq_free : UInt<1>[9], clk with : (reset => (reset, T_96))
    node T_129 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08"))
    node T_130 = mux(roq_free[6], UInt<3>("h06"), T_129)
    node T_131 = mux(roq_free[5], UInt<3>("h05"), T_130)
    node T_132 = mux(roq_free[4], UInt<3>("h04"), T_131)
    node T_133 = mux(roq_free[3], UInt<2>("h03"), T_132)
    node T_134 = mux(roq_free[2], UInt<2>("h02"), T_133)
    node T_135 = mux(roq_free[1], UInt<1>("h01"), T_134)
    node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_135)
    node T_137 = eq(roq_tags[0], io.deq.tag)
    node T_139 = eq(roq_free[0], UInt<1>("h00"))
    node T_140 = and(T_137, T_139)
    node T_141 = eq(roq_tags[1], io.deq.tag)
    node T_143 = eq(roq_free[1], UInt<1>("h00"))
    node T_144 = and(T_141, T_143)
    node T_145 = eq(roq_tags[2], io.deq.tag)
    node T_147 = eq(roq_free[2], UInt<1>("h00"))
    node T_148 = and(T_145, T_147)
    node T_149 = eq(roq_tags[3], io.deq.tag)
    node T_151 = eq(roq_free[3], UInt<1>("h00"))
    node T_152 = and(T_149, T_151)
    node T_153 = eq(roq_tags[4], io.deq.tag)
    node T_155 = eq(roq_free[4], UInt<1>("h00"))
    node T_156 = and(T_153, T_155)
    node T_157 = eq(roq_tags[5], io.deq.tag)
    node T_159 = eq(roq_free[5], UInt<1>("h00"))
    node T_160 = and(T_157, T_159)
    node T_161 = eq(roq_tags[6], io.deq.tag)
    node T_163 = eq(roq_free[6], UInt<1>("h00"))
    node T_164 = and(T_161, T_163)
    node T_165 = eq(roq_tags[7], io.deq.tag)
    node T_167 = eq(roq_free[7], UInt<1>("h00"))
    node T_168 = and(T_165, T_167)
    node T_169 = eq(roq_tags[8], io.deq.tag)
    node T_171 = eq(roq_free[8], UInt<1>("h00"))
    node T_172 = and(T_169, T_171)
    node T_182 = mux(T_168, UInt<3>("h07"), UInt<4>("h08"))
    node T_183 = mux(T_164, UInt<3>("h06"), T_182)
    node T_184 = mux(T_160, UInt<3>("h05"), T_183)
    node T_185 = mux(T_156, UInt<3>("h04"), T_184)
    node T_186 = mux(T_152, UInt<2>("h03"), T_185)
    node T_187 = mux(T_148, UInt<2>("h02"), T_186)
    node T_188 = mux(T_144, UInt<1>("h01"), T_187)
    node roq_deq_addr = mux(T_140, UInt<1>("h00"), T_188)
    node T_190 = or(roq_free[0], roq_free[1])
    node T_191 = or(T_190, roq_free[2])
    node T_192 = or(T_191, roq_free[3])
    node T_193 = or(T_192, roq_free[4])
    node T_194 = or(T_193, roq_free[5])
    node T_195 = or(T_194, roq_free[6])
    node T_196 = or(T_195, roq_free[7])
    node T_197 = or(T_196, roq_free[8])
    io.enq.ready <= T_197
    io.deq.data <= roq_data[roq_deq_addr]
    node T_199 = or(T_140, T_144)
    node T_200 = or(T_199, T_148)
    node T_201 = or(T_200, T_152)
    node T_202 = or(T_201, T_156)
    node T_203 = or(T_202, T_160)
    node T_204 = or(T_203, T_164)
    node T_205 = or(T_204, T_168)
    node T_206 = or(T_205, T_172)
    io.deq.matches <= T_206
    node T_207 = and(io.enq.valid, io.enq.ready)
    when T_207 :
      roq_data[roq_enq_addr] <= io.enq.bits.data
      roq_tags[roq_enq_addr] <= io.enq.bits.tag
      roq_free[roq_enq_addr] <= UInt<1>("h00")
      skip
    when io.deq.valid :
      roq_free[roq_deq_addr] <= UInt<1>("h01")
      skip
    
  module ClientTileLinkIOUnwrapper : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}}
    
    io is invalid
    inst acqArb of LockingRRArbiter_67
    acqArb.io is invalid
    acqArb.clk <= clk
    acqArb.reset <= reset
    inst acqRoq of ReorderQueue
    acqRoq.io is invalid
    acqRoq.clk <= clk
    acqRoq.reset <= reset
    inst relRoq of ReorderQueue
    relRoq.io is invalid
    relRoq.clk <= clk
    relRoq.reset <= reset
    node T_1215 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type)
    wire T_1218 : UInt<3>[1]
    T_1218[0] <= UInt<3>("h03")
    node T_1221 = eq(T_1218[0], io.in.acquire.bits.a_type)
    node T_1223 = or(UInt<1>("h00"), T_1221)
    node T_1224 = and(T_1215, T_1223)
    node T_1226 = eq(T_1224, UInt<1>("h00"))
    node T_1228 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00"))
    node acq_roq_enq = or(T_1226, T_1228)
    wire T_1232 : UInt<2>[3]
    T_1232[0] <= UInt<1>("h00")
    T_1232[1] <= UInt<1>("h01")
    T_1232[2] <= UInt<2>("h02")
    node T_1237 = eq(T_1232[0], io.in.release.bits.r_type)
    node T_1238 = eq(T_1232[1], io.in.release.bits.r_type)
    node T_1239 = eq(T_1232[2], io.in.release.bits.r_type)
    node T_1241 = or(UInt<1>("h00"), T_1237)
    node T_1242 = or(T_1241, T_1238)
    node T_1243 = or(T_1242, T_1239)
    node T_1244 = and(UInt<1>("h01"), T_1243)
    node T_1246 = eq(T_1244, UInt<1>("h00"))
    node T_1248 = eq(io.in.release.bits.addr_beat, UInt<1>("h00"))
    node rel_roq_enq = or(T_1246, T_1248)
    node T_1251 = eq(acq_roq_enq, UInt<1>("h00"))
    node acq_roq_ready = or(T_1251, acqRoq.io.enq.ready)
    node T_1254 = eq(rel_roq_enq, UInt<1>("h00"))
    node rel_roq_ready = or(T_1254, relRoq.io.enq.ready)
    node T_1256 = and(io.in.acquire.valid, acqArb.io.in[0].ready)
    node T_1257 = and(T_1256, acq_roq_enq)
    acqRoq.io.enq.valid <= T_1257
    acqRoq.io.enq.bits.data <= io.in.acquire.bits.is_builtin_type
    acqRoq.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id
    node T_1258 = and(io.in.acquire.valid, acq_roq_ready)
    acqArb.io.in[0].valid <= T_1258
    node T_1261 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h01"))
    node T_1263 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1264 = cat(UInt<3>("h07"), T_1263)
    node T_1265 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.union, T_1264)
    wire T_1294 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    T_1294 is invalid
    T_1294.is_builtin_type <= UInt<1>("h01")
    T_1294.a_type <= T_1261
    T_1294.client_xact_id <= io.in.acquire.bits.client_xact_id
    T_1294.addr_block <= io.in.acquire.bits.addr_block
    T_1294.addr_beat <= io.in.acquire.bits.addr_beat
    T_1294.data <= io.in.acquire.bits.data
    T_1294.union <= T_1265
    acqArb.io.in[0].bits <- T_1294
    node T_1322 = and(acq_roq_ready, acqArb.io.in[0].ready)
    io.in.acquire.ready <= T_1322
    node T_1323 = and(io.in.release.valid, acqArb.io.in[1].ready)
    node T_1324 = and(T_1323, rel_roq_enq)
    relRoq.io.enq.valid <= T_1324
    relRoq.io.enq.bits.data <= io.in.release.bits.voluntary
    relRoq.io.enq.bits.tag <= io.in.release.bits.client_xact_id
    node T_1325 = and(io.in.release.valid, rel_roq_ready)
    acqArb.io.in[1].valid <= T_1325
    node T_1347 = asUInt(asSInt(UInt<16>("h0ffff")))
    node T_1355 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1356 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1357 = cat(T_1355, T_1356)
    node T_1359 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1360 = cat(UInt<3>("h07"), T_1359)
    node T_1362 = cat(T_1347, UInt<1>("h01"))
    node T_1364 = cat(T_1347, UInt<1>("h01"))
    node T_1366 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1367 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1368 = cat(T_1366, T_1367)
    node T_1370 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1372 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_1373 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_1374 = mux(T_1373, T_1372, UInt<1>("h00"))
    node T_1375 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_1376 = mux(T_1375, T_1370, T_1374)
    node T_1377 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_1378 = mux(T_1377, T_1368, T_1376)
    node T_1379 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_1380 = mux(T_1379, T_1364, T_1378)
    node T_1381 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_1382 = mux(T_1381, T_1362, T_1380)
    node T_1383 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_1384 = mux(T_1383, T_1360, T_1382)
    node T_1385 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_1386 = mux(T_1385, T_1357, T_1384)
    wire T_1415 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    T_1415 is invalid
    T_1415.is_builtin_type <= UInt<1>("h01")
    T_1415.a_type <= UInt<3>("h03")
    T_1415.client_xact_id <= io.in.release.bits.client_xact_id
    T_1415.addr_block <= io.in.release.bits.addr_block
    T_1415.addr_beat <= io.in.release.bits.addr_beat
    T_1415.data <= io.in.release.bits.data
    T_1415.union <= T_1386
    acqArb.io.in[1].bits <- T_1415
    node T_1443 = and(rel_roq_ready, acqArb.io.in[1].ready)
    io.in.release.ready <= T_1443
    io.out.acquire <- acqArb.io.out
    node T_1444 = and(io.out.grant.ready, io.out.grant.valid)
    wire T_1448 : UInt<3>[1]
    T_1448[0] <= UInt<3>("h05")
    node T_1451 = eq(T_1448[0], io.out.grant.bits.g_type)
    node T_1453 = or(UInt<1>("h00"), T_1451)
    wire T_1455 : UInt<1>[1]
    T_1455[0] <= UInt<1>("h00")
    node T_1458 = eq(T_1455[0], io.out.grant.bits.g_type)
    node T_1460 = or(UInt<1>("h00"), T_1458)
    node T_1461 = mux(io.out.grant.bits.is_builtin_type, T_1453, T_1460)
    node T_1462 = and(UInt<1>("h01"), T_1461)
    node T_1464 = eq(T_1462, UInt<1>("h00"))
    node T_1466 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03"))
    node T_1467 = or(T_1464, T_1466)
    node T_1468 = and(T_1444, T_1467)
    acqRoq.io.deq.valid <= T_1468
    acqRoq.io.deq.tag <= io.out.grant.bits.client_xact_id
    node T_1469 = and(io.out.grant.ready, io.out.grant.valid)
    wire T_1473 : UInt<3>[1]
    T_1473[0] <= UInt<3>("h05")
    node T_1476 = eq(T_1473[0], io.out.grant.bits.g_type)
    node T_1478 = or(UInt<1>("h00"), T_1476)
    wire T_1480 : UInt<1>[1]
    T_1480[0] <= UInt<1>("h00")
    node T_1483 = eq(T_1480[0], io.out.grant.bits.g_type)
    node T_1485 = or(UInt<1>("h00"), T_1483)
    node T_1486 = mux(io.out.grant.bits.is_builtin_type, T_1478, T_1485)
    node T_1487 = and(UInt<1>("h01"), T_1486)
    node T_1489 = eq(T_1487, UInt<1>("h00"))
    node T_1491 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03"))
    node T_1492 = or(T_1489, T_1491)
    node T_1493 = and(T_1469, T_1492)
    relRoq.io.deq.valid <= T_1493
    relRoq.io.deq.tag <= io.out.grant.bits.client_xact_id
    node T_1494 = mux(acqRoq.io.deq.data, io.out.grant.bits.g_type, UInt<1>("h00"))
    wire acq_grant : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}
    acq_grant is invalid
    acq_grant.is_builtin_type <= acqRoq.io.deq.data
    acq_grant.g_type <= T_1494
    acq_grant.client_xact_id <= io.out.grant.bits.client_xact_id
    acq_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id
    acq_grant.addr_beat <= io.out.grant.bits.addr_beat
    acq_grant.data <= io.out.grant.bits.data
    node T_1551 = mux(relRoq.io.deq.data, UInt<3>("h00"), io.out.grant.bits.g_type)
    wire rel_grant : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}
    rel_grant is invalid
    rel_grant.is_builtin_type <= UInt<1>("h01")
    rel_grant.g_type <= T_1551
    rel_grant.client_xact_id <= io.out.grant.bits.client_xact_id
    rel_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id
    rel_grant.addr_beat <= io.out.grant.bits.addr_beat
    rel_grant.data <= io.out.grant.bits.data
    io.in.grant.valid <= io.out.grant.valid
    node T_1606 = mux(acqRoq.io.deq.matches, acq_grant, rel_grant)
    io.in.grant.bits <- T_1606
    io.out.grant.ready <= io.in.grant.ready
    io.in.probe.valid <= UInt<1>("h00")
    
  module TileLinkIONarrower : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}}
    
    io is invalid
    node T_815 = eq(io.in.acquire.bits.a_type, UInt<3>("h03"))
    node T_817 = eq(io.in.acquire.bits.a_type, UInt<3>("h01"))
    node T_819 = eq(io.in.acquire.bits.a_type, UInt<3>("h02"))
    node T_821 = eq(io.in.acquire.bits.a_type, UInt<3>("h00"))
    reg T_823 : UInt<128>, clk
    reg T_825 : UInt<16>, clk
    reg T_826 : UInt<4>, clk
    reg T_827 : UInt<26>, clk
    reg T_828 : UInt<2>, clk
    reg T_830 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_831 = bits(io.in.acquire.bits.union, 12, 9)
    node T_832 = cat(io.in.acquire.bits.addr_beat, T_831)
    node T_833 = cat(io.in.acquire.bits.addr_block, T_832)
    node T_834 = bits(T_833, 3, 3)
    node T_835 = bits(io.in.acquire.bits.union, 12, 9)
    node T_836 = cat(io.in.acquire.bits.addr_beat, T_835)
    node T_837 = cat(io.in.acquire.bits.addr_block, T_836)
    node T_838 = bits(T_837, 5, 3)
    node T_839 = bits(io.in.acquire.bits.union, 12, 9)
    node T_840 = cat(io.in.acquire.bits.addr_beat, T_839)
    node T_841 = cat(io.in.acquire.bits.addr_block, T_840)
    node T_842 = bits(T_841, 2, 0)
    node T_843 = bits(io.in.acquire.bits.union, 12, 9)
    node T_844 = bits(T_843, 3, 3)
    node T_846 = dshl(UInt<1>("h01"), T_844)
    node T_848 = eq(io.in.acquire.bits.a_type, UInt<3>("h04"))
    node T_849 = and(io.in.acquire.bits.is_builtin_type, T_848)
    node T_850 = bits(T_846, 0, 0)
    node T_851 = bits(T_846, 1, 1)
    wire T_853 : UInt<1>[2]
    T_853[0] <= T_850
    T_853[1] <= T_851
    node T_858 = sub(UInt<8>("h00"), T_853[0])
    node T_859 = tail(T_858, 1)
    node T_861 = sub(UInt<8>("h00"), T_853[1])
    node T_862 = tail(T_861, 1)
    wire T_864 : UInt<8>[2]
    T_864[0] <= T_859
    T_864[1] <= T_862
    node T_868 = cat(T_864[1], T_864[0])
    node T_870 = eq(io.in.acquire.bits.a_type, UInt<3>("h03"))
    node T_871 = and(io.in.acquire.bits.is_builtin_type, T_870)
    node T_873 = eq(io.in.acquire.bits.a_type, UInt<3>("h02"))
    node T_874 = and(io.in.acquire.bits.is_builtin_type, T_873)
    node T_875 = or(T_871, T_874)
    node T_876 = bits(io.in.acquire.bits.union, 16, 1)
    node T_878 = mux(T_875, T_876, UInt<16>("h00"))
    node T_879 = mux(T_849, T_868, T_878)
    node T_880 = bits(T_879, 7, 0)
    node T_881 = bits(io.in.acquire.bits.union, 12, 9)
    node T_882 = bits(T_881, 3, 3)
    node T_884 = dshl(UInt<1>("h01"), T_882)
    node T_886 = eq(io.in.acquire.bits.a_type, UInt<3>("h04"))
    node T_887 = and(io.in.acquire.bits.is_builtin_type, T_886)
    node T_888 = bits(T_884, 0, 0)
    node T_889 = bits(T_884, 1, 1)
    wire T_891 : UInt<1>[2]
    T_891[0] <= T_888
    T_891[1] <= T_889
    node T_896 = sub(UInt<8>("h00"), T_891[0])
    node T_897 = tail(T_896, 1)
    node T_899 = sub(UInt<8>("h00"), T_891[1])
    node T_900 = tail(T_899, 1)
    wire T_902 : UInt<8>[2]
    T_902[0] <= T_897
    T_902[1] <= T_900
    node T_906 = cat(T_902[1], T_902[0])
    node T_908 = eq(io.in.acquire.bits.a_type, UInt<3>("h03"))
    node T_909 = and(io.in.acquire.bits.is_builtin_type, T_908)
    node T_911 = eq(io.in.acquire.bits.a_type, UInt<3>("h02"))
    node T_912 = and(io.in.acquire.bits.is_builtin_type, T_911)
    node T_913 = or(T_909, T_912)
    node T_914 = bits(io.in.acquire.bits.union, 16, 1)
    node T_916 = mux(T_913, T_914, UInt<16>("h00"))
    node T_917 = mux(T_887, T_906, T_916)
    node T_918 = bits(T_917, 15, 8)
    wire T_920 : UInt<8>[2]
    T_920[0] <= T_880
    T_920[1] <= T_918
    node T_924 = bits(io.in.acquire.bits.data, 63, 0)
    node T_925 = bits(io.in.acquire.bits.data, 127, 64)
    wire T_927 : UInt<64>[2]
    T_927[0] <= T_924
    T_927[1] <= T_925
    node T_932 = neq(T_920[0], UInt<1>("h00"))
    node T_934 = neq(T_920[1], UInt<1>("h00"))
    node T_935 = cat(T_934, T_932)
    node T_936 = bits(T_935, 0, 0)
    node T_937 = bits(T_935, 1, 1)
    node T_939 = mux(T_936, T_927[0], UInt<1>("h00"))
    node T_941 = mux(T_937, T_927[1], UInt<1>("h00"))
    node T_943 = or(T_939, T_941)
    wire T_944 : UInt<64>
    T_944 is invalid
    T_944 <= T_943
    node T_945 = bits(T_935, 0, 0)
    node T_946 = bits(T_935, 1, 1)
    node T_948 = mux(T_945, T_920[0], UInt<1>("h00"))
    node T_950 = mux(T_946, T_920[1], UInt<1>("h00"))
    node T_952 = or(T_948, T_950)
    wire T_953 : UInt<8>
    T_953 is invalid
    T_953 <= T_952
    node T_954 = bits(T_935, 0, 0)
    node T_955 = bits(T_935, 1, 1)
    wire T_957 : UInt<1>[2]
    T_957[0] <= T_954
    T_957[1] <= T_955
    node T_963 = mux(T_957[0], UInt<1>("h00"), UInt<1>("h01"))
    node T_964 = cat(io.in.acquire.bits.addr_beat, T_963)
    node T_966 = eq(io.in.acquire.valid, UInt<1>("h00"))
    node T_968 = eq(T_819, UInt<1>("h00"))
    node T_969 = or(T_966, T_968)
    node T_970 = bits(T_935, 0, 0)
    node T_971 = bits(T_935, 1, 1)
    node T_973 = cat(UInt<1>("h00"), T_971)
    node T_974 = add(T_970, T_973)
    node T_975 = tail(T_974, 1)
    node T_977 = leq(T_975, UInt<1>("h01"))
    node T_978 = or(T_969, T_977)
    node T_980 = eq(reset, UInt<1>("h00"))
    when T_980 :
      node T_982 = eq(T_978, UInt<1>("h00"))
      when T_982 :
        node T_984 = eq(reset, UInt<1>("h00"))
        when T_984 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't perform Put wider than outer width")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_985 = bits(io.in.acquire.bits.union, 8, 6)
    node T_994 = eq(UInt<3>("h07"), T_985)
    node T_995 = mux(T_994, UInt<1>("h00"), UInt<1>("h00"))
    node T_996 = eq(UInt<3>("h03"), T_985)
    node T_997 = mux(T_996, UInt<1>("h01"), T_995)
    node T_998 = eq(UInt<3>("h02"), T_985)
    node T_999 = mux(T_998, UInt<1>("h01"), T_997)
    node T_1000 = eq(UInt<3>("h05"), T_985)
    node T_1001 = mux(T_1000, UInt<1>("h01"), T_999)
    node T_1002 = eq(UInt<3>("h01"), T_985)
    node T_1003 = mux(T_1002, UInt<1>("h01"), T_1001)
    node T_1004 = eq(UInt<3>("h04"), T_985)
    node T_1005 = mux(T_1004, UInt<1>("h01"), T_1003)
    node T_1006 = eq(UInt<3>("h00"), T_985)
    node T_1007 = mux(T_1006, UInt<1>("h01"), T_1005)
    node T_1009 = eq(io.in.acquire.valid, UInt<1>("h00"))
    node T_1011 = eq(T_821, UInt<1>("h00"))
    node T_1012 = or(T_1009, T_1011)
    node T_1013 = or(T_1012, T_1007)
    node T_1015 = eq(reset, UInt<1>("h00"))
    when T_1015 :
      node T_1017 = eq(T_1013, UInt<1>("h00"))
      when T_1017 :
        node T_1019 = eq(reset, UInt<1>("h00"))
        when T_1019 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't perform Get wider than outer width")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1020 = bits(io.in.acquire.bits.union, 0, 0)
    node T_1029 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1030 = cat(UInt<5>("h00"), T_1020)
    node T_1031 = cat(T_1029, T_1030)
    node T_1033 = cat(UInt<5>("h00"), T_1020)
    node T_1034 = cat(UInt<3>("h07"), T_1033)
    node T_1036 = cat(UInt<1>("h00"), T_1020)
    node T_1038 = cat(UInt<1>("h00"), T_1020)
    node T_1040 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1041 = cat(UInt<5>("h00"), T_1020)
    node T_1042 = cat(T_1040, T_1041)
    node T_1044 = cat(UInt<5>("h00"), T_1020)
    node T_1046 = cat(UInt<5>("h01"), T_1020)
    node T_1047 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_1048 = mux(T_1047, T_1046, UInt<1>("h00"))
    node T_1049 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_1050 = mux(T_1049, T_1044, T_1048)
    node T_1051 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_1052 = mux(T_1051, T_1042, T_1050)
    node T_1053 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_1054 = mux(T_1053, T_1038, T_1052)
    node T_1055 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_1056 = mux(T_1055, T_1036, T_1054)
    node T_1057 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_1058 = mux(T_1057, T_1034, T_1056)
    node T_1059 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_1060 = mux(T_1059, T_1031, T_1058)
    wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}
    T_1089 is invalid
    T_1089.is_builtin_type <= UInt<1>("h01")
    T_1089.a_type <= UInt<3>("h01")
    T_1089.client_xact_id <= io.in.acquire.bits.client_xact_id
    T_1089.addr_block <= io.in.acquire.bits.addr_block
    T_1089.addr_beat <= UInt<1>("h00")
    T_1089.data <= UInt<1>("h00")
    T_1089.union <= T_1060
    node T_1117 = cat(T_828, T_830)
    node T_1118 = bits(T_823, 63, 0)
    node T_1119 = bits(T_825, 7, 0)
    node T_1127 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1128 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1129 = cat(T_1127, T_1128)
    node T_1131 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1132 = cat(UInt<3>("h07"), T_1131)
    node T_1134 = cat(T_1119, UInt<1>("h01"))
    node T_1136 = cat(T_1119, UInt<1>("h01"))
    node T_1138 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1139 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1140 = cat(T_1138, T_1139)
    node T_1142 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1144 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_1145 = eq(UInt<3>("h06"), UInt<3>("h03"))
    node T_1146 = mux(T_1145, T_1144, UInt<1>("h00"))
    node T_1147 = eq(UInt<3>("h05"), UInt<3>("h03"))
    node T_1148 = mux(T_1147, T_1142, T_1146)
    node T_1149 = eq(UInt<3>("h04"), UInt<3>("h03"))
    node T_1150 = mux(T_1149, T_1140, T_1148)
    node T_1151 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_1152 = mux(T_1151, T_1136, T_1150)
    node T_1153 = eq(UInt<3>("h02"), UInt<3>("h03"))
    node T_1154 = mux(T_1153, T_1134, T_1152)
    node T_1155 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_1156 = mux(T_1155, T_1132, T_1154)
    node T_1157 = eq(UInt<3>("h00"), UInt<3>("h03"))
    node T_1158 = mux(T_1157, T_1129, T_1156)
    wire T_1187 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}
    T_1187 is invalid
    T_1187.is_builtin_type <= UInt<1>("h01")
    T_1187.a_type <= UInt<3>("h03")
    T_1187.client_xact_id <= T_826
    T_1187.addr_block <= T_827
    T_1187.addr_beat <= T_1117
    T_1187.data <= T_1118
    T_1187.union <= T_1158
    node T_1215 = bits(io.in.acquire.bits.union, 8, 6)
    node T_1216 = bits(io.in.acquire.bits.union, 0, 0)
    node T_1223 = cat(T_842, T_1215)
    node T_1224 = cat(UInt<5>("h00"), T_1216)
    node T_1225 = cat(T_1223, T_1224)
    node T_1227 = cat(UInt<5>("h00"), T_1216)
    node T_1228 = cat(T_1215, T_1227)
    node T_1230 = cat(UInt<1>("h00"), T_1216)
    node T_1232 = cat(UInt<1>("h00"), T_1216)
    node T_1234 = cat(T_842, T_1215)
    node T_1235 = cat(UInt<5>("h00"), T_1216)
    node T_1236 = cat(T_1234, T_1235)
    node T_1238 = cat(UInt<5>("h00"), T_1216)
    node T_1240 = cat(UInt<5>("h01"), T_1216)
    node T_1241 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_1242 = mux(T_1241, T_1240, UInt<1>("h00"))
    node T_1243 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_1244 = mux(T_1243, T_1238, T_1242)
    node T_1245 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_1246 = mux(T_1245, T_1236, T_1244)
    node T_1247 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_1248 = mux(T_1247, T_1232, T_1246)
    node T_1249 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_1250 = mux(T_1249, T_1230, T_1248)
    node T_1251 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_1252 = mux(T_1251, T_1228, T_1250)
    node T_1253 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_1254 = mux(T_1253, T_1225, T_1252)
    wire T_1283 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}
    T_1283 is invalid
    T_1283.is_builtin_type <= UInt<1>("h01")
    T_1283.a_type <= UInt<3>("h00")
    T_1283.client_xact_id <= io.in.acquire.bits.client_xact_id
    T_1283.addr_block <= io.in.acquire.bits.addr_block
    T_1283.addr_beat <= T_838
    T_1283.data <= UInt<1>("h00")
    T_1283.union <= T_1254
    node T_1318 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1319 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1320 = cat(T_1318, T_1319)
    node T_1322 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1323 = cat(UInt<3>("h07"), T_1322)
    node T_1325 = cat(T_953, UInt<1>("h01"))
    node T_1327 = cat(T_953, UInt<1>("h01"))
    node T_1329 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1330 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_1331 = cat(T_1329, T_1330)
    node T_1333 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_1335 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_1336 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_1337 = mux(T_1336, T_1335, UInt<1>("h00"))
    node T_1338 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_1339 = mux(T_1338, T_1333, T_1337)
    node T_1340 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_1341 = mux(T_1340, T_1331, T_1339)
    node T_1342 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_1343 = mux(T_1342, T_1327, T_1341)
    node T_1344 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_1345 = mux(T_1344, T_1325, T_1343)
    node T_1346 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_1347 = mux(T_1346, T_1323, T_1345)
    node T_1348 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_1349 = mux(T_1348, T_1320, T_1347)
    wire T_1378 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}
    T_1378 is invalid
    T_1378.is_builtin_type <= UInt<1>("h01")
    T_1378.a_type <= UInt<3>("h02")
    T_1378.client_xact_id <= io.in.acquire.bits.client_xact_id
    T_1378.addr_block <= io.in.acquire.bits.addr_block
    T_1378.addr_beat <= T_964
    T_1378.data <= T_944
    T_1378.union <= T_1349
    reg T_1407 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1409 = eq(T_815, UInt<1>("h00"))
    node T_1410 = and(io.in.acquire.valid, T_1409)
    node T_1412 = eq(T_821, UInt<1>("h00"))
    node T_1413 = and(T_1410, T_1412)
    node T_1414 = and(T_821, io.in.acquire.valid)
    inst T_1415 of ReorderQueue
    T_1415.io is invalid
    T_1415.clk <= clk
    T_1415.reset <= reset
    node T_1417 = eq(T_1407, UInt<1>("h00"))
    node T_1418 = and(T_1414, io.out.acquire.ready)
    node T_1419 = and(T_1418, T_1417)
    T_1415.io.enq.valid <= T_1419
    T_1415.io.enq.bits.data <= T_834
    T_1415.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id
    wire T_1420 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}
    T_1420 <- io.in.acquire.bits
    node T_1448 = mux(T_821, T_1283, T_1420)
    node T_1476 = mux(T_819, T_1378, T_1448)
    node T_1504 = mux(T_817, T_1089, T_1476)
    node T_1532 = mux(T_1407, T_1187, T_1504)
    io.out.acquire.bits <- T_1532
    node T_1560 = or(T_1407, T_1413)
    node T_1561 = and(T_1414, T_1415.io.enq.ready)
    node T_1562 = or(T_1560, T_1561)
    io.out.acquire.valid <= T_1562
    node T_1564 = eq(T_1407, UInt<1>("h00"))
    node T_1566 = eq(T_821, UInt<1>("h00"))
    node T_1567 = and(T_1566, io.out.acquire.ready)
    node T_1568 = or(T_815, T_1567)
    node T_1569 = and(T_1415.io.enq.ready, io.out.acquire.ready)
    node T_1570 = or(T_1568, T_1569)
    node T_1571 = and(T_1564, T_1570)
    io.in.acquire.ready <= T_1571
    node T_1572 = and(io.in.acquire.ready, io.in.acquire.valid)
    node T_1573 = and(T_1572, T_815)
    when T_1573 :
      T_823 <= io.in.acquire.bits.data
      node T_1574 = bits(io.in.acquire.bits.union, 12, 9)
      node T_1575 = bits(T_1574, 3, 3)
      node T_1577 = dshl(UInt<1>("h01"), T_1575)
      node T_1579 = eq(io.in.acquire.bits.a_type, UInt<3>("h04"))
      node T_1580 = and(io.in.acquire.bits.is_builtin_type, T_1579)
      node T_1581 = bits(T_1577, 0, 0)
      node T_1582 = bits(T_1577, 1, 1)
      wire T_1584 : UInt<1>[2]
      T_1584[0] <= T_1581
      T_1584[1] <= T_1582
      node T_1589 = sub(UInt<8>("h00"), T_1584[0])
      node T_1590 = tail(T_1589, 1)
      node T_1592 = sub(UInt<8>("h00"), T_1584[1])
      node T_1593 = tail(T_1592, 1)
      wire T_1595 : UInt<8>[2]
      T_1595[0] <= T_1590
      T_1595[1] <= T_1593
      node T_1599 = cat(T_1595[1], T_1595[0])
      node T_1601 = eq(io.in.acquire.bits.a_type, UInt<3>("h03"))
      node T_1602 = and(io.in.acquire.bits.is_builtin_type, T_1601)
      node T_1604 = eq(io.in.acquire.bits.a_type, UInt<3>("h02"))
      node T_1605 = and(io.in.acquire.bits.is_builtin_type, T_1604)
      node T_1606 = or(T_1602, T_1605)
      node T_1607 = bits(io.in.acquire.bits.union, 16, 1)
      node T_1609 = mux(T_1606, T_1607, UInt<16>("h00"))
      node T_1610 = mux(T_1580, T_1599, T_1609)
      T_825 <= T_1610
      T_826 <= io.in.acquire.bits.client_xact_id
      T_827 <= io.in.acquire.bits.addr_block
      T_828 <= io.in.acquire.bits.addr_beat
      T_1407 <= UInt<1>("h01")
      skip
    node T_1612 = and(T_1407, io.out.acquire.ready)
    when T_1612 :
      node T_1613 = shr(T_823, 64)
      T_823 <= T_1613
      node T_1614 = shr(T_825, 8)
      T_825 <= T_1614
      node T_1616 = eq(T_830, UInt<1>("h01"))
      node T_1618 = and(UInt<1>("h00"), T_1616)
      node T_1621 = add(T_830, UInt<1>("h01"))
      node T_1622 = tail(T_1621, 1)
      node T_1623 = mux(T_1618, UInt<1>("h00"), T_1622)
      T_830 <= T_1623
      when T_1616 :
        T_1407 <= UInt<1>("h00")
        skip
      skip
    wire T_1628 : UInt<3>[1]
    T_1628[0] <= UInt<3>("h05")
    node T_1631 = eq(T_1628[0], io.out.grant.bits.g_type)
    node T_1633 = or(UInt<1>("h00"), T_1631)
    wire T_1635 : UInt<1>[1]
    T_1635[0] <= UInt<1>("h00")
    node T_1638 = eq(T_1635[0], io.out.grant.bits.g_type)
    node T_1640 = or(UInt<1>("h00"), T_1638)
    node T_1641 = mux(io.out.grant.bits.is_builtin_type, T_1633, T_1640)
    node T_1642 = and(UInt<1>("h01"), T_1641)
    reg T_1651 : UInt<64>[2], clk
    reg T_1655 : UInt<4>, clk
    reg T_1656 : UInt<1>, clk
    reg T_1658 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    reg T_1660 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_1662 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_1665 = cat(T_1651[1], T_1651[0])
    wire T_1693 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}
    T_1693 is invalid
    T_1693.is_builtin_type <= UInt<1>("h01")
    T_1693.g_type <= UInt<3>("h05")
    T_1693.client_xact_id <= T_1655
    T_1693.manager_xact_id <= T_1656
    T_1693.addr_beat <= T_1658
    T_1693.data <= T_1665
    node T_1721 = eq(io.out.grant.bits.g_type, UInt<3>("h04"))
    node T_1723 = cat(T_1415.io.deq.data, UInt<6>("h00"))
    node T_1724 = and(io.out.grant.ready, io.out.grant.valid)
    node T_1725 = and(T_1724, T_1721)
    T_1415.io.deq.valid <= T_1725
    T_1415.io.deq.tag <= io.out.grant.bits.client_xact_id
    node T_1729 = dshr(io.out.grant.bits.addr_beat, UInt<1>("h01"))
    node T_1730 = dshl(io.out.grant.bits.data, T_1723)
    wire T_1758 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}
    T_1758 is invalid
    T_1758.is_builtin_type <= UInt<1>("h01")
    T_1758.g_type <= UInt<3>("h04")
    T_1758.client_xact_id <= io.out.grant.bits.client_xact_id
    T_1758.manager_xact_id <= io.out.grant.bits.manager_xact_id
    T_1758.addr_beat <= T_1729
    T_1758.data <= T_1730
    node T_1786 = eq(T_1642, UInt<1>("h00"))
    node T_1787 = and(io.out.grant.valid, T_1786)
    node T_1788 = or(T_1662, T_1787)
    io.in.grant.valid <= T_1788
    node T_1790 = eq(T_1662, UInt<1>("h00"))
    node T_1791 = or(T_1642, io.in.grant.ready)
    node T_1792 = and(T_1790, T_1791)
    io.out.grant.ready <= T_1792
    wire T_1793 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}
    T_1793 <- io.out.grant.bits
    node T_1820 = mux(T_1721, T_1758, T_1793)
    node T_1847 = mux(T_1662, T_1693, T_1820)
    io.in.grant.bits <- T_1847
    node T_1874 = and(io.out.grant.valid, T_1642)
    node T_1876 = eq(T_1662, UInt<1>("h00"))
    node T_1877 = and(T_1874, T_1876)
    when T_1877 :
      T_1651[T_1660] <= io.out.grant.bits.data
      node T_1880 = eq(T_1660, UInt<1>("h01"))
      node T_1882 = and(UInt<1>("h00"), T_1880)
      node T_1885 = add(T_1660, UInt<1>("h01"))
      node T_1886 = tail(T_1885, 1)
      node T_1887 = mux(T_1882, UInt<1>("h00"), T_1886)
      T_1660 <= T_1887
      when T_1880 :
        T_1655 <= io.out.grant.bits.client_xact_id
        T_1656 <= io.out.grant.bits.manager_xact_id
        T_1662 <= UInt<1>("h01")
        skip
      skip
    node T_1889 = and(io.in.grant.ready, T_1662)
    when T_1889 :
      node T_1891 = eq(T_1658, UInt<2>("h03"))
      node T_1893 = and(UInt<1>("h00"), T_1891)
      node T_1896 = add(T_1658, UInt<1>("h01"))
      node T_1897 = tail(T_1896, 1)
      node T_1898 = mux(T_1893, UInt<1>("h00"), T_1897)
      T_1658 <= T_1898
      T_1662 <= UInt<1>("h00")
      skip
    
  module ReorderQueue_70 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, tag : UInt<5>}}, deq : {flip valid : UInt<1>, flip tag : UInt<5>, data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, matches : UInt<1>}}
    
    io is invalid
    reg roq_data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}[9], clk
    reg roq_tags : UInt<5>[9], clk
    wire T_832 : UInt<1>[9]
    T_832[0] <= UInt<1>("h01")
    T_832[1] <= UInt<1>("h01")
    T_832[2] <= UInt<1>("h01")
    T_832[3] <= UInt<1>("h01")
    T_832[4] <= UInt<1>("h01")
    T_832[5] <= UInt<1>("h01")
    T_832[6] <= UInt<1>("h01")
    T_832[7] <= UInt<1>("h01")
    T_832[8] <= UInt<1>("h01")
    reg roq_free : UInt<1>[9], clk with : (reset => (reset, T_832))
    node T_865 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08"))
    node T_866 = mux(roq_free[6], UInt<3>("h06"), T_865)
    node T_867 = mux(roq_free[5], UInt<3>("h05"), T_866)
    node T_868 = mux(roq_free[4], UInt<3>("h04"), T_867)
    node T_869 = mux(roq_free[3], UInt<2>("h03"), T_868)
    node T_870 = mux(roq_free[2], UInt<2>("h02"), T_869)
    node T_871 = mux(roq_free[1], UInt<1>("h01"), T_870)
    node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_871)
    node T_873 = eq(roq_tags[0], io.deq.tag)
    node T_875 = eq(roq_free[0], UInt<1>("h00"))
    node T_876 = and(T_873, T_875)
    node T_877 = eq(roq_tags[1], io.deq.tag)
    node T_879 = eq(roq_free[1], UInt<1>("h00"))
    node T_880 = and(T_877, T_879)
    node T_881 = eq(roq_tags[2], io.deq.tag)
    node T_883 = eq(roq_free[2], UInt<1>("h00"))
    node T_884 = and(T_881, T_883)
    node T_885 = eq(roq_tags[3], io.deq.tag)
    node T_887 = eq(roq_free[3], UInt<1>("h00"))
    node T_888 = and(T_885, T_887)
    node T_889 = eq(roq_tags[4], io.deq.tag)
    node T_891 = eq(roq_free[4], UInt<1>("h00"))
    node T_892 = and(T_889, T_891)
    node T_893 = eq(roq_tags[5], io.deq.tag)
    node T_895 = eq(roq_free[5], UInt<1>("h00"))
    node T_896 = and(T_893, T_895)
    node T_897 = eq(roq_tags[6], io.deq.tag)
    node T_899 = eq(roq_free[6], UInt<1>("h00"))
    node T_900 = and(T_897, T_899)
    node T_901 = eq(roq_tags[7], io.deq.tag)
    node T_903 = eq(roq_free[7], UInt<1>("h00"))
    node T_904 = and(T_901, T_903)
    node T_905 = eq(roq_tags[8], io.deq.tag)
    node T_907 = eq(roq_free[8], UInt<1>("h00"))
    node T_908 = and(T_905, T_907)
    node T_918 = mux(T_904, UInt<3>("h07"), UInt<4>("h08"))
    node T_919 = mux(T_900, UInt<3>("h06"), T_918)
    node T_920 = mux(T_896, UInt<3>("h05"), T_919)
    node T_921 = mux(T_892, UInt<3>("h04"), T_920)
    node T_922 = mux(T_888, UInt<2>("h03"), T_921)
    node T_923 = mux(T_884, UInt<2>("h02"), T_922)
    node T_924 = mux(T_880, UInt<1>("h01"), T_923)
    node roq_deq_addr = mux(T_876, UInt<1>("h00"), T_924)
    node T_926 = or(roq_free[0], roq_free[1])
    node T_927 = or(T_926, roq_free[2])
    node T_928 = or(T_927, roq_free[3])
    node T_929 = or(T_928, roq_free[4])
    node T_930 = or(T_929, roq_free[5])
    node T_931 = or(T_930, roq_free[6])
    node T_932 = or(T_931, roq_free[7])
    node T_933 = or(T_932, roq_free[8])
    io.enq.ready <= T_933
    io.deq.data <- roq_data[roq_deq_addr]
    node T_958 = or(T_876, T_880)
    node T_959 = or(T_958, T_884)
    node T_960 = or(T_959, T_888)
    node T_961 = or(T_960, T_892)
    node T_962 = or(T_961, T_896)
    node T_963 = or(T_962, T_900)
    node T_964 = or(T_963, T_904)
    node T_965 = or(T_964, T_908)
    io.deq.matches <= T_965
    node T_966 = and(io.enq.valid, io.enq.ready)
    when T_966 :
      roq_data[roq_enq_addr] <- io.enq.bits.data
      roq_tags[roq_enq_addr] <= io.enq.bits.tag
      roq_free[roq_enq_addr] <= UInt<1>("h00")
      skip
    when io.deq.valid :
      roq_free[roq_deq_addr] <= UInt<1>("h01")
      skip
    
  module Arbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_658 : UInt<1>
    T_658 is invalid
    io.out.valid <= io.in[T_658].valid
    io.out.bits <- io.in[T_658].bits
    io.chosen <= T_658
    io.in[T_658].ready <= UInt<1>("h00")
    node T_839 = or(UInt<1>("h00"), io.in[0].valid)
    node T_841 = eq(T_839, UInt<1>("h00"))
    node T_843 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_844 = mux(UInt<1>("h00"), T_843, UInt<1>("h01"))
    node T_845 = and(T_844, io.out.ready)
    io.in[0].ready <= T_845
    node T_847 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_848 = mux(UInt<1>("h00"), T_847, T_841)
    node T_849 = and(T_848, io.out.ready)
    io.in[1].ready <= T_849
    node T_852 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_853 = mux(UInt<1>("h00"), UInt<1>("h01"), T_852)
    T_658 <= T_853
    
  module NastiIOTileLinkIOConverter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}
    
    io is invalid
    wire T_685 : UInt<3>[3]
    T_685[0] <= UInt<3>("h02")
    T_685[1] <= UInt<3>("h03")
    T_685[2] <= UInt<3>("h04")
    node T_690 = eq(T_685[0], io.tl.acquire.bits.a_type)
    node T_691 = eq(T_685[1], io.tl.acquire.bits.a_type)
    node T_692 = eq(T_685[2], io.tl.acquire.bits.a_type)
    node T_694 = or(UInt<1>("h00"), T_690)
    node T_695 = or(T_694, T_691)
    node T_696 = or(T_695, T_692)
    node has_data = and(io.tl.acquire.bits.is_builtin_type, T_696)
    wire T_702 : UInt<3>[3]
    T_702[0] <= UInt<3>("h02")
    T_702[1] <= UInt<3>("h00")
    T_702[2] <= UInt<3>("h04")
    node T_707 = eq(T_702[0], io.tl.acquire.bits.a_type)
    node T_708 = eq(T_702[1], io.tl.acquire.bits.a_type)
    node T_709 = eq(T_702[2], io.tl.acquire.bits.a_type)
    node T_711 = or(UInt<1>("h00"), T_707)
    node T_712 = or(T_711, T_708)
    node T_713 = or(T_712, T_709)
    node is_subblock = and(io.tl.acquire.bits.is_builtin_type, T_713)
    node T_716 = and(UInt<1>("h01"), io.tl.acquire.bits.is_builtin_type)
    wire T_719 : UInt<3>[1]
    T_719[0] <= UInt<3>("h03")
    node T_722 = eq(T_719[0], io.tl.acquire.bits.a_type)
    node T_724 = or(UInt<1>("h00"), T_722)
    node is_multibeat = and(T_716, T_724)
    node T_726 = and(io.tl.acquire.ready, io.tl.acquire.valid)
    node T_727 = and(T_726, is_multibeat)
    reg tl_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    when T_727 :
      node T_731 = eq(tl_cnt_out, UInt<3>("h07"))
      node T_733 = and(UInt<1>("h00"), T_731)
      node T_736 = add(tl_cnt_out, UInt<1>("h01"))
      node T_737 = tail(T_736, 1)
      node T_738 = mux(T_733, UInt<1>("h00"), T_737)
      tl_cnt_out <= T_738
      skip
    node tl_wrap_out = and(T_727, T_731)
    node T_741 = eq(has_data, UInt<1>("h00"))
    node get_valid = and(io.tl.acquire.valid, T_741)
    node put_valid = and(io.tl.acquire.valid, has_data)
    inst roq of ReorderQueue_70
    roq.io is invalid
    roq.clk <= clk
    roq.reset <= reset
    reg w_inflight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node aw_ready = or(w_inflight, io.nasti.aw.ready)
    node T_772 = and(io.nasti.r.ready, io.nasti.r.valid)
    node T_774 = eq(roq.io.deq.data.subblock, UInt<1>("h00"))
    node T_775 = and(T_772, T_774)
    reg nasti_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    when T_775 :
      node T_779 = eq(nasti_cnt_out, UInt<3>("h07"))
      node T_781 = and(UInt<1>("h00"), T_779)
      node T_784 = add(nasti_cnt_out, UInt<1>("h01"))
      node T_785 = tail(T_784, 1)
      node T_786 = mux(T_781, UInt<1>("h00"), T_785)
      nasti_cnt_out <= T_786
      skip
    node nasti_wrap_out = and(T_775, T_779)
    node T_788 = and(get_valid, io.nasti.ar.ready)
    roq.io.enq.valid <= T_788
    roq.io.enq.bits.tag <= io.nasti.ar.bits.id
    roq.io.enq.bits.data.addr_beat <= io.tl.acquire.bits.addr_beat
    node T_789 = bits(io.tl.acquire.bits.union, 11, 9)
    roq.io.enq.bits.data.byteOff <= T_789
    roq.io.enq.bits.data.subblock <= is_subblock
    node T_790 = and(io.nasti.r.ready, io.nasti.r.valid)
    node T_791 = or(nasti_wrap_out, roq.io.deq.data.subblock)
    node T_792 = and(T_790, T_791)
    roq.io.deq.valid <= T_792
    roq.io.deq.tag <= io.nasti.r.bits.id
    node T_793 = and(get_valid, roq.io.enq.ready)
    io.nasti.ar.valid <= T_793
    node T_794 = bits(io.tl.acquire.bits.union, 11, 9)
    node T_795 = cat(io.tl.acquire.bits.addr_beat, T_794)
    node T_796 = cat(io.tl.acquire.bits.addr_block, T_795)
    node T_797 = bits(io.tl.acquire.bits.union, 8, 6)
    node T_806 = eq(UInt<3>("h07"), T_797)
    node T_807 = mux(T_806, UInt<2>("h03"), UInt<3>("h07"))
    node T_808 = eq(UInt<3>("h03"), T_797)
    node T_809 = mux(T_808, UInt<2>("h03"), T_807)
    node T_810 = eq(UInt<3>("h02"), T_797)
    node T_811 = mux(T_810, UInt<2>("h02"), T_809)
    node T_812 = eq(UInt<3>("h05"), T_797)
    node T_813 = mux(T_812, UInt<1>("h01"), T_811)
    node T_814 = eq(UInt<3>("h01"), T_797)
    node T_815 = mux(T_814, UInt<1>("h01"), T_813)
    node T_816 = eq(UInt<3>("h04"), T_797)
    node T_817 = mux(T_816, UInt<1>("h00"), T_815)
    node T_818 = eq(UInt<3>("h00"), T_797)
    node T_819 = mux(T_818, UInt<1>("h00"), T_817)
    node T_821 = mux(is_subblock, T_819, UInt<2>("h03"))
    node T_824 = mux(is_subblock, UInt<1>("h00"), UInt<3>("h07"))
    wire T_837 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}
    T_837 is invalid
    T_837.id <= io.tl.acquire.bits.client_xact_id
    T_837.addr <= T_796
    T_837.len <= T_824
    T_837.size <= T_821
    T_837.burst <= UInt<2>("h01")
    T_837.lock <= UInt<1>("h00")
    T_837.cache <= UInt<1>("h00")
    T_837.prot <= UInt<1>("h00")
    T_837.qos <= UInt<1>("h00")
    T_837.region <= UInt<1>("h00")
    T_837.user <= UInt<1>("h00")
    io.nasti.ar.bits <- T_837
    node T_856 = eq(w_inflight, UInt<1>("h00"))
    node T_857 = and(put_valid, io.nasti.w.ready)
    node T_858 = and(T_857, T_856)
    io.nasti.aw.valid <= T_858
    node T_859 = bits(io.tl.acquire.bits.union, 11, 9)
    node T_860 = cat(io.tl.acquire.bits.addr_beat, T_859)
    node T_861 = cat(io.tl.acquire.bits.addr_block, T_860)
    node T_865 = mux(is_multibeat, UInt<3>("h07"), UInt<1>("h00"))
    wire T_878 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}
    T_878 is invalid
    T_878.id <= io.tl.acquire.bits.client_xact_id
    T_878.addr <= T_861
    T_878.len <= T_865
    T_878.size <= UInt<2>("h03")
    T_878.burst <= UInt<2>("h01")
    T_878.lock <= UInt<1>("h00")
    T_878.cache <= UInt<4>("h00")
    T_878.prot <= UInt<3>("h00")
    T_878.qos <= UInt<4>("h00")
    T_878.region <= UInt<4>("h00")
    T_878.user <= UInt<1>("h00")
    io.nasti.aw.bits <- T_878
    node T_896 = and(put_valid, aw_ready)
    io.nasti.w.valid <= T_896
    node T_899 = eq(io.tl.acquire.bits.a_type, UInt<3>("h04"))
    node T_900 = and(io.tl.acquire.bits.is_builtin_type, T_899)
    wire T_903 : UInt<1>[1]
    T_903[0] <= UInt<1>("h01")
    node T_907 = sub(UInt<8>("h00"), T_903[0])
    node T_908 = tail(T_907, 1)
    wire T_910 : UInt<8>[1]
    T_910[0] <= T_908
    node T_914 = eq(io.tl.acquire.bits.a_type, UInt<3>("h03"))
    node T_915 = and(io.tl.acquire.bits.is_builtin_type, T_914)
    node T_917 = eq(io.tl.acquire.bits.a_type, UInt<3>("h02"))
    node T_918 = and(io.tl.acquire.bits.is_builtin_type, T_917)
    node T_919 = or(T_915, T_918)
    node T_920 = bits(io.tl.acquire.bits.union, 8, 1)
    node T_922 = mux(T_919, T_920, UInt<8>("h00"))
    node T_923 = mux(T_900, T_910[0], T_922)
    node T_924 = and(io.tl.acquire.ready, io.tl.acquire.valid)
    node T_925 = and(T_924, is_subblock)
    node T_926 = or(tl_wrap_out, T_925)
    wire T_932 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}
    T_932 is invalid
    node T_938 = cat(UInt<1>("h01"), UInt<1>("h01"))
    node T_939 = cat(T_938, T_938)
    node T_940 = cat(T_939, T_939)
    T_932.strb <= T_940
    T_932.data <= io.tl.acquire.bits.data
    T_932.last <= T_926
    T_932.user <= UInt<1>("h00")
    T_932.strb <= T_923
    io.nasti.w.bits <- T_932
    node T_942 = and(aw_ready, io.nasti.w.ready)
    node T_943 = and(roq.io.enq.ready, io.nasti.ar.ready)
    node T_944 = mux(has_data, T_942, T_943)
    io.tl.acquire.ready <= T_944
    node T_946 = eq(w_inflight, UInt<1>("h00"))
    node T_947 = and(io.tl.acquire.ready, io.tl.acquire.valid)
    node T_948 = and(T_946, T_947)
    node T_949 = and(T_948, is_multibeat)
    when T_949 :
      w_inflight <= UInt<1>("h01")
      skip
    when w_inflight :
      when tl_wrap_out :
        w_inflight <= UInt<1>("h00")
        skip
      skip
    node T_952 = and(io.tl.grant.ready, io.tl.grant.valid)
    wire T_956 : UInt<3>[1]
    T_956[0] <= UInt<3>("h05")
    node T_959 = eq(T_956[0], io.tl.grant.bits.g_type)
    node T_961 = or(UInt<1>("h00"), T_959)
    wire T_963 : UInt<1>[1]
    T_963[0] <= UInt<1>("h00")
    node T_966 = eq(T_963[0], io.tl.grant.bits.g_type)
    node T_968 = or(UInt<1>("h00"), T_966)
    node T_969 = mux(io.tl.grant.bits.is_builtin_type, T_961, T_968)
    node T_970 = and(UInt<1>("h01"), T_969)
    node T_971 = and(T_952, T_970)
    reg tl_cnt_in : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    when T_971 :
      node T_975 = eq(tl_cnt_in, UInt<3>("h07"))
      node T_977 = and(UInt<1>("h00"), T_975)
      node T_980 = add(tl_cnt_in, UInt<1>("h01"))
      node T_981 = tail(T_980, 1)
      node T_982 = mux(T_977, UInt<1>("h00"), T_981)
      tl_cnt_in <= T_982
      skip
    node tl_wrap_in = and(T_971, T_975)
    inst gnt_arb of Arbiter
    gnt_arb.io is invalid
    gnt_arb.clk <= clk
    gnt_arb.reset <= reset
    io.tl.grant <- gnt_arb.io.out
    node T_1014 = cat(roq.io.deq.data.byteOff, UInt<3>("h00"))
    node T_1015 = dshl(io.nasti.r.bits.data, T_1014)
    node r_aligned_data = mux(roq.io.deq.data.subblock, T_1015, io.nasti.r.bits.data)
    gnt_arb.io.in[0].valid <= io.nasti.r.valid
    io.nasti.r.ready <= gnt_arb.io.in[0].ready
    node T_1020 = mux(roq.io.deq.data.subblock, UInt<3>("h04"), UInt<3>("h05"))
    node T_1022 = mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in)
    wire T_1050 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}
    T_1050 is invalid
    T_1050.is_builtin_type <= UInt<1>("h01")
    T_1050.g_type <= T_1020
    T_1050.client_xact_id <= io.nasti.r.bits.id
    T_1050.manager_xact_id <= UInt<1>("h00")
    T_1050.addr_beat <= T_1022
    T_1050.data <= r_aligned_data
    gnt_arb.io.in[0].bits <- T_1050
    gnt_arb.io.in[1].valid <= io.nasti.b.valid
    io.nasti.b.ready <= gnt_arb.io.in[1].ready
    wire T_1109 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}
    T_1109 is invalid
    T_1109.is_builtin_type <= UInt<1>("h01")
    T_1109.g_type <= UInt<3>("h03")
    T_1109.client_xact_id <= io.nasti.b.bits.id
    T_1109.manager_xact_id <= UInt<1>("h00")
    T_1109.addr_beat <= UInt<1>("h00")
    T_1109.data <= UInt<1>("h00")
    gnt_arb.io.in[1].bits <- T_1109
    node T_1137 = eq(io.nasti.r.valid, UInt<1>("h00"))
    node T_1139 = eq(io.nasti.r.bits.resp, UInt<1>("h00"))
    node T_1140 = or(T_1137, T_1139)
    node T_1142 = eq(reset, UInt<1>("h00"))
    when T_1142 :
      node T_1144 = eq(T_1140, UInt<1>("h00"))
      when T_1144 :
        node T_1146 = eq(reset, UInt<1>("h00"))
        when T_1146 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): NASTI read error")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1148 = eq(io.nasti.b.valid, UInt<1>("h00"))
    node T_1150 = eq(io.nasti.b.bits.resp, UInt<1>("h00"))
    node T_1151 = or(T_1148, T_1150)
    node T_1153 = eq(reset, UInt<1>("h00"))
    when T_1153 :
      node T_1155 = eq(T_1151, UInt<1>("h00"))
      when T_1155 :
        node T_1157 = eq(reset, UInt<1>("h00"))
        when T_1157 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): NASTI write error")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    
  module ClientTileLinkIOWrapper_71 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}
    
    io is invalid
    io.out.acquire <- io.in.acquire
    io.in.grant <- io.out.grant
    io.out.probe.ready <= UInt<1>("h01")
    io.out.release.valid <= UInt<1>("h00")
    
  module ClientTileLinkEnqueuer : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip inner : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}
    
    io is invalid
    io.outer.acquire <- io.inner.acquire
    io.inner.probe <- io.outer.probe
    io.outer.release <- io.inner.release
    io.inner.grant <- io.outer.grant
    
  module Queue_74 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, count : UInt<4>}
    
    io is invalid
    cmem ram : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}[8]
    reg T_62 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg T_64 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_62, T_64)
    node T_69 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_69)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_75 = and(io.enq.ready, io.enq.valid)
    node T_77 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_75, T_77)
    node T_79 = and(io.deq.ready, io.deq.valid)
    node T_81 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_79, T_81)
    when do_enq :
      infer mport T_83 = ram[T_62], clk
      T_83 <- io.enq.bits
      node T_89 = eq(T_62, UInt<3>("h07"))
      node T_91 = and(UInt<1>("h00"), T_89)
      node T_94 = add(T_62, UInt<1>("h01"))
      node T_95 = tail(T_94, 1)
      node T_96 = mux(T_91, UInt<1>("h00"), T_95)
      T_62 <= T_96
      skip
    when do_deq :
      node T_98 = eq(T_64, UInt<3>("h07"))
      node T_100 = and(UInt<1>("h00"), T_98)
      node T_103 = add(T_64, UInt<1>("h01"))
      node T_104 = tail(T_103, 1)
      node T_105 = mux(T_100, UInt<1>("h00"), T_104)
      T_64 <= T_105
      skip
    node T_106 = neq(do_enq, do_deq)
    when T_106 :
      maybe_full <= do_enq
      skip
    node T_108 = eq(empty, UInt<1>("h00"))
    node T_110 = and(UInt<1>("h00"), io.enq.valid)
    node T_111 = or(T_108, T_110)
    io.deq.valid <= T_111
    node T_113 = eq(full, UInt<1>("h00"))
    node T_115 = and(UInt<1>("h00"), io.deq.ready)
    node T_116 = or(T_113, T_115)
    io.enq.ready <= T_116
    infer mport T_117 = ram[T_64], clk
    node T_122 = mux(maybe_flow, io.enq.bits, T_117)
    io.deq.bits <- T_122
    node T_127 = sub(T_62, T_64)
    node ptr_diff = tail(T_127, 1)
    node T_129 = and(maybe_full, ptr_match)
    node T_130 = cat(T_129, ptr_diff)
    io.count <= T_130
    
  module Queue_75 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<4>}
    
    io is invalid
    cmem ram : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}[8]
    reg T_71 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg T_73 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_71, T_73)
    node T_78 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_78)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_84 = and(io.enq.ready, io.enq.valid)
    node T_86 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_84, T_86)
    node T_88 = and(io.deq.ready, io.deq.valid)
    node T_90 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_88, T_90)
    when do_enq :
      infer mport T_92 = ram[T_71], clk
      T_92 <- io.enq.bits
      node T_99 = eq(T_71, UInt<3>("h07"))
      node T_101 = and(UInt<1>("h00"), T_99)
      node T_104 = add(T_71, UInt<1>("h01"))
      node T_105 = tail(T_104, 1)
      node T_106 = mux(T_101, UInt<1>("h00"), T_105)
      T_71 <= T_106
      skip
    when do_deq :
      node T_108 = eq(T_73, UInt<3>("h07"))
      node T_110 = and(UInt<1>("h00"), T_108)
      node T_113 = add(T_73, UInt<1>("h01"))
      node T_114 = tail(T_113, 1)
      node T_115 = mux(T_110, UInt<1>("h00"), T_114)
      T_73 <= T_115
      skip
    node T_116 = neq(do_enq, do_deq)
    when T_116 :
      maybe_full <= do_enq
      skip
    node T_118 = eq(empty, UInt<1>("h00"))
    node T_120 = and(UInt<1>("h00"), io.enq.valid)
    node T_121 = or(T_118, T_120)
    io.deq.valid <= T_121
    node T_123 = eq(full, UInt<1>("h00"))
    node T_125 = and(UInt<1>("h00"), io.deq.ready)
    node T_126 = or(T_123, T_125)
    io.enq.ready <= T_126
    infer mport T_127 = ram[T_73], clk
    node T_133 = mux(maybe_flow, io.enq.bits, T_127)
    io.deq.bits <- T_133
    node T_139 = sub(T_71, T_73)
    node ptr_diff = tail(T_139, 1)
    node T_141 = and(maybe_full, ptr_match)
    node T_142 = cat(T_141, ptr_diff)
    io.count <= T_142
    
  module Queue_76 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>}
    
    io is invalid
    cmem ram : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}[2]
    reg T_53 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_55 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_53, T_55)
    node T_60 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_60)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_66 = and(io.enq.ready, io.enq.valid)
    node T_68 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_66, T_68)
    node T_70 = and(io.deq.ready, io.deq.valid)
    node T_72 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_70, T_72)
    when do_enq :
      infer mport T_74 = ram[T_53], clk
      T_74 <- io.enq.bits
      node T_79 = eq(T_53, UInt<1>("h01"))
      node T_81 = and(UInt<1>("h00"), T_79)
      node T_84 = add(T_53, UInt<1>("h01"))
      node T_85 = tail(T_84, 1)
      node T_86 = mux(T_81, UInt<1>("h00"), T_85)
      T_53 <= T_86
      skip
    when do_deq :
      node T_88 = eq(T_55, UInt<1>("h01"))
      node T_90 = and(UInt<1>("h00"), T_88)
      node T_93 = add(T_55, UInt<1>("h01"))
      node T_94 = tail(T_93, 1)
      node T_95 = mux(T_90, UInt<1>("h00"), T_94)
      T_55 <= T_95
      skip
    node T_96 = neq(do_enq, do_deq)
    when T_96 :
      maybe_full <= do_enq
      skip
    node T_98 = eq(empty, UInt<1>("h00"))
    node T_100 = and(UInt<1>("h00"), io.enq.valid)
    node T_101 = or(T_98, T_100)
    io.deq.valid <= T_101
    node T_103 = eq(full, UInt<1>("h00"))
    node T_105 = and(UInt<1>("h00"), io.deq.ready)
    node T_106 = or(T_103, T_105)
    io.enq.ready <= T_106
    infer mport T_107 = ram[T_55], clk
    node T_111 = mux(maybe_flow, io.enq.bits, T_107)
    io.deq.bits <- T_111
    node T_115 = sub(T_53, T_55)
    node ptr_diff = tail(T_115, 1)
    node T_117 = and(maybe_full, ptr_match)
    node T_118 = cat(T_117, ptr_diff)
    io.count <= T_118
    
  module RTC : 
    input clk : Clock
    input reset : UInt<1>
    output io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}
    
    io is invalid
    wire addrTable : UInt<31>[1]
    addrTable[0] <= UInt<31>("h04000b808")
    reg rtc : UInt<64>, clk with : (reset => (reset, UInt<64>("h00")))
    reg T_217 : UInt<7>, clk with : (reset => (reset, UInt<7>("h00")))
    node rtc_tick = eq(T_217, UInt<7>("h063"))
    node T_221 = and(UInt<1>("h01"), rtc_tick)
    node T_224 = add(T_217, UInt<1>("h01"))
    node T_225 = tail(T_224, 1)
    node T_226 = mux(T_221, UInt<1>("h00"), T_225)
    T_217 <= T_226
    reg sending_addr : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg sending_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_233 : UInt<1>[1]
    T_233[0] <= UInt<1>("h01")
    reg send_acked : UInt<1>[1], clk with : (reset => (reset, T_233))
    wire coreId : UInt<1>
    coreId is invalid
    when rtc_tick :
      node T_244 = add(rtc, UInt<1>("h01"))
      node T_245 = tail(T_244, 1)
      rtc <= T_245
      wire T_248 : UInt<1>[1]
      T_248[0] <= UInt<1>("h00")
      send_acked <= T_248
      sending_addr <= UInt<1>("h01")
      sending_data <= UInt<1>("h01")
      skip
    node T_253 = and(io.aw.ready, io.aw.valid)
    when T_253 :
      sending_addr <= UInt<1>("h00")
      skip
    node T_255 = and(io.w.ready, io.w.valid)
    when T_255 :
      sending_addr <= UInt<1>("h00")
      skip
    coreId <= UInt<1>("h00")
    node T_258 = and(io.b.ready, io.b.valid)
    when T_258 :
      send_acked[io.b.bits.id] <= UInt<1>("h01")
      skip
    io.aw.valid <= sending_addr
    wire T_276 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}
    T_276 is invalid
    T_276.id <= coreId
    T_276.addr <= addrTable[coreId]
    T_276.len <= UInt<1>("h00")
    T_276.size <= UInt<2>("h03")
    T_276.burst <= UInt<2>("h01")
    T_276.lock <= UInt<1>("h00")
    T_276.cache <= UInt<4>("h00")
    T_276.prot <= UInt<3>("h00")
    T_276.qos <= UInt<4>("h00")
    T_276.region <= UInt<4>("h00")
    T_276.user <= UInt<1>("h00")
    io.aw.bits <- T_276
    io.w.valid <= sending_data
    wire T_300 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}
    T_300 is invalid
    node T_306 = cat(UInt<1>("h01"), UInt<1>("h01"))
    node T_307 = cat(T_306, T_306)
    node T_308 = cat(T_307, T_307)
    T_300.strb <= T_308
    T_300.data <= rtc
    T_300.last <= UInt<1>("h01")
    T_300.user <= UInt<1>("h00")
    io.w.bits <- T_300
    io.b.ready <= UInt<1>("h01")
    io.ar.valid <= UInt<1>("h00")
    io.r.ready <= UInt<1>("h00")
    node T_314 = eq(rtc_tick, UInt<1>("h00"))
    node T_315 = or(T_314, send_acked[0])
    node T_317 = eq(reset, UInt<1>("h00"))
    when T_317 :
      node T_319 = eq(T_315, UInt<1>("h00"))
      when T_319 :
        node T_321 = eq(reset, UInt<1>("h00"))
        when T_321 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Not all clocks were updated for rtc tick")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    
  module SmiIONastiReadIOConverter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg nWords : UInt<1>, clk
    reg nBeats : UInt<8>, clk
    reg addr : UInt<12>, clk
    reg id : UInt<5>, clk
    reg byteOff : UInt<3>, clk
    reg sendInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg recvInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg sendDone : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_141 : UInt<64>[1]
    T_141[0] <= UInt<64>("h00")
    reg buffer : UInt<64>[1], clk with : (reset => (reset, T_141))
    node T_149 = eq(state, UInt<1>("h00"))
    io.ar.ready <= T_149
    node T_150 = eq(state, UInt<1>("h01"))
    node T_152 = eq(sendDone, UInt<1>("h00"))
    node T_153 = and(T_150, T_152)
    io.smi.req.valid <= T_153
    io.smi.req.bits.rw <= UInt<1>("h00")
    io.smi.req.bits.addr <= addr
    node T_155 = eq(state, UInt<1>("h01"))
    io.smi.resp.ready <= T_155
    node T_156 = eq(state, UInt<2>("h02"))
    io.r.valid <= T_156
    node T_158 = eq(nBeats, UInt<1>("h00"))
    wire T_166 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}
    T_166 is invalid
    T_166.id <= id
    T_166.data <= buffer[0]
    T_166.last <= T_158
    T_166.resp <= UInt<1>("h00")
    T_166.user <= UInt<1>("h00")
    io.r.bits <- T_166
    node T_173 = and(io.ar.ready, io.ar.valid)
    when T_173 :
      node T_175 = lt(io.ar.bits.size, UInt<2>("h03"))
      when T_175 :
        nWords <= UInt<1>("h00")
        node T_177 = bits(io.ar.bits.addr, 2, 0)
        byteOff <= T_177
        skip
      node T_179 = eq(T_175, UInt<1>("h00"))
      when T_179 :
        node T_182 = sub(io.ar.bits.size, UInt<2>("h03"))
        node T_183 = tail(T_182, 1)
        node T_184 = dshl(UInt<1>("h01"), T_183)
        node T_186 = sub(T_184, UInt<1>("h01"))
        node T_187 = tail(T_186, 1)
        nWords <= T_187
        byteOff <= UInt<1>("h00")
        skip
      nBeats <= io.ar.bits.len
      node T_189 = bits(io.ar.bits.addr, 14, 3)
      addr <= T_189
      id <= io.ar.bits.id
      state <= UInt<1>("h01")
      skip
    node T_190 = and(io.smi.req.ready, io.smi.req.valid)
    when T_190 :
      node T_192 = add(addr, UInt<1>("h01"))
      node T_193 = tail(T_192, 1)
      addr <= T_193
      node T_195 = add(sendInd, UInt<1>("h01"))
      node T_196 = tail(T_195, 1)
      sendInd <= T_196
      node T_197 = eq(sendInd, nWords)
      sendDone <= T_197
      skip
    node T_198 = and(io.smi.resp.ready, io.smi.resp.valid)
    when T_198 :
      node T_200 = add(recvInd, UInt<1>("h01"))
      node T_201 = tail(T_200, 1)
      recvInd <= T_201
      node T_204 = cat(byteOff, UInt<3>("h00"))
      node T_205 = dshr(io.smi.resp.bits, T_204)
      buffer[recvInd] <= T_205
      node T_206 = eq(recvInd, nWords)
      when T_206 :
        state <= UInt<2>("h02")
        skip
      skip
    node T_207 = and(io.r.ready, io.r.valid)
    when T_207 :
      recvInd <= UInt<1>("h00")
      sendInd <= UInt<1>("h00")
      sendDone <= UInt<1>("h00")
      buffer[0] <= UInt<1>("h00")
      node T_213 = sub(nBeats, UInt<1>("h01"))
      node T_214 = tail(T_213, 1)
      nBeats <= T_214
      node T_215 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01"))
      state <= T_215
      skip
    
  module SmiIONastiWriteIOConverter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    node T_144 = eq(io.aw.valid, UInt<1>("h00"))
    node T_146 = geq(io.aw.bits.size, UInt<2>("h03"))
    node T_147 = or(T_144, T_146)
    node T_149 = eq(reset, UInt<1>("h00"))
    when T_149 :
      node T_151 = eq(T_147, UInt<1>("h00"))
      when T_151 :
        node T_153 = eq(reset, UInt<1>("h00"))
        when T_153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg id : UInt<5>, clk
    reg addr : UInt<12>, clk
    reg size : UInt<3>, clk
    reg strb : UInt<1>, clk
    reg data : UInt<64>, clk
    reg last : UInt<1>, clk
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    node T_173 = eq(state, UInt<1>("h00"))
    io.aw.ready <= T_173
    node T_174 = eq(state, UInt<1>("h01"))
    io.w.ready <= T_174
    node T_175 = eq(state, UInt<2>("h02"))
    node T_176 = bits(strb, 0, 0)
    node T_177 = and(T_175, T_176)
    io.smi.req.valid <= T_177
    io.smi.req.bits.rw <= UInt<1>("h01")
    io.smi.req.bits.addr <= addr
    node T_179 = bits(data, 63, 0)
    io.smi.req.bits.data <= T_179
    node T_180 = eq(state, UInt<2>("h03"))
    io.smi.resp.ready <= T_180
    node T_181 = eq(state, UInt<3>("h04"))
    io.b.valid <= T_181
    wire T_187 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}
    T_187 is invalid
    T_187.id <= id
    T_187.resp <= UInt<1>("h00")
    T_187.user <= UInt<1>("h00")
    io.b.bits <- T_187
    node T_193 = and(io.aw.ready, io.aw.valid)
    when T_193 :
      node T_194 = bits(io.aw.bits.addr, 14, 3)
      addr <= T_194
      id <= io.aw.bits.id
      size <= io.aw.bits.size
      last <= UInt<1>("h00")
      state <= UInt<1>("h01")
      skip
    node T_196 = and(io.w.ready, io.w.valid)
    when T_196 :
      last <= io.w.bits.last
      node T_199 = dshl(UInt<1>("h01"), size)
      node T_200 = dshl(UInt<1>("h01"), T_199)
      node T_202 = sub(T_200, UInt<1>("h01"))
      node T_203 = tail(T_202, 1)
      node T_204 = and(T_203, io.w.bits.strb)
      node T_205 = bits(T_204, 0, 0)
      wire T_207 : UInt<1>[1]
      T_207[0] <= T_205
      strb <= T_207[0]
      data <= io.w.bits.data
      state <= UInt<2>("h02")
      skip
    node T_210 = eq(state, UInt<2>("h02"))
    when T_210 :
      node T_212 = eq(strb, UInt<1>("h00"))
      when T_212 :
        node T_213 = mux(last, UInt<2>("h03"), UInt<1>("h01"))
        state <= T_213
        skip
      node T_214 = bits(strb, 0, 0)
      node T_216 = eq(T_214, UInt<1>("h00"))
      node T_217 = or(io.smi.req.ready, T_216)
      node T_219 = eq(T_212, UInt<1>("h00"))
      node T_220 = and(T_219, T_217)
      when T_220 :
        node T_221 = dshr(strb, UInt<1>("h01"))
        strb <= T_221
        node T_223 = cat(UInt<1>("h01"), UInt<6>("h00"))
        node T_224 = dshr(data, T_223)
        data <= T_224
        node T_225 = add(addr, UInt<1>("h01"))
        node T_226 = tail(T_225, 1)
        addr <= T_226
        skip
      skip
    node T_227 = and(io.smi.resp.ready, io.smi.resp.valid)
    when T_227 :
      state <= UInt<3>("h04")
      skip
    node T_228 = and(io.b.ready, io.b.valid)
    when T_228 :
      state <= UInt<1>("h00")
      skip
    
  module RRArbiter_77 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_130 : UInt<1>
    T_130 is invalid
    io.out.valid <= io.in[T_130].valid
    io.out.bits <- io.in[T_130].bits
    io.chosen <= T_130
    io.in[T_130].ready <= UInt<1>("h00")
    reg T_167 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_168 = gt(UInt<1>("h00"), T_167)
    node T_169 = and(io.in[0].valid, T_168)
    node T_171 = gt(UInt<1>("h01"), T_167)
    node T_172 = and(io.in[1].valid, T_171)
    node T_175 = or(UInt<1>("h00"), T_169)
    node T_177 = eq(T_175, UInt<1>("h00"))
    node T_179 = or(UInt<1>("h00"), T_169)
    node T_180 = or(T_179, T_172)
    node T_182 = eq(T_180, UInt<1>("h00"))
    node T_184 = or(UInt<1>("h00"), T_169)
    node T_185 = or(T_184, T_172)
    node T_186 = or(T_185, io.in[0].valid)
    node T_188 = eq(T_186, UInt<1>("h00"))
    node T_190 = gt(UInt<1>("h00"), T_167)
    node T_191 = and(UInt<1>("h01"), T_190)
    node T_192 = or(T_191, T_182)
    node T_194 = gt(UInt<1>("h01"), T_167)
    node T_195 = and(T_177, T_194)
    node T_196 = or(T_195, T_188)
    node T_198 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_199 = mux(UInt<1>("h00"), T_198, T_192)
    node T_200 = and(T_199, io.out.ready)
    io.in[0].ready <= T_200
    node T_202 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_203 = mux(UInt<1>("h00"), T_202, T_196)
    node T_204 = and(T_203, io.out.ready)
    io.in[1].ready <= T_204
    node T_207 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_209 = gt(UInt<1>("h01"), T_167)
    node T_210 = and(io.in[1].valid, T_209)
    node T_212 = mux(T_210, UInt<1>("h01"), T_207)
    node T_213 = mux(UInt<1>("h00"), UInt<1>("h01"), T_212)
    T_130 <= T_213
    node T_214 = and(io.out.ready, io.out.valid)
    when T_214 :
      T_167 <= T_130
      skip
    
  module SmiArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    reg wait_resp : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg choice : UInt<1>, clk
    inst req_arb of RRArbiter_77
    req_arb.io is invalid
    req_arb.clk <= clk
    req_arb.reset <= reset
    req_arb.io.in[0] <- io.in[0].req
    req_arb.io.in[1] <- io.in[1].req
    node T_313 = eq(wait_resp, UInt<1>("h00"))
    node T_314 = and(io.out.req.ready, T_313)
    req_arb.io.out.ready <= T_314
    io.out.req.bits <- req_arb.io.out.bits
    node T_316 = eq(wait_resp, UInt<1>("h00"))
    node T_317 = and(req_arb.io.out.valid, T_316)
    io.out.req.valid <= T_317
    node T_318 = and(io.out.req.ready, io.out.req.valid)
    when T_318 :
      choice <= req_arb.io.chosen
      wait_resp <= UInt<1>("h01")
      skip
    node T_320 = and(io.out.resp.ready, io.out.resp.valid)
    when T_320 :
      wait_resp <= UInt<1>("h00")
      skip
    io.in[0].resp.bits <= io.out.resp.bits
    node T_323 = eq(choice, UInt<1>("h00"))
    node T_324 = and(io.out.resp.valid, T_323)
    io.in[0].resp.valid <= T_324
    io.in[1].resp.bits <= io.out.resp.bits
    node T_326 = eq(choice, UInt<1>("h01"))
    node T_327 = and(io.out.resp.valid, T_326)
    io.in[1].resp.valid <= T_327
    io.out.resp.ready <= io.in[choice].resp.ready
    
  module SmiIONastiIOConverter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    inst reader of SmiIONastiReadIOConverter
    reader.io is invalid
    reader.clk <= clk
    reader.reset <= reset
    reader.io.ar <- io.nasti.ar
    io.nasti.r <- reader.io.r
    inst writer of SmiIONastiWriteIOConverter
    writer.io is invalid
    writer.clk <= clk
    writer.reset <= reset
    writer.io.aw <- io.nasti.aw
    writer.io.w <- io.nasti.w
    io.nasti.b <- writer.io.b
    inst arb of SmiArbiter
    arb.io is invalid
    arb.clk <= clk
    arb.reset <= reset
    arb.io.in[0] <- reader.io.smi
    arb.io.in[1] <- writer.io.smi
    io.smi <- arb.io.out
    
  module SmiIONastiReadIOConverter_79 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg nWords : UInt<1>, clk
    reg nBeats : UInt<8>, clk
    reg addr : UInt<6>, clk
    reg id : UInt<5>, clk
    reg byteOff : UInt<3>, clk
    reg sendInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg recvInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg sendDone : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_141 : UInt<64>[1]
    T_141[0] <= UInt<64>("h00")
    reg buffer : UInt<64>[1], clk with : (reset => (reset, T_141))
    node T_149 = eq(state, UInt<1>("h00"))
    io.ar.ready <= T_149
    node T_150 = eq(state, UInt<1>("h01"))
    node T_152 = eq(sendDone, UInt<1>("h00"))
    node T_153 = and(T_150, T_152)
    io.smi.req.valid <= T_153
    io.smi.req.bits.rw <= UInt<1>("h00")
    io.smi.req.bits.addr <= addr
    node T_155 = eq(state, UInt<1>("h01"))
    io.smi.resp.ready <= T_155
    node T_156 = eq(state, UInt<2>("h02"))
    io.r.valid <= T_156
    node T_158 = eq(nBeats, UInt<1>("h00"))
    wire T_166 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}
    T_166 is invalid
    T_166.id <= id
    T_166.data <= buffer[0]
    T_166.last <= T_158
    T_166.resp <= UInt<1>("h00")
    T_166.user <= UInt<1>("h00")
    io.r.bits <- T_166
    node T_173 = and(io.ar.ready, io.ar.valid)
    when T_173 :
      node T_175 = lt(io.ar.bits.size, UInt<2>("h03"))
      when T_175 :
        nWords <= UInt<1>("h00")
        node T_177 = bits(io.ar.bits.addr, 2, 0)
        byteOff <= T_177
        skip
      node T_179 = eq(T_175, UInt<1>("h00"))
      when T_179 :
        node T_182 = sub(io.ar.bits.size, UInt<2>("h03"))
        node T_183 = tail(T_182, 1)
        node T_184 = dshl(UInt<1>("h01"), T_183)
        node T_186 = sub(T_184, UInt<1>("h01"))
        node T_187 = tail(T_186, 1)
        nWords <= T_187
        byteOff <= UInt<1>("h00")
        skip
      nBeats <= io.ar.bits.len
      node T_189 = bits(io.ar.bits.addr, 8, 3)
      addr <= T_189
      id <= io.ar.bits.id
      state <= UInt<1>("h01")
      skip
    node T_190 = and(io.smi.req.ready, io.smi.req.valid)
    when T_190 :
      node T_192 = add(addr, UInt<1>("h01"))
      node T_193 = tail(T_192, 1)
      addr <= T_193
      node T_195 = add(sendInd, UInt<1>("h01"))
      node T_196 = tail(T_195, 1)
      sendInd <= T_196
      node T_197 = eq(sendInd, nWords)
      sendDone <= T_197
      skip
    node T_198 = and(io.smi.resp.ready, io.smi.resp.valid)
    when T_198 :
      node T_200 = add(recvInd, UInt<1>("h01"))
      node T_201 = tail(T_200, 1)
      recvInd <= T_201
      node T_204 = cat(byteOff, UInt<3>("h00"))
      node T_205 = dshr(io.smi.resp.bits, T_204)
      buffer[recvInd] <= T_205
      node T_206 = eq(recvInd, nWords)
      when T_206 :
        state <= UInt<2>("h02")
        skip
      skip
    node T_207 = and(io.r.ready, io.r.valid)
    when T_207 :
      recvInd <= UInt<1>("h00")
      sendInd <= UInt<1>("h00")
      sendDone <= UInt<1>("h00")
      buffer[0] <= UInt<1>("h00")
      node T_213 = sub(nBeats, UInt<1>("h01"))
      node T_214 = tail(T_213, 1)
      nBeats <= T_214
      node T_215 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01"))
      state <= T_215
      skip
    
  module SmiIONastiWriteIOConverter_80 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    node T_144 = eq(io.aw.valid, UInt<1>("h00"))
    node T_146 = geq(io.aw.bits.size, UInt<2>("h03"))
    node T_147 = or(T_144, T_146)
    node T_149 = eq(reset, UInt<1>("h00"))
    when T_149 :
      node T_151 = eq(T_147, UInt<1>("h00"))
      when T_151 :
        node T_153 = eq(reset, UInt<1>("h00"))
        when T_153 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg id : UInt<5>, clk
    reg addr : UInt<6>, clk
    reg size : UInt<3>, clk
    reg strb : UInt<1>, clk
    reg data : UInt<64>, clk
    reg last : UInt<1>, clk
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    node T_173 = eq(state, UInt<1>("h00"))
    io.aw.ready <= T_173
    node T_174 = eq(state, UInt<1>("h01"))
    io.w.ready <= T_174
    node T_175 = eq(state, UInt<2>("h02"))
    node T_176 = bits(strb, 0, 0)
    node T_177 = and(T_175, T_176)
    io.smi.req.valid <= T_177
    io.smi.req.bits.rw <= UInt<1>("h01")
    io.smi.req.bits.addr <= addr
    node T_179 = bits(data, 63, 0)
    io.smi.req.bits.data <= T_179
    node T_180 = eq(state, UInt<2>("h03"))
    io.smi.resp.ready <= T_180
    node T_181 = eq(state, UInt<3>("h04"))
    io.b.valid <= T_181
    wire T_187 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}
    T_187 is invalid
    T_187.id <= id
    T_187.resp <= UInt<1>("h00")
    T_187.user <= UInt<1>("h00")
    io.b.bits <- T_187
    node T_193 = and(io.aw.ready, io.aw.valid)
    when T_193 :
      node T_194 = bits(io.aw.bits.addr, 8, 3)
      addr <= T_194
      id <= io.aw.bits.id
      size <= io.aw.bits.size
      last <= UInt<1>("h00")
      state <= UInt<1>("h01")
      skip
    node T_196 = and(io.w.ready, io.w.valid)
    when T_196 :
      last <= io.w.bits.last
      node T_199 = dshl(UInt<1>("h01"), size)
      node T_200 = dshl(UInt<1>("h01"), T_199)
      node T_202 = sub(T_200, UInt<1>("h01"))
      node T_203 = tail(T_202, 1)
      node T_204 = and(T_203, io.w.bits.strb)
      node T_205 = bits(T_204, 0, 0)
      wire T_207 : UInt<1>[1]
      T_207[0] <= T_205
      strb <= T_207[0]
      data <= io.w.bits.data
      state <= UInt<2>("h02")
      skip
    node T_210 = eq(state, UInt<2>("h02"))
    when T_210 :
      node T_212 = eq(strb, UInt<1>("h00"))
      when T_212 :
        node T_213 = mux(last, UInt<2>("h03"), UInt<1>("h01"))
        state <= T_213
        skip
      node T_214 = bits(strb, 0, 0)
      node T_216 = eq(T_214, UInt<1>("h00"))
      node T_217 = or(io.smi.req.ready, T_216)
      node T_219 = eq(T_212, UInt<1>("h00"))
      node T_220 = and(T_219, T_217)
      when T_220 :
        node T_221 = dshr(strb, UInt<1>("h01"))
        strb <= T_221
        node T_223 = cat(UInt<1>("h01"), UInt<6>("h00"))
        node T_224 = dshr(data, T_223)
        data <= T_224
        node T_225 = add(addr, UInt<1>("h01"))
        node T_226 = tail(T_225, 1)
        addr <= T_226
        skip
      skip
    node T_227 = and(io.smi.resp.ready, io.smi.resp.valid)
    when T_227 :
      state <= UInt<3>("h04")
      skip
    node T_228 = and(io.b.ready, io.b.valid)
    when T_228 :
      state <= UInt<1>("h00")
      skip
    
  module RRArbiter_82 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_130 : UInt<1>
    T_130 is invalid
    io.out.valid <= io.in[T_130].valid
    io.out.bits <- io.in[T_130].bits
    io.chosen <= T_130
    io.in[T_130].ready <= UInt<1>("h00")
    reg T_167 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_168 = gt(UInt<1>("h00"), T_167)
    node T_169 = and(io.in[0].valid, T_168)
    node T_171 = gt(UInt<1>("h01"), T_167)
    node T_172 = and(io.in[1].valid, T_171)
    node T_175 = or(UInt<1>("h00"), T_169)
    node T_177 = eq(T_175, UInt<1>("h00"))
    node T_179 = or(UInt<1>("h00"), T_169)
    node T_180 = or(T_179, T_172)
    node T_182 = eq(T_180, UInt<1>("h00"))
    node T_184 = or(UInt<1>("h00"), T_169)
    node T_185 = or(T_184, T_172)
    node T_186 = or(T_185, io.in[0].valid)
    node T_188 = eq(T_186, UInt<1>("h00"))
    node T_190 = gt(UInt<1>("h00"), T_167)
    node T_191 = and(UInt<1>("h01"), T_190)
    node T_192 = or(T_191, T_182)
    node T_194 = gt(UInt<1>("h01"), T_167)
    node T_195 = and(T_177, T_194)
    node T_196 = or(T_195, T_188)
    node T_198 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_199 = mux(UInt<1>("h00"), T_198, T_192)
    node T_200 = and(T_199, io.out.ready)
    io.in[0].ready <= T_200
    node T_202 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_203 = mux(UInt<1>("h00"), T_202, T_196)
    node T_204 = and(T_203, io.out.ready)
    io.in[1].ready <= T_204
    node T_207 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_209 = gt(UInt<1>("h01"), T_167)
    node T_210 = and(io.in[1].valid, T_209)
    node T_212 = mux(T_210, UInt<1>("h01"), T_207)
    node T_213 = mux(UInt<1>("h00"), UInt<1>("h01"), T_212)
    T_130 <= T_213
    node T_214 = and(io.out.ready, io.out.valid)
    when T_214 :
      T_167 <= T_130
      skip
    
  module SmiArbiter_81 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    reg wait_resp : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg choice : UInt<1>, clk
    inst req_arb of RRArbiter_82
    req_arb.io is invalid
    req_arb.clk <= clk
    req_arb.reset <= reset
    req_arb.io.in[0] <- io.in[0].req
    req_arb.io.in[1] <- io.in[1].req
    node T_313 = eq(wait_resp, UInt<1>("h00"))
    node T_314 = and(io.out.req.ready, T_313)
    req_arb.io.out.ready <= T_314
    io.out.req.bits <- req_arb.io.out.bits
    node T_316 = eq(wait_resp, UInt<1>("h00"))
    node T_317 = and(req_arb.io.out.valid, T_316)
    io.out.req.valid <= T_317
    node T_318 = and(io.out.req.ready, io.out.req.valid)
    when T_318 :
      choice <= req_arb.io.chosen
      wait_resp <= UInt<1>("h01")
      skip
    node T_320 = and(io.out.resp.ready, io.out.resp.valid)
    when T_320 :
      wait_resp <= UInt<1>("h00")
      skip
    io.in[0].resp.bits <= io.out.resp.bits
    node T_323 = eq(choice, UInt<1>("h00"))
    node T_324 = and(io.out.resp.valid, T_323)
    io.in[0].resp.valid <= T_324
    io.in[1].resp.bits <= io.out.resp.bits
    node T_326 = eq(choice, UInt<1>("h01"))
    node T_327 = and(io.out.resp.valid, T_326)
    io.in[1].resp.valid <= T_327
    io.out.resp.ready <= io.in[choice].resp.ready
    
  module SmiIONastiIOConverter_78 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
    
    io is invalid
    inst reader of SmiIONastiReadIOConverter_79
    reader.io is invalid
    reader.clk <= clk
    reader.reset <= reset
    reader.io.ar <- io.nasti.ar
    io.nasti.r <- reader.io.r
    inst writer of SmiIONastiWriteIOConverter_80
    writer.io is invalid
    writer.clk <= clk
    writer.reset <= reset
    writer.io.aw <- io.nasti.aw
    writer.io.w <- io.nasti.w
    io.nasti.b <- writer.io.b
    inst arb of SmiArbiter_81
    arb.io is invalid
    arb.clk <= clk
    arb.reset <= reset
    arb.io.in[0] <- reader.io.smi
    arb.io.in[1] <- writer.io.smi
    io.smi <- arb.io.out
    
  module NastiArbiter_83 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}
    
    io is invalid
    io.slave <- io.master[0]
    
  module MemIONastiIOConverter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, mem : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}}
    
    io is invalid
    node T_368 = and(io.mem.resp.ready, io.mem.resp.valid)
    reg mif_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    when T_368 :
      node T_372 = eq(mif_cnt_out, UInt<3>("h07"))
      node T_374 = and(UInt<1>("h00"), T_372)
      node T_377 = add(mif_cnt_out, UInt<1>("h01"))
      node T_378 = tail(T_377, 1)
      node T_379 = mux(T_374, UInt<1>("h00"), T_378)
      mif_cnt_out <= T_379
      skip
    node mif_wrap_out = and(T_368, T_372)
    node T_382 = eq(io.nasti.aw.valid, UInt<1>("h00"))
    node T_384 = eq(io.nasti.aw.bits.size, UInt<2>("h03"))
    node T_385 = or(T_382, T_384)
    node T_387 = eq(reset, UInt<1>("h00"))
    when T_387 :
      node T_389 = eq(T_385, UInt<1>("h00"))
      when T_389 :
        node T_391 = eq(reset, UInt<1>("h00"))
        when T_391 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_393 = eq(io.nasti.ar.valid, UInt<1>("h00"))
    node T_395 = eq(io.nasti.ar.bits.size, UInt<2>("h03"))
    node T_396 = or(T_393, T_395)
    node T_398 = eq(reset, UInt<1>("h00"))
    when T_398 :
      node T_400 = eq(T_396, UInt<1>("h00"))
      when T_400 :
        node T_402 = eq(reset, UInt<1>("h00"))
        when T_402 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_404 = eq(io.nasti.aw.valid, UInt<1>("h00"))
    node T_406 = eq(io.nasti.aw.bits.len, UInt<3>("h07"))
    node T_407 = or(T_404, T_406)
    node T_409 = eq(reset, UInt<1>("h00"))
    when T_409 :
      node T_411 = eq(T_407, UInt<1>("h00"))
      when T_411 :
        node T_413 = eq(reset, UInt<1>("h00"))
        when T_413 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_415 = eq(io.nasti.ar.valid, UInt<1>("h00"))
    node T_417 = eq(io.nasti.ar.bits.len, UInt<3>("h07"))
    node T_418 = or(T_415, T_417)
    node T_420 = eq(reset, UInt<1>("h00"))
    when T_420 :
      node T_422 = eq(T_418, UInt<1>("h00"))
      when T_422 :
        node T_424 = eq(reset, UInt<1>("h00"))
        when T_424 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    reg b_ok : UInt<1>, clk with : (reset => (reset, UInt<1>("h01")))
    node T_427 = and(io.nasti.aw.ready, io.nasti.aw.valid)
    when T_427 :
      b_ok <= UInt<1>("h00")
      skip
    node T_429 = and(io.nasti.w.ready, io.nasti.w.valid)
    node T_430 = and(T_429, io.nasti.w.bits.last)
    when T_430 :
      b_ok <= UInt<1>("h01")
      skip
    inst id_q of Queue_37
    id_q.io is invalid
    id_q.clk <= clk
    id_q.reset <= reset
    node T_434 = and(io.nasti.aw.valid, io.mem.req_cmd.ready)
    id_q.io.enq.valid <= T_434
    id_q.io.enq.bits <= io.nasti.aw.bits.id
    node T_435 = and(io.nasti.b.ready, b_ok)
    id_q.io.deq.ready <= T_435
    node T_436 = mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr)
    node T_438 = dshr(T_436, UInt<3>("h06"))
    io.mem.req_cmd.bits.addr <= T_438
    node T_439 = mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id)
    io.mem.req_cmd.bits.tag <= T_439
    io.mem.req_cmd.bits.rw <= io.nasti.aw.valid
    node T_440 = and(io.nasti.aw.valid, id_q.io.enq.ready)
    node T_441 = or(T_440, io.nasti.ar.valid)
    io.mem.req_cmd.valid <= T_441
    node T_443 = eq(io.nasti.aw.valid, UInt<1>("h00"))
    node T_444 = and(io.mem.req_cmd.ready, T_443)
    io.nasti.ar.ready <= T_444
    node T_445 = and(io.mem.req_cmd.ready, id_q.io.enq.ready)
    io.nasti.aw.ready <= T_445
    node T_446 = and(id_q.io.deq.valid, b_ok)
    io.nasti.b.valid <= T_446
    io.nasti.b.bits.id <= id_q.io.deq.bits
    io.nasti.b.bits.resp <= UInt<1>("h00")
    io.nasti.w.ready <= io.mem.req_data.ready
    io.mem.req_data.valid <= io.nasti.w.valid
    io.mem.req_data.bits.data <= io.nasti.w.bits.data
    node T_449 = eq(io.nasti.w.valid, UInt<1>("h00"))
    node T_450 = not(io.nasti.w.bits.strb)
    node T_452 = eq(T_450, UInt<1>("h00"))
    node T_453 = or(T_449, T_452)
    node T_455 = eq(reset, UInt<1>("h00"))
    when T_455 :
      node T_457 = eq(T_453, UInt<1>("h00"))
      when T_457 :
        node T_459 = eq(reset, UInt<1>("h00"))
        when T_459 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): MemIO must write full cache line")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    io.nasti.r.valid <= io.mem.resp.valid
    io.nasti.r.bits.data <= io.mem.resp.bits.data
    io.nasti.r.bits.last <= mif_wrap_out
    io.nasti.r.bits.id <= io.mem.resp.bits.tag
    io.nasti.r.bits.resp <= UInt<1>("h00")
    io.mem.resp.ready <= io.nasti.r.ready
    
  module MemSerdes : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}, narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}}
    
    io is invalid
    node T_112 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw)
    node T_113 = cat(io.wide.req_cmd.bits.addr, T_112)
    reg out_buf : UInt, clk
    reg in_buf : UInt, clk
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg send_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    reg data_send_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    node T_130 = eq(send_cnt, UInt<1>("h01"))
    node adone = and(io.narrow.req.ready, T_130)
    node T_133 = eq(send_cnt, UInt<2>("h03"))
    node ddone = and(io.narrow.req.ready, T_133)
    node T_135 = and(io.narrow.req.valid, io.narrow.req.ready)
    when T_135 :
      node T_137 = add(send_cnt, UInt<1>("h01"))
      node T_138 = tail(T_137, 1)
      send_cnt <= T_138
      node T_140 = dshr(out_buf, UInt<5>("h010"))
      out_buf <= T_140
      skip
    node T_141 = and(io.wide.req_cmd.valid, io.wide.req_cmd.ready)
    when T_141 :
      node T_142 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw)
      node T_143 = cat(io.wide.req_cmd.bits.addr, T_142)
      out_buf <= T_143
      skip
    node T_144 = and(io.wide.req_data.valid, io.wide.req_data.ready)
    when T_144 :
      out_buf <= io.wide.req_data.bits.data
      skip
    node T_145 = eq(state, UInt<1>("h00"))
    io.wide.req_cmd.ready <= T_145
    node T_146 = eq(state, UInt<2>("h03"))
    io.wide.req_data.ready <= T_146
    node T_147 = eq(state, UInt<1>("h01"))
    node T_148 = eq(state, UInt<2>("h02"))
    node T_149 = or(T_147, T_148)
    node T_150 = eq(state, UInt<3>("h04"))
    node T_151 = or(T_149, T_150)
    io.narrow.req.valid <= T_151
    io.narrow.req.bits <= out_buf
    node T_152 = eq(state, UInt<1>("h00"))
    node T_153 = and(T_152, io.wide.req_cmd.valid)
    when T_153 :
      node T_154 = mux(io.wide.req_cmd.bits.rw, UInt<2>("h02"), UInt<1>("h01"))
      state <= T_154
      skip
    node T_155 = eq(state, UInt<1>("h01"))
    node T_156 = and(T_155, adone)
    when T_156 :
      state <= UInt<1>("h00")
      send_cnt <= UInt<1>("h00")
      skip
    node T_158 = eq(state, UInt<2>("h02"))
    node T_159 = and(T_158, adone)
    when T_159 :
      state <= UInt<2>("h03")
      send_cnt <= UInt<1>("h00")
      skip
    node T_161 = eq(state, UInt<2>("h03"))
    node T_162 = and(T_161, io.wide.req_data.valid)
    when T_162 :
      state <= UInt<3>("h04")
      skip
    node T_163 = eq(state, UInt<3>("h04"))
    node T_164 = and(T_163, ddone)
    when T_164 :
      node T_166 = add(data_send_cnt, UInt<1>("h01"))
      node T_167 = tail(T_166, 1)
      data_send_cnt <= T_167
      node T_169 = eq(data_send_cnt, UInt<3>("h07"))
      node T_170 = mux(T_169, UInt<1>("h00"), UInt<2>("h03"))
      state <= T_170
      send_cnt <= UInt<1>("h00")
      skip
    reg recv_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg data_recv_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg resp_val : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    resp_val <= UInt<1>("h00")
    when io.narrow.resp.valid :
      node T_180 = add(recv_cnt, UInt<1>("h01"))
      node T_181 = tail(T_180, 1)
      recv_cnt <= T_181
      node T_183 = eq(recv_cnt, UInt<3>("h04"))
      when T_183 :
        recv_cnt <= UInt<1>("h00")
        node T_186 = add(data_recv_cnt, UInt<1>("h01"))
        node T_187 = tail(T_186, 1)
        data_recv_cnt <= T_187
        resp_val <= UInt<1>("h01")
        skip
      node T_189 = bits(in_buf, 79, 16)
      node T_190 = cat(io.narrow.resp.bits, T_189)
      in_buf <= T_190
      skip
    io.wide.resp.valid <= resp_val
    wire T_194 : {data : UInt<64>, tag : UInt<5>}
    T_194 is invalid
    node T_197 = bits(in_buf, 4, 0)
    T_194.tag <= T_197
    node T_198 = bits(in_buf, 68, 5)
    T_194.data <= T_198
    io.wide.resp.bits <- T_194
    
  module OuterMemorySystem : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, flip incoherent : UInt<1>[1], mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], mem_backup : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}, flip mem_backup_en : UInt<1>, csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[1], scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, deviceTree : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}
    
    io is invalid
    inst T_8064 of ClientTileLinkIOWrapper
    T_8064.io is invalid
    T_8064.clk <= clk
    T_8064.reset <= reset
    T_8064.io.in <- io.tiles_uncached[0]
    inst T_8065 of ClientTileLinkIOWrapper
    T_8065.io is invalid
    T_8065.clk <= clk
    T_8065.reset <= reset
    T_8065.io.in <- io.htif_uncached
    inst l1tol2net of RocketChipTileLinkArbiter
    l1tol2net.io is invalid
    l1tol2net.clk <= clk
    l1tol2net.reset <= reset
    inst T_8067 of L2BroadcastHub
    T_8067.io is invalid
    T_8067.clk <= clk
    T_8067.reset <= reset
    T_8067.io.incoherent <= io.incoherent
    l1tol2net.io.clients[0] <- io.tiles_cached[0]
    l1tol2net.io.clients[1] <- T_8064.io.out
    l1tol2net.io.clients[2] <- T_8065.io.out
    l1tol2net.io.managers[0] <- T_8067.io.inner
    inst interconnect of NastiRecursiveInterconnect
    interconnect.io is invalid
    interconnect.clk <= clk
    interconnect.reset <= reset
    inst T_8069 of ClientTileLinkIOUnwrapper
    T_8069.io is invalid
    T_8069.clk <= clk
    T_8069.reset <= reset
    inst T_8070 of TileLinkIONarrower
    T_8070.io is invalid
    T_8070.clk <= clk
    T_8070.reset <= reset
    inst T_8071 of NastiIOTileLinkIOConverter
    T_8071.io is invalid
    T_8071.clk <= clk
    T_8071.reset <= reset
    inst T_8072 of ClientTileLinkIOWrapper_71
    T_8072.io is invalid
    T_8072.clk <= clk
    T_8072.reset <= reset
    T_8072.io.in <- T_8067.io.outer
    inst T_8073 of ClientTileLinkEnqueuer
    T_8073.io is invalid
    T_8073.clk <= clk
    T_8073.reset <= reset
    T_8073.io.inner <- T_8072.io.out
    T_8069.io.in <- T_8073.io.outer
    T_8070.io.in <- T_8069.io.out
    T_8071.io.tl <- T_8070.io.out
    inst T_8086 of Queue_36
    T_8086.io is invalid
    T_8086.clk <= clk
    T_8086.reset <= reset
    T_8086.io.enq.valid <= T_8071.io.nasti.ar.valid
    T_8086.io.enq.bits <- T_8071.io.nasti.ar.bits
    T_8071.io.nasti.ar.ready <= T_8086.io.enq.ready
    interconnect.io.masters[0].ar <- T_8086.io.deq
    inst T_8099 of Queue_36
    T_8099.io is invalid
    T_8099.clk <= clk
    T_8099.reset <= reset
    T_8099.io.enq.valid <= T_8071.io.nasti.aw.valid
    T_8099.io.enq.bits <- T_8071.io.nasti.aw.bits
    T_8071.io.nasti.aw.ready <= T_8099.io.enq.ready
    interconnect.io.masters[0].aw <- T_8099.io.deq
    inst T_8105 of Queue_74
    T_8105.io is invalid
    T_8105.clk <= clk
    T_8105.reset <= reset
    T_8105.io.enq.valid <= T_8071.io.nasti.w.valid
    T_8105.io.enq.bits <- T_8071.io.nasti.w.bits
    T_8071.io.nasti.w.ready <= T_8105.io.enq.ready
    interconnect.io.masters[0].w <- T_8105.io.deq
    inst T_8112 of Queue_75
    T_8112.io is invalid
    T_8112.clk <= clk
    T_8112.reset <= reset
    T_8112.io.enq.valid <= interconnect.io.masters[0].r.valid
    T_8112.io.enq.bits <- interconnect.io.masters[0].r.bits
    interconnect.io.masters[0].r.ready <= T_8112.io.enq.ready
    T_8071.io.nasti.r <- T_8112.io.deq
    inst T_8117 of Queue_76
    T_8117.io is invalid
    T_8117.clk <= clk
    T_8117.reset <= reset
    T_8117.io.enq.valid <= interconnect.io.masters[0].b.valid
    T_8117.io.enq.bits <- interconnect.io.masters[0].b.bits
    interconnect.io.masters[0].b.ready <= T_8117.io.enq.ready
    T_8071.io.nasti.b <- T_8117.io.deq
    inst rtc of RTC
    rtc.io is invalid
    rtc.clk <= clk
    rtc.reset <= reset
    interconnect.io.masters[1] <- rtc.io
    inst T_8119 of SmiIONastiIOConverter
    T_8119.io is invalid
    T_8119.clk <= clk
    T_8119.reset <= reset
    T_8119.io.nasti <- interconnect.io.slaves[2]
    io.csr[0] <- T_8119.io.smi
    inst src_conv of SmiIONastiIOConverter_78
    src_conv.io is invalid
    src_conv.clk <= clk
    src_conv.reset <= reset
    src_conv.io.nasti <- interconnect.io.slaves[3]
    io.scr <- src_conv.io.smi
    io.mmio <- interconnect.io.slaves[4]
    io.deviceTree <- interconnect.io.slaves[1]
    inst T_8121 of NastiArbiter_83
    T_8121.io is invalid
    T_8121.clk <= clk
    T_8121.reset <= reset
    inst T_8122 of MemIONastiIOConverter
    T_8122.io is invalid
    T_8122.clk <= clk
    T_8122.reset <= reset
    inst T_8123 of MemSerdes
    T_8123.io is invalid
    T_8123.clk <= clk
    T_8123.reset <= reset
    T_8122.io.nasti <- T_8121.io.slave
    T_8123.io.wide <- T_8122.io.mem
    io.mem_backup <- T_8123.io.narrow
    node T_8124 = mux(io.mem_backup_en, T_8121.io.master[0].ar.ready, io.mem[0].ar.ready)
    interconnect.io.slaves[0].ar.ready <= T_8124
    node T_8126 = eq(io.mem_backup_en, UInt<1>("h00"))
    node T_8127 = and(interconnect.io.slaves[0].ar.valid, T_8126)
    io.mem[0].ar.valid <= T_8127
    io.mem[0].ar.bits <- interconnect.io.slaves[0].ar.bits
    node T_8128 = and(interconnect.io.slaves[0].ar.valid, io.mem_backup_en)
    T_8121.io.master[0].ar.valid <= T_8128
    T_8121.io.master[0].ar.bits <- interconnect.io.slaves[0].ar.bits
    node T_8129 = mux(io.mem_backup_en, T_8121.io.master[0].aw.ready, io.mem[0].aw.ready)
    interconnect.io.slaves[0].aw.ready <= T_8129
    node T_8131 = eq(io.mem_backup_en, UInt<1>("h00"))
    node T_8132 = and(interconnect.io.slaves[0].aw.valid, T_8131)
    io.mem[0].aw.valid <= T_8132
    io.mem[0].aw.bits <- interconnect.io.slaves[0].aw.bits
    node T_8133 = and(interconnect.io.slaves[0].aw.valid, io.mem_backup_en)
    T_8121.io.master[0].aw.valid <= T_8133
    T_8121.io.master[0].aw.bits <- interconnect.io.slaves[0].aw.bits
    node T_8134 = mux(io.mem_backup_en, T_8121.io.master[0].w.ready, io.mem[0].w.ready)
    interconnect.io.slaves[0].w.ready <= T_8134
    node T_8136 = eq(io.mem_backup_en, UInt<1>("h00"))
    node T_8137 = and(interconnect.io.slaves[0].w.valid, T_8136)
    io.mem[0].w.valid <= T_8137
    io.mem[0].w.bits <- interconnect.io.slaves[0].w.bits
    node T_8138 = and(interconnect.io.slaves[0].w.valid, io.mem_backup_en)
    T_8121.io.master[0].w.valid <= T_8138
    T_8121.io.master[0].w.bits <- interconnect.io.slaves[0].w.bits
    node T_8139 = mux(io.mem_backup_en, T_8121.io.master[0].b.valid, io.mem[0].b.valid)
    interconnect.io.slaves[0].b.valid <= T_8139
    node T_8140 = mux(io.mem_backup_en, T_8121.io.master[0].b.bits, io.mem[0].b.bits)
    interconnect.io.slaves[0].b.bits <- T_8140
    node T_8145 = eq(io.mem_backup_en, UInt<1>("h00"))
    node T_8146 = and(interconnect.io.slaves[0].b.ready, T_8145)
    io.mem[0].b.ready <= T_8146
    node T_8147 = and(interconnect.io.slaves[0].b.ready, io.mem_backup_en)
    T_8121.io.master[0].b.ready <= T_8147
    node T_8148 = mux(io.mem_backup_en, T_8121.io.master[0].r.valid, io.mem[0].r.valid)
    interconnect.io.slaves[0].r.valid <= T_8148
    node T_8149 = mux(io.mem_backup_en, T_8121.io.master[0].r.bits, io.mem[0].r.bits)
    interconnect.io.slaves[0].r.bits <- T_8149
    node T_8156 = eq(io.mem_backup_en, UInt<1>("h00"))
    node T_8157 = and(interconnect.io.slaves[0].r.ready, T_8156)
    io.mem[0].r.ready <= T_8157
    node T_8158 = and(interconnect.io.slaves[0].r.ready, io.mem_backup_en)
    T_8121.io.master[0].r.ready <= T_8158
    
  module SCRFile : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>}}
    
    io is invalid
    wire scr_rdata : UInt<64>[64]
    scr_rdata is invalid
    scr_rdata[0] <= io.scr.rdata[0]
    scr_rdata[1] <= io.scr.rdata[1]
    scr_rdata[2] <= io.scr.rdata[2]
    scr_rdata[3] <= io.scr.rdata[3]
    scr_rdata[4] <= io.scr.rdata[4]
    scr_rdata[5] <= io.scr.rdata[5]
    scr_rdata[6] <= io.scr.rdata[6]
    scr_rdata[7] <= io.scr.rdata[7]
    scr_rdata[8] <= io.scr.rdata[8]
    scr_rdata[9] <= io.scr.rdata[9]
    scr_rdata[10] <= io.scr.rdata[10]
    scr_rdata[11] <= io.scr.rdata[11]
    scr_rdata[12] <= io.scr.rdata[12]
    scr_rdata[13] <= io.scr.rdata[13]
    scr_rdata[14] <= io.scr.rdata[14]
    scr_rdata[15] <= io.scr.rdata[15]
    scr_rdata[16] <= io.scr.rdata[16]
    scr_rdata[17] <= io.scr.rdata[17]
    scr_rdata[18] <= io.scr.rdata[18]
    scr_rdata[19] <= io.scr.rdata[19]
    scr_rdata[20] <= io.scr.rdata[20]
    scr_rdata[21] <= io.scr.rdata[21]
    scr_rdata[22] <= io.scr.rdata[22]
    scr_rdata[23] <= io.scr.rdata[23]
    scr_rdata[24] <= io.scr.rdata[24]
    scr_rdata[25] <= io.scr.rdata[25]
    scr_rdata[26] <= io.scr.rdata[26]
    scr_rdata[27] <= io.scr.rdata[27]
    scr_rdata[28] <= io.scr.rdata[28]
    scr_rdata[29] <= io.scr.rdata[29]
    scr_rdata[30] <= io.scr.rdata[30]
    scr_rdata[31] <= io.scr.rdata[31]
    scr_rdata[32] <= io.scr.rdata[32]
    scr_rdata[33] <= io.scr.rdata[33]
    scr_rdata[34] <= io.scr.rdata[34]
    scr_rdata[35] <= io.scr.rdata[35]
    scr_rdata[36] <= io.scr.rdata[36]
    scr_rdata[37] <= io.scr.rdata[37]
    scr_rdata[38] <= io.scr.rdata[38]
    scr_rdata[39] <= io.scr.rdata[39]
    scr_rdata[40] <= io.scr.rdata[40]
    scr_rdata[41] <= io.scr.rdata[41]
    scr_rdata[42] <= io.scr.rdata[42]
    scr_rdata[43] <= io.scr.rdata[43]
    scr_rdata[44] <= io.scr.rdata[44]
    scr_rdata[45] <= io.scr.rdata[45]
    scr_rdata[46] <= io.scr.rdata[46]
    scr_rdata[47] <= io.scr.rdata[47]
    scr_rdata[48] <= io.scr.rdata[48]
    scr_rdata[49] <= io.scr.rdata[49]
    scr_rdata[50] <= io.scr.rdata[50]
    scr_rdata[51] <= io.scr.rdata[51]
    scr_rdata[52] <= io.scr.rdata[52]
    scr_rdata[53] <= io.scr.rdata[53]
    scr_rdata[54] <= io.scr.rdata[54]
    scr_rdata[55] <= io.scr.rdata[55]
    scr_rdata[56] <= io.scr.rdata[56]
    scr_rdata[57] <= io.scr.rdata[57]
    scr_rdata[58] <= io.scr.rdata[58]
    scr_rdata[59] <= io.scr.rdata[59]
    scr_rdata[60] <= io.scr.rdata[60]
    scr_rdata[61] <= io.scr.rdata[61]
    scr_rdata[62] <= io.scr.rdata[62]
    scr_rdata[63] <= io.scr.rdata[63]
    scr_rdata[0] <= UInt<1>("h01")
    scr_rdata[1] <= UInt<11>("h0400")
    reg read_addr : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    reg resp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_365 = eq(resp_valid, UInt<1>("h00"))
    io.smi.req.ready <= T_365
    io.smi.resp.valid <= resp_valid
    io.smi.resp.bits <= scr_rdata[read_addr]
    node T_367 = and(io.smi.req.ready, io.smi.req.valid)
    node T_368 = and(T_367, io.smi.req.bits.rw)
    io.scr.wen <= T_368
    io.scr.wdata <= io.smi.req.bits.data
    io.scr.waddr <= io.smi.req.bits.addr
    node T_369 = and(io.smi.req.ready, io.smi.req.valid)
    when T_369 :
      read_addr <= io.smi.req.bits.addr
      resp_valid <= UInt<1>("h01")
      skip
    node T_371 = and(io.smi.resp.ready, io.smi.resp.valid)
    when T_371 :
      resp_valid <= UInt<1>("h00")
      skip
    
  module Queue_89 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>}
    
    io is invalid
    cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[1]
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_130 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_130)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_136 = and(io.enq.ready, io.enq.valid)
    node T_138 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_136, T_138)
    node T_140 = and(io.deq.ready, io.deq.valid)
    node T_142 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_140, T_142)
    when do_enq :
      infer mport T_144 = ram[UInt<1>("h00")], clk
      T_144 <- io.enq.bits
      skip
    when do_deq :
      skip
    node T_158 = neq(do_enq, do_deq)
    when T_158 :
      maybe_full <= do_enq
      skip
    node T_160 = eq(empty, UInt<1>("h00"))
    node T_162 = and(UInt<1>("h00"), io.enq.valid)
    node T_163 = or(T_160, T_162)
    io.deq.valid <= T_163
    node T_165 = eq(full, UInt<1>("h00"))
    node T_167 = and(UInt<1>("h00"), io.deq.ready)
    node T_168 = or(T_165, T_167)
    io.enq.ready <= T_168
    infer mport T_169 = ram[UInt<1>("h00")], clk
    node T_181 = mux(maybe_flow, io.enq.bits, T_169)
    io.deq.bits <- T_181
    node T_193 = sub(UInt<1>("h00"), UInt<1>("h00"))
    node ptr_diff = tail(T_193, 1)
    node T_195 = and(maybe_full, ptr_match)
    node T_196 = cat(T_195, ptr_diff)
    io.count <= T_196
    
  module NastiROM : 
    input clk : Clock
    input reset : UInt<1>
    input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}
    
    io is invalid
    inst T_334 of Queue_89
    T_334.io is invalid
    T_334.clk <= clk
    T_334.reset <= reset
    T_334.io.enq.valid <= io.ar.valid
    T_334.io.enq.bits <- io.ar.bits
    io.ar.ready <= T_334.io.enq.ready
    when T_334.io.deq.valid :
      node T_336 = eq(T_334.io.deq.bits.len, UInt<1>("h00"))
      node T_338 = eq(reset, UInt<1>("h00"))
      when T_338 :
        node T_340 = eq(T_336, UInt<1>("h00"))
        when T_340 :
          node T_342 = eq(reset, UInt<1>("h00"))
          when T_342 :
            printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't burst-read from NastiROM")
            skip
          stop(clk, UInt<1>(1), 1)
          skip
        skip
      skip
    node T_343 = or(io.aw.valid, io.w.valid)
    node T_345 = eq(T_343, UInt<1>("h00"))
    node T_347 = eq(reset, UInt<1>("h00"))
    when T_347 :
      node T_349 = eq(T_345, UInt<1>("h00"))
      when T_349 :
        node T_351 = eq(reset, UInt<1>("h00"))
        when T_351 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't write to NastiROM")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    io.aw.ready <= UInt<1>("h00")
    io.w.ready <= UInt<1>("h00")
    io.b.valid <= UInt<1>("h00")
    wire rom : UInt<64>[67]
    rom[0] <= UInt<60>("h0b020000edfe0dd0")
    rom[1] <= UInt<64>("h0c001000038000000")
    rom[2] <= UInt<61>("h01100000028000000")
    rom[3] <= UInt<29>("h010000000")
    rom[4] <= UInt<64>("h0880100004b000000")
    rom[5] <= UInt<1>("h00")
    rom[6] <= UInt<1>("h00")
    rom[7] <= UInt<25>("h01000000")
    rom[8] <= UInt<59>("h0400000003000000")
    rom[9] <= UInt<58>("h0200000000000000")
    rom[10] <= UInt<59>("h0400000003000000")
    rom[11] <= UInt<58>("h020000000f000000")
    rom[12] <= UInt<60>("h0c00000003000000")
    rom[13] <= UInt<63>("h06b636f521b000000")
    rom[14] <= UInt<55>("h0706968432d7465")
    rom[15] <= UInt<63>("h06f6d656d01000000")
    rom[16] <= UInt<30>("h030407972")
    rom[17] <= UInt<59>("h0700000003000000")
    rom[18] <= UInt<63>("h06f6d656d21000000")
    rom[19] <= UInt<58>("h0300000000007972")
    rom[20] <= UInt<62>("h02d00000010000000")
    rom[21] <= UInt<1>("h00")
    rom[22] <= UInt<39>("h04000000000")
    rom[23] <= UInt<57>("h0100000002000000")
    rom[24] <= UInt<31>("h073757063")
    rom[25] <= UInt<59>("h0400000003000000")
    rom[26] <= UInt<58>("h0200000000000000")
    rom[27] <= UInt<59>("h0400000003000000")
    rom[28] <= UInt<58>("h020000000f000000")
    rom[29] <= UInt<63>("h04075706301000000")
    rom[30] <= UInt<62>("h03030303830303034")
    rom[31] <= UInt<58>("h0300000000000000")
    rom[32] <= UInt<62>("h02100000004000000")
    rom[33] <= UInt<58>("h0300000000757063")
    rom[34] <= UInt<62>("h03100000006000000")
    rom[35] <= UInt<39>("h07663736972")
    rom[36] <= UInt<59>("h0500000003000000")
    rom[37] <= UInt<62>("h0343676723c000000")
    rom[38] <= UInt<58>("h0300000000000000")
    rom[39] <= UInt<62>("h02d00000008000000")
    rom[40] <= UInt<56>("h080004000000000")
    rom[41] <= UInt<58>("h0200000002000000")
    rom[42] <= UInt<63>("h04072637301000000")
    rom[43] <= UInt<62>("h03030303031303034")
    rom[44] <= UInt<58>("h0300000000000000")
    rom[45] <= UInt<62>("h02100000004000000")
    rom[46] <= UInt<58>("h0300000000726373")
    rom[47] <= UInt<62>("h03100000006000000")
    rom[48] <= UInt<39>("h07663736972")
    rom[49] <= UInt<59>("h0400000003000000")
    rom[50] <= UInt<58>("h0300000040000000")
    rom[51] <= UInt<61>("h01000000003000000")
    rom[52] <= UInt<30>("h02d000000")
    rom[53] <= UInt<9>("h0140")
    rom[54] <= UInt<58>("h0200000000020000")
    rom[55] <= UInt<60>("h0900000002000000")
    rom[56] <= UInt<63>("h07373657264646123")
    rom[57] <= UInt<62>("h02300736c6c65632d")
    rom[58] <= UInt<63>("h06c65632d657a6973")
    rom[59] <= UInt<63>("h06c65646f6d00736c")
    rom[60] <= UInt<63>("h05f65636976656400")
    rom[61] <= UInt<63>("h06765720065707974")
    rom[62] <= UInt<63>("h0697461706d6f6300")
    rom[63] <= UInt<55>("h061736900656c62")
    rom[64] <= UInt<63>("h069746365746f7270")
    rom[65] <= UInt<15>("h06e6f")
    rom[66] <= UInt<1>("h00")
    node T_492 = bits(T_334.io.deq.bits.addr, 9, 3)
    node T_495 = cat(UInt<1>("h01"), T_334.io.deq.bits.size)
    node T_497 = bits(T_495, 1, 0)
    node T_498 = asSInt(T_495)
    node T_500 = geq(T_498, asSInt(UInt<1>("h00")))
    node T_501 = bits(T_334.io.deq.bits.addr, 2, 2)
    node T_502 = bits(rom[T_492], 63, 32)
    node T_503 = bits(rom[T_492], 31, 0)
    node T_504 = mux(T_501, T_502, T_503)
    node T_506 = and(UInt<1>("h00"), UInt<1>("h00"))
    node T_508 = mux(T_506, UInt<1>("h00"), T_504)
    node T_510 = eq(T_497, UInt<2>("h02"))
    node T_511 = or(T_510, T_506)
    node T_512 = bits(T_508, 31, 31)
    node T_513 = and(T_500, T_512)
    node T_515 = sub(UInt<32>("h00"), T_513)
    node T_516 = tail(T_515, 1)
    node T_517 = bits(rom[T_492], 63, 32)
    node T_518 = mux(T_511, T_516, T_517)
    node T_519 = cat(T_518, T_508)
    node T_520 = bits(T_334.io.deq.bits.addr, 1, 1)
    node T_521 = bits(T_519, 31, 16)
    node T_522 = bits(T_519, 15, 0)
    node T_523 = mux(T_520, T_521, T_522)
    node T_525 = and(UInt<1>("h00"), UInt<1>("h00"))
    node T_527 = mux(T_525, UInt<1>("h00"), T_523)
    node T_529 = eq(T_497, UInt<1>("h01"))
    node T_530 = or(T_529, T_525)
    node T_531 = bits(T_527, 15, 15)
    node T_532 = and(T_500, T_531)
    node T_534 = sub(UInt<48>("h00"), T_532)
    node T_535 = tail(T_534, 1)
    node T_536 = bits(T_519, 63, 16)
    node T_537 = mux(T_530, T_535, T_536)
    node T_538 = cat(T_537, T_527)
    node T_539 = bits(T_334.io.deq.bits.addr, 0, 0)
    node T_540 = bits(T_538, 15, 8)
    node T_541 = bits(T_538, 7, 0)
    node T_542 = mux(T_539, T_540, T_541)
    node T_544 = and(UInt<1>("h01"), UInt<1>("h00"))
    node T_546 = mux(T_544, UInt<1>("h00"), T_542)
    node T_548 = eq(T_497, UInt<1>("h00"))
    node T_549 = or(T_548, T_544)
    node T_550 = bits(T_546, 7, 7)
    node T_551 = and(T_500, T_550)
    node T_553 = sub(UInt<56>("h00"), T_551)
    node T_554 = tail(T_553, 1)
    node T_555 = bits(T_538, 63, 8)
    node T_556 = mux(T_549, T_554, T_555)
    node rdata = cat(T_556, T_546)
    io.r <- T_334.io.deq
    wire T_566 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}
    T_566 is invalid
    T_566.id <= T_334.io.deq.bits.id
    T_566.data <= rdata
    T_566.last <= UInt<1>("h01")
    T_566.resp <= UInt<1>("h00")
    T_566.user <= UInt<1>("h00")
    io.r.bits <- T_566
    
  module Queue_90 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, count : UInt<1>}
    
    io is invalid
    cmem ram : UInt<17>[1]
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_31 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_31)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_37 = and(io.enq.ready, io.enq.valid)
    node T_39 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_37, T_39)
    node T_41 = and(io.deq.ready, io.deq.valid)
    node T_43 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_41, T_43)
    when do_enq :
      infer mport T_45 = ram[UInt<1>("h00")], clk
      T_45 <= io.enq.bits
      skip
    when do_deq :
      skip
    node T_48 = neq(do_enq, do_deq)
    when T_48 :
      maybe_full <= do_enq
      skip
    node T_50 = eq(empty, UInt<1>("h00"))
    node T_52 = and(UInt<1>("h00"), io.enq.valid)
    node T_53 = or(T_50, T_52)
    io.deq.valid <= T_53
    node T_55 = eq(full, UInt<1>("h00"))
    node T_57 = and(UInt<1>("h00"), io.deq.ready)
    node T_58 = or(T_55, T_57)
    io.enq.ready <= T_58
    infer mport T_59 = ram[UInt<1>("h00")], clk
    node T_60 = mux(maybe_flow, io.enq.bits, T_59)
    io.deq.bits <= T_60
    node T_61 = sub(UInt<1>("h00"), UInt<1>("h00"))
    node ptr_diff = tail(T_61, 1)
    node T_63 = and(maybe_full, ptr_match)
    node T_64 = cat(T_63, ptr_diff)
    io.count <= T_64
    
  module SlowIO : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, flip in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, clk_slow : UInt<1>, flip set_divisor : {valid : UInt<1>, bits : UInt<32>}, divisor : UInt<32>}
    
    io is invalid
    reg divisor : UInt, clk with : (reset => (reset, UInt<9>("h01ff")))
    reg d_shadow : UInt, clk with : (reset => (reset, UInt<9>("h01ff")))
    reg hold : UInt, clk with : (reset => (reset, UInt<7>("h07f")))
    reg h_shadow : UInt, clk with : (reset => (reset, UInt<7>("h07f")))
    when io.set_divisor.valid :
      node T_57 = bits(io.set_divisor.bits, 8, 0)
      d_shadow <= T_57
      node T_58 = bits(io.set_divisor.bits, 24, 16)
      h_shadow <= T_58
      skip
    node T_59 = shl(hold, 16)
    node T_60 = or(T_59, divisor)
    io.divisor <= T_60
    reg count : UInt<9>, clk
    reg myclock : UInt<1>, clk
    node T_66 = add(count, UInt<1>("h01"))
    node T_67 = tail(T_66, 1)
    count <= T_67
    node T_68 = shr(divisor, 1)
    node rising = eq(count, T_68)
    node falling = eq(count, divisor)
    node T_71 = shr(divisor, 1)
    node T_72 = add(T_71, hold)
    node T_73 = tail(T_72, 1)
    node held = eq(count, T_73)
    when falling :
      divisor <= d_shadow
      hold <= h_shadow
      count <= UInt<1>("h00")
      myclock <= UInt<1>("h00")
      skip
    when rising :
      myclock <= UInt<1>("h01")
      skip
    reg in_slow_rdy : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg out_slow_val : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg out_slow_bits : UInt<17>, clk
    inst fromhost_q of Queue_90
    fromhost_q.io is invalid
    fromhost_q.clk <= clk
    fromhost_q.reset <= reset
    node T_86 = and(io.in_slow.valid, in_slow_rdy)
    node T_87 = or(T_86, reset)
    node T_88 = and(rising, T_87)
    fromhost_q.io.enq.valid <= T_88
    fromhost_q.io.enq.bits <= io.in_slow.bits
    io.in_fast <- fromhost_q.io.deq
    inst tohost_q of Queue_90
    tohost_q.io is invalid
    tohost_q.clk <= clk
    tohost_q.reset <= reset
    tohost_q.io.enq <- io.out_fast
    node T_91 = and(rising, io.out_slow.ready)
    node T_92 = and(T_91, out_slow_val)
    tohost_q.io.deq.ready <= T_92
    when held :
      in_slow_rdy <= fromhost_q.io.enq.ready
      out_slow_val <= tohost_q.io.deq.valid
      node T_93 = mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
      out_slow_bits <= T_93
      skip
    io.in_slow.ready <= in_slow_rdy
    io.out_slow.valid <= out_slow_val
    io.out_slow.bits <= out_slow_bits
    io.clk_slow <= myclock
    
  module Uncore : 
    input clk : Clock
    input reset : UInt<1>
    output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}[1]}
    
    io is invalid
    inst htif of Htif
    htif.io is invalid
    htif.clk <= clk
    htif.reset <= reset
    inst outmemsys of OuterMemorySystem
    outmemsys.io is invalid
    outmemsys.clk <= clk
    outmemsys.reset <= reset
    outmemsys.io.incoherent[0] <= htif.io.cpu[0].reset
    outmemsys.io.htif_uncached <- htif.io.mem
    outmemsys.io.tiles_uncached <= io.tiles_uncached
    outmemsys.io.tiles_cached <= io.tiles_cached
    io.htif[0].reset <= htif.io.cpu[0].reset
    io.htif[0].id <= htif.io.cpu[0].id
    htif.io.cpu[0].debug_stats_csr <= io.htif[0].debug_stats_csr
    inst T_8362 of SmiArbiter
    T_8362.io is invalid
    T_8362.clk <= clk
    T_8362.reset <= reset
    T_8362.io.in[0] <- htif.io.cpu[0].csr
    T_8362.io.in[1] <- outmemsys.io.csr[0]
    io.htif[0].csr <- T_8362.io.out
    inst scrFile of SCRFile
    scrFile.io is invalid
    scrFile.clk <= clk
    scrFile.reset <= reset
    inst scrArb of SmiArbiter_81
    scrArb.io is invalid
    scrArb.clk <= clk
    scrArb.reset <= reset
    scrArb.io.in[0] <- htif.io.scr
    scrArb.io.in[1] <- outmemsys.io.scr
    scrFile.io.smi <- scrArb.io.out
    inst deviceTree of NastiROM
    deviceTree.io is invalid
    deviceTree.clk <= clk
    deviceTree.reset <= reset
    deviceTree.io <- outmemsys.io.deviceTree
    io.host.debug_stats_csr <= htif.io.host.debug_stats_csr
    io.mem <= outmemsys.io.mem
    io.mmio <- outmemsys.io.mmio
    outmemsys.io.mem_backup_en <= io.mem_backup_ctrl.en
    inst T_8366 of SlowIO
    T_8366.io is invalid
    T_8366.clk <= clk
    T_8366.reset <= reset
    node T_8368 = eq(scrFile.io.scr.waddr, UInt<6>("h03f"))
    node T_8369 = and(scrFile.io.scr.wen, T_8368)
    T_8366.io.set_divisor.valid <= T_8369
    T_8366.io.set_divisor.bits <= scrFile.io.scr.wdata
    scrFile.io.scr.rdata[63] <= T_8366.io.divisor
    node T_8370 = or(htif.io.host.out.valid, outmemsys.io.mem_backup.req.valid)
    T_8366.io.out_fast.valid <= T_8370
    node T_8371 = mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits)
    node T_8372 = cat(htif.io.host.out.valid, T_8371)
    T_8366.io.out_fast.bits <= T_8372
    htif.io.host.out.ready <= T_8366.io.out_fast.ready
    node T_8374 = eq(htif.io.host.out.valid, UInt<1>("h00"))
    node T_8375 = and(T_8366.io.out_fast.ready, T_8374)
    outmemsys.io.mem_backup.req.ready <= T_8375
    node T_8376 = bits(T_8366.io.out_slow.bits, 16, 16)
    node T_8377 = and(T_8366.io.out_slow.valid, T_8376)
    io.host.out.valid <= T_8377
    io.host.out.bits <= T_8366.io.out_slow.bits
    node T_8378 = bits(T_8366.io.out_slow.bits, 16, 16)
    node T_8380 = eq(T_8378, UInt<1>("h00"))
    node T_8381 = and(T_8366.io.out_slow.valid, T_8380)
    io.mem_backup_ctrl.out_valid <= T_8381
    node T_8382 = bits(T_8366.io.out_slow.bits, 16, 16)
    node T_8383 = mux(T_8382, io.host.out.ready, io.mem_backup_ctrl.out_ready)
    T_8366.io.out_slow.ready <= T_8383
    node T_8384 = and(io.mem_backup_ctrl.en, io.mem_backup_ctrl.in_valid)
    node T_8385 = or(T_8384, io.host.in.valid)
    T_8366.io.in_slow.valid <= T_8385
    node T_8386 = cat(T_8384, io.host.in.bits)
    T_8366.io.in_slow.bits <= T_8386
    io.host.in.ready <= T_8366.io.in_slow.ready
    node T_8387 = bits(T_8366.io.in_fast.bits, 16, 16)
    node T_8388 = and(T_8366.io.in_fast.valid, T_8387)
    outmemsys.io.mem_backup.resp.valid <= T_8388
    outmemsys.io.mem_backup.resp.bits <= T_8366.io.in_fast.bits
    node T_8389 = bits(T_8366.io.in_fast.bits, 16, 16)
    node T_8391 = eq(T_8389, UInt<1>("h00"))
    node T_8392 = and(T_8366.io.in_fast.valid, T_8391)
    htif.io.host.in.valid <= T_8392
    htif.io.host.in.bits <= T_8366.io.in_fast.bits
    node T_8393 = bits(T_8366.io.in_fast.bits, 16, 16)
    node T_8395 = mux(T_8393, UInt<1>("h01"), htif.io.host.in.ready)
    T_8366.io.in_fast.ready <= T_8395
    io.host.clk <= T_8366.io.clk_slow
    reg T_8396 : UInt<1>, clk
    T_8396 <= io.host.clk
    node T_8398 = eq(T_8396, UInt<1>("h00"))
    node T_8399 = and(io.host.clk, T_8398)
    reg T_8400 : UInt<1>, clk
    T_8400 <= T_8399
    io.host.clk_edge <= T_8400
    
  module CSRFile : 
    input clk : Clock
    input reset : UInt<1>
    output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, csr_stall : UInt<1>, csr_xcpt : UInt<1>, eret : UInt<1>, status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, ptbr : UInt<32>, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip uarch_counters : UInt<1>[16], flip custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}, interrupt : UInt<1>, interrupt_cause : UInt<64>}
    
    io is invalid
    reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clk
    wire T_4480 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_4480 is invalid
    T_4480.usip <= UInt<1>("h00")
    T_4480.ssip <= UInt<1>("h00")
    T_4480.hsip <= UInt<1>("h00")
    T_4480.msip <= UInt<1>("h00")
    T_4480.utip <= UInt<1>("h00")
    T_4480.stip <= UInt<1>("h00")
    T_4480.htip <= UInt<1>("h00")
    T_4480.mtip <= UInt<1>("h00")
    reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : (reset => (reset, T_4480))
    wire T_4525 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_4525 is invalid
    T_4525.usip <= UInt<1>("h00")
    T_4525.ssip <= UInt<1>("h00")
    T_4525.hsip <= UInt<1>("h00")
    T_4525.msip <= UInt<1>("h00")
    T_4525.utip <= UInt<1>("h00")
    T_4525.stip <= UInt<1>("h00")
    T_4525.htip <= UInt<1>("h00")
    T_4525.mtip <= UInt<1>("h00")
    reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : (reset => (reset, T_4525))
    reg reg_mepc : UInt<40>, clk
    reg reg_mcause : UInt<64>, clk
    reg reg_mbadaddr : UInt<40>, clk
    reg reg_mscratch : UInt<64>, clk
    reg reg_sepc : UInt<40>, clk
    reg reg_scause : UInt<64>, clk
    reg reg_sbadaddr : UInt<40>, clk
    reg reg_sscratch : UInt<64>, clk
    reg reg_stvec : UInt<39>, clk
    reg reg_mtimecmp : UInt<64>, clk
    reg reg_sptbr : UInt<32>, clk
    reg reg_wfi : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg reg_tohost : UInt<64>, clk with : (reset => (reset, UInt<64>("h00")))
    reg reg_fromhost : UInt<64>, clk with : (reset => (reset, UInt<64>("h00")))
    reg reg_stats : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg reg_time : UInt<64>, clk
    reg T_4584 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4586 = neq(io.retire, UInt<1>("h00"))
    node T_4588 = add(T_4584, UInt<7>("h01"))
    node T_4589 = tail(T_4588, 1)
    when T_4586 :
      node T_4590 = bits(T_4589, 5, 0)
      T_4584 <= T_4590
      skip
    reg T_4592 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4593 = bits(T_4589, 6, 6)
    node T_4594 = and(T_4586, T_4593)
    when T_4594 :
      node T_4596 = add(T_4592, UInt<1>("h01"))
      node T_4597 = tail(T_4596, 1)
      T_4592 <= T_4597
      skip
    node T_4598 = cat(T_4592, T_4584)
    reg T_4601 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4603 = neq(UInt<1>("h01"), UInt<1>("h00"))
    node T_4605 = add(T_4601, UInt<7>("h01"))
    node T_4606 = tail(T_4605, 1)
    when T_4603 :
      node T_4607 = bits(T_4606, 5, 0)
      T_4601 <= T_4607
      skip
    reg T_4609 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4610 = bits(T_4606, 6, 6)
    node T_4611 = and(T_4603, T_4610)
    when T_4611 :
      node T_4613 = add(T_4609, UInt<1>("h01"))
      node T_4614 = tail(T_4613, 1)
      T_4609 <= T_4614
      skip
    node T_4615 = cat(T_4609, T_4601)
    reg T_4617 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4619 = neq(io.uarch_counters[0], UInt<1>("h00"))
    node T_4621 = add(T_4617, UInt<7>("h01"))
    node T_4622 = tail(T_4621, 1)
    when T_4619 :
      node T_4623 = bits(T_4622, 5, 0)
      T_4617 <= T_4623
      skip
    reg T_4625 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4626 = bits(T_4622, 6, 6)
    node T_4627 = and(T_4619, T_4626)
    when T_4627 :
      node T_4629 = add(T_4625, UInt<1>("h01"))
      node T_4630 = tail(T_4629, 1)
      T_4625 <= T_4630
      skip
    node T_4631 = cat(T_4625, T_4617)
    reg T_4633 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4635 = neq(io.uarch_counters[1], UInt<1>("h00"))
    node T_4637 = add(T_4633, UInt<7>("h01"))
    node T_4638 = tail(T_4637, 1)
    when T_4635 :
      node T_4639 = bits(T_4638, 5, 0)
      T_4633 <= T_4639
      skip
    reg T_4641 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4642 = bits(T_4638, 6, 6)
    node T_4643 = and(T_4635, T_4642)
    when T_4643 :
      node T_4645 = add(T_4641, UInt<1>("h01"))
      node T_4646 = tail(T_4645, 1)
      T_4641 <= T_4646
      skip
    node T_4647 = cat(T_4641, T_4633)
    reg T_4649 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4651 = neq(io.uarch_counters[2], UInt<1>("h00"))
    node T_4653 = add(T_4649, UInt<7>("h01"))
    node T_4654 = tail(T_4653, 1)
    when T_4651 :
      node T_4655 = bits(T_4654, 5, 0)
      T_4649 <= T_4655
      skip
    reg T_4657 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4658 = bits(T_4654, 6, 6)
    node T_4659 = and(T_4651, T_4658)
    when T_4659 :
      node T_4661 = add(T_4657, UInt<1>("h01"))
      node T_4662 = tail(T_4661, 1)
      T_4657 <= T_4662
      skip
    node T_4663 = cat(T_4657, T_4649)
    reg T_4665 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4667 = neq(io.uarch_counters[3], UInt<1>("h00"))
    node T_4669 = add(T_4665, UInt<7>("h01"))
    node T_4670 = tail(T_4669, 1)
    when T_4667 :
      node T_4671 = bits(T_4670, 5, 0)
      T_4665 <= T_4671
      skip
    reg T_4673 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4674 = bits(T_4670, 6, 6)
    node T_4675 = and(T_4667, T_4674)
    when T_4675 :
      node T_4677 = add(T_4673, UInt<1>("h01"))
      node T_4678 = tail(T_4677, 1)
      T_4673 <= T_4678
      skip
    node T_4679 = cat(T_4673, T_4665)
    reg T_4681 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4683 = neq(io.uarch_counters[4], UInt<1>("h00"))
    node T_4685 = add(T_4681, UInt<7>("h01"))
    node T_4686 = tail(T_4685, 1)
    when T_4683 :
      node T_4687 = bits(T_4686, 5, 0)
      T_4681 <= T_4687
      skip
    reg T_4689 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4690 = bits(T_4686, 6, 6)
    node T_4691 = and(T_4683, T_4690)
    when T_4691 :
      node T_4693 = add(T_4689, UInt<1>("h01"))
      node T_4694 = tail(T_4693, 1)
      T_4689 <= T_4694
      skip
    node T_4695 = cat(T_4689, T_4681)
    reg T_4697 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4699 = neq(io.uarch_counters[5], UInt<1>("h00"))
    node T_4701 = add(T_4697, UInt<7>("h01"))
    node T_4702 = tail(T_4701, 1)
    when T_4699 :
      node T_4703 = bits(T_4702, 5, 0)
      T_4697 <= T_4703
      skip
    reg T_4705 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4706 = bits(T_4702, 6, 6)
    node T_4707 = and(T_4699, T_4706)
    when T_4707 :
      node T_4709 = add(T_4705, UInt<1>("h01"))
      node T_4710 = tail(T_4709, 1)
      T_4705 <= T_4710
      skip
    node T_4711 = cat(T_4705, T_4697)
    reg T_4713 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4715 = neq(io.uarch_counters[6], UInt<1>("h00"))
    node T_4717 = add(T_4713, UInt<7>("h01"))
    node T_4718 = tail(T_4717, 1)
    when T_4715 :
      node T_4719 = bits(T_4718, 5, 0)
      T_4713 <= T_4719
      skip
    reg T_4721 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4722 = bits(T_4718, 6, 6)
    node T_4723 = and(T_4715, T_4722)
    when T_4723 :
      node T_4725 = add(T_4721, UInt<1>("h01"))
      node T_4726 = tail(T_4725, 1)
      T_4721 <= T_4726
      skip
    node T_4727 = cat(T_4721, T_4713)
    reg T_4729 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4731 = neq(io.uarch_counters[7], UInt<1>("h00"))
    node T_4733 = add(T_4729, UInt<7>("h01"))
    node T_4734 = tail(T_4733, 1)
    when T_4731 :
      node T_4735 = bits(T_4734, 5, 0)
      T_4729 <= T_4735
      skip
    reg T_4737 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4738 = bits(T_4734, 6, 6)
    node T_4739 = and(T_4731, T_4738)
    when T_4739 :
      node T_4741 = add(T_4737, UInt<1>("h01"))
      node T_4742 = tail(T_4741, 1)
      T_4737 <= T_4742
      skip
    node T_4743 = cat(T_4737, T_4729)
    reg T_4745 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4747 = neq(io.uarch_counters[8], UInt<1>("h00"))
    node T_4749 = add(T_4745, UInt<7>("h01"))
    node T_4750 = tail(T_4749, 1)
    when T_4747 :
      node T_4751 = bits(T_4750, 5, 0)
      T_4745 <= T_4751
      skip
    reg T_4753 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4754 = bits(T_4750, 6, 6)
    node T_4755 = and(T_4747, T_4754)
    when T_4755 :
      node T_4757 = add(T_4753, UInt<1>("h01"))
      node T_4758 = tail(T_4757, 1)
      T_4753 <= T_4758
      skip
    node T_4759 = cat(T_4753, T_4745)
    reg T_4761 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4763 = neq(io.uarch_counters[9], UInt<1>("h00"))
    node T_4765 = add(T_4761, UInt<7>("h01"))
    node T_4766 = tail(T_4765, 1)
    when T_4763 :
      node T_4767 = bits(T_4766, 5, 0)
      T_4761 <= T_4767
      skip
    reg T_4769 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4770 = bits(T_4766, 6, 6)
    node T_4771 = and(T_4763, T_4770)
    when T_4771 :
      node T_4773 = add(T_4769, UInt<1>("h01"))
      node T_4774 = tail(T_4773, 1)
      T_4769 <= T_4774
      skip
    node T_4775 = cat(T_4769, T_4761)
    reg T_4777 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4779 = neq(io.uarch_counters[10], UInt<1>("h00"))
    node T_4781 = add(T_4777, UInt<7>("h01"))
    node T_4782 = tail(T_4781, 1)
    when T_4779 :
      node T_4783 = bits(T_4782, 5, 0)
      T_4777 <= T_4783
      skip
    reg T_4785 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4786 = bits(T_4782, 6, 6)
    node T_4787 = and(T_4779, T_4786)
    when T_4787 :
      node T_4789 = add(T_4785, UInt<1>("h01"))
      node T_4790 = tail(T_4789, 1)
      T_4785 <= T_4790
      skip
    node T_4791 = cat(T_4785, T_4777)
    reg T_4793 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4795 = neq(io.uarch_counters[11], UInt<1>("h00"))
    node T_4797 = add(T_4793, UInt<7>("h01"))
    node T_4798 = tail(T_4797, 1)
    when T_4795 :
      node T_4799 = bits(T_4798, 5, 0)
      T_4793 <= T_4799
      skip
    reg T_4801 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4802 = bits(T_4798, 6, 6)
    node T_4803 = and(T_4795, T_4802)
    when T_4803 :
      node T_4805 = add(T_4801, UInt<1>("h01"))
      node T_4806 = tail(T_4805, 1)
      T_4801 <= T_4806
      skip
    node T_4807 = cat(T_4801, T_4793)
    reg T_4809 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4811 = neq(io.uarch_counters[12], UInt<1>("h00"))
    node T_4813 = add(T_4809, UInt<7>("h01"))
    node T_4814 = tail(T_4813, 1)
    when T_4811 :
      node T_4815 = bits(T_4814, 5, 0)
      T_4809 <= T_4815
      skip
    reg T_4817 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4818 = bits(T_4814, 6, 6)
    node T_4819 = and(T_4811, T_4818)
    when T_4819 :
      node T_4821 = add(T_4817, UInt<1>("h01"))
      node T_4822 = tail(T_4821, 1)
      T_4817 <= T_4822
      skip
    node T_4823 = cat(T_4817, T_4809)
    reg T_4825 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4827 = neq(io.uarch_counters[13], UInt<1>("h00"))
    node T_4829 = add(T_4825, UInt<7>("h01"))
    node T_4830 = tail(T_4829, 1)
    when T_4827 :
      node T_4831 = bits(T_4830, 5, 0)
      T_4825 <= T_4831
      skip
    reg T_4833 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4834 = bits(T_4830, 6, 6)
    node T_4835 = and(T_4827, T_4834)
    when T_4835 :
      node T_4837 = add(T_4833, UInt<1>("h01"))
      node T_4838 = tail(T_4837, 1)
      T_4833 <= T_4838
      skip
    node T_4839 = cat(T_4833, T_4825)
    reg T_4841 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4843 = neq(io.uarch_counters[14], UInt<1>("h00"))
    node T_4845 = add(T_4841, UInt<7>("h01"))
    node T_4846 = tail(T_4845, 1)
    when T_4843 :
      node T_4847 = bits(T_4846, 5, 0)
      T_4841 <= T_4847
      skip
    reg T_4849 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4850 = bits(T_4846, 6, 6)
    node T_4851 = and(T_4843, T_4850)
    when T_4851 :
      node T_4853 = add(T_4849, UInt<1>("h01"))
      node T_4854 = tail(T_4853, 1)
      T_4849 <= T_4854
      skip
    node T_4855 = cat(T_4849, T_4841)
    reg T_4857 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    node T_4859 = neq(io.uarch_counters[15], UInt<1>("h00"))
    node T_4861 = add(T_4857, UInt<7>("h01"))
    node T_4862 = tail(T_4861, 1)
    when T_4859 :
      node T_4863 = bits(T_4862, 5, 0)
      T_4857 <= T_4863
      skip
    reg T_4865 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00")))
    node T_4866 = bits(T_4862, 6, 6)
    node T_4867 = and(T_4859, T_4866)
    when T_4867 :
      node T_4869 = add(T_4865, UInt<1>("h01"))
      node T_4870 = tail(T_4869, 1)
      T_4865 <= T_4870
      skip
    node T_4871 = cat(T_4865, T_4857)
    reg reg_fflags : UInt<5>, clk
    reg reg_frm : UInt<3>, clk
    node irq_rocc = and(UInt<1>("h00"), io.rocc.interrupt)
    io.interrupt_cause <= UInt<1>("h00")
    node T_4879 = bits(io.interrupt_cause, 63, 63)
    io.interrupt <= T_4879
    wire some_interrupt_pending : UInt<1>
    some_interrupt_pending <= UInt<1>("h00")
    node T_4883 = and(reg_mie.ssip, reg_mip.ssip)
    node T_4884 = lt(reg_mstatus.prv, UInt<1>("h01"))
    node T_4885 = eq(reg_mstatus.prv, UInt<1>("h01"))
    node T_4886 = and(T_4885, reg_mstatus.ie)
    node T_4887 = or(T_4884, T_4886)
    node T_4888 = and(T_4883, T_4887)
    when T_4888 :
      io.interrupt_cause <= UInt<64>("h08000000000000000")
      skip
    node T_4890 = leq(reg_mstatus.prv, UInt<1>("h01"))
    node T_4891 = and(T_4883, T_4890)
    when T_4891 :
      some_interrupt_pending <= UInt<1>("h01")
      skip
    node T_4894 = and(reg_mie.msip, reg_mip.msip)
    node T_4895 = lt(reg_mstatus.prv, UInt<2>("h03"))
    node T_4896 = eq(reg_mstatus.prv, UInt<2>("h03"))
    node T_4897 = and(T_4896, reg_mstatus.ie)
    node T_4898 = or(T_4895, T_4897)
    node T_4899 = and(T_4894, T_4898)
    when T_4899 :
      io.interrupt_cause <= UInt<64>("h08000000000000000")
      skip
    node T_4901 = leq(reg_mstatus.prv, UInt<2>("h03"))
    node T_4902 = and(T_4894, T_4901)
    when T_4902 :
      some_interrupt_pending <= UInt<1>("h01")
      skip
    node T_4905 = and(reg_mie.stip, reg_mip.stip)
    node T_4906 = lt(reg_mstatus.prv, UInt<1>("h01"))
    node T_4907 = eq(reg_mstatus.prv, UInt<1>("h01"))
    node T_4908 = and(T_4907, reg_mstatus.ie)
    node T_4909 = or(T_4906, T_4908)
    node T_4910 = and(T_4905, T_4909)
    when T_4910 :
      io.interrupt_cause <= UInt<64>("h08000000000000001")
      skip
    node T_4912 = leq(reg_mstatus.prv, UInt<1>("h01"))
    node T_4913 = and(T_4905, T_4912)
    when T_4913 :
      some_interrupt_pending <= UInt<1>("h01")
      skip
    node T_4916 = and(reg_mie.mtip, reg_mip.mtip)
    node T_4917 = lt(reg_mstatus.prv, UInt<2>("h03"))
    node T_4918 = eq(reg_mstatus.prv, UInt<2>("h03"))
    node T_4919 = and(T_4918, reg_mstatus.ie)
    node T_4920 = or(T_4917, T_4919)
    node T_4921 = and(T_4916, T_4920)
    when T_4921 :
      io.interrupt_cause <= UInt<64>("h08000000000000001")
      skip
    node T_4923 = leq(reg_mstatus.prv, UInt<2>("h03"))
    node T_4924 = and(T_4916, T_4923)
    when T_4924 :
      some_interrupt_pending <= UInt<1>("h01")
      skip
    node T_4928 = neq(reg_fromhost, UInt<1>("h00"))
    node T_4929 = lt(reg_mstatus.prv, UInt<2>("h03"))
    node T_4930 = eq(reg_mstatus.prv, UInt<2>("h03"))
    node T_4931 = and(T_4930, reg_mstatus.ie)
    node T_4932 = or(T_4929, T_4931)
    node T_4933 = and(T_4928, T_4932)
    when T_4933 :
      io.interrupt_cause <= UInt<64>("h08000000000000002")
      skip
    node T_4935 = leq(reg_mstatus.prv, UInt<2>("h03"))
    node T_4936 = and(T_4928, T_4935)
    when T_4936 :
      some_interrupt_pending <= UInt<1>("h01")
      skip
    node T_4939 = lt(reg_mstatus.prv, UInt<2>("h03"))
    node T_4940 = eq(reg_mstatus.prv, UInt<2>("h03"))
    node T_4941 = and(T_4940, reg_mstatus.ie)
    node T_4942 = or(T_4939, T_4941)
    node T_4943 = and(irq_rocc, T_4942)
    when T_4943 :
      io.interrupt_cause <= UInt<64>("h08000000000000003")
      skip
    node T_4945 = leq(reg_mstatus.prv, UInt<2>("h03"))
    node T_4946 = and(irq_rocc, T_4945)
    when T_4946 :
      some_interrupt_pending <= UInt<1>("h01")
      skip
    node system_insn = eq(io.rw.cmd, UInt<3>("h04"))
    node T_4949 = neq(io.rw.cmd, UInt<3>("h00"))
    node T_4951 = eq(system_insn, UInt<1>("h00"))
    node cpu_ren = and(T_4949, T_4951)
    reg host_csr_req_valid : UInt<1>, clk
    node T_4956 = eq(cpu_ren, UInt<1>("h00"))
    node host_csr_req_fire = and(host_csr_req_valid, T_4956)
    reg host_csr_rep_valid : UInt<1>, clk
    reg host_csr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clk
    node T_4965 = eq(host_csr_req_valid, UInt<1>("h00"))
    node T_4967 = eq(host_csr_rep_valid, UInt<1>("h00"))
    node T_4968 = and(T_4965, T_4967)
    io.host.csr.req.ready <= T_4968
    io.host.csr.resp.valid <= host_csr_rep_valid
    io.host.csr.resp.bits <= host_csr_bits.data
    node T_4969 = and(io.host.csr.req.ready, io.host.csr.req.valid)
    when T_4969 :
      host_csr_req_valid <= UInt<1>("h01")
      host_csr_bits <- io.host.csr.req.bits
      skip
    when host_csr_req_fire :
      host_csr_req_valid <= UInt<1>("h00")
      host_csr_rep_valid <= UInt<1>("h01")
      host_csr_bits.data <= io.rw.rdata
      skip
    node T_4973 = and(io.host.csr.resp.ready, io.host.csr.resp.valid)
    when T_4973 :
      host_csr_rep_valid <= UInt<1>("h00")
      skip
    io.host.debug_stats_csr <= reg_stats
    node T_4975 = cat(io.status.sd, io.status.zero2)
    node T_4976 = cat(io.status.sd_rv32, io.status.zero1)
    node T_4977 = cat(T_4975, T_4976)
    node T_4978 = cat(io.status.vm, io.status.mprv)
    node T_4979 = cat(io.status.xs, io.status.fs)
    node T_4980 = cat(T_4978, T_4979)
    node T_4981 = cat(T_4977, T_4980)
    node T_4982 = cat(io.status.prv3, io.status.ie3)
    node T_4983 = cat(io.status.prv2, io.status.ie2)
    node T_4984 = cat(T_4982, T_4983)
    node T_4985 = cat(io.status.prv1, io.status.ie1)
    node T_4986 = cat(io.status.prv, io.status.ie)
    node T_4987 = cat(T_4985, T_4986)
    node T_4988 = cat(T_4984, T_4987)
    node read_mstatus = cat(T_4981, T_4988)
    node T_4990 = cat(reg_frm, reg_fflags)
    node T_4998 = cat(reg_mip.mtip, reg_mip.htip)
    node T_4999 = cat(reg_mip.stip, reg_mip.utip)
    node T_5000 = cat(T_4998, T_4999)
    node T_5001 = cat(reg_mip.msip, reg_mip.hsip)
    node T_5002 = cat(reg_mip.ssip, reg_mip.usip)
    node T_5003 = cat(T_5001, T_5002)
    node T_5004 = cat(T_5000, T_5003)
    node T_5005 = cat(reg_mie.mtip, reg_mie.htip)
    node T_5006 = cat(reg_mie.stip, reg_mie.utip)
    node T_5007 = cat(T_5005, T_5006)
    node T_5008 = cat(reg_mie.msip, reg_mie.hsip)
    node T_5009 = cat(reg_mie.ssip, reg_mie.usip)
    node T_5010 = cat(T_5008, T_5009)
    node T_5011 = cat(T_5007, T_5010)
    node T_5012 = bits(reg_mepc, 39, 39)
    node T_5014 = sub(UInt<24>("h00"), T_5012)
    node T_5015 = tail(T_5014, 1)
    node T_5016 = cat(T_5015, reg_mepc)
    node T_5017 = bits(reg_mbadaddr, 39, 39)
    node T_5019 = sub(UInt<24>("h00"), T_5017)
    node T_5020 = tail(T_5019, 1)
    node T_5021 = cat(T_5020, reg_mbadaddr)
    wire T_5048 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>}
    T_5048 is invalid
    node T_5061 = bits(read_mstatus, 0, 0)
    T_5048.ie <= T_5061
    node T_5062 = bits(read_mstatus, 2, 1)
    T_5048.zero1 <= T_5062
    node T_5063 = bits(read_mstatus, 3, 3)
    T_5048.pie <= T_5063
    node T_5064 = bits(read_mstatus, 4, 4)
    T_5048.ps <= T_5064
    node T_5065 = bits(read_mstatus, 11, 5)
    T_5048.zero2 <= T_5065
    node T_5066 = bits(read_mstatus, 13, 12)
    T_5048.fs <= T_5066
    node T_5067 = bits(read_mstatus, 15, 14)
    T_5048.xs <= T_5067
    node T_5068 = bits(read_mstatus, 16, 16)
    T_5048.mprv <= T_5068
    node T_5069 = bits(read_mstatus, 30, 17)
    T_5048.zero3 <= T_5069
    node T_5070 = bits(read_mstatus, 31, 31)
    T_5048.sd_rv32 <= T_5070
    node T_5071 = bits(read_mstatus, 62, 32)
    T_5048.zero4 <= T_5071
    node T_5072 = bits(read_mstatus, 63, 63)
    T_5048.sd <= T_5072
    wire T_5073 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>}
    T_5073 <- T_5048
    T_5073.zero1 <= UInt<1>("h00")
    T_5073.zero2 <= UInt<1>("h00")
    T_5073.zero3 <= UInt<1>("h00")
    T_5073.zero4 <= UInt<1>("h00")
    wire T_5109 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_5109 is invalid
    T_5109.usip <= UInt<1>("h00")
    T_5109.ssip <= UInt<1>("h00")
    T_5109.hsip <= UInt<1>("h00")
    T_5109.msip <= UInt<1>("h00")
    T_5109.utip <= UInt<1>("h00")
    T_5109.stip <= UInt<1>("h00")
    T_5109.htip <= UInt<1>("h00")
    T_5109.mtip <= UInt<1>("h00")
    wire T_5126 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_5126 <- T_5109
    T_5126.ssip <= reg_mip.ssip
    T_5126.stip <= reg_mip.stip
    wire T_5154 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_5154 is invalid
    T_5154.usip <= UInt<1>("h00")
    T_5154.ssip <= UInt<1>("h00")
    T_5154.hsip <= UInt<1>("h00")
    T_5154.msip <= UInt<1>("h00")
    T_5154.utip <= UInt<1>("h00")
    T_5154.stip <= UInt<1>("h00")
    T_5154.htip <= UInt<1>("h00")
    T_5154.mtip <= UInt<1>("h00")
    wire T_5171 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_5171 <- T_5154
    T_5171.ssip <= reg_mie.ssip
    T_5171.stip <= reg_mie.stip
    node T_5180 = cat(T_5073.zero4, T_5073.sd_rv32)
    node T_5181 = cat(T_5073.sd, T_5180)
    node T_5182 = cat(T_5073.mprv, T_5073.xs)
    node T_5183 = cat(T_5073.zero3, T_5182)
    node T_5184 = cat(T_5181, T_5183)
    node T_5185 = cat(T_5073.zero2, T_5073.ps)
    node T_5186 = cat(T_5073.fs, T_5185)
    node T_5187 = cat(T_5073.zero1, T_5073.ie)
    node T_5188 = cat(T_5073.pie, T_5187)
    node T_5189 = cat(T_5186, T_5188)
    node T_5190 = cat(T_5184, T_5189)
    node T_5191 = cat(T_5126.mtip, T_5126.htip)
    node T_5192 = cat(T_5126.stip, T_5126.utip)
    node T_5193 = cat(T_5191, T_5192)
    node T_5194 = cat(T_5126.msip, T_5126.hsip)
    node T_5195 = cat(T_5126.ssip, T_5126.usip)
    node T_5196 = cat(T_5194, T_5195)
    node T_5197 = cat(T_5193, T_5196)
    node T_5198 = cat(T_5171.mtip, T_5171.htip)
    node T_5199 = cat(T_5171.stip, T_5171.utip)
    node T_5200 = cat(T_5198, T_5199)
    node T_5201 = cat(T_5171.msip, T_5171.hsip)
    node T_5202 = cat(T_5171.ssip, T_5171.usip)
    node T_5203 = cat(T_5201, T_5202)
    node T_5204 = cat(T_5200, T_5203)
    node T_5205 = bits(reg_sbadaddr, 39, 39)
    node T_5207 = sub(UInt<24>("h00"), T_5205)
    node T_5208 = tail(T_5207, 1)
    node T_5209 = cat(T_5208, reg_sbadaddr)
    node T_5211 = bits(reg_sepc, 39, 39)
    node T_5213 = sub(UInt<24>("h00"), T_5211)
    node T_5214 = tail(T_5213, 1)
    node T_5215 = cat(T_5214, reg_sepc)
    node T_5216 = bits(reg_stvec, 38, 38)
    node T_5218 = sub(UInt<25>("h00"), T_5216)
    node T_5219 = tail(T_5218, 1)
    node T_5220 = cat(T_5219, reg_stvec)
    node addr = mux(cpu_ren, io.rw.addr, host_csr_bits.addr)
    node T_5223 = eq(addr, UInt<1>("h01"))
    node T_5225 = eq(addr, UInt<2>("h02"))
    node T_5227 = eq(addr, UInt<2>("h03"))
    node T_5229 = eq(addr, UInt<12>("h0c00"))
    node T_5231 = eq(addr, UInt<12>("h0900"))
    node T_5233 = eq(addr, UInt<12>("h0c01"))
    node T_5235 = eq(addr, UInt<12>("h0901"))
    node T_5237 = eq(addr, UInt<12>("h0d01"))
    node T_5239 = eq(addr, UInt<12>("h0a01"))
    node T_5241 = eq(addr, UInt<11>("h0701"))
    node T_5243 = eq(addr, UInt<12>("h0f00"))
    node T_5245 = eq(addr, UInt<12>("h0f01"))
    node T_5247 = eq(addr, UInt<10>("h0300"))
    node T_5249 = eq(addr, UInt<10>("h0302"))
    node T_5251 = eq(addr, UInt<11>("h0782"))
    node T_5253 = eq(addr, UInt<10>("h0301"))
    node T_5255 = eq(addr, UInt<11>("h0784"))
    node T_5257 = eq(addr, UInt<11>("h0783"))
    node T_5259 = eq(addr, UInt<10>("h0344"))
    node T_5261 = eq(addr, UInt<10>("h0304"))
    node T_5263 = eq(addr, UInt<10>("h0340"))
    node T_5265 = eq(addr, UInt<10>("h0341"))
    node T_5267 = eq(addr, UInt<10>("h0343"))
    node T_5269 = eq(addr, UInt<10>("h0342"))
    node T_5271 = eq(addr, UInt<10>("h0321"))
    node T_5273 = eq(addr, UInt<12>("h0f10"))
    node T_5275 = eq(addr, UInt<8>("h0c0"))
    node T_5277 = eq(addr, UInt<11>("h0780"))
    node T_5279 = eq(addr, UInt<11>("h0781"))
    node T_5281 = eq(addr, UInt<12>("h0c02"))
    node T_5283 = eq(addr, UInt<12>("h0902"))
    node T_5285 = eq(addr, UInt<12>("h0cc0"))
    node T_5287 = eq(addr, UInt<12>("h0cc1"))
    node T_5289 = eq(addr, UInt<12>("h0cc2"))
    node T_5291 = eq(addr, UInt<12>("h0cc3"))
    node T_5293 = eq(addr, UInt<12>("h0cc4"))
    node T_5295 = eq(addr, UInt<12>("h0cc5"))
    node T_5297 = eq(addr, UInt<12>("h0cc6"))
    node T_5299 = eq(addr, UInt<12>("h0cc7"))
    node T_5301 = eq(addr, UInt<12>("h0cc8"))
    node T_5303 = eq(addr, UInt<12>("h0cc9"))
    node T_5305 = eq(addr, UInt<12>("h0cca"))
    node T_5307 = eq(addr, UInt<12>("h0ccb"))
    node T_5309 = eq(addr, UInt<12>("h0ccc"))
    node T_5311 = eq(addr, UInt<12>("h0ccd"))
    node T_5313 = eq(addr, UInt<12>("h0cce"))
    node T_5315 = eq(addr, UInt<12>("h0ccf"))
    node T_5317 = eq(addr, UInt<9>("h0100"))
    node T_5319 = eq(addr, UInt<9>("h0144"))
    node T_5321 = eq(addr, UInt<9>("h0104"))
    node T_5323 = eq(addr, UInt<9>("h0140"))
    node T_5325 = eq(addr, UInt<12>("h0d42"))
    node T_5327 = eq(addr, UInt<12>("h0d43"))
    node T_5329 = eq(addr, UInt<9>("h0180"))
    node T_5331 = eq(addr, UInt<9>("h0181"))
    node T_5333 = eq(addr, UInt<9>("h0141"))
    node T_5335 = eq(addr, UInt<9>("h0101"))
    node T_5336 = or(T_5223, T_5225)
    node T_5337 = or(T_5336, T_5227)
    node T_5338 = or(T_5337, T_5229)
    node T_5339 = or(T_5338, T_5231)
    node T_5340 = or(T_5339, T_5233)
    node T_5341 = or(T_5340, T_5235)
    node T_5342 = or(T_5341, T_5237)
    node T_5343 = or(T_5342, T_5239)
    node T_5344 = or(T_5343, T_5241)
    node T_5345 = or(T_5344, T_5243)
    node T_5346 = or(T_5345, T_5245)
    node T_5347 = or(T_5346, T_5247)
    node T_5348 = or(T_5347, T_5249)
    node T_5349 = or(T_5348, T_5251)
    node T_5350 = or(T_5349, T_5253)
    node T_5351 = or(T_5350, T_5255)
    node T_5352 = or(T_5351, T_5257)
    node T_5353 = or(T_5352, T_5259)
    node T_5354 = or(T_5353, T_5261)
    node T_5355 = or(T_5354, T_5263)
    node T_5356 = or(T_5355, T_5265)
    node T_5357 = or(T_5356, T_5267)
    node T_5358 = or(T_5357, T_5269)
    node T_5359 = or(T_5358, T_5271)
    node T_5360 = or(T_5359, T_5273)
    node T_5361 = or(T_5360, T_5275)
    node T_5362 = or(T_5361, T_5277)
    node T_5363 = or(T_5362, T_5279)
    node T_5364 = or(T_5363, T_5281)
    node T_5365 = or(T_5364, T_5283)
    node T_5366 = or(T_5365, T_5285)
    node T_5367 = or(T_5366, T_5287)
    node T_5368 = or(T_5367, T_5289)
    node T_5369 = or(T_5368, T_5291)
    node T_5370 = or(T_5369, T_5293)
    node T_5371 = or(T_5370, T_5295)
    node T_5372 = or(T_5371, T_5297)
    node T_5373 = or(T_5372, T_5299)
    node T_5374 = or(T_5373, T_5301)
    node T_5375 = or(T_5374, T_5303)
    node T_5376 = or(T_5375, T_5305)
    node T_5377 = or(T_5376, T_5307)
    node T_5378 = or(T_5377, T_5309)
    node T_5379 = or(T_5378, T_5311)
    node T_5380 = or(T_5379, T_5313)
    node T_5381 = or(T_5380, T_5315)
    node T_5382 = or(T_5381, T_5317)
    node T_5383 = or(T_5382, T_5319)
    node T_5384 = or(T_5383, T_5321)
    node T_5385 = or(T_5384, T_5323)
    node T_5386 = or(T_5385, T_5325)
    node T_5387 = or(T_5386, T_5327)
    node T_5388 = or(T_5387, T_5329)
    node T_5389 = or(T_5388, T_5331)
    node T_5390 = or(T_5389, T_5333)
    node addr_valid = or(T_5390, T_5335)
    node T_5392 = or(T_5223, T_5225)
    node fp_csr = or(T_5392, T_5227)
    node csr_addr_priv = bits(io.rw.addr, 9, 8)
    node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv)
    node T_5396 = bits(io.rw.addr, 11, 10)
    node T_5397 = not(T_5396)
    node read_only = eq(T_5397, UInt<1>("h00"))
    node T_5400 = neq(io.rw.cmd, UInt<3>("h05"))
    node T_5401 = and(cpu_ren, T_5400)
    node cpu_wen = and(T_5401, priv_sufficient)
    node T_5404 = eq(read_only, UInt<1>("h00"))
    node T_5405 = and(cpu_wen, T_5404)
    node T_5406 = and(host_csr_req_fire, host_csr_bits.rw)
    node wen = or(T_5405, T_5406)
    node T_5408 = eq(io.rw.cmd, UInt<3>("h01"))
    node T_5409 = eq(io.rw.cmd, UInt<3>("h03"))
    node T_5410 = not(io.rw.wdata)
    node T_5411 = and(io.rw.rdata, T_5410)
    node T_5412 = eq(io.rw.cmd, UInt<3>("h02"))
    node T_5413 = or(io.rw.rdata, io.rw.wdata)
    node T_5414 = mux(T_5412, T_5413, host_csr_bits.data)
    node T_5415 = mux(T_5409, T_5411, T_5414)
    node wdata = mux(T_5408, io.rw.wdata, T_5415)
    node T_5417 = bits(io.rw.addr, 8, 8)
    node T_5419 = eq(T_5417, UInt<1>("h00"))
    node T_5420 = bits(io.rw.addr, 0, 0)
    node T_5422 = eq(T_5420, UInt<1>("h00"))
    node T_5423 = and(T_5419, T_5422)
    node insn_call = and(T_5423, system_insn)
    node T_5425 = bits(io.rw.addr, 8, 8)
    node T_5427 = eq(T_5425, UInt<1>("h00"))
    node T_5428 = bits(io.rw.addr, 0, 0)
    node T_5429 = and(T_5427, T_5428)
    node insn_break = and(T_5429, system_insn)
    node T_5431 = bits(io.rw.addr, 8, 8)
    node T_5432 = bits(io.rw.addr, 1, 1)
    node T_5434 = eq(T_5432, UInt<1>("h00"))
    node T_5435 = and(T_5431, T_5434)
    node T_5436 = bits(io.rw.addr, 0, 0)
    node T_5438 = eq(T_5436, UInt<1>("h00"))
    node T_5439 = and(T_5435, T_5438)
    node T_5440 = and(T_5439, system_insn)
    node insn_ret = and(T_5440, priv_sufficient)
    node T_5442 = bits(io.rw.addr, 8, 8)
    node T_5443 = bits(io.rw.addr, 1, 1)
    node T_5445 = eq(T_5443, UInt<1>("h00"))
    node T_5446 = and(T_5442, T_5445)
    node T_5447 = bits(io.rw.addr, 0, 0)
    node T_5448 = and(T_5446, T_5447)
    node T_5449 = and(T_5448, system_insn)
    node insn_sfence_vm = and(T_5449, priv_sufficient)
    node T_5451 = bits(io.rw.addr, 2, 2)
    node maybe_insn_redirect_trap = and(T_5451, system_insn)
    node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient)
    node T_5454 = bits(io.rw.addr, 8, 8)
    node T_5455 = bits(io.rw.addr, 1, 1)
    node T_5456 = and(T_5454, T_5455)
    node T_5457 = bits(io.rw.addr, 0, 0)
    node T_5459 = eq(T_5457, UInt<1>("h00"))
    node T_5460 = and(T_5456, T_5459)
    node T_5461 = and(T_5460, system_insn)
    node insn_wfi = and(T_5461, priv_sufficient)
    node T_5463 = and(cpu_wen, read_only)
    node T_5465 = eq(priv_sufficient, UInt<1>("h00"))
    node T_5467 = eq(addr_valid, UInt<1>("h00"))
    node T_5468 = or(T_5465, T_5467)
    node T_5470 = neq(io.status.fs, UInt<1>("h00"))
    node T_5472 = eq(T_5470, UInt<1>("h00"))
    node T_5473 = and(fp_csr, T_5472)
    node T_5474 = or(T_5468, T_5473)
    node T_5475 = and(cpu_ren, T_5474)
    node T_5476 = or(T_5463, T_5475)
    node T_5478 = eq(priv_sufficient, UInt<1>("h00"))
    node T_5479 = and(system_insn, T_5478)
    node T_5480 = or(T_5476, T_5479)
    node T_5481 = or(T_5480, insn_call)
    node csr_xcpt = or(T_5481, insn_break)
    when insn_wfi :
      reg_wfi <= UInt<1>("h01")
      skip
    when some_interrupt_pending :
      reg_wfi <= UInt<1>("h00")
      skip
    io.fatc <= insn_sfence_vm
    node T_5485 = or(io.exception, csr_xcpt)
    node T_5486 = shl(reg_mstatus.prv, 6)
    node T_5488 = add(T_5486, UInt<9>("h0100"))
    node T_5489 = tail(T_5488, 1)
    node T_5490 = bits(reg_stvec, 38, 38)
    node T_5491 = cat(T_5490, reg_stvec)
    node T_5492 = bits(reg_mstatus.prv, 1, 1)
    node T_5494 = or(T_5492, UInt<1>("h00"))
    node T_5495 = mux(T_5494, reg_mepc, reg_sepc)
    node T_5496 = mux(maybe_insn_redirect_trap, T_5491, T_5495)
    node T_5497 = mux(T_5485, T_5489, T_5496)
    io.evec <= T_5497
    io.ptbr <= reg_sptbr
    io.csr_xcpt <= csr_xcpt
    node T_5498 = or(insn_ret, insn_redirect_trap)
    io.eret <= T_5498
    io.status <- reg_mstatus
    node T_5500 = neq(reg_mstatus.fs, UInt<1>("h00"))
    node T_5502 = sub(UInt<2>("h00"), T_5500)
    node T_5503 = tail(T_5502, 1)
    io.status.fs <= T_5503
    node T_5505 = neq(reg_mstatus.xs, UInt<1>("h00"))
    node T_5507 = sub(UInt<2>("h00"), T_5505)
    node T_5508 = tail(T_5507, 1)
    io.status.xs <= T_5508
    node T_5509 = not(io.status.fs)
    node T_5511 = eq(T_5509, UInt<1>("h00"))
    node T_5512 = not(io.status.xs)
    node T_5514 = eq(T_5512, UInt<1>("h00"))
    node T_5515 = or(T_5511, T_5514)
    io.status.sd <= T_5515
    node T_5516 = or(io.exception, csr_xcpt)
    when T_5516 :
      reg_mstatus.ie <= UInt<1>("h00")
      reg_mstatus.prv <= UInt<2>("h03")
      reg_mstatus.mprv <= UInt<1>("h00")
      reg_mstatus.prv1 <= reg_mstatus.prv
      reg_mstatus.ie1 <= reg_mstatus.ie
      reg_mstatus.prv2 <= reg_mstatus.prv1
      reg_mstatus.ie2 <= reg_mstatus.ie1
      node T_5520 = not(io.pc)
      node T_5522 = or(T_5520, UInt<2>("h03"))
      node T_5523 = not(T_5522)
      reg_mepc <= T_5523
      reg_mcause <= io.cause
      when csr_xcpt :
        reg_mcause <= UInt<2>("h02")
        when insn_break :
          reg_mcause <= UInt<2>("h03")
          skip
        when insn_call :
          node T_5527 = add(reg_mstatus.prv, UInt<4>("h08"))
          node T_5528 = tail(T_5527, 1)
          reg_mcause <= T_5528
          skip
        skip
      reg_mbadaddr <= io.pc
      node T_5530 = eq(io.cause, UInt<3>("h05"))
      node T_5532 = eq(io.cause, UInt<3>("h04"))
      node T_5533 = or(T_5530, T_5532)
      node T_5535 = eq(io.cause, UInt<3>("h07"))
      node T_5536 = or(T_5533, T_5535)
      node T_5538 = eq(io.cause, UInt<3>("h06"))
      node T_5539 = or(T_5536, T_5538)
      when T_5539 :
        node T_5540 = bits(io.rw.wdata, 63, 39)
        node T_5541 = bits(io.rw.wdata, 38, 0)
        node T_5542 = asSInt(T_5541)
        node T_5544 = lt(T_5542, asSInt(UInt<1>("h00")))
        node T_5545 = not(T_5540)
        node T_5547 = eq(T_5545, UInt<1>("h00"))
        node T_5549 = neq(T_5540, UInt<1>("h00"))
        node T_5550 = mux(T_5544, T_5547, T_5549)
        node T_5551 = cat(T_5550, T_5541)
        reg_mbadaddr <= T_5551
        skip
      skip
    when insn_ret :
      reg_mstatus.ie <= reg_mstatus.ie1
      reg_mstatus.prv <= reg_mstatus.prv1
      reg_mstatus.prv1 <= reg_mstatus.prv2
      reg_mstatus.ie1 <= reg_mstatus.ie2
      reg_mstatus.prv2 <= UInt<1>("h00")
      reg_mstatus.ie2 <= UInt<1>("h01")
      skip
    when insn_redirect_trap :
      reg_mstatus.prv <= UInt<1>("h01")
      reg_sbadaddr <= reg_mbadaddr
      reg_scause <= reg_mcause
      reg_sepc <= reg_mepc
      skip
    node T_5556 = cat(UInt<1>("h00"), insn_redirect_trap)
    node T_5557 = add(insn_ret, T_5556)
    node T_5558 = tail(T_5557, 1)
    node T_5561 = cat(UInt<1>("h00"), csr_xcpt)
    node T_5562 = add(io.exception, T_5561)
    node T_5563 = tail(T_5562, 1)
    node T_5564 = cat(UInt<1>("h00"), T_5563)
    node T_5565 = add(T_5558, T_5564)
    node T_5566 = tail(T_5565, 1)
    node T_5568 = leq(T_5566, UInt<1>("h01"))
    node T_5570 = eq(reset, UInt<1>("h00"))
    when T_5570 :
      node T_5572 = eq(T_5568, UInt<1>("h00"))
      when T_5572 :
        node T_5574 = eq(reset, UInt<1>("h00"))
        when T_5574 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): these conditions must be mutually exclusive")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_5575 = geq(reg_time, reg_mtimecmp)
    when T_5575 :
      reg_mip.mtip <= UInt<1>("h01")
      skip
    io.time <= T_4615
    io.csr_stall <= reg_wfi
    node T_5578 = eq(host_csr_bits.rw, UInt<1>("h00"))
    node T_5579 = and(host_csr_req_fire, T_5578)
    node T_5580 = and(T_5579, T_5277)
    when T_5580 :
      reg_tohost <= UInt<1>("h00")
      skip
    node T_5583 = mux(T_5223, reg_fflags, UInt<1>("h00"))
    node T_5585 = mux(T_5225, reg_frm, UInt<1>("h00"))
    node T_5587 = mux(T_5227, T_4990, UInt<1>("h00"))
    node T_5589 = mux(T_5229, T_4615, UInt<1>("h00"))
    node T_5591 = mux(T_5231, T_4615, UInt<1>("h00"))
    node T_5593 = mux(T_5233, reg_time, UInt<1>("h00"))
    node T_5595 = mux(T_5235, reg_time, UInt<1>("h00"))
    node T_5597 = mux(T_5237, reg_time, UInt<1>("h00"))
    node T_5599 = mux(T_5239, reg_time, UInt<1>("h00"))
    node T_5601 = mux(T_5241, reg_time, UInt<1>("h00"))
    node T_5603 = mux(T_5243, UInt<64>("h08000000000041129"), UInt<1>("h00"))
    node T_5605 = mux(T_5245, UInt<1>("h01"), UInt<1>("h00"))
    node T_5607 = mux(T_5247, read_mstatus, UInt<1>("h00"))
    node T_5609 = mux(T_5249, UInt<1>("h00"), UInt<1>("h00"))
    node T_5611 = mux(T_5251, UInt<1>("h00"), UInt<1>("h00"))
    node T_5613 = mux(T_5253, UInt<9>("h0100"), UInt<1>("h00"))
    node T_5615 = mux(T_5255, UInt<31>("h040000000"), UInt<1>("h00"))
    node T_5617 = mux(T_5257, UInt<1>("h00"), UInt<1>("h00"))
    node T_5619 = mux(T_5259, T_5004, UInt<1>("h00"))
    node T_5621 = mux(T_5261, T_5011, UInt<1>("h00"))
    node T_5623 = mux(T_5263, reg_mscratch, UInt<1>("h00"))
    node T_5625 = mux(T_5265, T_5016, UInt<1>("h00"))
    node T_5627 = mux(T_5267, T_5021, UInt<1>("h00"))
    node T_5629 = mux(T_5269, reg_mcause, UInt<1>("h00"))
    node T_5631 = mux(T_5271, reg_mtimecmp, UInt<1>("h00"))
    node T_5633 = mux(T_5273, io.host.id, UInt<1>("h00"))
    node T_5635 = shl(reg_stats, 0)
    node T_5636 = mux(T_5275, T_5635, UInt<1>("h00"))
    node T_5638 = mux(T_5277, reg_tohost, UInt<1>("h00"))
    node T_5640 = mux(T_5279, reg_fromhost, UInt<1>("h00"))
    node T_5642 = mux(T_5281, T_4598, UInt<1>("h00"))
    node T_5644 = mux(T_5283, T_4598, UInt<1>("h00"))
    node T_5646 = mux(T_5285, T_4631, UInt<1>("h00"))
    node T_5648 = mux(T_5287, T_4647, UInt<1>("h00"))
    node T_5650 = mux(T_5289, T_4663, UInt<1>("h00"))
    node T_5652 = mux(T_5291, T_4679, UInt<1>("h00"))
    node T_5654 = mux(T_5293, T_4695, UInt<1>("h00"))
    node T_5656 = mux(T_5295, T_4711, UInt<1>("h00"))
    node T_5658 = mux(T_5297, T_4727, UInt<1>("h00"))
    node T_5660 = mux(T_5299, T_4743, UInt<1>("h00"))
    node T_5662 = mux(T_5301, T_4759, UInt<1>("h00"))
    node T_5664 = mux(T_5303, T_4775, UInt<1>("h00"))
    node T_5666 = mux(T_5305, T_4791, UInt<1>("h00"))
    node T_5668 = mux(T_5307, T_4807, UInt<1>("h00"))
    node T_5670 = mux(T_5309, T_4823, UInt<1>("h00"))
    node T_5672 = mux(T_5311, T_4839, UInt<1>("h00"))
    node T_5674 = mux(T_5313, T_4855, UInt<1>("h00"))
    node T_5676 = mux(T_5315, T_4871, UInt<1>("h00"))
    node T_5678 = mux(T_5317, T_5190, UInt<1>("h00"))
    node T_5680 = mux(T_5319, T_5197, UInt<1>("h00"))
    node T_5682 = mux(T_5321, T_5204, UInt<1>("h00"))
    node T_5684 = mux(T_5323, reg_sscratch, UInt<1>("h00"))
    node T_5686 = mux(T_5325, reg_scause, UInt<1>("h00"))
    node T_5688 = mux(T_5327, T_5209, UInt<1>("h00"))
    node T_5690 = mux(T_5329, reg_sptbr, UInt<1>("h00"))
    node T_5692 = mux(T_5331, UInt<1>("h00"), UInt<1>("h00"))
    node T_5694 = mux(T_5333, T_5215, UInt<1>("h00"))
    node T_5696 = mux(T_5335, T_5220, UInt<1>("h00"))
    node T_5698 = or(T_5583, T_5585)
    node T_5699 = or(T_5698, T_5587)
    node T_5700 = or(T_5699, T_5589)
    node T_5701 = or(T_5700, T_5591)
    node T_5702 = or(T_5701, T_5593)
    node T_5703 = or(T_5702, T_5595)
    node T_5704 = or(T_5703, T_5597)
    node T_5705 = or(T_5704, T_5599)
    node T_5706 = or(T_5705, T_5601)
    node T_5707 = or(T_5706, T_5603)
    node T_5708 = or(T_5707, T_5605)
    node T_5709 = or(T_5708, T_5607)
    node T_5710 = or(T_5709, T_5609)
    node T_5711 = or(T_5710, T_5611)
    node T_5712 = or(T_5711, T_5613)
    node T_5713 = or(T_5712, T_5615)
    node T_5714 = or(T_5713, T_5617)
    node T_5715 = or(T_5714, T_5619)
    node T_5716 = or(T_5715, T_5621)
    node T_5717 = or(T_5716, T_5623)
    node T_5718 = or(T_5717, T_5625)
    node T_5719 = or(T_5718, T_5627)
    node T_5720 = or(T_5719, T_5629)
    node T_5721 = or(T_5720, T_5631)
    node T_5722 = or(T_5721, T_5633)
    node T_5723 = or(T_5722, T_5636)
    node T_5724 = or(T_5723, T_5638)
    node T_5725 = or(T_5724, T_5640)
    node T_5726 = or(T_5725, T_5642)
    node T_5727 = or(T_5726, T_5644)
    node T_5728 = or(T_5727, T_5646)
    node T_5729 = or(T_5728, T_5648)
    node T_5730 = or(T_5729, T_5650)
    node T_5731 = or(T_5730, T_5652)
    node T_5732 = or(T_5731, T_5654)
    node T_5733 = or(T_5732, T_5656)
    node T_5734 = or(T_5733, T_5658)
    node T_5735 = or(T_5734, T_5660)
    node T_5736 = or(T_5735, T_5662)
    node T_5737 = or(T_5736, T_5664)
    node T_5738 = or(T_5737, T_5666)
    node T_5739 = or(T_5738, T_5668)
    node T_5740 = or(T_5739, T_5670)
    node T_5741 = or(T_5740, T_5672)
    node T_5742 = or(T_5741, T_5674)
    node T_5743 = or(T_5742, T_5676)
    node T_5744 = or(T_5743, T_5678)
    node T_5745 = or(T_5744, T_5680)
    node T_5746 = or(T_5745, T_5682)
    node T_5747 = or(T_5746, T_5684)
    node T_5748 = or(T_5747, T_5686)
    node T_5749 = or(T_5748, T_5688)
    node T_5750 = or(T_5749, T_5690)
    node T_5751 = or(T_5750, T_5692)
    node T_5752 = or(T_5751, T_5694)
    node T_5753 = or(T_5752, T_5696)
    wire T_5754 : UInt<64>
    T_5754 is invalid
    T_5754 <= T_5753
    io.rw.rdata <= T_5754
    io.fcsr_rm <= reg_frm
    when io.fcsr_flags.valid :
      node T_5755 = or(reg_fflags, io.fcsr_flags.bits)
      reg_fflags <= T_5755
      skip
    when wen :
      when T_5247 :
        wire T_5790 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}
        T_5790 is invalid
        node T_5807 = bits(wdata, 0, 0)
        T_5790.ie <= T_5807
        node T_5808 = bits(wdata, 2, 1)
        T_5790.prv <= T_5808
        node T_5809 = bits(wdata, 3, 3)
        T_5790.ie1 <= T_5809
        node T_5810 = bits(wdata, 5, 4)
        T_5790.prv1 <= T_5810
        node T_5811 = bits(wdata, 6, 6)
        T_5790.ie2 <= T_5811
        node T_5812 = bits(wdata, 8, 7)
        T_5790.prv2 <= T_5812
        node T_5813 = bits(wdata, 9, 9)
        T_5790.ie3 <= T_5813
        node T_5814 = bits(wdata, 11, 10)
        T_5790.prv3 <= T_5814
        node T_5815 = bits(wdata, 13, 12)
        T_5790.fs <= T_5815
        node T_5816 = bits(wdata, 15, 14)
        T_5790.xs <= T_5816
        node T_5817 = bits(wdata, 16, 16)
        T_5790.mprv <= T_5817
        node T_5818 = bits(wdata, 21, 17)
        T_5790.vm <= T_5818
        node T_5819 = bits(wdata, 30, 22)
        T_5790.zero1 <= T_5819
        node T_5820 = bits(wdata, 31, 31)
        T_5790.sd_rv32 <= T_5820
        node T_5821 = bits(wdata, 62, 32)
        T_5790.zero2 <= T_5821
        node T_5822 = bits(wdata, 63, 63)
        T_5790.sd <= T_5822
        reg_mstatus.ie <= T_5790.ie
        reg_mstatus.ie1 <= T_5790.ie1
        wire T_5827 : UInt<2>[3]
        T_5827[0] <= UInt<2>("h03")
        T_5827[1] <= UInt<1>("h00")
        T_5827[2] <= UInt<1>("h01")
        reg_mstatus.mprv <= T_5790.mprv
        node T_5832 = eq(T_5827[0], T_5790.prv)
        node T_5833 = eq(T_5827[1], T_5790.prv)
        node T_5834 = eq(T_5827[2], T_5790.prv)
        node T_5836 = or(UInt<1>("h00"), T_5832)
        node T_5837 = or(T_5836, T_5833)
        node T_5838 = or(T_5837, T_5834)
        when T_5838 :
          reg_mstatus.prv <= T_5790.prv
          skip
        node T_5839 = eq(T_5827[0], T_5790.prv1)
        node T_5840 = eq(T_5827[1], T_5790.prv1)
        node T_5841 = eq(T_5827[2], T_5790.prv1)
        node T_5843 = or(UInt<1>("h00"), T_5839)
        node T_5844 = or(T_5843, T_5840)
        node T_5845 = or(T_5844, T_5841)
        when T_5845 :
          reg_mstatus.prv1 <= T_5790.prv1
          skip
        node T_5846 = eq(T_5827[0], T_5790.prv2)
        node T_5847 = eq(T_5827[1], T_5790.prv2)
        node T_5848 = eq(T_5827[2], T_5790.prv2)
        node T_5850 = or(UInt<1>("h00"), T_5846)
        node T_5851 = or(T_5850, T_5847)
        node T_5852 = or(T_5851, T_5848)
        when T_5852 :
          reg_mstatus.prv2 <= T_5790.prv2
          skip
        reg_mstatus.ie2 <= T_5790.ie2
        node T_5854 = eq(T_5790.vm, UInt<1>("h00"))
        when T_5854 :
          reg_mstatus.vm <= UInt<1>("h00")
          skip
        node T_5857 = eq(T_5790.vm, UInt<4>("h09"))
        when T_5857 :
          reg_mstatus.vm <= UInt<4>("h09")
          skip
        reg_mstatus.fs <= T_5790.fs
        skip
      when T_5259 :
        wire T_5877 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
        T_5877 is invalid
        node T_5886 = bits(wdata, 0, 0)
        T_5877.usip <= T_5886
        node T_5887 = bits(wdata, 1, 1)
        T_5877.ssip <= T_5887
        node T_5888 = bits(wdata, 2, 2)
        T_5877.hsip <= T_5888
        node T_5889 = bits(wdata, 3, 3)
        T_5877.msip <= T_5889
        node T_5890 = bits(wdata, 4, 4)
        T_5877.utip <= T_5890
        node T_5891 = bits(wdata, 5, 5)
        T_5877.stip <= T_5891
        node T_5892 = bits(wdata, 6, 6)
        T_5877.htip <= T_5892
        node T_5893 = bits(wdata, 7, 7)
        T_5877.mtip <= T_5893
        reg_mip.ssip <= T_5877.ssip
        reg_mip.stip <= T_5877.stip
        reg_mip.msip <= T_5877.msip
        skip
      when T_5257 :
        node T_5894 = bits(wdata, 0, 0)
        reg_mip.msip <= T_5894
        skip
      when T_5261 :
        wire T_5913 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
        T_5913 is invalid
        node T_5922 = bits(wdata, 0, 0)
        T_5913.usip <= T_5922
        node T_5923 = bits(wdata, 1, 1)
        T_5913.ssip <= T_5923
        node T_5924 = bits(wdata, 2, 2)
        T_5913.hsip <= T_5924
        node T_5925 = bits(wdata, 3, 3)
        T_5913.msip <= T_5925
        node T_5926 = bits(wdata, 4, 4)
        T_5913.utip <= T_5926
        node T_5927 = bits(wdata, 5, 5)
        T_5913.stip <= T_5927
        node T_5928 = bits(wdata, 6, 6)
        T_5913.htip <= T_5928
        node T_5929 = bits(wdata, 7, 7)
        T_5913.mtip <= T_5929
        reg_mie.ssip <= T_5913.ssip
        reg_mie.stip <= T_5913.stip
        reg_mie.msip <= T_5913.msip
        reg_mie.mtip <= T_5913.mtip
        skip
      when T_5223 :
        reg_fflags <= wdata
        skip
      when T_5225 :
        reg_frm <= wdata
        skip
      when T_5227 :
        reg_fflags <= wdata
        node T_5930 = shr(wdata, 5)
        reg_frm <= T_5930
        skip
      when T_5265 :
        node T_5931 = not(wdata)
        node T_5933 = or(T_5931, UInt<2>("h03"))
        node T_5934 = not(T_5933)
        reg_mepc <= T_5934
        skip
      when T_5263 :
        reg_mscratch <= wdata
        skip
      when T_5269 :
        node T_5936 = and(wdata, UInt<64>("h0800000000000001f"))
        reg_mcause <= T_5936
        skip
      when T_5267 :
        node T_5937 = bits(wdata, 39, 0)
        reg_mbadaddr <= T_5937
        skip
      when T_5283 :
        node T_5938 = bits(wdata, 5, 0)
        T_4584 <= T_5938
        node T_5939 = bits(wdata, 63, 6)
        T_4592 <= T_5939
        skip
      when T_5271 :
        reg_mtimecmp <= wdata
        reg_mip.mtip <= UInt<1>("h00")
        skip
      when T_5241 :
        reg_time <= wdata
        skip
      when T_5279 :
        node T_5942 = eq(reg_fromhost, UInt<1>("h00"))
        node T_5944 = eq(host_csr_req_fire, UInt<1>("h00"))
        node T_5945 = or(T_5942, T_5944)
        when T_5945 :
          reg_fromhost <= wdata
          skip
        skip
      when T_5277 :
        node T_5947 = eq(reg_tohost, UInt<1>("h00"))
        node T_5948 = or(T_5947, host_csr_req_fire)
        when T_5948 :
          reg_tohost <= wdata
          skip
        skip
      when T_5275 :
        node T_5949 = bits(wdata, 0, 0)
        reg_stats <= T_5949
        skip
      when T_5317 :
        wire T_5976 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>}
        T_5976 is invalid
        node T_5989 = bits(wdata, 0, 0)
        T_5976.ie <= T_5989
        node T_5990 = bits(wdata, 2, 1)
        T_5976.zero1 <= T_5990
        node T_5991 = bits(wdata, 3, 3)
        T_5976.pie <= T_5991
        node T_5992 = bits(wdata, 4, 4)
        T_5976.ps <= T_5992
        node T_5993 = bits(wdata, 11, 5)
        T_5976.zero2 <= T_5993
        node T_5994 = bits(wdata, 13, 12)
        T_5976.fs <= T_5994
        node T_5995 = bits(wdata, 15, 14)
        T_5976.xs <= T_5995
        node T_5996 = bits(wdata, 16, 16)
        T_5976.mprv <= T_5996
        node T_5997 = bits(wdata, 30, 17)
        T_5976.zero3 <= T_5997
        node T_5998 = bits(wdata, 31, 31)
        T_5976.sd_rv32 <= T_5998
        node T_5999 = bits(wdata, 62, 32)
        T_5976.zero4 <= T_5999
        node T_6000 = bits(wdata, 63, 63)
        T_5976.sd <= T_6000
        reg_mstatus.ie <= T_5976.ie
        reg_mstatus.ie1 <= T_5976.pie
        node T_6003 = mux(T_5976.ps, UInt<1>("h01"), UInt<1>("h00"))
        reg_mstatus.prv1 <= T_6003
        reg_mstatus.mprv <= T_5976.mprv
        reg_mstatus.fs <= T_5976.fs
        skip
      when T_5319 :
        wire T_6022 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
        T_6022 is invalid
        node T_6031 = bits(wdata, 0, 0)
        T_6022.usip <= T_6031
        node T_6032 = bits(wdata, 1, 1)
        T_6022.ssip <= T_6032
        node T_6033 = bits(wdata, 2, 2)
        T_6022.hsip <= T_6033
        node T_6034 = bits(wdata, 3, 3)
        T_6022.msip <= T_6034
        node T_6035 = bits(wdata, 4, 4)
        T_6022.utip <= T_6035
        node T_6036 = bits(wdata, 5, 5)
        T_6022.stip <= T_6036
        node T_6037 = bits(wdata, 6, 6)
        T_6022.htip <= T_6037
        node T_6038 = bits(wdata, 7, 7)
        T_6022.mtip <= T_6038
        reg_mip.ssip <= T_6022.ssip
        skip
      when T_5321 :
        wire T_6057 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
        T_6057 is invalid
        node T_6066 = bits(wdata, 0, 0)
        T_6057.usip <= T_6066
        node T_6067 = bits(wdata, 1, 1)
        T_6057.ssip <= T_6067
        node T_6068 = bits(wdata, 2, 2)
        T_6057.hsip <= T_6068
        node T_6069 = bits(wdata, 3, 3)
        T_6057.msip <= T_6069
        node T_6070 = bits(wdata, 4, 4)
        T_6057.utip <= T_6070
        node T_6071 = bits(wdata, 5, 5)
        T_6057.stip <= T_6071
        node T_6072 = bits(wdata, 6, 6)
        T_6057.htip <= T_6072
        node T_6073 = bits(wdata, 7, 7)
        T_6057.mtip <= T_6073
        reg_mie.ssip <= T_6057.ssip
        reg_mie.stip <= T_6057.stip
        skip
      when T_5323 :
        reg_sscratch <= wdata
        skip
      when T_5329 :
        node T_6074 = bits(wdata, 31, 12)
        node T_6076 = cat(T_6074, UInt<12>("h00"))
        reg_sptbr <= T_6076
        skip
      when T_5333 :
        node T_6077 = not(wdata)
        node T_6079 = or(T_6077, UInt<2>("h03"))
        node T_6080 = not(T_6079)
        reg_sepc <= T_6080
        skip
      when T_5335 :
        node T_6081 = not(wdata)
        node T_6083 = or(T_6081, UInt<2>("h03"))
        node T_6084 = not(T_6083)
        reg_stvec <= T_6084
        skip
      skip
    when reset :
      reg_mstatus.zero1 <= UInt<1>("h00")
      reg_mstatus.zero2 <= UInt<1>("h00")
      reg_mstatus.ie <= UInt<1>("h00")
      reg_mstatus.prv <= UInt<2>("h03")
      reg_mstatus.ie1 <= UInt<1>("h00")
      reg_mstatus.prv1 <= UInt<2>("h03")
      reg_mstatus.ie2 <= UInt<1>("h00")
      reg_mstatus.prv2 <= UInt<1>("h00")
      reg_mstatus.ie3 <= UInt<1>("h00")
      reg_mstatus.prv3 <= UInt<1>("h00")
      reg_mstatus.mprv <= UInt<1>("h00")
      reg_mstatus.vm <= UInt<1>("h00")
      reg_mstatus.fs <= UInt<1>("h00")
      reg_mstatus.xs <= UInt<1>("h00")
      reg_mstatus.sd_rv32 <= UInt<1>("h00")
      reg_mstatus.sd <= UInt<1>("h00")
      skip
    
  module ALU : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>}
    
    io is invalid
    node T_11 = bits(io.fn, 3, 3)
    node T_12 = not(io.in2)
    node in2_inv = mux(T_11, T_12, io.in2)
    node in1_xor_in2 = xor(io.in1, in2_inv)
    node T_15 = add(io.in1, in2_inv)
    node T_16 = tail(T_15, 1)
    node T_17 = bits(io.fn, 3, 3)
    node T_18 = add(T_16, T_17)
    node T_19 = tail(T_18, 1)
    io.adder_out <= T_19
    node T_20 = bits(io.fn, 0, 0)
    node T_21 = bits(io.fn, 3, 3)
    node T_23 = eq(T_21, UInt<1>("h00"))
    node T_25 = eq(in1_xor_in2, UInt<1>("h00"))
    node T_26 = bits(io.in1, 63, 63)
    node T_27 = bits(io.in2, 63, 63)
    node T_28 = eq(T_26, T_27)
    node T_29 = bits(io.adder_out, 63, 63)
    node T_30 = bits(io.fn, 1, 1)
    node T_31 = bits(io.in2, 63, 63)
    node T_32 = bits(io.in1, 63, 63)
    node T_33 = mux(T_30, T_31, T_32)
    node T_34 = mux(T_28, T_29, T_33)
    node T_35 = mux(T_23, T_25, T_34)
    node T_36 = xor(T_20, T_35)
    io.cmp_out <= T_36
    node T_37 = bits(io.fn, 3, 3)
    node T_38 = bits(io.in1, 31, 31)
    node T_39 = and(T_37, T_38)
    node T_41 = sub(UInt<32>("h00"), T_39)
    node T_42 = tail(T_41, 1)
    node T_45 = and(io.dw, UInt<1>("h01"))
    node T_46 = eq(UInt<1>("h01"), T_45)
    node T_47 = bits(io.in1, 63, 32)
    node T_48 = mux(T_46, T_47, T_42)
    node T_49 = bits(io.in2, 5, 5)
    node T_52 = and(io.dw, UInt<1>("h01"))
    node T_53 = eq(UInt<1>("h01"), T_52)
    node T_54 = and(T_49, T_53)
    node T_55 = bits(io.in2, 4, 0)
    node shamt = cat(T_54, T_55)
    node T_57 = bits(io.in1, 31, 0)
    node shin_r = cat(T_48, T_57)
    node T_59 = eq(io.fn, UInt<3>("h05"))
    node T_60 = eq(io.fn, UInt<4>("h0b"))
    node T_61 = or(T_59, T_60)
    node T_64 = shl(UInt<32>("h0ffffffff"), 32)
    node T_65 = xor(UInt<64>("h0ffffffffffffffff"), T_64)
    node T_66 = shr(shin_r, 32)
    node T_67 = and(T_66, T_65)
    node T_68 = bits(shin_r, 31, 0)
    node T_69 = shl(T_68, 32)
    node T_70 = not(T_65)
    node T_71 = and(T_69, T_70)
    node T_72 = or(T_67, T_71)
    node T_73 = bits(T_65, 47, 0)
    node T_74 = shl(T_73, 16)
    node T_75 = xor(T_65, T_74)
    node T_76 = shr(T_72, 16)
    node T_77 = and(T_76, T_75)
    node T_78 = bits(T_72, 47, 0)
    node T_79 = shl(T_78, 16)
    node T_80 = not(T_75)
    node T_81 = and(T_79, T_80)
    node T_82 = or(T_77, T_81)
    node T_83 = bits(T_75, 55, 0)
    node T_84 = shl(T_83, 8)
    node T_85 = xor(T_75, T_84)
    node T_86 = shr(T_82, 8)
    node T_87 = and(T_86, T_85)
    node T_88 = bits(T_82, 55, 0)
    node T_89 = shl(T_88, 8)
    node T_90 = not(T_85)
    node T_91 = and(T_89, T_90)
    node T_92 = or(T_87, T_91)
    node T_93 = bits(T_85, 59, 0)
    node T_94 = shl(T_93, 4)
    node T_95 = xor(T_85, T_94)
    node T_96 = shr(T_92, 4)
    node T_97 = and(T_96, T_95)
    node T_98 = bits(T_92, 59, 0)
    node T_99 = shl(T_98, 4)
    node T_100 = not(T_95)
    node T_101 = and(T_99, T_100)
    node T_102 = or(T_97, T_101)
    node T_103 = bits(T_95, 61, 0)
    node T_104 = shl(T_103, 2)
    node T_105 = xor(T_95, T_104)
    node T_106 = shr(T_102, 2)
    node T_107 = and(T_106, T_105)
    node T_108 = bits(T_102, 61, 0)
    node T_109 = shl(T_108, 2)
    node T_110 = not(T_105)
    node T_111 = and(T_109, T_110)
    node T_112 = or(T_107, T_111)
    node T_113 = bits(T_105, 62, 0)
    node T_114 = shl(T_113, 1)
    node T_115 = xor(T_105, T_114)
    node T_116 = shr(T_112, 1)
    node T_117 = and(T_116, T_115)
    node T_118 = bits(T_112, 62, 0)
    node T_119 = shl(T_118, 1)
    node T_120 = not(T_115)
    node T_121 = and(T_119, T_120)
    node T_122 = or(T_117, T_121)
    node shin = mux(T_61, shin_r, T_122)
    node T_124 = bits(io.fn, 3, 3)
    node T_125 = bits(shin, 63, 63)
    node T_126 = and(T_124, T_125)
    node T_127 = cat(T_126, shin)
    node T_128 = asSInt(T_127)
    node T_129 = dshr(T_128, shamt)
    node shout_r = bits(T_129, 63, 0)
    node T_133 = shl(UInt<32>("h0ffffffff"), 32)
    node T_134 = xor(UInt<64>("h0ffffffffffffffff"), T_133)
    node T_135 = shr(shout_r, 32)
    node T_136 = and(T_135, T_134)
    node T_137 = bits(shout_r, 31, 0)
    node T_138 = shl(T_137, 32)
    node T_139 = not(T_134)
    node T_140 = and(T_138, T_139)
    node T_141 = or(T_136, T_140)
    node T_142 = bits(T_134, 47, 0)
    node T_143 = shl(T_142, 16)
    node T_144 = xor(T_134, T_143)
    node T_145 = shr(T_141, 16)
    node T_146 = and(T_145, T_144)
    node T_147 = bits(T_141, 47, 0)
    node T_148 = shl(T_147, 16)
    node T_149 = not(T_144)
    node T_150 = and(T_148, T_149)
    node T_151 = or(T_146, T_150)
    node T_152 = bits(T_144, 55, 0)
    node T_153 = shl(T_152, 8)
    node T_154 = xor(T_144, T_153)
    node T_155 = shr(T_151, 8)
    node T_156 = and(T_155, T_154)
    node T_157 = bits(T_151, 55, 0)
    node T_158 = shl(T_157, 8)
    node T_159 = not(T_154)
    node T_160 = and(T_158, T_159)
    node T_161 = or(T_156, T_160)
    node T_162 = bits(T_154, 59, 0)
    node T_163 = shl(T_162, 4)
    node T_164 = xor(T_154, T_163)
    node T_165 = shr(T_161, 4)
    node T_166 = and(T_165, T_164)
    node T_167 = bits(T_161, 59, 0)
    node T_168 = shl(T_167, 4)
    node T_169 = not(T_164)
    node T_170 = and(T_168, T_169)
    node T_171 = or(T_166, T_170)
    node T_172 = bits(T_164, 61, 0)
    node T_173 = shl(T_172, 2)
    node T_174 = xor(T_164, T_173)
    node T_175 = shr(T_171, 2)
    node T_176 = and(T_175, T_174)
    node T_177 = bits(T_171, 61, 0)
    node T_178 = shl(T_177, 2)
    node T_179 = not(T_174)
    node T_180 = and(T_178, T_179)
    node T_181 = or(T_176, T_180)
    node T_182 = bits(T_174, 62, 0)
    node T_183 = shl(T_182, 1)
    node T_184 = xor(T_174, T_183)
    node T_185 = shr(T_181, 1)
    node T_186 = and(T_185, T_184)
    node T_187 = bits(T_181, 62, 0)
    node T_188 = shl(T_187, 1)
    node T_189 = not(T_184)
    node T_190 = and(T_188, T_189)
    node shout_l = or(T_186, T_190)
    node T_192 = eq(io.fn, UInt<3>("h05"))
    node T_193 = eq(io.fn, UInt<4>("h0b"))
    node T_194 = or(T_192, T_193)
    node T_196 = mux(T_194, shout_r, UInt<1>("h00"))
    node T_197 = eq(io.fn, UInt<1>("h01"))
    node T_199 = mux(T_197, shout_l, UInt<1>("h00"))
    node shout = or(T_196, T_199)
    node T_201 = eq(io.fn, UInt<3>("h04"))
    node T_202 = eq(io.fn, UInt<3>("h06"))
    node T_203 = or(T_201, T_202)
    node T_205 = mux(T_203, in1_xor_in2, UInt<1>("h00"))
    node T_206 = eq(io.fn, UInt<3>("h06"))
    node T_207 = eq(io.fn, UInt<3>("h07"))
    node T_208 = or(T_206, T_207)
    node T_209 = and(io.in1, io.in2)
    node T_211 = mux(T_208, T_209, UInt<1>("h00"))
    node logic = or(T_205, T_211)
    node T_213 = eq(io.fn, UInt<2>("h02"))
    node T_214 = eq(io.fn, UInt<2>("h03"))
    node T_215 = or(T_213, T_214)
    node T_216 = geq(io.fn, UInt<4>("h0c"))
    node T_217 = or(T_215, T_216)
    node T_218 = and(T_217, io.cmp_out)
    node T_219 = or(T_218, logic)
    node shift_logic = or(T_219, shout)
    node T_221 = eq(io.fn, UInt<1>("h00"))
    node T_222 = eq(io.fn, UInt<4>("h0a"))
    node T_223 = or(T_221, T_222)
    node out = mux(T_223, io.adder_out, shift_logic)
    io.out <= out
    node T_227 = and(io.dw, UInt<1>("h01"))
    node T_228 = eq(UInt<1>("h00"), T_227)
    when T_228 :
      node T_229 = bits(out, 31, 31)
      node T_231 = sub(UInt<32>("h00"), T_229)
      node T_232 = tail(T_231, 1)
      node T_233 = bits(out, 31, 0)
      node T_234 = cat(T_232, T_233)
      io.out <= T_234
      skip
    
  module MulDiv : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk
    reg count : UInt<7>, clk
    reg neg_out : UInt<1>, clk
    reg isMul : UInt<1>, clk
    reg isHi : UInt<1>, clk
    reg divisor : UInt<65>, clk
    reg remainder : UInt<130>, clk
    node T_81 = and(io.req.bits.fn, UInt<4>("h04"))
    node T_83 = eq(T_81, UInt<4>("h00"))
    node T_85 = and(io.req.bits.fn, UInt<4>("h08"))
    node T_87 = eq(T_85, UInt<4>("h08"))
    node T_89 = or(UInt<1>("h00"), T_83)
    node T_90 = or(T_89, T_87)
    node T_92 = and(io.req.bits.fn, UInt<4>("h05"))
    node T_94 = eq(T_92, UInt<4>("h01"))
    node T_96 = and(io.req.bits.fn, UInt<4>("h02"))
    node T_98 = eq(T_96, UInt<4>("h02"))
    node T_100 = or(UInt<1>("h00"), T_94)
    node T_101 = or(T_100, T_98)
    node T_102 = or(T_101, T_87)
    node T_104 = and(io.req.bits.fn, UInt<4>("h09"))
    node T_106 = eq(T_104, UInt<4>("h00"))
    node T_108 = and(io.req.bits.fn, UInt<4>("h03"))
    node T_110 = eq(T_108, UInt<4>("h00"))
    node T_112 = or(UInt<1>("h00"), T_106)
    node T_113 = or(T_112, T_83)
    node T_114 = or(T_113, T_110)
    node T_116 = or(UInt<1>("h00"), T_106)
    node T_117 = or(T_116, T_83)
    node cmdMul = bits(T_90, 0, 0)
    node cmdHi = bits(T_102, 0, 0)
    node lhsSigned = bits(T_114, 0, 0)
    node rhsSigned = bits(T_117, 0, 0)
    node T_124 = and(io.req.bits.dw, UInt<1>("h01"))
    node T_125 = eq(UInt<1>("h01"), T_124)
    node T_126 = bits(io.req.bits.in1, 63, 63)
    node T_127 = bits(io.req.bits.in1, 31, 31)
    node T_128 = mux(T_125, T_126, T_127)
    node lhs_sign = and(lhsSigned, T_128)
    node T_132 = and(io.req.bits.dw, UInt<1>("h01"))
    node T_133 = eq(UInt<1>("h01"), T_132)
    node T_134 = bits(io.req.bits.in1, 63, 32)
    node T_136 = sub(UInt<32>("h00"), lhs_sign)
    node T_137 = tail(T_136, 1)
    node T_138 = mux(T_133, T_134, T_137)
    node T_139 = bits(io.req.bits.in1, 31, 0)
    node lhs_in = cat(T_138, T_139)
    node T_143 = and(io.req.bits.dw, UInt<1>("h01"))
    node T_144 = eq(UInt<1>("h01"), T_143)
    node T_145 = bits(io.req.bits.in2, 63, 63)
    node T_146 = bits(io.req.bits.in2, 31, 31)
    node T_147 = mux(T_144, T_145, T_146)
    node rhs_sign = and(rhsSigned, T_147)
    node T_151 = and(io.req.bits.dw, UInt<1>("h01"))
    node T_152 = eq(UInt<1>("h01"), T_151)
    node T_153 = bits(io.req.bits.in2, 63, 32)
    node T_155 = sub(UInt<32>("h00"), rhs_sign)
    node T_156 = tail(T_155, 1)
    node T_157 = mux(T_152, T_153, T_156)
    node T_158 = bits(io.req.bits.in2, 31, 0)
    node rhs_in = cat(T_157, T_158)
    node T_160 = bits(remainder, 128, 64)
    node T_161 = bits(divisor, 64, 0)
    node T_162 = sub(T_160, T_161)
    node subtractor = tail(T_162, 1)
    node less = bits(subtractor, 64, 64)
    node T_165 = bits(remainder, 63, 0)
    node T_167 = sub(UInt<1>("h00"), T_165)
    node negated_remainder = tail(T_167, 1)
    node T_169 = eq(state, UInt<1>("h01"))
    when T_169 :
      node T_170 = bits(remainder, 63, 63)
      node T_171 = or(T_170, isMul)
      when T_171 :
        remainder <= negated_remainder
        skip
      node T_172 = bits(divisor, 63, 63)
      node T_173 = or(T_172, isMul)
      when T_173 :
        divisor <= subtractor
        skip
      state <= UInt<2>("h02")
      skip
    node T_174 = eq(state, UInt<3>("h04"))
    when T_174 :
      remainder <= negated_remainder
      state <= UInt<3>("h05")
      skip
    node T_175 = eq(state, UInt<2>("h03"))
    when T_175 :
      node T_176 = bits(remainder, 128, 65)
      remainder <= T_176
      node T_177 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05"))
      state <= T_177
      skip
    node T_178 = eq(state, UInt<2>("h02"))
    node T_179 = and(T_178, isMul)
    when T_179 :
      node T_180 = bits(remainder, 129, 65)
      node T_181 = bits(remainder, 63, 0)
      node T_182 = cat(T_180, T_181)
      node T_183 = bits(T_182, 63, 0)
      node T_184 = bits(T_182, 128, 64)
      node T_185 = asSInt(T_184)
      node T_186 = asSInt(divisor)
      node T_187 = bits(T_183, 7, 0)
      node T_188 = mul(T_186, T_187)
      node T_189 = add(T_188, T_185)
      node T_190 = tail(T_189, 1)
      node T_191 = asSInt(T_190)
      node T_192 = bits(T_183, 63, 8)
      node T_193 = asUInt(T_191)
      node T_194 = cat(T_193, T_192)
      node T_197 = mul(count, UInt<4>("h08"))
      node T_198 = bits(T_197, 5, 0)
      node T_199 = dshr(asSInt(UInt<65>("h010000000000000000")), T_198)
      node T_200 = bits(T_199, 63, 0)
      node T_203 = neq(count, UInt<3>("h07"))
      node T_204 = and(UInt<1>("h01"), T_203)
      node T_206 = neq(count, UInt<1>("h00"))
      node T_207 = and(T_204, T_206)
      node T_209 = eq(isHi, UInt<1>("h00"))
      node T_210 = and(T_207, T_209)
      node T_211 = not(T_200)
      node T_212 = and(T_183, T_211)
      node T_214 = eq(T_212, UInt<1>("h00"))
      node T_215 = and(T_210, T_214)
      node T_218 = mul(count, UInt<4>("h08"))
      node T_219 = sub(UInt<7>("h040"), T_218)
      node T_220 = tail(T_219, 1)
      node T_221 = bits(T_220, 5, 0)
      node T_222 = dshr(T_182, T_221)
      node T_223 = bits(T_194, 128, 64)
      node T_224 = mux(T_215, T_222, T_194)
      node T_225 = bits(T_224, 63, 0)
      node T_226 = cat(T_223, T_225)
      node T_227 = shr(T_226, 64)
      node T_229 = bits(T_226, 63, 0)
      node T_230 = cat(UInt<1>("h00"), T_229)
      node T_231 = cat(T_227, T_230)
      remainder <= T_231
      node T_233 = add(count, UInt<1>("h01"))
      node T_234 = tail(T_233, 1)
      count <= T_234
      node T_236 = eq(count, UInt<3>("h07"))
      node T_237 = or(T_215, T_236)
      when T_237 :
        node T_238 = mux(isHi, UInt<2>("h03"), UInt<3>("h05"))
        state <= T_238
        skip
      skip
    node T_239 = eq(state, UInt<2>("h02"))
    node T_241 = eq(isMul, UInt<1>("h00"))
    node T_242 = and(T_239, T_241)
    when T_242 :
      node T_244 = eq(count, UInt<7>("h040"))
      when T_244 :
        node T_245 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05"))
        node T_246 = mux(isHi, UInt<2>("h03"), T_245)
        state <= T_246
        skip
      node T_248 = add(count, UInt<1>("h01"))
      node T_249 = tail(T_248, 1)
      count <= T_249
      node T_250 = bits(remainder, 127, 64)
      node T_251 = bits(subtractor, 63, 0)
      node T_252 = mux(less, T_250, T_251)
      node T_253 = bits(remainder, 63, 0)
      node T_255 = eq(less, UInt<1>("h00"))
      node T_256 = cat(T_253, T_255)
      node T_257 = cat(T_252, T_256)
      remainder <= T_257
      node T_258 = bits(divisor, 63, 0)
      node T_259 = bits(T_258, 63, 63)
      node T_261 = bits(T_258, 62, 62)
      node T_263 = bits(T_258, 61, 61)
      node T_265 = bits(T_258, 60, 60)
      node T_267 = bits(T_258, 59, 59)
      node T_269 = bits(T_258, 58, 58)
      node T_271 = bits(T_258, 57, 57)
      node T_273 = bits(T_258, 56, 56)
      node T_275 = bits(T_258, 55, 55)
      node T_277 = bits(T_258, 54, 54)
      node T_279 = bits(T_258, 53, 53)
      node T_281 = bits(T_258, 52, 52)
      node T_283 = bits(T_258, 51, 51)
      node T_285 = bits(T_258, 50, 50)
      node T_287 = bits(T_258, 49, 49)
      node T_289 = bits(T_258, 48, 48)
      node T_291 = bits(T_258, 47, 47)
      node T_293 = bits(T_258, 46, 46)
      node T_295 = bits(T_258, 45, 45)
      node T_297 = bits(T_258, 44, 44)
      node T_299 = bits(T_258, 43, 43)
      node T_301 = bits(T_258, 42, 42)
      node T_303 = bits(T_258, 41, 41)
      node T_305 = bits(T_258, 40, 40)
      node T_307 = bits(T_258, 39, 39)
      node T_309 = bits(T_258, 38, 38)
      node T_311 = bits(T_258, 37, 37)
      node T_313 = bits(T_258, 36, 36)
      node T_315 = bits(T_258, 35, 35)
      node T_317 = bits(T_258, 34, 34)
      node T_319 = bits(T_258, 33, 33)
      node T_321 = bits(T_258, 32, 32)
      node T_323 = bits(T_258, 31, 31)
      node T_325 = bits(T_258, 30, 30)
      node T_327 = bits(T_258, 29, 29)
      node T_329 = bits(T_258, 28, 28)
      node T_331 = bits(T_258, 27, 27)
      node T_333 = bits(T_258, 26, 26)
      node T_335 = bits(T_258, 25, 25)
      node T_337 = bits(T_258, 24, 24)
      node T_339 = bits(T_258, 23, 23)
      node T_341 = bits(T_258, 22, 22)
      node T_343 = bits(T_258, 21, 21)
      node T_345 = bits(T_258, 20, 20)
      node T_347 = bits(T_258, 19, 19)
      node T_349 = bits(T_258, 18, 18)
      node T_351 = bits(T_258, 17, 17)
      node T_353 = bits(T_258, 16, 16)
      node T_355 = bits(T_258, 15, 15)
      node T_357 = bits(T_258, 14, 14)
      node T_359 = bits(T_258, 13, 13)
      node T_361 = bits(T_258, 12, 12)
      node T_363 = bits(T_258, 11, 11)
      node T_365 = bits(T_258, 10, 10)
      node T_367 = bits(T_258, 9, 9)
      node T_369 = bits(T_258, 8, 8)
      node T_371 = bits(T_258, 7, 7)
      node T_373 = bits(T_258, 6, 6)
      node T_375 = bits(T_258, 5, 5)
      node T_377 = bits(T_258, 4, 4)
      node T_379 = bits(T_258, 3, 3)
      node T_381 = bits(T_258, 2, 2)
      node T_383 = bits(T_258, 1, 1)
      node T_384 = shl(T_383, 0)
      node T_385 = mux(T_381, UInt<2>("h02"), T_384)
      node T_386 = mux(T_379, UInt<2>("h03"), T_385)
      node T_387 = mux(T_377, UInt<3>("h04"), T_386)
      node T_388 = mux(T_375, UInt<3>("h05"), T_387)
      node T_389 = mux(T_373, UInt<3>("h06"), T_388)
      node T_390 = mux(T_371, UInt<3>("h07"), T_389)
      node T_391 = mux(T_369, UInt<4>("h08"), T_390)
      node T_392 = mux(T_367, UInt<4>("h09"), T_391)
      node T_393 = mux(T_365, UInt<4>("h0a"), T_392)
      node T_394 = mux(T_363, UInt<4>("h0b"), T_393)
      node T_395 = mux(T_361, UInt<4>("h0c"), T_394)
      node T_396 = mux(T_359, UInt<4>("h0d"), T_395)
      node T_397 = mux(T_357, UInt<4>("h0e"), T_396)
      node T_398 = mux(T_355, UInt<4>("h0f"), T_397)
      node T_399 = mux(T_353, UInt<5>("h010"), T_398)
      node T_400 = mux(T_351, UInt<5>("h011"), T_399)
      node T_401 = mux(T_349, UInt<5>("h012"), T_400)
      node T_402 = mux(T_347, UInt<5>("h013"), T_401)
      node T_403 = mux(T_345, UInt<5>("h014"), T_402)
      node T_404 = mux(T_343, UInt<5>("h015"), T_403)
      node T_405 = mux(T_341, UInt<5>("h016"), T_404)
      node T_406 = mux(T_339, UInt<5>("h017"), T_405)
      node T_407 = mux(T_337, UInt<5>("h018"), T_406)
      node T_408 = mux(T_335, UInt<5>("h019"), T_407)
      node T_409 = mux(T_333, UInt<5>("h01a"), T_408)
      node T_410 = mux(T_331, UInt<5>("h01b"), T_409)
      node T_411 = mux(T_329, UInt<5>("h01c"), T_410)
      node T_412 = mux(T_327, UInt<5>("h01d"), T_411)
      node T_413 = mux(T_325, UInt<5>("h01e"), T_412)
      node T_414 = mux(T_323, UInt<5>("h01f"), T_413)
      node T_415 = mux(T_321, UInt<6>("h020"), T_414)
      node T_416 = mux(T_319, UInt<6>("h021"), T_415)
      node T_417 = mux(T_317, UInt<6>("h022"), T_416)
      node T_418 = mux(T_315, UInt<6>("h023"), T_417)
      node T_419 = mux(T_313, UInt<6>("h024"), T_418)
      node T_420 = mux(T_311, UInt<6>("h025"), T_419)
      node T_421 = mux(T_309, UInt<6>("h026"), T_420)
      node T_422 = mux(T_307, UInt<6>("h027"), T_421)
      node T_423 = mux(T_305, UInt<6>("h028"), T_422)
      node T_424 = mux(T_303, UInt<6>("h029"), T_423)
      node T_425 = mux(T_301, UInt<6>("h02a"), T_424)
      node T_426 = mux(T_299, UInt<6>("h02b"), T_425)
      node T_427 = mux(T_297, UInt<6>("h02c"), T_426)
      node T_428 = mux(T_295, UInt<6>("h02d"), T_427)
      node T_429 = mux(T_293, UInt<6>("h02e"), T_428)
      node T_430 = mux(T_291, UInt<6>("h02f"), T_429)
      node T_431 = mux(T_289, UInt<6>("h030"), T_430)
      node T_432 = mux(T_287, UInt<6>("h031"), T_431)
      node T_433 = mux(T_285, UInt<6>("h032"), T_432)
      node T_434 = mux(T_283, UInt<6>("h033"), T_433)
      node T_435 = mux(T_281, UInt<6>("h034"), T_434)
      node T_436 = mux(T_279, UInt<6>("h035"), T_435)
      node T_437 = mux(T_277, UInt<6>("h036"), T_436)
      node T_438 = mux(T_275, UInt<6>("h037"), T_437)
      node T_439 = mux(T_273, UInt<6>("h038"), T_438)
      node T_440 = mux(T_271, UInt<6>("h039"), T_439)
      node T_441 = mux(T_269, UInt<6>("h03a"), T_440)
      node T_442 = mux(T_267, UInt<6>("h03b"), T_441)
      node T_443 = mux(T_265, UInt<6>("h03c"), T_442)
      node T_444 = mux(T_263, UInt<6>("h03d"), T_443)
      node T_445 = mux(T_261, UInt<6>("h03e"), T_444)
      node T_446 = mux(T_259, UInt<6>("h03f"), T_445)
      node T_447 = bits(remainder, 63, 0)
      node T_448 = bits(T_447, 63, 63)
      node T_450 = bits(T_447, 62, 62)
      node T_452 = bits(T_447, 61, 61)
      node T_454 = bits(T_447, 60, 60)
      node T_456 = bits(T_447, 59, 59)
      node T_458 = bits(T_447, 58, 58)
      node T_460 = bits(T_447, 57, 57)
      node T_462 = bits(T_447, 56, 56)
      node T_464 = bits(T_447, 55, 55)
      node T_466 = bits(T_447, 54, 54)
      node T_468 = bits(T_447, 53, 53)
      node T_470 = bits(T_447, 52, 52)
      node T_472 = bits(T_447, 51, 51)
      node T_474 = bits(T_447, 50, 50)
      node T_476 = bits(T_447, 49, 49)
      node T_478 = bits(T_447, 48, 48)
      node T_480 = bits(T_447, 47, 47)
      node T_482 = bits(T_447, 46, 46)
      node T_484 = bits(T_447, 45, 45)
      node T_486 = bits(T_447, 44, 44)
      node T_488 = bits(T_447, 43, 43)
      node T_490 = bits(T_447, 42, 42)
      node T_492 = bits(T_447, 41, 41)
      node T_494 = bits(T_447, 40, 40)
      node T_496 = bits(T_447, 39, 39)
      node T_498 = bits(T_447, 38, 38)
      node T_500 = bits(T_447, 37, 37)
      node T_502 = bits(T_447, 36, 36)
      node T_504 = bits(T_447, 35, 35)
      node T_506 = bits(T_447, 34, 34)
      node T_508 = bits(T_447, 33, 33)
      node T_510 = bits(T_447, 32, 32)
      node T_512 = bits(T_447, 31, 31)
      node T_514 = bits(T_447, 30, 30)
      node T_516 = bits(T_447, 29, 29)
      node T_518 = bits(T_447, 28, 28)
      node T_520 = bits(T_447, 27, 27)
      node T_522 = bits(T_447, 26, 26)
      node T_524 = bits(T_447, 25, 25)
      node T_526 = bits(T_447, 24, 24)
      node T_528 = bits(T_447, 23, 23)
      node T_530 = bits(T_447, 22, 22)
      node T_532 = bits(T_447, 21, 21)
      node T_534 = bits(T_447, 20, 20)
      node T_536 = bits(T_447, 19, 19)
      node T_538 = bits(T_447, 18, 18)
      node T_540 = bits(T_447, 17, 17)
      node T_542 = bits(T_447, 16, 16)
      node T_544 = bits(T_447, 15, 15)
      node T_546 = bits(T_447, 14, 14)
      node T_548 = bits(T_447, 13, 13)
      node T_550 = bits(T_447, 12, 12)
      node T_552 = bits(T_447, 11, 11)
      node T_554 = bits(T_447, 10, 10)
      node T_556 = bits(T_447, 9, 9)
      node T_558 = bits(T_447, 8, 8)
      node T_560 = bits(T_447, 7, 7)
      node T_562 = bits(T_447, 6, 6)
      node T_564 = bits(T_447, 5, 5)
      node T_566 = bits(T_447, 4, 4)
      node T_568 = bits(T_447, 3, 3)
      node T_570 = bits(T_447, 2, 2)
      node T_572 = bits(T_447, 1, 1)
      node T_573 = shl(T_572, 0)
      node T_574 = mux(T_570, UInt<2>("h02"), T_573)
      node T_575 = mux(T_568, UInt<2>("h03"), T_574)
      node T_576 = mux(T_566, UInt<3>("h04"), T_575)
      node T_577 = mux(T_564, UInt<3>("h05"), T_576)
      node T_578 = mux(T_562, UInt<3>("h06"), T_577)
      node T_579 = mux(T_560, UInt<3>("h07"), T_578)
      node T_580 = mux(T_558, UInt<4>("h08"), T_579)
      node T_581 = mux(T_556, UInt<4>("h09"), T_580)
      node T_582 = mux(T_554, UInt<4>("h0a"), T_581)
      node T_583 = mux(T_552, UInt<4>("h0b"), T_582)
      node T_584 = mux(T_550, UInt<4>("h0c"), T_583)
      node T_585 = mux(T_548, UInt<4>("h0d"), T_584)
      node T_586 = mux(T_546, UInt<4>("h0e"), T_585)
      node T_587 = mux(T_544, UInt<4>("h0f"), T_586)
      node T_588 = mux(T_542, UInt<5>("h010"), T_587)
      node T_589 = mux(T_540, UInt<5>("h011"), T_588)
      node T_590 = mux(T_538, UInt<5>("h012"), T_589)
      node T_591 = mux(T_536, UInt<5>("h013"), T_590)
      node T_592 = mux(T_534, UInt<5>("h014"), T_591)
      node T_593 = mux(T_532, UInt<5>("h015"), T_592)
      node T_594 = mux(T_530, UInt<5>("h016"), T_593)
      node T_595 = mux(T_528, UInt<5>("h017"), T_594)
      node T_596 = mux(T_526, UInt<5>("h018"), T_595)
      node T_597 = mux(T_524, UInt<5>("h019"), T_596)
      node T_598 = mux(T_522, UInt<5>("h01a"), T_597)
      node T_599 = mux(T_520, UInt<5>("h01b"), T_598)
      node T_600 = mux(T_518, UInt<5>("h01c"), T_599)
      node T_601 = mux(T_516, UInt<5>("h01d"), T_600)
      node T_602 = mux(T_514, UInt<5>("h01e"), T_601)
      node T_603 = mux(T_512, UInt<5>("h01f"), T_602)
      node T_604 = mux(T_510, UInt<6>("h020"), T_603)
      node T_605 = mux(T_508, UInt<6>("h021"), T_604)
      node T_606 = mux(T_506, UInt<6>("h022"), T_605)
      node T_607 = mux(T_504, UInt<6>("h023"), T_606)
      node T_608 = mux(T_502, UInt<6>("h024"), T_607)
      node T_609 = mux(T_500, UInt<6>("h025"), T_608)
      node T_610 = mux(T_498, UInt<6>("h026"), T_609)
      node T_611 = mux(T_496, UInt<6>("h027"), T_610)
      node T_612 = mux(T_494, UInt<6>("h028"), T_611)
      node T_613 = mux(T_492, UInt<6>("h029"), T_612)
      node T_614 = mux(T_490, UInt<6>("h02a"), T_613)
      node T_615 = mux(T_488, UInt<6>("h02b"), T_614)
      node T_616 = mux(T_486, UInt<6>("h02c"), T_615)
      node T_617 = mux(T_484, UInt<6>("h02d"), T_616)
      node T_618 = mux(T_482, UInt<6>("h02e"), T_617)
      node T_619 = mux(T_480, UInt<6>("h02f"), T_618)
      node T_620 = mux(T_478, UInt<6>("h030"), T_619)
      node T_621 = mux(T_476, UInt<6>("h031"), T_620)
      node T_622 = mux(T_474, UInt<6>("h032"), T_621)
      node T_623 = mux(T_472, UInt<6>("h033"), T_622)
      node T_624 = mux(T_470, UInt<6>("h034"), T_623)
      node T_625 = mux(T_468, UInt<6>("h035"), T_624)
      node T_626 = mux(T_466, UInt<6>("h036"), T_625)
      node T_627 = mux(T_464, UInt<6>("h037"), T_626)
      node T_628 = mux(T_462, UInt<6>("h038"), T_627)
      node T_629 = mux(T_460, UInt<6>("h039"), T_628)
      node T_630 = mux(T_458, UInt<6>("h03a"), T_629)
      node T_631 = mux(T_456, UInt<6>("h03b"), T_630)
      node T_632 = mux(T_454, UInt<6>("h03c"), T_631)
      node T_633 = mux(T_452, UInt<6>("h03d"), T_632)
      node T_634 = mux(T_450, UInt<6>("h03e"), T_633)
      node T_635 = mux(T_448, UInt<6>("h03f"), T_634)
      node T_637 = add(UInt<6>("h03f"), T_446)
      node T_638 = tail(T_637, 1)
      node T_639 = sub(T_638, T_635)
      node T_640 = tail(T_639, 1)
      node T_641 = gt(T_446, T_635)
      node T_643 = eq(count, UInt<1>("h00"))
      node T_644 = and(T_643, less)
      node T_646 = gt(T_640, UInt<1>("h00"))
      node T_647 = or(T_646, T_641)
      node T_648 = and(T_644, T_647)
      node T_650 = and(UInt<1>("h01"), T_648)
      when T_650 :
        node T_652 = bits(T_640, 5, 0)
        node T_653 = mux(T_641, UInt<6>("h03f"), T_652)
        node T_654 = bits(remainder, 63, 0)
        node T_655 = dshl(T_654, T_653)
        remainder <= T_655
        count <= T_653
        skip
      node T_657 = eq(count, UInt<1>("h00"))
      node T_659 = eq(less, UInt<1>("h00"))
      node T_660 = and(T_657, T_659)
      node T_662 = eq(isHi, UInt<1>("h00"))
      node T_663 = and(T_660, T_662)
      when T_663 :
        neg_out <= UInt<1>("h00")
        skip
      skip
    node T_665 = and(io.resp.ready, io.resp.valid)
    node T_666 = or(T_665, io.kill)
    when T_666 :
      state <= UInt<1>("h00")
      skip
    node T_667 = and(io.req.ready, io.req.valid)
    when T_667 :
      node T_669 = eq(cmdMul, UInt<1>("h00"))
      node T_670 = and(rhs_sign, T_669)
      node T_671 = or(lhs_sign, T_670)
      node T_672 = mux(T_671, UInt<1>("h01"), UInt<2>("h02"))
      state <= T_672
      isMul <= cmdMul
      isHi <= cmdHi
      count <= UInt<1>("h00")
      node T_675 = eq(cmdMul, UInt<1>("h00"))
      node T_676 = neq(lhs_sign, rhs_sign)
      node T_677 = mux(cmdHi, lhs_sign, T_676)
      node T_678 = and(T_675, T_677)
      neg_out <= T_678
      node T_679 = cat(rhs_sign, rhs_in)
      divisor <= T_679
      remainder <= lhs_in
      req <- io.req.bits
      skip
    io.resp.bits <- req
    node T_682 = and(req.dw, UInt<1>("h01"))
    node T_683 = eq(UInt<1>("h00"), T_682)
    node T_684 = bits(remainder, 31, 31)
    node T_686 = sub(UInt<32>("h00"), T_684)
    node T_687 = tail(T_686, 1)
    node T_688 = bits(remainder, 31, 0)
    node T_689 = cat(T_687, T_688)
    node T_690 = bits(remainder, 63, 0)
    node T_691 = mux(T_683, T_689, T_690)
    io.resp.bits.data <= T_691
    node T_692 = eq(state, UInt<3>("h05"))
    io.resp.valid <= T_692
    node T_693 = eq(state, UInt<1>("h00"))
    io.req.ready <= T_693
    
  module Rocket : 
    input clk : Clock
    input reset : UInt<1>
    output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}}
    
    io is invalid
    reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk
    reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk
    reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk
    reg ex_reg_xcpt_interrupt : UInt<1>, clk
    reg ex_reg_valid : UInt<1>, clk
    reg ex_reg_btb_hit : UInt<1>, clk
    reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk
    reg ex_reg_xcpt : UInt<1>, clk
    reg ex_reg_flush_pipe : UInt<1>, clk
    reg ex_reg_load_use : UInt<1>, clk
    reg ex_reg_cause : UInt, clk
    reg ex_reg_pc : UInt, clk
    reg ex_reg_inst : UInt, clk
    reg mem_reg_xcpt_interrupt : UInt<1>, clk
    reg mem_reg_valid : UInt<1>, clk
    reg mem_reg_btb_hit : UInt<1>, clk
    reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk
    reg mem_reg_xcpt : UInt<1>, clk
    reg mem_reg_replay : UInt<1>, clk
    reg mem_reg_flush_pipe : UInt<1>, clk
    reg mem_reg_cause : UInt, clk
    reg mem_reg_slow_bypass : UInt<1>, clk
    reg mem_reg_pc : UInt, clk
    reg mem_reg_inst : UInt, clk
    reg mem_reg_wdata : UInt, clk
    reg mem_reg_rs2 : UInt, clk
    wire take_pc_mem : UInt<1>
    take_pc_mem is invalid
    reg wb_reg_valid : UInt<1>, clk
    reg wb_reg_xcpt : UInt<1>, clk
    reg wb_reg_replay : UInt<1>, clk
    reg wb_reg_cause : UInt, clk
    reg wb_reg_rocc_pending : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg wb_reg_pc : UInt, clk
    reg wb_reg_inst : UInt, clk
    reg wb_reg_wdata : UInt, clk
    reg wb_reg_rs2 : UInt, clk
    wire take_pc_wb : UInt<1>
    take_pc_wb is invalid
    node take_pc_mem_wb = or(take_pc_wb, take_pc_mem)
    wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}
    id_ctrl is invalid
    node T_6071 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f"))
    node T_6073 = eq(T_6071, UInt<32>("h03"))
    node T_6075 = and(io.imem.resp.bits.data[0], UInt<32>("h0106f"))
    node T_6077 = eq(T_6075, UInt<32>("h03"))
    node T_6079 = and(io.imem.resp.bits.data[0], UInt<32>("h0607f"))
    node T_6081 = eq(T_6079, UInt<32>("h0f"))
    node T_6083 = and(io.imem.resp.bits.data[0], UInt<32>("h07077"))
    node T_6085 = eq(T_6083, UInt<32>("h013"))
    node T_6087 = and(io.imem.resp.bits.data[0], UInt<32>("h05f"))
    node T_6089 = eq(T_6087, UInt<32>("h017"))
    node T_6091 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00007f"))
    node T_6093 = eq(T_6091, UInt<32>("h033"))
    node T_6095 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077"))
    node T_6097 = eq(T_6095, UInt<32>("h033"))
    node T_6099 = and(io.imem.resp.bits.data[0], UInt<32>("h04000073"))
    node T_6101 = eq(T_6099, UInt<32>("h043"))
    node T_6103 = and(io.imem.resp.bits.data[0], UInt<32>("h0e400007f"))
    node T_6105 = eq(T_6103, UInt<32>("h053"))
    node T_6107 = and(io.imem.resp.bits.data[0], UInt<32>("h0707b"))
    node T_6109 = eq(T_6107, UInt<32>("h063"))
    node T_6111 = and(io.imem.resp.bits.data[0], UInt<32>("h07f"))
    node T_6113 = eq(T_6111, UInt<32>("h06f"))
    node T_6115 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffefffff"))
    node T_6117 = eq(T_6115, UInt<32>("h073"))
    node T_6119 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00305f"))
    node T_6121 = eq(T_6119, UInt<32>("h01013"))
    node T_6123 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe00305f"))
    node T_6125 = eq(T_6123, UInt<32>("h0101b"))
    node T_6127 = and(io.imem.resp.bits.data[0], UInt<32>("h0605b"))
    node T_6129 = eq(T_6127, UInt<32>("h02003"))
    node T_6131 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f"))
    node T_6133 = eq(T_6131, UInt<32>("h02013"))
    node T_6135 = and(io.imem.resp.bits.data[0], UInt<32>("h01800607f"))
    node T_6137 = eq(T_6135, UInt<32>("h0202f"))
    node T_6139 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f"))
    node T_6141 = eq(T_6139, UInt<32>("h02073"))
    node T_6143 = and(io.imem.resp.bits.data[0], UInt<32>("h0bc00707f"))
    node T_6145 = eq(T_6143, UInt<32>("h05013"))
    node T_6147 = and(io.imem.resp.bits.data[0], UInt<32>("h0be00705f"))
    node T_6149 = eq(T_6147, UInt<32>("h0501b"))
    node T_6151 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077"))
    node T_6153 = eq(T_6151, UInt<32>("h05033"))
    node T_6155 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe004077"))
    node T_6157 = eq(T_6155, UInt<32>("h02004033"))
    node T_6159 = and(io.imem.resp.bits.data[0], UInt<32>("h0e800607f"))
    node T_6161 = eq(T_6159, UInt<32>("h0800202f"))
    node T_6163 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffdfffff"))
    node T_6165 = eq(T_6163, UInt<32>("h010000073"))
    node T_6167 = and(io.imem.resp.bits.data[0], UInt<32>("h0f9f0607f"))
    node T_6169 = eq(T_6167, UInt<32>("h01000202f"))
    node T_6171 = and(io.imem.resp.bits.data[0], UInt<32>("h0fff07fff"))
    node T_6173 = eq(T_6171, UInt<32>("h010100073"))
    node T_6175 = and(io.imem.resp.bits.data[0], UInt<32>("h0f400607f"))
    node T_6177 = eq(T_6175, UInt<32>("h020000053"))
    node T_6179 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00607f"))
    node T_6181 = eq(T_6179, UInt<32>("h020000053"))
    node T_6183 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00507f"))
    node T_6185 = eq(T_6183, UInt<32>("h020000053"))
    node T_6187 = eq(io.imem.resp.bits.data[0], UInt<32>("h030500073"))
    node T_6189 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f"))
    node T_6191 = eq(T_6189, UInt<32>("h040100053"))
    node T_6193 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f"))
    node T_6195 = eq(T_6193, UInt<32>("h042000053"))
    node T_6197 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0007f"))
    node T_6199 = eq(T_6197, UInt<32>("h058000053"))
    node T_6201 = and(io.imem.resp.bits.data[0], UInt<32>("h0edc0007f"))
    node T_6203 = eq(T_6201, UInt<32>("h0c0000053"))
    node T_6205 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0607f"))
    node T_6207 = eq(T_6205, UInt<32>("h0e0000053"))
    node T_6209 = and(io.imem.resp.bits.data[0], UInt<32>("h0edf0707f"))
    node T_6211 = eq(T_6209, UInt<32>("h0e0000053"))
    node T_6213 = and(io.imem.resp.bits.data[0], UInt<32>("h0603f"))
    node T_6215 = eq(T_6213, UInt<32>("h023"))
    node T_6217 = and(io.imem.resp.bits.data[0], UInt<32>("h0306f"))
    node T_6219 = eq(T_6217, UInt<32>("h01063"))
    node T_6221 = and(io.imem.resp.bits.data[0], UInt<32>("h0407f"))
    node T_6223 = eq(T_6221, UInt<32>("h04063"))
    node T_6225 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc007077"))
    node T_6227 = eq(T_6225, UInt<32>("h033"))
    node T_6229 = or(UInt<1>("h00"), T_6073)
    node T_6230 = or(T_6229, T_6077)
    node T_6231 = or(T_6230, T_6081)
    node T_6232 = or(T_6231, T_6085)
    node T_6233 = or(T_6232, T_6089)
    node T_6234 = or(T_6233, T_6093)
    node T_6235 = or(T_6234, T_6097)
    node T_6236 = or(T_6235, T_6101)
    node T_6237 = or(T_6236, T_6105)
    node T_6238 = or(T_6237, T_6109)
    node T_6239 = or(T_6238, T_6113)
    node T_6240 = or(T_6239, T_6117)
    node T_6241 = or(T_6240, T_6121)
    node T_6242 = or(T_6241, T_6125)
    node T_6243 = or(T_6242, T_6129)
    node T_6244 = or(T_6243, T_6133)
    node T_6245 = or(T_6244, T_6137)
    node T_6246 = or(T_6245, T_6141)
    node T_6247 = or(T_6246, T_6145)
    node T_6248 = or(T_6247, T_6149)
    node T_6249 = or(T_6248, T_6153)
    node T_6250 = or(T_6249, T_6157)
    node T_6251 = or(T_6250, T_6161)
    node T_6252 = or(T_6251, T_6165)
    node T_6253 = or(T_6252, T_6169)
    node T_6254 = or(T_6253, T_6173)
    node T_6255 = or(T_6254, T_6177)
    node T_6256 = or(T_6255, T_6181)
    node T_6257 = or(T_6256, T_6185)
    node T_6258 = or(T_6257, T_6187)
    node T_6259 = or(T_6258, T_6191)
    node T_6260 = or(T_6259, T_6195)
    node T_6261 = or(T_6260, T_6199)
    node T_6262 = or(T_6261, T_6203)
    node T_6263 = or(T_6262, T_6207)
    node T_6264 = or(T_6263, T_6211)
    node T_6265 = or(T_6264, T_6215)
    node T_6266 = or(T_6265, T_6219)
    node T_6267 = or(T_6266, T_6223)
    node T_6268 = or(T_6267, T_6227)
    node T_6270 = and(io.imem.resp.bits.data[0], UInt<32>("h05c"))
    node T_6272 = eq(T_6270, UInt<32>("h04"))
    node T_6274 = and(io.imem.resp.bits.data[0], UInt<32>("h060"))
    node T_6276 = eq(T_6274, UInt<32>("h040"))
    node T_6278 = or(UInt<1>("h00"), T_6272)
    node T_6279 = or(T_6278, T_6276)
    node T_6282 = and(io.imem.resp.bits.data[0], UInt<32>("h074"))
    node T_6284 = eq(T_6282, UInt<32>("h060"))
    node T_6286 = or(UInt<1>("h00"), T_6284)
    node T_6288 = and(io.imem.resp.bits.data[0], UInt<32>("h068"))
    node T_6290 = eq(T_6288, UInt<32>("h068"))
    node T_6292 = or(UInt<1>("h00"), T_6290)
    node T_6294 = and(io.imem.resp.bits.data[0], UInt<32>("h0203c"))
    node T_6296 = eq(T_6294, UInt<32>("h024"))
    node T_6298 = or(UInt<1>("h00"), T_6296)
    node T_6300 = and(io.imem.resp.bits.data[0], UInt<32>("h064"))
    node T_6302 = eq(T_6300, UInt<32>("h020"))
    node T_6304 = and(io.imem.resp.bits.data[0], UInt<32>("h034"))
    node T_6306 = eq(T_6304, UInt<32>("h020"))
    node T_6308 = and(io.imem.resp.bits.data[0], UInt<32>("h02048"))
    node T_6310 = eq(T_6308, UInt<32>("h02008"))
    node T_6312 = or(UInt<1>("h00"), T_6302)
    node T_6313 = or(T_6312, T_6306)
    node T_6314 = or(T_6313, T_6310)
    node T_6316 = and(io.imem.resp.bits.data[0], UInt<32>("h044"))
    node T_6318 = eq(T_6316, UInt<32>("h00"))
    node T_6320 = and(io.imem.resp.bits.data[0], UInt<32>("h04024"))
    node T_6322 = eq(T_6320, UInt<32>("h020"))
    node T_6324 = and(io.imem.resp.bits.data[0], UInt<32>("h038"))
    node T_6326 = eq(T_6324, UInt<32>("h020"))
    node T_6328 = and(io.imem.resp.bits.data[0], UInt<32>("h02050"))
    node T_6330 = eq(T_6328, UInt<32>("h02000"))
    node T_6332 = and(io.imem.resp.bits.data[0], UInt<32>("h090000034"))
    node T_6334 = eq(T_6332, UInt<32>("h090000010"))
    node T_6336 = or(UInt<1>("h00"), T_6318)
    node T_6337 = or(T_6336, T_6322)
    node T_6338 = or(T_6337, T_6326)
    node T_6339 = or(T_6338, T_6330)
    node T_6340 = or(T_6339, T_6334)
    node T_6342 = and(io.imem.resp.bits.data[0], UInt<32>("h058"))
    node T_6344 = eq(T_6342, UInt<32>("h00"))
    node T_6346 = and(io.imem.resp.bits.data[0], UInt<32>("h020"))
    node T_6348 = eq(T_6346, UInt<32>("h00"))
    node T_6350 = and(io.imem.resp.bits.data[0], UInt<32>("h0c"))
    node T_6352 = eq(T_6350, UInt<32>("h04"))
    node T_6354 = and(io.imem.resp.bits.data[0], UInt<32>("h048"))
    node T_6356 = eq(T_6354, UInt<32>("h048"))
    node T_6358 = and(io.imem.resp.bits.data[0], UInt<32>("h04050"))
    node T_6360 = eq(T_6358, UInt<32>("h04050"))
    node T_6362 = or(UInt<1>("h00"), T_6344)
    node T_6363 = or(T_6362, T_6348)
    node T_6364 = or(T_6363, T_6352)
    node T_6365 = or(T_6364, T_6356)
    node T_6366 = or(T_6365, T_6360)
    node T_6368 = and(io.imem.resp.bits.data[0], UInt<32>("h048"))
    node T_6370 = eq(T_6368, UInt<32>("h00"))
    node T_6372 = and(io.imem.resp.bits.data[0], UInt<32>("h018"))
    node T_6374 = eq(T_6372, UInt<32>("h00"))
    node T_6376 = and(io.imem.resp.bits.data[0], UInt<32>("h04008"))
    node T_6378 = eq(T_6376, UInt<32>("h04000"))
    node T_6380 = or(UInt<1>("h00"), T_6370)
    node T_6381 = or(T_6380, T_6318)
    node T_6382 = or(T_6381, T_6374)
    node T_6383 = or(T_6382, T_6378)
    node T_6384 = cat(T_6383, T_6366)
    node T_6386 = and(io.imem.resp.bits.data[0], UInt<32>("h04004"))
    node T_6388 = eq(T_6386, UInt<32>("h00"))
    node T_6390 = and(io.imem.resp.bits.data[0], UInt<32>("h050"))
    node T_6392 = eq(T_6390, UInt<32>("h00"))
    node T_6394 = and(io.imem.resp.bits.data[0], UInt<32>("h024"))
    node T_6396 = eq(T_6394, UInt<32>("h00"))
    node T_6398 = or(UInt<1>("h00"), T_6388)
    node T_6399 = or(T_6398, T_6392)
    node T_6400 = or(T_6399, T_6318)
    node T_6401 = or(T_6400, T_6396)
    node T_6402 = or(T_6401, T_6374)
    node T_6404 = and(io.imem.resp.bits.data[0], UInt<32>("h034"))
    node T_6406 = eq(T_6404, UInt<32>("h014"))
    node T_6408 = or(UInt<1>("h00"), T_6406)
    node T_6409 = or(T_6408, T_6356)
    node T_6410 = cat(T_6409, T_6402)
    node T_6412 = and(io.imem.resp.bits.data[0], UInt<32>("h018"))
    node T_6414 = eq(T_6412, UInt<32>("h08"))
    node T_6416 = and(io.imem.resp.bits.data[0], UInt<32>("h044"))
    node T_6418 = eq(T_6416, UInt<32>("h040"))
    node T_6420 = or(UInt<1>("h00"), T_6414)
    node T_6421 = or(T_6420, T_6418)
    node T_6423 = and(io.imem.resp.bits.data[0], UInt<32>("h014"))
    node T_6425 = eq(T_6423, UInt<32>("h014"))
    node T_6427 = or(UInt<1>("h00"), T_6414)
    node T_6428 = or(T_6427, T_6425)
    node T_6430 = and(io.imem.resp.bits.data[0], UInt<32>("h030"))
    node T_6432 = eq(T_6430, UInt<32>("h00"))
    node T_6434 = and(io.imem.resp.bits.data[0], UInt<32>("h0201c"))
    node T_6436 = eq(T_6434, UInt<32>("h04"))
    node T_6438 = and(io.imem.resp.bits.data[0], UInt<32>("h014"))
    node T_6440 = eq(T_6438, UInt<32>("h010"))
    node T_6442 = or(UInt<1>("h00"), T_6432)
    node T_6443 = or(T_6442, T_6436)
    node T_6444 = or(T_6443, T_6440)
    node T_6445 = cat(T_6428, T_6421)
    node T_6446 = cat(T_6444, T_6445)
    node T_6448 = and(io.imem.resp.bits.data[0], UInt<32>("h010"))
    node T_6450 = eq(T_6448, UInt<32>("h00"))
    node T_6452 = and(io.imem.resp.bits.data[0], UInt<32>("h08"))
    node T_6454 = eq(T_6452, UInt<32>("h00"))
    node T_6456 = or(UInt<1>("h00"), T_6450)
    node T_6457 = or(T_6456, T_6454)
    node T_6459 = and(io.imem.resp.bits.data[0], UInt<32>("h03054"))
    node T_6461 = eq(T_6459, UInt<32>("h01010"))
    node T_6463 = and(io.imem.resp.bits.data[0], UInt<32>("h01058"))
    node T_6465 = eq(T_6463, UInt<32>("h01040"))
    node T_6467 = and(io.imem.resp.bits.data[0], UInt<32>("h07044"))
    node T_6469 = eq(T_6467, UInt<32>("h07000"))
    node T_6471 = or(UInt<1>("h00"), T_6461)
    node T_6472 = or(T_6471, T_6465)
    node T_6473 = or(T_6472, T_6469)
    node T_6475 = and(io.imem.resp.bits.data[0], UInt<32>("h04054"))
    node T_6477 = eq(T_6475, UInt<32>("h040"))
    node T_6479 = and(io.imem.resp.bits.data[0], UInt<32>("h02058"))
    node T_6481 = eq(T_6479, UInt<32>("h02040"))
    node T_6483 = and(io.imem.resp.bits.data[0], UInt<32>("h03054"))
    node T_6485 = eq(T_6483, UInt<32>("h03010"))
    node T_6487 = and(io.imem.resp.bits.data[0], UInt<32>("h06054"))
    node T_6489 = eq(T_6487, UInt<32>("h06010"))
    node T_6491 = and(io.imem.resp.bits.data[0], UInt<32>("h040003034"))
    node T_6493 = eq(T_6491, UInt<32>("h040000030"))
    node T_6495 = and(io.imem.resp.bits.data[0], UInt<32>("h040001054"))
    node T_6497 = eq(T_6495, UInt<32>("h040001010"))
    node T_6499 = or(UInt<1>("h00"), T_6477)
    node T_6500 = or(T_6499, T_6481)
    node T_6501 = or(T_6500, T_6485)
    node T_6502 = or(T_6501, T_6489)
    node T_6503 = or(T_6502, T_6493)
    node T_6504 = or(T_6503, T_6497)
    node T_6506 = and(io.imem.resp.bits.data[0], UInt<32>("h02054"))
    node T_6508 = eq(T_6506, UInt<32>("h02010"))
    node T_6510 = and(io.imem.resp.bits.data[0], UInt<32>("h040004054"))
    node T_6512 = eq(T_6510, UInt<32>("h04010"))
    node T_6514 = and(io.imem.resp.bits.data[0], UInt<32>("h05054"))
    node T_6516 = eq(T_6514, UInt<32>("h04010"))
    node T_6518 = and(io.imem.resp.bits.data[0], UInt<32>("h04058"))
    node T_6520 = eq(T_6518, UInt<32>("h04040"))
    node T_6522 = or(UInt<1>("h00"), T_6508)
    node T_6523 = or(T_6522, T_6512)
    node T_6524 = or(T_6523, T_6516)
    node T_6525 = or(T_6524, T_6520)
    node T_6527 = and(io.imem.resp.bits.data[0], UInt<32>("h06054"))
    node T_6529 = eq(T_6527, UInt<32>("h02010"))
    node T_6531 = and(io.imem.resp.bits.data[0], UInt<32>("h040003054"))
    node T_6533 = eq(T_6531, UInt<32>("h040001010"))
    node T_6535 = or(UInt<1>("h00"), T_6529)
    node T_6536 = or(T_6535, T_6520)
    node T_6537 = or(T_6536, T_6493)
    node T_6538 = or(T_6537, T_6533)
    node T_6539 = cat(T_6504, T_6473)
    node T_6540 = cat(T_6525, T_6539)
    node T_6541 = cat(T_6538, T_6540)
    node T_6543 = and(io.imem.resp.bits.data[0], UInt<32>("h0405f"))
    node T_6545 = eq(T_6543, UInt<32>("h03"))
    node T_6547 = and(io.imem.resp.bits.data[0], UInt<32>("h0107f"))
    node T_6549 = eq(T_6547, UInt<32>("h03"))
    node T_6551 = or(UInt<1>("h00"), T_6545)
    node T_6552 = or(T_6551, T_6073)
    node T_6553 = or(T_6552, T_6549)
    node T_6554 = or(T_6553, T_6129)
    node T_6555 = or(T_6554, T_6137)
    node T_6556 = or(T_6555, T_6161)
    node T_6557 = or(T_6556, T_6169)
    node T_6559 = and(io.imem.resp.bits.data[0], UInt<32>("h028"))
    node T_6561 = eq(T_6559, UInt<32>("h020"))
    node T_6563 = and(io.imem.resp.bits.data[0], UInt<32>("h018000020"))
    node T_6565 = eq(T_6563, UInt<32>("h018000020"))
    node T_6567 = and(io.imem.resp.bits.data[0], UInt<32>("h020000020"))
    node T_6569 = eq(T_6567, UInt<32>("h020000020"))
    node T_6571 = or(UInt<1>("h00"), T_6561)
    node T_6572 = or(T_6571, T_6565)
    node T_6573 = or(T_6572, T_6569)
    node T_6575 = and(io.imem.resp.bits.data[0], UInt<32>("h010000008"))
    node T_6577 = eq(T_6575, UInt<32>("h010000008"))
    node T_6579 = and(io.imem.resp.bits.data[0], UInt<32>("h040000008"))
    node T_6581 = eq(T_6579, UInt<32>("h040000008"))
    node T_6583 = or(UInt<1>("h00"), T_6577)
    node T_6584 = or(T_6583, T_6581)
    node T_6586 = and(io.imem.resp.bits.data[0], UInt<32>("h08000008"))
    node T_6588 = eq(T_6586, UInt<32>("h08000008"))
    node T_6590 = and(io.imem.resp.bits.data[0], UInt<32>("h080000008"))
    node T_6592 = eq(T_6590, UInt<32>("h080000008"))
    node T_6594 = or(UInt<1>("h00"), T_6588)
    node T_6595 = or(T_6594, T_6577)
    node T_6596 = or(T_6595, T_6592)
    node T_6598 = and(io.imem.resp.bits.data[0], UInt<32>("h018000008"))
    node T_6600 = eq(T_6598, UInt<32>("h08"))
    node T_6602 = or(UInt<1>("h00"), T_6600)
    node T_6604 = cat(T_6584, T_6573)
    node T_6605 = cat(T_6596, T_6604)
    node T_6606 = cat(T_6602, T_6605)
    node T_6607 = cat(UInt<1>("h00"), T_6606)
    node T_6609 = and(io.imem.resp.bits.data[0], UInt<32>("h01000"))
    node T_6611 = eq(T_6609, UInt<32>("h01000"))
    node T_6613 = or(UInt<1>("h00"), T_6611)
    node T_6615 = and(io.imem.resp.bits.data[0], UInt<32>("h02000"))
    node T_6617 = eq(T_6615, UInt<32>("h02000"))
    node T_6619 = or(UInt<1>("h00"), T_6617)
    node T_6621 = and(io.imem.resp.bits.data[0], UInt<32>("h04000"))
    node T_6623 = eq(T_6621, UInt<32>("h04000"))
    node T_6625 = or(UInt<1>("h00"), T_6623)
    node T_6626 = cat(T_6619, T_6613)
    node T_6627 = cat(T_6625, T_6626)
    node T_6629 = and(io.imem.resp.bits.data[0], UInt<32>("h080000060"))
    node T_6631 = eq(T_6629, UInt<32>("h040"))
    node T_6633 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060"))
    node T_6635 = eq(T_6633, UInt<32>("h040"))
    node T_6637 = and(io.imem.resp.bits.data[0], UInt<32>("h070"))
    node T_6639 = eq(T_6637, UInt<32>("h040"))
    node T_6641 = or(UInt<1>("h00"), T_6631)
    node T_6642 = or(T_6641, T_6635)
    node T_6643 = or(T_6642, T_6639)
    node T_6645 = and(io.imem.resp.bits.data[0], UInt<32>("h07c"))
    node T_6647 = eq(T_6645, UInt<32>("h024"))
    node T_6649 = and(io.imem.resp.bits.data[0], UInt<32>("h040000060"))
    node T_6651 = eq(T_6649, UInt<32>("h040"))
    node T_6653 = and(io.imem.resp.bits.data[0], UInt<32>("h090000060"))
    node T_6655 = eq(T_6653, UInt<32>("h010000040"))
    node T_6657 = or(UInt<1>("h00"), T_6647)
    node T_6658 = or(T_6657, T_6651)
    node T_6659 = or(T_6658, T_6639)
    node T_6660 = or(T_6659, T_6655)
    node T_6662 = or(UInt<1>("h00"), T_6639)
    node T_6664 = and(io.imem.resp.bits.data[0], UInt<32>("h03c"))
    node T_6666 = eq(T_6664, UInt<32>("h04"))
    node T_6668 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060"))
    node T_6670 = eq(T_6668, UInt<32>("h010000040"))
    node T_6672 = or(UInt<1>("h00"), T_6666)
    node T_6673 = or(T_6672, T_6631)
    node T_6674 = or(T_6673, T_6639)
    node T_6675 = or(T_6674, T_6670)
    node T_6677 = and(io.imem.resp.bits.data[0], UInt<32>("h02000074"))
    node T_6679 = eq(T_6677, UInt<32>("h02000030"))
    node T_6681 = or(UInt<1>("h00"), T_6679)
    node T_6683 = and(io.imem.resp.bits.data[0], UInt<32>("h064"))
    node T_6685 = eq(T_6683, UInt<32>("h00"))
    node T_6687 = and(io.imem.resp.bits.data[0], UInt<32>("h050"))
    node T_6689 = eq(T_6687, UInt<32>("h010"))
    node T_6691 = and(io.imem.resp.bits.data[0], UInt<32>("h02024"))
    node T_6693 = eq(T_6691, UInt<32>("h024"))
    node T_6695 = and(io.imem.resp.bits.data[0], UInt<32>("h028"))
    node T_6697 = eq(T_6695, UInt<32>("h028"))
    node T_6699 = and(io.imem.resp.bits.data[0], UInt<32>("h01030"))
    node T_6701 = eq(T_6699, UInt<32>("h01030"))
    node T_6703 = and(io.imem.resp.bits.data[0], UInt<32>("h02030"))
    node T_6705 = eq(T_6703, UInt<32>("h02030"))
    node T_6707 = and(io.imem.resp.bits.data[0], UInt<32>("h090000010"))
    node T_6709 = eq(T_6707, UInt<32>("h080000010"))
    node T_6711 = or(UInt<1>("h00"), T_6685)
    node T_6712 = or(T_6711, T_6689)
    node T_6713 = or(T_6712, T_6693)
    node T_6714 = or(T_6713, T_6697)
    node T_6715 = or(T_6714, T_6701)
    node T_6716 = or(T_6715, T_6705)
    node T_6717 = or(T_6716, T_6709)
    node T_6719 = and(io.imem.resp.bits.data[0], UInt<32>("h01070"))
    node T_6721 = eq(T_6719, UInt<32>("h01070"))
    node T_6723 = or(UInt<1>("h00"), T_6721)
    node T_6725 = and(io.imem.resp.bits.data[0], UInt<32>("h02070"))
    node T_6727 = eq(T_6725, UInt<32>("h02070"))
    node T_6729 = or(UInt<1>("h00"), T_6727)
    node T_6731 = and(io.imem.resp.bits.data[0], UInt<32>("h03070"))
    node T_6733 = eq(T_6731, UInt<32>("h070"))
    node T_6735 = or(UInt<1>("h00"), T_6733)
    node T_6736 = cat(T_6729, T_6723)
    node T_6737 = cat(T_6735, T_6736)
    node T_6739 = and(io.imem.resp.bits.data[0], UInt<32>("h03058"))
    node T_6741 = eq(T_6739, UInt<32>("h01008"))
    node T_6743 = or(UInt<1>("h00"), T_6741)
    node T_6745 = and(io.imem.resp.bits.data[0], UInt<32>("h03058"))
    node T_6747 = eq(T_6745, UInt<32>("h08"))
    node T_6749 = or(UInt<1>("h00"), T_6747)
    node T_6751 = and(io.imem.resp.bits.data[0], UInt<32>("h06048"))
    node T_6753 = eq(T_6751, UInt<32>("h02008"))
    node T_6755 = or(UInt<1>("h00"), T_6753)
    id_ctrl.legal <= T_6268
    id_ctrl.fp <= T_6279
    id_ctrl.rocc <= UInt<1>("h00")
    id_ctrl.branch <= T_6286
    id_ctrl.jal <= T_6292
    id_ctrl.jalr <= T_6298
    id_ctrl.rxs2 <= T_6314
    id_ctrl.rxs1 <= T_6340
    id_ctrl.sel_alu2 <= T_6384
    id_ctrl.sel_alu1 <= T_6410
    id_ctrl.sel_imm <= T_6446
    id_ctrl.alu_dw <= T_6457
    id_ctrl.alu_fn <= T_6541
    id_ctrl.mem <= T_6557
    id_ctrl.mem_cmd <= T_6607
    id_ctrl.mem_type <= T_6627
    id_ctrl.rfs1 <= T_6643
    id_ctrl.rfs2 <= T_6660
    id_ctrl.rfs3 <= T_6662
    id_ctrl.wfd <= T_6675
    id_ctrl.div <= T_6681
    id_ctrl.wxd <= T_6717
    id_ctrl.csr <= T_6737
    id_ctrl.fence_i <= T_6743
    id_ctrl.fence <= T_6749
    id_ctrl.amo <= T_6755
    node id_raddr3 = bits(io.imem.resp.bits.data[0], 31, 27)
    node id_raddr2 = bits(io.imem.resp.bits.data[0], 24, 20)
    node id_raddr1 = bits(io.imem.resp.bits.data[0], 19, 15)
    node id_waddr = bits(io.imem.resp.bits.data[0], 11, 7)
    wire id_load_use : UInt<1>
    id_load_use is invalid
    reg id_reg_fence : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    cmem T_6766 : UInt<64>[31]
    wire T_6768 : UInt
    T_6768 is invalid
    node T_6771 = eq(id_raddr1, UInt<1>("h00"))
    node T_6772 = and(UInt<1>("h00"), T_6771)
    node T_6774 = bits(id_raddr1, 4, 0)
    node T_6775 = not(T_6774)
    infer mport T_6776 = T_6766[T_6775], clk
    node T_6777 = mux(T_6772, UInt<1>("h00"), T_6776)
    T_6768 <= T_6777
    wire T_6779 : UInt
    T_6779 is invalid
    node T_6782 = eq(id_raddr2, UInt<1>("h00"))
    node T_6783 = and(UInt<1>("h00"), T_6782)
    node T_6785 = bits(id_raddr2, 4, 0)
    node T_6786 = not(T_6785)
    infer mport T_6787 = T_6766[T_6786], clk
    node T_6788 = mux(T_6783, UInt<1>("h00"), T_6787)
    T_6779 <= T_6788
    wire ctrl_killd : UInt<1>
    ctrl_killd is invalid
    inst csr of CSRFile
    csr.io is invalid
    csr.clk <= clk
    csr.reset <= reset
    node id_csr_en = neq(id_ctrl.csr, UInt<3>("h00"))
    node id_system_insn = eq(id_ctrl.csr, UInt<3>("h04"))
    node T_6794 = eq(id_ctrl.csr, UInt<3>("h02"))
    node T_6795 = eq(id_ctrl.csr, UInt<3>("h03"))
    node T_6796 = or(T_6794, T_6795)
    node T_6798 = eq(id_raddr1, UInt<1>("h00"))
    node id_csr_ren = and(T_6796, T_6798)
    node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr)
    node id_csr_addr = bits(io.imem.resp.bits.data[0], 31, 20)
    node T_6803 = eq(id_csr_ren, UInt<1>("h00"))
    node T_6804 = and(id_csr_en, T_6803)
    node T_6863 = and(id_csr_addr, UInt<12>("h08c4"))
    node T_6865 = eq(T_6863, UInt<12>("h040"))
    node T_6867 = or(UInt<1>("h00"), T_6865)
    node T_6868 = bits(T_6867, 0, 0)
    node T_6870 = eq(T_6868, UInt<1>("h00"))
    node T_6871 = and(T_6804, T_6870)
    node id_csr_flush = or(id_system_insn, T_6871)
    node T_6874 = eq(id_ctrl.legal, UInt<1>("h00"))
    node T_6876 = neq(csr.io.status.fs, UInt<1>("h00"))
    node T_6878 = eq(T_6876, UInt<1>("h00"))
    node T_6879 = and(id_ctrl.fp, T_6878)
    node T_6880 = or(T_6874, T_6879)
    node T_6882 = neq(csr.io.status.xs, UInt<1>("h00"))
    node T_6884 = eq(T_6882, UInt<1>("h00"))
    node T_6885 = and(id_ctrl.rocc, T_6884)
    node id_illegal_insn = or(T_6880, T_6885)
    node id_amo_aq = bits(io.imem.resp.bits.data[0], 26, 26)
    node id_amo_rl = bits(io.imem.resp.bits.data[0], 25, 25)
    node T_6889 = and(id_ctrl.amo, id_amo_rl)
    node id_fence_next = or(id_ctrl.fence, T_6889)
    node T_6892 = eq(io.dmem.ordered, UInt<1>("h00"))
    node id_mem_busy = or(T_6892, io.dmem.req.valid)
    node T_6895 = and(ex_reg_valid, ex_ctrl.rocc)
    node T_6896 = or(io.rocc.busy, T_6895)
    node T_6897 = and(mem_reg_valid, mem_ctrl.rocc)
    node T_6898 = or(T_6896, T_6897)
    node T_6899 = and(wb_reg_valid, wb_ctrl.rocc)
    node T_6900 = or(T_6898, T_6899)
    node id_rocc_busy = and(UInt<1>("h00"), T_6900)
    node T_6902 = and(id_reg_fence, id_mem_busy)
    node T_6903 = or(id_fence_next, T_6902)
    id_reg_fence <= T_6903
    node T_6904 = and(id_rocc_busy, id_ctrl.fence)
    node T_6905 = and(id_ctrl.amo, id_amo_aq)
    node T_6906 = or(T_6905, id_ctrl.fence_i)
    node T_6907 = or(id_ctrl.mem, id_ctrl.rocc)
    node T_6908 = and(id_reg_fence, T_6907)
    node T_6909 = or(T_6906, T_6908)
    node T_6910 = or(T_6909, id_csr_en)
    node T_6911 = and(id_mem_busy, T_6910)
    node id_do_fence = or(T_6904, T_6911)
    node T_6915 = or(csr.io.interrupt, io.imem.resp.bits.xcpt_if)
    node id_xcpt = or(T_6915, id_illegal_insn)
    node T_6917 = mux(io.imem.resp.bits.xcpt_if, UInt<1>("h01"), UInt<2>("h02"))
    node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_6917)
    node ex_waddr = bits(ex_reg_inst, 11, 7)
    node mem_waddr = bits(mem_reg_inst, 11, 7)
    node wb_waddr = bits(wb_reg_inst, 11, 7)
    node T_6925 = and(ex_reg_valid, ex_ctrl.wxd)
    node T_6926 = and(mem_reg_valid, mem_ctrl.wxd)
    node T_6928 = eq(mem_ctrl.mem, UInt<1>("h00"))
    node T_6929 = and(T_6926, T_6928)
    node T_6930 = and(mem_reg_valid, mem_ctrl.wxd)
    node T_6931 = eq(UInt<1>("h00"), id_raddr1)
    node T_6932 = and(UInt<1>("h01"), T_6931)
    node T_6933 = eq(ex_waddr, id_raddr1)
    node T_6934 = and(T_6925, T_6933)
    node T_6935 = eq(mem_waddr, id_raddr1)
    node T_6936 = and(T_6929, T_6935)
    node T_6937 = eq(mem_waddr, id_raddr1)
    node T_6938 = and(T_6930, T_6937)
    node T_6939 = eq(UInt<1>("h00"), id_raddr2)
    node T_6940 = and(UInt<1>("h01"), T_6939)
    node T_6941 = eq(ex_waddr, id_raddr2)
    node T_6942 = and(T_6925, T_6941)
    node T_6943 = eq(mem_waddr, id_raddr2)
    node T_6944 = and(T_6929, T_6943)
    node T_6945 = eq(mem_waddr, id_raddr2)
    node T_6946 = and(T_6930, T_6945)
    wire bypass_mux : UInt[4]
    bypass_mux[0] <= UInt<1>("h00")
    bypass_mux[1] <= mem_reg_wdata
    bypass_mux[2] <= wb_reg_wdata
    bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass
    reg ex_reg_rs_bypass : UInt<1>[2], clk
    reg ex_reg_rs_lsb : UInt[2], clk
    reg ex_reg_rs_msb : UInt[2], clk
    node T_6991 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0])
    node T_6992 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_6991)
    node T_6994 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1])
    node T_6995 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], T_6994)
    node T_6996 = eq(ex_ctrl.sel_imm, UInt<3>("h05"))
    node T_6998 = bits(ex_reg_inst, 31, 31)
    node T_6999 = asSInt(T_6998)
    node T_7000 = mux(T_6996, asSInt(UInt<1>("h00")), T_6999)
    node T_7001 = eq(ex_ctrl.sel_imm, UInt<3>("h02"))
    node T_7002 = bits(ex_reg_inst, 30, 20)
    node T_7003 = asSInt(T_7002)
    node T_7004 = mux(T_7001, T_7003, T_7000)
    node T_7005 = neq(ex_ctrl.sel_imm, UInt<3>("h02"))
    node T_7006 = neq(ex_ctrl.sel_imm, UInt<3>("h03"))
    node T_7007 = and(T_7005, T_7006)
    node T_7008 = bits(ex_reg_inst, 19, 12)
    node T_7009 = asSInt(T_7008)
    node T_7010 = mux(T_7007, T_7000, T_7009)
    node T_7011 = eq(ex_ctrl.sel_imm, UInt<3>("h02"))
    node T_7012 = eq(ex_ctrl.sel_imm, UInt<3>("h05"))
    node T_7013 = or(T_7011, T_7012)
    node T_7015 = eq(ex_ctrl.sel_imm, UInt<3>("h03"))
    node T_7016 = bits(ex_reg_inst, 20, 20)
    node T_7017 = asSInt(T_7016)
    node T_7018 = eq(ex_ctrl.sel_imm, UInt<3>("h01"))
    node T_7019 = bits(ex_reg_inst, 7, 7)
    node T_7020 = asSInt(T_7019)
    node T_7021 = mux(T_7018, T_7020, T_7000)
    node T_7022 = mux(T_7015, T_7017, T_7021)
    node T_7023 = mux(T_7013, asSInt(UInt<1>("h00")), T_7022)
    node T_7024 = eq(ex_ctrl.sel_imm, UInt<3>("h02"))
    node T_7025 = eq(ex_ctrl.sel_imm, UInt<3>("h05"))
    node T_7026 = or(T_7024, T_7025)
    node T_7028 = bits(ex_reg_inst, 30, 25)
    node T_7029 = mux(T_7026, UInt<1>("h00"), T_7028)
    node T_7030 = eq(ex_ctrl.sel_imm, UInt<3>("h02"))
    node T_7032 = eq(ex_ctrl.sel_imm, UInt<3>("h00"))
    node T_7033 = eq(ex_ctrl.sel_imm, UInt<3>("h01"))
    node T_7034 = or(T_7032, T_7033)
    node T_7035 = bits(ex_reg_inst, 11, 8)
    node T_7036 = eq(ex_ctrl.sel_imm, UInt<3>("h05"))
    node T_7037 = bits(ex_reg_inst, 19, 16)
    node T_7038 = bits(ex_reg_inst, 24, 21)
    node T_7039 = mux(T_7036, T_7037, T_7038)
    node T_7040 = mux(T_7034, T_7035, T_7039)
    node T_7041 = mux(T_7030, UInt<1>("h00"), T_7040)
    node T_7042 = eq(ex_ctrl.sel_imm, UInt<3>("h00"))
    node T_7043 = bits(ex_reg_inst, 7, 7)
    node T_7044 = eq(ex_ctrl.sel_imm, UInt<3>("h04"))
    node T_7045 = bits(ex_reg_inst, 20, 20)
    node T_7046 = eq(ex_ctrl.sel_imm, UInt<3>("h05"))
    node T_7047 = bits(ex_reg_inst, 15, 15)
    node T_7049 = shl(T_7047, 0)
    node T_7050 = mux(T_7046, T_7049, UInt<1>("h00"))
    node T_7051 = shl(T_7045, 0)
    node T_7052 = mux(T_7044, T_7051, T_7050)
    node T_7053 = shl(T_7043, 0)
    node T_7054 = mux(T_7042, T_7053, T_7052)
    node T_7055 = asUInt(T_7000)
    node T_7056 = asUInt(T_7004)
    node T_7057 = asUInt(T_7010)
    node T_7058 = cat(T_7056, T_7057)
    node T_7059 = cat(T_7055, T_7058)
    node T_7060 = asUInt(T_7023)
    node T_7061 = cat(T_7060, T_7029)
    node T_7062 = cat(T_7041, T_7054)
    node T_7063 = cat(T_7061, T_7062)
    node T_7064 = cat(T_7059, T_7063)
    node ex_imm = asSInt(T_7064)
    node T_7067 = asSInt(T_6992)
    node T_7068 = asSInt(ex_reg_pc)
    node T_7069 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1)
    node T_7070 = mux(T_7069, T_7068, asSInt(UInt<1>("h00")))
    node T_7071 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1)
    node ex_op1 = mux(T_7071, T_7067, T_7070)
    node T_7074 = asSInt(T_6995)
    node T_7076 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2)
    node T_7077 = mux(T_7076, asSInt(UInt<4>("h04")), asSInt(UInt<1>("h00")))
    node T_7078 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2)
    node T_7079 = mux(T_7078, ex_imm, T_7077)
    node T_7080 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2)
    node ex_op2 = mux(T_7080, T_7074, T_7079)
    inst alu of ALU
    alu.io is invalid
    alu.clk <= clk
    alu.reset <= reset
    alu.io.dw <= ex_ctrl.alu_dw
    alu.io.fn <= ex_ctrl.alu_fn
    node T_7083 = asUInt(ex_op2)
    alu.io.in2 <= T_7083
    node T_7084 = asUInt(ex_op1)
    alu.io.in1 <= T_7084
    inst div of MulDiv
    div.io is invalid
    div.clk <= clk
    div.reset <= reset
    node T_7086 = and(ex_reg_valid, ex_ctrl.div)
    div.io.req.valid <= T_7086
    div.io.req.bits.dw <= ex_ctrl.alu_dw
    div.io.req.bits.fn <= ex_ctrl.alu_fn
    div.io.req.bits.in1 <= T_6992
    div.io.req.bits.in2 <= T_6995
    div.io.req.bits.tag <= ex_waddr
    node T_7088 = eq(ctrl_killd, UInt<1>("h00"))
    ex_reg_valid <= T_7088
    node T_7090 = eq(ctrl_killd, UInt<1>("h00"))
    node T_7091 = and(T_7090, id_xcpt)
    ex_reg_xcpt <= T_7091
    node T_7093 = eq(take_pc_mem_wb, UInt<1>("h00"))
    node T_7094 = and(csr.io.interrupt, T_7093)
    node T_7095 = and(T_7094, io.imem.resp.valid)
    ex_reg_xcpt_interrupt <= T_7095
    when id_xcpt :
      ex_reg_cause <= id_cause
      skip
    node T_7097 = eq(ctrl_killd, UInt<1>("h00"))
    when T_7097 :
      ex_ctrl <- id_ctrl
      ex_ctrl.csr <= id_csr
      ex_reg_btb_hit <= io.imem.btb_resp.valid
      when io.imem.btb_resp.valid :
        ex_reg_btb_resp <- io.imem.btb_resp.bits
        skip
      node T_7098 = or(id_ctrl.fence_i, id_csr_flush)
      ex_reg_flush_pipe <= T_7098
      ex_reg_load_use <= id_load_use
      node T_7099 = or(T_6932, T_6934)
      node T_7100 = or(T_7099, T_6936)
      node T_7101 = or(T_7100, T_6938)
      node T_7106 = mux(T_6936, UInt<2>("h02"), UInt<2>("h03"))
      node T_7107 = mux(T_6934, UInt<1>("h01"), T_7106)
      node T_7108 = mux(T_6932, UInt<1>("h00"), T_7107)
      ex_reg_rs_bypass[0] <= T_7101
      ex_reg_rs_lsb[0] <= T_7108
      node T_7110 = eq(T_7101, UInt<1>("h00"))
      node T_7111 = and(id_ctrl.rxs1, T_7110)
      when T_7111 :
        node T_7112 = bits(T_6768, 1, 0)
        ex_reg_rs_lsb[0] <= T_7112
        node T_7113 = shr(T_6768, 2)
        ex_reg_rs_msb[0] <= T_7113
        skip
      node T_7114 = or(T_6940, T_6942)
      node T_7115 = or(T_7114, T_6944)
      node T_7116 = or(T_7115, T_6946)
      node T_7121 = mux(T_6944, UInt<2>("h02"), UInt<2>("h03"))
      node T_7122 = mux(T_6942, UInt<1>("h01"), T_7121)
      node T_7123 = mux(T_6940, UInt<1>("h00"), T_7122)
      ex_reg_rs_bypass[1] <= T_7116
      ex_reg_rs_lsb[1] <= T_7123
      node T_7125 = eq(T_7116, UInt<1>("h00"))
      node T_7126 = and(id_ctrl.rxs2, T_7125)
      when T_7126 :
        node T_7127 = bits(T_6779, 1, 0)
        ex_reg_rs_lsb[1] <= T_7127
        node T_7128 = shr(T_6779, 2)
        ex_reg_rs_msb[1] <= T_7128
        skip
      skip
    node T_7130 = eq(ctrl_killd, UInt<1>("h00"))
    node T_7131 = or(T_7130, csr.io.interrupt)
    when T_7131 :
      ex_reg_inst <= io.imem.resp.bits.data[0]
      ex_reg_pc <= io.imem.resp.bits.pc
      skip
    node T_7133 = eq(io.dmem.resp.valid, UInt<1>("h00"))
    node wb_dcache_miss = and(wb_ctrl.mem, T_7133)
    node T_7136 = eq(io.dmem.req.ready, UInt<1>("h00"))
    node T_7137 = and(ex_ctrl.mem, T_7136)
    node T_7139 = eq(div.io.req.ready, UInt<1>("h00"))
    node T_7140 = and(ex_ctrl.div, T_7139)
    node replay_ex_structural = or(T_7137, T_7140)
    node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use)
    node T_7143 = or(replay_ex_structural, replay_ex_load_use)
    node replay_ex = and(ex_reg_valid, T_7143)
    node T_7145 = or(take_pc_mem_wb, replay_ex)
    node T_7147 = eq(ex_reg_valid, UInt<1>("h00"))
    node ctrl_killx = or(T_7145, T_7147)
    node T_7149 = eq(ex_ctrl.mem_cmd, UInt<5>("h07"))
    wire T_7151 : UInt<3>[4]
    T_7151[0] <= UInt<3>("h00")
    T_7151[1] <= UInt<3>("h04")
    T_7151[2] <= UInt<3>("h01")
    T_7151[3] <= UInt<3>("h05")
    node T_7157 = eq(T_7151[0], ex_ctrl.mem_type)
    node T_7158 = eq(T_7151[1], ex_ctrl.mem_type)
    node T_7159 = eq(T_7151[2], ex_ctrl.mem_type)
    node T_7160 = eq(T_7151[3], ex_ctrl.mem_type)
    node T_7162 = or(UInt<1>("h00"), T_7157)
    node T_7163 = or(T_7162, T_7158)
    node T_7164 = or(T_7163, T_7159)
    node T_7165 = or(T_7164, T_7160)
    node ex_slow_bypass = or(T_7149, T_7165)
    node T_7167 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt)
    node T_7168 = and(ex_ctrl.fp, io.fpu.illegal_rm)
    node ex_xcpt = or(T_7167, T_7168)
    node ex_cause = mux(T_7167, ex_reg_cause, UInt<2>("h02"))
    node mem_br_taken = bits(mem_reg_wdata, 0, 0)
    node T_7173 = asSInt(mem_reg_pc)
    node T_7174 = and(mem_ctrl.branch, mem_br_taken)
    node T_7175 = eq(UInt<3>("h01"), UInt<3>("h05"))
    node T_7177 = bits(mem_reg_inst, 31, 31)
    node T_7178 = asSInt(T_7177)
    node T_7179 = mux(T_7175, asSInt(UInt<1>("h00")), T_7178)
    node T_7180 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_7181 = bits(mem_reg_inst, 30, 20)
    node T_7182 = asSInt(T_7181)
    node T_7183 = mux(T_7180, T_7182, T_7179)
    node T_7184 = neq(UInt<3>("h01"), UInt<3>("h02"))
    node T_7185 = neq(UInt<3>("h01"), UInt<3>("h03"))
    node T_7186 = and(T_7184, T_7185)
    node T_7187 = bits(mem_reg_inst, 19, 12)
    node T_7188 = asSInt(T_7187)
    node T_7189 = mux(T_7186, T_7179, T_7188)
    node T_7190 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_7191 = eq(UInt<3>("h01"), UInt<3>("h05"))
    node T_7192 = or(T_7190, T_7191)
    node T_7194 = eq(UInt<3>("h01"), UInt<3>("h03"))
    node T_7195 = bits(mem_reg_inst, 20, 20)
    node T_7196 = asSInt(T_7195)
    node T_7197 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_7198 = bits(mem_reg_inst, 7, 7)
    node T_7199 = asSInt(T_7198)
    node T_7200 = mux(T_7197, T_7199, T_7179)
    node T_7201 = mux(T_7194, T_7196, T_7200)
    node T_7202 = mux(T_7192, asSInt(UInt<1>("h00")), T_7201)
    node T_7203 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_7204 = eq(UInt<3>("h01"), UInt<3>("h05"))
    node T_7205 = or(T_7203, T_7204)
    node T_7207 = bits(mem_reg_inst, 30, 25)
    node T_7208 = mux(T_7205, UInt<1>("h00"), T_7207)
    node T_7209 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_7211 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_7212 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_7213 = or(T_7211, T_7212)
    node T_7214 = bits(mem_reg_inst, 11, 8)
    node T_7215 = eq(UInt<3>("h01"), UInt<3>("h05"))
    node T_7216 = bits(mem_reg_inst, 19, 16)
    node T_7217 = bits(mem_reg_inst, 24, 21)
    node T_7218 = mux(T_7215, T_7216, T_7217)
    node T_7219 = mux(T_7213, T_7214, T_7218)
    node T_7220 = mux(T_7209, UInt<1>("h00"), T_7219)
    node T_7221 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_7222 = bits(mem_reg_inst, 7, 7)
    node T_7223 = eq(UInt<3>("h01"), UInt<3>("h04"))
    node T_7224 = bits(mem_reg_inst, 20, 20)
    node T_7225 = eq(UInt<3>("h01"), UInt<3>("h05"))
    node T_7226 = bits(mem_reg_inst, 15, 15)
    node T_7228 = shl(T_7226, 0)
    node T_7229 = mux(T_7225, T_7228, UInt<1>("h00"))
    node T_7230 = shl(T_7224, 0)
    node T_7231 = mux(T_7223, T_7230, T_7229)
    node T_7232 = shl(T_7222, 0)
    node T_7233 = mux(T_7221, T_7232, T_7231)
    node T_7234 = asUInt(T_7179)
    node T_7235 = asUInt(T_7183)
    node T_7236 = asUInt(T_7189)
    node T_7237 = cat(T_7235, T_7236)
    node T_7238 = cat(T_7234, T_7237)
    node T_7239 = asUInt(T_7202)
    node T_7240 = cat(T_7239, T_7208)
    node T_7241 = cat(T_7220, T_7233)
    node T_7242 = cat(T_7240, T_7241)
    node T_7243 = cat(T_7238, T_7242)
    node T_7244 = asSInt(T_7243)
    node T_7245 = eq(UInt<3>("h03"), UInt<3>("h05"))
    node T_7247 = bits(mem_reg_inst, 31, 31)
    node T_7248 = asSInt(T_7247)
    node T_7249 = mux(T_7245, asSInt(UInt<1>("h00")), T_7248)
    node T_7250 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_7251 = bits(mem_reg_inst, 30, 20)
    node T_7252 = asSInt(T_7251)
    node T_7253 = mux(T_7250, T_7252, T_7249)
    node T_7254 = neq(UInt<3>("h03"), UInt<3>("h02"))
    node T_7255 = neq(UInt<3>("h03"), UInt<3>("h03"))
    node T_7256 = and(T_7254, T_7255)
    node T_7257 = bits(mem_reg_inst, 19, 12)
    node T_7258 = asSInt(T_7257)
    node T_7259 = mux(T_7256, T_7249, T_7258)
    node T_7260 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_7261 = eq(UInt<3>("h03"), UInt<3>("h05"))
    node T_7262 = or(T_7260, T_7261)
    node T_7264 = eq(UInt<3>("h03"), UInt<3>("h03"))
    node T_7265 = bits(mem_reg_inst, 20, 20)
    node T_7266 = asSInt(T_7265)
    node T_7267 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_7268 = bits(mem_reg_inst, 7, 7)
    node T_7269 = asSInt(T_7268)
    node T_7270 = mux(T_7267, T_7269, T_7249)
    node T_7271 = mux(T_7264, T_7266, T_7270)
    node T_7272 = mux(T_7262, asSInt(UInt<1>("h00")), T_7271)
    node T_7273 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_7274 = eq(UInt<3>("h03"), UInt<3>("h05"))
    node T_7275 = or(T_7273, T_7274)
    node T_7277 = bits(mem_reg_inst, 30, 25)
    node T_7278 = mux(T_7275, UInt<1>("h00"), T_7277)
    node T_7279 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_7281 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_7282 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_7283 = or(T_7281, T_7282)
    node T_7284 = bits(mem_reg_inst, 11, 8)
    node T_7285 = eq(UInt<3>("h03"), UInt<3>("h05"))
    node T_7286 = bits(mem_reg_inst, 19, 16)
    node T_7287 = bits(mem_reg_inst, 24, 21)
    node T_7288 = mux(T_7285, T_7286, T_7287)
    node T_7289 = mux(T_7283, T_7284, T_7288)
    node T_7290 = mux(T_7279, UInt<1>("h00"), T_7289)
    node T_7291 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_7292 = bits(mem_reg_inst, 7, 7)
    node T_7293 = eq(UInt<3>("h03"), UInt<3>("h04"))
    node T_7294 = bits(mem_reg_inst, 20, 20)
    node T_7295 = eq(UInt<3>("h03"), UInt<3>("h05"))
    node T_7296 = bits(mem_reg_inst, 15, 15)
    node T_7298 = shl(T_7296, 0)
    node T_7299 = mux(T_7295, T_7298, UInt<1>("h00"))
    node T_7300 = shl(T_7294, 0)
    node T_7301 = mux(T_7293, T_7300, T_7299)
    node T_7302 = shl(T_7292, 0)
    node T_7303 = mux(T_7291, T_7302, T_7301)
    node T_7304 = asUInt(T_7249)
    node T_7305 = asUInt(T_7253)
    node T_7306 = asUInt(T_7259)
    node T_7307 = cat(T_7305, T_7306)
    node T_7308 = cat(T_7304, T_7307)
    node T_7309 = asUInt(T_7272)
    node T_7310 = cat(T_7309, T_7278)
    node T_7311 = cat(T_7290, T_7303)
    node T_7312 = cat(T_7310, T_7311)
    node T_7313 = cat(T_7308, T_7312)
    node T_7314 = asSInt(T_7313)
    node T_7316 = mux(mem_ctrl.jal, T_7314, asSInt(UInt<4>("h04")))
    node T_7317 = mux(T_7174, T_7244, T_7316)
    node T_7318 = add(T_7173, T_7317)
    node T_7319 = tail(T_7318, 1)
    node mem_br_target = asSInt(T_7319)
    node T_7321 = asSInt(mem_reg_wdata)
    node T_7322 = mux(mem_ctrl.jalr, mem_br_target, T_7321)
    node mem_int_wdata = asUInt(T_7322)
    node T_7324 = shr(mem_reg_wdata, 38)
    node T_7325 = bits(mem_reg_wdata, 39, 38)
    node T_7327 = eq(T_7324, UInt<1>("h00"))
    node T_7329 = eq(T_7324, UInt<1>("h01"))
    node T_7330 = or(T_7327, T_7329)
    node T_7332 = neq(T_7325, UInt<1>("h00"))
    node T_7333 = asSInt(T_7324)
    node T_7335 = eq(T_7333, asSInt(UInt<1>("h01")))
    node T_7336 = asSInt(T_7324)
    node T_7338 = eq(T_7336, asSInt(UInt<2>("h02")))
    node T_7339 = or(T_7335, T_7338)
    node T_7340 = asSInt(T_7325)
    node T_7342 = eq(T_7340, asSInt(UInt<1>("h01")))
    node T_7343 = bits(T_7325, 0, 0)
    node T_7344 = mux(T_7339, T_7342, T_7343)
    node T_7345 = mux(T_7330, T_7332, T_7344)
    node T_7346 = bits(mem_reg_wdata, 38, 0)
    node T_7347 = cat(T_7345, T_7346)
    node T_7348 = asSInt(T_7347)
    node T_7349 = mux(mem_ctrl.jalr, T_7348, mem_br_target)
    node T_7351 = and(T_7349, asSInt(UInt<2>("h02")))
    node T_7352 = asSInt(T_7351)
    node mem_npc = asUInt(T_7352)
    node T_7354 = neq(mem_npc, ex_reg_pc)
    node T_7356 = eq(ex_reg_valid, UInt<1>("h00"))
    node mem_wrong_npc = or(T_7354, T_7356)
    node mem_npc_misaligned = bits(mem_npc, 1, 1)
    node T_7359 = and(mem_wrong_npc, mem_reg_valid)
    node T_7360 = or(mem_ctrl.branch, mem_ctrl.jalr)
    node T_7361 = or(T_7360, mem_ctrl.jal)
    node mem_misprediction = and(T_7359, T_7361)
    node T_7363 = or(mem_misprediction, mem_reg_flush_pipe)
    node want_take_pc_mem = and(mem_reg_valid, T_7363)
    node T_7366 = eq(mem_npc_misaligned, UInt<1>("h00"))
    node T_7367 = and(want_take_pc_mem, T_7366)
    take_pc_mem <= T_7367
    node T_7369 = eq(ctrl_killx, UInt<1>("h00"))
    mem_reg_valid <= T_7369
    node T_7371 = eq(take_pc_mem_wb, UInt<1>("h00"))
    node T_7372 = and(T_7371, replay_ex)
    mem_reg_replay <= T_7372
    node T_7374 = eq(ctrl_killx, UInt<1>("h00"))
    node T_7375 = and(T_7374, ex_xcpt)
    mem_reg_xcpt <= T_7375
    node T_7377 = eq(take_pc_mem_wb, UInt<1>("h00"))
    node T_7378 = and(T_7377, ex_reg_xcpt_interrupt)
    mem_reg_xcpt_interrupt <= T_7378
    when ex_xcpt :
      mem_reg_cause <= ex_cause
      skip
    node T_7379 = or(ex_reg_valid, ex_reg_xcpt_interrupt)
    when T_7379 :
      mem_ctrl <- ex_ctrl
      mem_reg_btb_hit <= ex_reg_btb_hit
      when ex_reg_btb_hit :
        mem_reg_btb_resp <- ex_reg_btb_resp
        skip
      mem_reg_flush_pipe <= ex_reg_flush_pipe
      mem_reg_slow_bypass <= ex_slow_bypass
      mem_reg_inst <= ex_reg_inst
      mem_reg_pc <= ex_reg_pc
      mem_reg_wdata <= alu.io.out
      node T_7380 = or(ex_ctrl.mem, ex_ctrl.rocc)
      node T_7381 = and(ex_ctrl.rxs2, T_7380)
      when T_7381 :
        mem_reg_rs2 <= T_6995
        skip
      skip
    node T_7382 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt)
    node T_7383 = and(want_take_pc_mem, mem_npc_misaligned)
    node T_7385 = and(mem_reg_valid, mem_ctrl.mem)
    node T_7386 = and(T_7385, io.dmem.xcpt.ma.st)
    node T_7388 = and(mem_reg_valid, mem_ctrl.mem)
    node T_7389 = and(T_7388, io.dmem.xcpt.ma.ld)
    node T_7391 = and(mem_reg_valid, mem_ctrl.mem)
    node T_7392 = and(T_7391, io.dmem.xcpt.pf.st)
    node T_7394 = and(mem_reg_valid, mem_ctrl.mem)
    node T_7395 = and(T_7394, io.dmem.xcpt.pf.ld)
    node T_7397 = or(T_7382, T_7383)
    node T_7398 = or(T_7397, T_7386)
    node T_7399 = or(T_7398, T_7389)
    node T_7400 = or(T_7399, T_7392)
    node mem_xcpt = or(T_7400, T_7395)
    node T_7402 = mux(T_7392, UInt<3>("h07"), UInt<3>("h05"))
    node T_7403 = mux(T_7389, UInt<3>("h04"), T_7402)
    node T_7404 = mux(T_7386, UInt<3>("h06"), T_7403)
    node T_7405 = mux(T_7383, UInt<1>("h00"), T_7404)
    node mem_cause = mux(T_7382, mem_reg_cause, T_7405)
    node T_7407 = and(mem_reg_valid, mem_ctrl.wxd)
    node dcache_kill_mem = and(T_7407, io.dmem.replay_next.valid)
    node T_7409 = and(mem_reg_valid, mem_ctrl.fp)
    node fpu_kill_mem = and(T_7409, io.fpu.nack_mem)
    node T_7411 = or(dcache_kill_mem, mem_reg_replay)
    node replay_mem = or(T_7411, fpu_kill_mem)
    node T_7413 = or(dcache_kill_mem, take_pc_wb)
    node T_7414 = or(T_7413, mem_reg_xcpt)
    node T_7416 = eq(mem_reg_valid, UInt<1>("h00"))
    node killm_common = or(T_7414, T_7416)
    node T_7418 = and(div.io.req.ready, div.io.req.valid)
    reg T_7419 : UInt<1>, clk
    T_7419 <= T_7418
    node T_7420 = and(killm_common, T_7419)
    div.io.kill <= T_7420
    node T_7421 = or(killm_common, mem_xcpt)
    node ctrl_killm = or(T_7421, fpu_kill_mem)
    node T_7424 = eq(ctrl_killm, UInt<1>("h00"))
    wb_reg_valid <= T_7424
    node T_7426 = eq(take_pc_wb, UInt<1>("h00"))
    node T_7427 = and(replay_mem, T_7426)
    wb_reg_replay <= T_7427
    node T_7429 = eq(take_pc_wb, UInt<1>("h00"))
    node T_7430 = and(mem_xcpt, T_7429)
    wb_reg_xcpt <= T_7430
    when mem_xcpt :
      wb_reg_cause <= mem_cause
      skip
    node T_7431 = or(mem_reg_valid, mem_reg_replay)
    node T_7432 = or(T_7431, mem_reg_xcpt_interrupt)
    when T_7432 :
      wb_ctrl <- mem_ctrl
      node T_7433 = and(mem_ctrl.fp, mem_ctrl.wxd)
      node T_7434 = mux(T_7433, io.fpu.toint_data, mem_int_wdata)
      wb_reg_wdata <= T_7434
      when mem_ctrl.rocc :
        wb_reg_rs2 <= mem_reg_rs2
        skip
      wb_reg_inst <= mem_reg_inst
      wb_reg_pc <= mem_reg_pc
      skip
    node T_7435 = or(wb_ctrl.div, wb_dcache_miss)
    node wb_set_sboard = or(T_7435, wb_ctrl.rocc)
    node replay_wb_common = or(io.dmem.resp.bits.nack, wb_reg_replay)
    node T_7438 = and(wb_reg_valid, wb_ctrl.rocc)
    node T_7440 = eq(replay_wb_common, UInt<1>("h00"))
    node wb_rocc_val = and(T_7438, T_7440)
    node T_7442 = and(wb_reg_valid, wb_ctrl.rocc)
    node T_7444 = eq(io.rocc.cmd.ready, UInt<1>("h00"))
    node T_7445 = and(T_7442, T_7444)
    node replay_wb = or(replay_wb_common, T_7445)
    node wb_xcpt = or(wb_reg_xcpt, csr.io.csr_xcpt)
    node T_7448 = or(replay_wb, wb_xcpt)
    node T_7449 = or(T_7448, csr.io.eret)
    take_pc_wb <= T_7449
    when wb_rocc_val :
      node T_7451 = eq(io.rocc.cmd.ready, UInt<1>("h00"))
      wb_reg_rocc_pending <= T_7451
      skip
    when wb_reg_xcpt :
      wb_reg_rocc_pending <= UInt<1>("h00")
      skip
    node T_7453 = bits(io.dmem.resp.bits.tag, 0, 0)
    node T_7454 = bits(T_7453, 0, 0)
    node dmem_resp_xpu = eq(T_7454, UInt<1>("h00"))
    node T_7457 = bits(io.dmem.resp.bits.tag, 0, 0)
    node dmem_resp_fpu = bits(T_7457, 0, 0)
    node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1)
    node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data)
    node dmem_resp_replay = and(io.dmem.resp.bits.replay, io.dmem.resp.bits.has_data)
    node T_7462 = and(wb_reg_valid, wb_ctrl.wxd)
    node T_7464 = eq(T_7462, UInt<1>("h00"))
    div.io.resp.ready <= T_7464
    wire ll_wdata : UInt
    ll_wdata <= div.io.resp.bits.data
    wire ll_waddr : UInt
    ll_waddr <= div.io.resp.bits.tag
    node T_7467 = and(div.io.resp.ready, div.io.resp.valid)
    wire ll_wen : UInt<1>
    ll_wen <= T_7467
    node T_7469 = and(dmem_resp_replay, dmem_resp_xpu)
    when T_7469 :
      div.io.resp.ready <= UInt<1>("h00")
      ll_waddr <= dmem_resp_waddr
      ll_wen <= UInt<1>("h01")
      skip
    node T_7473 = eq(replay_wb, UInt<1>("h00"))
    node T_7474 = and(wb_reg_valid, T_7473)
    node T_7476 = eq(csr.io.csr_xcpt, UInt<1>("h00"))
    node wb_valid = and(T_7474, T_7476)
    node wb_wen = and(wb_valid, wb_ctrl.wxd)
    node rf_wen = or(wb_wen, ll_wen)
    node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr)
    node T_7481 = and(dmem_resp_valid, dmem_resp_xpu)
    node T_7482 = neq(wb_ctrl.csr, UInt<3>("h00"))
    node T_7483 = mux(T_7482, csr.io.rw.rdata, wb_reg_wdata)
    node T_7484 = mux(ll_wen, ll_wdata, T_7483)
    node rf_wdata = mux(T_7481, io.dmem.resp.bits.data, T_7484)
    when rf_wen :
      node T_7487 = neq(rf_waddr, UInt<1>("h00"))
      when T_7487 :
        node T_7488 = bits(rf_waddr, 4, 0)
        node T_7489 = not(T_7488)
        infer mport T_7490 = T_6766[T_7489], clk
        T_7490 <= rf_wdata
        node T_7491 = eq(rf_waddr, id_raddr1)
        when T_7491 :
          T_6768 <= rf_wdata
          skip
        node T_7492 = eq(rf_waddr, id_raddr2)
        when T_7492 :
          T_6779 <= rf_wdata
          skip
        skip
      skip
    csr.io.exception <= wb_reg_xcpt
    csr.io.cause <= wb_reg_cause
    csr.io.retire <= wb_valid
    io.host <- csr.io.host
    io.fpu.fcsr_rm <= csr.io.fcsr_rm
    csr.io.fcsr_flags <- io.fpu.fcsr_flags
    csr.io.rocc <- io.rocc
    csr.io.pc <= wb_reg_pc
    csr.io.uarch_counters[0] <= UInt<1>("h00")
    csr.io.uarch_counters[1] <= UInt<1>("h00")
    csr.io.uarch_counters[2] <= UInt<1>("h00")
    csr.io.uarch_counters[3] <= UInt<1>("h00")
    csr.io.uarch_counters[4] <= UInt<1>("h00")
    csr.io.uarch_counters[5] <= UInt<1>("h00")
    csr.io.uarch_counters[6] <= UInt<1>("h00")
    csr.io.uarch_counters[7] <= UInt<1>("h00")
    csr.io.uarch_counters[8] <= UInt<1>("h00")
    csr.io.uarch_counters[9] <= UInt<1>("h00")
    csr.io.uarch_counters[10] <= UInt<1>("h00")
    csr.io.uarch_counters[11] <= UInt<1>("h00")
    csr.io.uarch_counters[12] <= UInt<1>("h00")
    csr.io.uarch_counters[13] <= UInt<1>("h00")
    csr.io.uarch_counters[14] <= UInt<1>("h00")
    csr.io.uarch_counters[15] <= UInt<1>("h00")
    io.ptw.ptbr <= csr.io.ptbr
    io.ptw.invalidate <= csr.io.fatc
    io.ptw.status <- csr.io.status
    node T_7509 = bits(wb_reg_inst, 31, 20)
    csr.io.rw.addr <= T_7509
    node T_7510 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00"))
    csr.io.rw.cmd <= T_7510
    csr.io.rw.wdata <= wb_reg_wdata
    node T_7512 = neq(id_raddr1, UInt<1>("h00"))
    node T_7513 = and(id_ctrl.rxs1, T_7512)
    node T_7515 = neq(id_raddr2, UInt<1>("h00"))
    node T_7516 = and(id_ctrl.rxs2, T_7515)
    node T_7518 = neq(id_waddr, UInt<1>("h00"))
    node T_7519 = and(id_ctrl.wxd, T_7518)
    reg T_7521 : UInt<32>, clk with : (reset => (reset, UInt<32>("h00")))
    node T_7524 = dshl(UInt<1>("h01"), ll_waddr)
    node T_7526 = mux(ll_wen, T_7524, UInt<1>("h00"))
    node T_7527 = not(T_7526)
    node T_7528 = and(T_7521, T_7527)
    node T_7529 = or(UInt<1>("h00"), ll_wen)
    when T_7529 :
      T_7521 <= T_7528
      skip
    node T_7530 = dshr(T_7528, id_raddr1)
    node T_7531 = bits(T_7530, 0, 0)
    node T_7532 = and(T_7513, T_7531)
    node T_7533 = dshr(T_7528, id_raddr2)
    node T_7534 = bits(T_7533, 0, 0)
    node T_7535 = and(T_7516, T_7534)
    node T_7536 = dshr(T_7528, id_waddr)
    node T_7537 = bits(T_7536, 0, 0)
    node T_7538 = and(T_7519, T_7537)
    node T_7539 = or(T_7532, T_7535)
    node id_sboard_hazard = or(T_7539, T_7538)
    node T_7541 = and(wb_set_sboard, wb_wen)
    node T_7543 = dshl(UInt<1>("h01"), wb_waddr)
    node T_7545 = mux(T_7541, T_7543, UInt<1>("h00"))
    node T_7546 = or(T_7528, T_7545)
    node T_7547 = or(T_7529, T_7541)
    when T_7547 :
      T_7521 <= T_7546
      skip
    node T_7548 = neq(ex_ctrl.csr, UInt<3>("h00"))
    node T_7549 = or(T_7548, ex_ctrl.jalr)
    node T_7550 = or(T_7549, ex_ctrl.mem)
    node T_7551 = or(T_7550, ex_ctrl.div)
    node T_7552 = or(T_7551, ex_ctrl.fp)
    node ex_cannot_bypass = or(T_7552, ex_ctrl.rocc)
    node T_7554 = eq(id_raddr1, ex_waddr)
    node T_7555 = and(T_7513, T_7554)
    node T_7556 = eq(id_raddr2, ex_waddr)
    node T_7557 = and(T_7516, T_7556)
    node T_7558 = eq(id_waddr, ex_waddr)
    node T_7559 = and(T_7519, T_7558)
    node T_7560 = or(T_7555, T_7557)
    node T_7561 = or(T_7560, T_7559)
    node data_hazard_ex = and(ex_ctrl.wxd, T_7561)
    node T_7563 = eq(id_raddr1, ex_waddr)
    node T_7564 = and(io.fpu.dec.ren1, T_7563)
    node T_7565 = eq(id_raddr2, ex_waddr)
    node T_7566 = and(io.fpu.dec.ren2, T_7565)
    node T_7567 = eq(id_raddr3, ex_waddr)
    node T_7568 = and(io.fpu.dec.ren3, T_7567)
    node T_7569 = eq(id_waddr, ex_waddr)
    node T_7570 = and(io.fpu.dec.wen, T_7569)
    node T_7571 = or(T_7564, T_7566)
    node T_7572 = or(T_7571, T_7568)
    node T_7573 = or(T_7572, T_7570)
    node fp_data_hazard_ex = and(ex_ctrl.wfd, T_7573)
    node T_7575 = and(data_hazard_ex, ex_cannot_bypass)
    node T_7576 = or(T_7575, fp_data_hazard_ex)
    node id_ex_hazard = and(ex_reg_valid, T_7576)
    node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass)
    node T_7580 = neq(mem_ctrl.csr, UInt<3>("h00"))
    node T_7581 = and(mem_ctrl.mem, mem_mem_cmd_bh)
    node T_7582 = or(T_7580, T_7581)
    node T_7583 = or(T_7582, mem_ctrl.div)
    node T_7584 = or(T_7583, mem_ctrl.fp)
    node mem_cannot_bypass = or(T_7584, mem_ctrl.rocc)
    node T_7586 = eq(id_raddr1, mem_waddr)
    node T_7587 = and(T_7513, T_7586)
    node T_7588 = eq(id_raddr2, mem_waddr)
    node T_7589 = and(T_7516, T_7588)
    node T_7590 = eq(id_waddr, mem_waddr)
    node T_7591 = and(T_7519, T_7590)
    node T_7592 = or(T_7587, T_7589)
    node T_7593 = or(T_7592, T_7591)
    node data_hazard_mem = and(mem_ctrl.wxd, T_7593)
    node T_7595 = eq(id_raddr1, mem_waddr)
    node T_7596 = and(io.fpu.dec.ren1, T_7595)
    node T_7597 = eq(id_raddr2, mem_waddr)
    node T_7598 = and(io.fpu.dec.ren2, T_7597)
    node T_7599 = eq(id_raddr3, mem_waddr)
    node T_7600 = and(io.fpu.dec.ren3, T_7599)
    node T_7601 = eq(id_waddr, mem_waddr)
    node T_7602 = and(io.fpu.dec.wen, T_7601)
    node T_7603 = or(T_7596, T_7598)
    node T_7604 = or(T_7603, T_7600)
    node T_7605 = or(T_7604, T_7602)
    node fp_data_hazard_mem = and(mem_ctrl.wfd, T_7605)
    node T_7607 = and(data_hazard_mem, mem_cannot_bypass)
    node T_7608 = or(T_7607, fp_data_hazard_mem)
    node id_mem_hazard = and(mem_reg_valid, T_7608)
    node T_7610 = and(mem_reg_valid, data_hazard_mem)
    node T_7611 = and(T_7610, mem_ctrl.mem)
    id_load_use <= T_7611
    node T_7612 = eq(id_raddr1, wb_waddr)
    node T_7613 = and(T_7513, T_7612)
    node T_7614 = eq(id_raddr2, wb_waddr)
    node T_7615 = and(T_7516, T_7614)
    node T_7616 = eq(id_waddr, wb_waddr)
    node T_7617 = and(T_7519, T_7616)
    node T_7618 = or(T_7613, T_7615)
    node T_7619 = or(T_7618, T_7617)
    node data_hazard_wb = and(wb_ctrl.wxd, T_7619)
    node T_7621 = eq(id_raddr1, wb_waddr)
    node T_7622 = and(io.fpu.dec.ren1, T_7621)
    node T_7623 = eq(id_raddr2, wb_waddr)
    node T_7624 = and(io.fpu.dec.ren2, T_7623)
    node T_7625 = eq(id_raddr3, wb_waddr)
    node T_7626 = and(io.fpu.dec.ren3, T_7625)
    node T_7627 = eq(id_waddr, wb_waddr)
    node T_7628 = and(io.fpu.dec.wen, T_7627)
    node T_7629 = or(T_7622, T_7624)
    node T_7630 = or(T_7629, T_7626)
    node T_7631 = or(T_7630, T_7628)
    node fp_data_hazard_wb = and(wb_ctrl.wfd, T_7631)
    node T_7633 = and(data_hazard_wb, wb_set_sboard)
    node T_7634 = or(T_7633, fp_data_hazard_wb)
    node id_wb_hazard = and(wb_reg_valid, T_7634)
    reg T_7637 : UInt<32>, clk with : (reset => (reset, UInt<32>("h00")))
    node T_7639 = and(wb_dcache_miss, wb_ctrl.wfd)
    node T_7640 = or(T_7639, io.fpu.sboard_set)
    node T_7641 = and(T_7640, wb_valid)
    node T_7643 = dshl(UInt<1>("h01"), wb_waddr)
    node T_7645 = mux(T_7641, T_7643, UInt<1>("h00"))
    node T_7646 = or(T_7637, T_7645)
    node T_7647 = or(UInt<1>("h00"), T_7641)
    when T_7647 :
      T_7637 <= T_7646
      skip
    node T_7648 = and(dmem_resp_replay, dmem_resp_fpu)
    node T_7650 = dshl(UInt<1>("h01"), dmem_resp_waddr)
    node T_7652 = mux(T_7648, T_7650, UInt<1>("h00"))
    node T_7653 = not(T_7652)
    node T_7654 = and(T_7646, T_7653)
    node T_7655 = or(T_7647, T_7648)
    when T_7655 :
      T_7637 <= T_7654
      skip
    node T_7657 = dshl(UInt<1>("h01"), io.fpu.sboard_clra)
    node T_7659 = mux(io.fpu.sboard_clr, T_7657, UInt<1>("h00"))
    node T_7660 = not(T_7659)
    node T_7661 = and(T_7654, T_7660)
    node T_7662 = or(T_7655, io.fpu.sboard_clr)
    when T_7662 :
      T_7637 <= T_7661
      skip
    node T_7664 = eq(io.fpu.fcsr_rdy, UInt<1>("h00"))
    node T_7665 = and(id_csr_en, T_7664)
    node T_7666 = dshr(T_7637, id_raddr1)
    node T_7667 = bits(T_7666, 0, 0)
    node T_7668 = and(io.fpu.dec.ren1, T_7667)
    node T_7669 = dshr(T_7637, id_raddr2)
    node T_7670 = bits(T_7669, 0, 0)
    node T_7671 = and(io.fpu.dec.ren2, T_7670)
    node T_7672 = dshr(T_7637, id_raddr3)
    node T_7673 = bits(T_7672, 0, 0)
    node T_7674 = and(io.fpu.dec.ren3, T_7673)
    node T_7675 = dshr(T_7637, id_waddr)
    node T_7676 = bits(T_7675, 0, 0)
    node T_7677 = and(io.fpu.dec.wen, T_7676)
    node T_7678 = or(T_7668, T_7671)
    node T_7679 = or(T_7678, T_7674)
    node T_7680 = or(T_7679, T_7677)
    node id_stall_fpu = or(T_7665, T_7680)
    node T_7682 = or(id_ex_hazard, id_mem_hazard)
    node T_7683 = or(T_7682, id_wb_hazard)
    node T_7684 = or(T_7683, id_sboard_hazard)
    node T_7685 = and(id_ctrl.fp, id_stall_fpu)
    node T_7686 = or(T_7684, T_7685)
    node T_7688 = eq(io.dmem.req.ready, UInt<1>("h00"))
    node T_7689 = and(id_ctrl.mem, T_7688)
    node T_7690 = or(T_7686, T_7689)
    node T_7692 = and(UInt<1>("h00"), wb_reg_rocc_pending)
    node T_7693 = and(T_7692, id_ctrl.rocc)
    node T_7695 = eq(io.rocc.cmd.ready, UInt<1>("h00"))
    node T_7696 = and(T_7693, T_7695)
    node T_7697 = or(T_7690, T_7696)
    node T_7698 = or(T_7697, id_do_fence)
    node ctrl_stalld = or(T_7698, csr.io.csr_stall)
    node T_7701 = eq(io.imem.resp.valid, UInt<1>("h00"))
    node T_7702 = or(T_7701, take_pc_mem_wb)
    node T_7703 = or(T_7702, ctrl_stalld)
    node T_7704 = or(T_7703, csr.io.interrupt)
    ctrl_killd <= T_7704
    io.imem.req.valid <= take_pc_mem_wb
    node T_7705 = or(wb_xcpt, csr.io.eret)
    node T_7706 = mux(replay_wb, wb_reg_pc, mem_npc)
    node T_7707 = mux(T_7705, csr.io.evec, T_7706)
    io.imem.req.bits.pc <= T_7707
    node T_7708 = and(wb_reg_valid, wb_ctrl.fence_i)
    io.imem.invalidate <= T_7708
    node T_7710 = eq(ctrl_stalld, UInt<1>("h00"))
    node T_7711 = or(T_7710, csr.io.interrupt)
    io.imem.resp.ready <= T_7711
    node T_7713 = eq(mem_npc_misaligned, UInt<1>("h00"))
    node T_7714 = and(mem_reg_valid, T_7713)
    node T_7715 = and(T_7714, mem_wrong_npc)
    node T_7716 = and(mem_ctrl.branch, mem_br_taken)
    node T_7717 = or(T_7716, mem_ctrl.jalr)
    node T_7718 = or(T_7717, mem_ctrl.jal)
    node T_7719 = and(T_7715, T_7718)
    node T_7721 = eq(take_pc_wb, UInt<1>("h00"))
    node T_7722 = and(T_7719, T_7721)
    io.imem.btb_update.valid <= T_7722
    node T_7723 = or(mem_ctrl.jal, mem_ctrl.jalr)
    io.imem.btb_update.bits.isJump <= T_7723
    node T_7724 = bits(mem_reg_inst, 19, 15)
    node T_7727 = and(T_7724, UInt<5>("h019"))
    node T_7728 = eq(UInt<1>("h01"), T_7727)
    node T_7729 = and(mem_ctrl.jalr, T_7728)
    io.imem.btb_update.bits.isReturn <= T_7729
    io.imem.btb_update.bits.pc <= mem_reg_pc
    io.imem.btb_update.bits.target <= io.imem.req.bits.pc
    io.imem.btb_update.bits.br_pc <= mem_reg_pc
    io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit
    io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp
    node T_7730 = and(mem_reg_valid, mem_ctrl.branch)
    node T_7732 = eq(take_pc_wb, UInt<1>("h00"))
    node T_7733 = and(T_7730, T_7732)
    io.imem.bht_update.valid <= T_7733
    io.imem.bht_update.bits.pc <= mem_reg_pc
    io.imem.bht_update.bits.taken <= mem_br_taken
    io.imem.bht_update.bits.mispredict <= mem_wrong_npc
    io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction
    node T_7734 = and(mem_reg_valid, io.imem.btb_update.bits.isJump)
    node T_7736 = eq(mem_npc_misaligned, UInt<1>("h00"))
    node T_7737 = and(T_7734, T_7736)
    node T_7739 = eq(take_pc_wb, UInt<1>("h00"))
    node T_7740 = and(T_7737, T_7739)
    io.imem.ras_update.valid <= T_7740
    io.imem.ras_update.bits.returnAddr <= mem_int_wdata
    node T_7741 = bits(mem_waddr, 0, 0)
    node T_7742 = and(mem_ctrl.wxd, T_7741)
    io.imem.ras_update.bits.isCall <= T_7742
    io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn
    io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction
    node T_7744 = eq(ctrl_killd, UInt<1>("h00"))
    node T_7745 = and(T_7744, id_ctrl.fp)
    io.fpu.valid <= T_7745
    io.fpu.killx <= ctrl_killx
    io.fpu.killm <= killm_common
    io.fpu.inst <= io.imem.resp.bits.data[0]
    io.fpu.fromint_data <= T_6992
    node T_7746 = and(dmem_resp_valid, dmem_resp_fpu)
    io.fpu.dmem_resp_val <= T_7746
    io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass
    io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ
    io.fpu.dmem_resp_tag <= dmem_resp_waddr
    node T_7747 = and(ex_reg_valid, ex_ctrl.mem)
    io.dmem.req.valid <= T_7747
    node T_7748 = or(killm_common, mem_xcpt)
    io.dmem.req.bits.kill <= T_7748
    io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd
    io.dmem.req.bits.typ <= ex_ctrl.mem_type
    io.dmem.req.bits.phys <= UInt<1>("h00")
    node T_7750 = shr(T_6992, 38)
    node T_7751 = bits(alu.io.adder_out, 39, 38)
    node T_7753 = eq(T_7750, UInt<1>("h00"))
    node T_7755 = eq(T_7750, UInt<1>("h01"))
    node T_7756 = or(T_7753, T_7755)
    node T_7758 = neq(T_7751, UInt<1>("h00"))
    node T_7759 = asSInt(T_7750)
    node T_7761 = eq(T_7759, asSInt(UInt<1>("h01")))
    node T_7762 = asSInt(T_7750)
    node T_7764 = eq(T_7762, asSInt(UInt<2>("h02")))
    node T_7765 = or(T_7761, T_7764)
    node T_7766 = asSInt(T_7751)
    node T_7768 = eq(T_7766, asSInt(UInt<1>("h01")))
    node T_7769 = bits(T_7751, 0, 0)
    node T_7770 = mux(T_7765, T_7768, T_7769)
    node T_7771 = mux(T_7756, T_7758, T_7770)
    node T_7772 = bits(alu.io.adder_out, 38, 0)
    node T_7773 = cat(T_7771, T_7772)
    io.dmem.req.bits.addr <= T_7773
    node T_7774 = cat(ex_waddr, ex_ctrl.fp)
    io.dmem.req.bits.tag <= T_7774
    node T_7775 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
    io.dmem.req.bits.data <= T_7775
    io.dmem.invalidate_lr <= wb_xcpt
    io.rocc.cmd.valid <= wb_rocc_val
    node T_7777 = neq(csr.io.status.xs, UInt<1>("h00"))
    node T_7778 = and(wb_xcpt, T_7777)
    io.rocc.exception <= T_7778
    node T_7780 = neq(csr.io.status.prv, UInt<1>("h00"))
    io.rocc.s <= T_7780
    wire T_7799 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}
    T_7799 is invalid
    node T_7808 = bits(wb_reg_inst, 6, 0)
    T_7799.opcode <= T_7808
    node T_7809 = bits(wb_reg_inst, 11, 7)
    T_7799.rd <= T_7809
    node T_7810 = bits(wb_reg_inst, 12, 12)
    T_7799.xs2 <= T_7810
    node T_7811 = bits(wb_reg_inst, 13, 13)
    T_7799.xs1 <= T_7811
    node T_7812 = bits(wb_reg_inst, 14, 14)
    T_7799.xd <= T_7812
    node T_7813 = bits(wb_reg_inst, 19, 15)
    T_7799.rs1 <= T_7813
    node T_7814 = bits(wb_reg_inst, 24, 20)
    T_7799.rs2 <= T_7814
    node T_7815 = bits(wb_reg_inst, 31, 25)
    T_7799.funct <= T_7815
    io.rocc.cmd.bits.inst <- T_7799
    io.rocc.cmd.bits.rs1 <= wb_reg_wdata
    io.rocc.cmd.bits.rs2 <= wb_reg_rs2
    node T_7816 = bits(csr.io.time, 32, 0)
    node T_7818 = mux(rf_wen, rf_waddr, UInt<1>("h00"))
    node T_7819 = bits(wb_reg_inst, 19, 15)
    reg T_7820 : UInt, clk
    T_7820 <= T_6992
    reg T_7821 : UInt, clk
    T_7821 <= T_7820
    node T_7822 = bits(wb_reg_inst, 24, 20)
    reg T_7823 : UInt, clk
    T_7823 <= T_6995
    reg T_7824 : UInt, clk
    T_7824 <= T_7823
    node T_7826 = eq(reset, UInt<1>("h00"))
    when T_7826 :
      printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst)
      skip
    
  module BTB : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, flip btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flip invalidate : UInt<1>}
    
    io is invalid
    reg idxValid : UInt<62>, clk with : (reset => (reset, UInt<62>("h00")))
    cmem idxs : UInt<12>[62]
    cmem idxPages : UInt<3>[62]
    cmem tgts : UInt<12>[62]
    cmem tgtPages : UInt<3>[62]
    cmem pages : UInt<27>[6]
    reg pageValid : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    infer mport T_590 = idxPages[UInt<1>("h00")], clk
    node T_592 = dshl(UInt<1>("h01"), T_590)
    node T_593 = bits(T_592, 5, 0)
    infer mport T_595 = idxPages[UInt<1>("h01")], clk
    node T_597 = dshl(UInt<1>("h01"), T_595)
    node T_598 = bits(T_597, 5, 0)
    infer mport T_600 = idxPages[UInt<2>("h02")], clk
    node T_602 = dshl(UInt<1>("h01"), T_600)
    node T_603 = bits(T_602, 5, 0)
    infer mport T_605 = idxPages[UInt<2>("h03")], clk
    node T_607 = dshl(UInt<1>("h01"), T_605)
    node T_608 = bits(T_607, 5, 0)
    infer mport T_610 = idxPages[UInt<3>("h04")], clk
    node T_612 = dshl(UInt<1>("h01"), T_610)
    node T_613 = bits(T_612, 5, 0)
    infer mport T_615 = idxPages[UInt<3>("h05")], clk
    node T_617 = dshl(UInt<1>("h01"), T_615)
    node T_618 = bits(T_617, 5, 0)
    infer mport T_620 = idxPages[UInt<3>("h06")], clk
    node T_622 = dshl(UInt<1>("h01"), T_620)
    node T_623 = bits(T_622, 5, 0)
    infer mport T_625 = idxPages[UInt<3>("h07")], clk
    node T_627 = dshl(UInt<1>("h01"), T_625)
    node T_628 = bits(T_627, 5, 0)
    infer mport T_630 = idxPages[UInt<4>("h08")], clk
    node T_632 = dshl(UInt<1>("h01"), T_630)
    node T_633 = bits(T_632, 5, 0)
    infer mport T_635 = idxPages[UInt<4>("h09")], clk
    node T_637 = dshl(UInt<1>("h01"), T_635)
    node T_638 = bits(T_637, 5, 0)
    infer mport T_640 = idxPages[UInt<4>("h0a")], clk
    node T_642 = dshl(UInt<1>("h01"), T_640)
    node T_643 = bits(T_642, 5, 0)
    infer mport T_645 = idxPages[UInt<4>("h0b")], clk
    node T_647 = dshl(UInt<1>("h01"), T_645)
    node T_648 = bits(T_647, 5, 0)
    infer mport T_650 = idxPages[UInt<4>("h0c")], clk
    node T_652 = dshl(UInt<1>("h01"), T_650)
    node T_653 = bits(T_652, 5, 0)
    infer mport T_655 = idxPages[UInt<4>("h0d")], clk
    node T_657 = dshl(UInt<1>("h01"), T_655)
    node T_658 = bits(T_657, 5, 0)
    infer mport T_660 = idxPages[UInt<4>("h0e")], clk
    node T_662 = dshl(UInt<1>("h01"), T_660)
    node T_663 = bits(T_662, 5, 0)
    infer mport T_665 = idxPages[UInt<4>("h0f")], clk
    node T_667 = dshl(UInt<1>("h01"), T_665)
    node T_668 = bits(T_667, 5, 0)
    infer mport T_670 = idxPages[UInt<5>("h010")], clk
    node T_672 = dshl(UInt<1>("h01"), T_670)
    node T_673 = bits(T_672, 5, 0)
    infer mport T_675 = idxPages[UInt<5>("h011")], clk
    node T_677 = dshl(UInt<1>("h01"), T_675)
    node T_678 = bits(T_677, 5, 0)
    infer mport T_680 = idxPages[UInt<5>("h012")], clk
    node T_682 = dshl(UInt<1>("h01"), T_680)
    node T_683 = bits(T_682, 5, 0)
    infer mport T_685 = idxPages[UInt<5>("h013")], clk
    node T_687 = dshl(UInt<1>("h01"), T_685)
    node T_688 = bits(T_687, 5, 0)
    infer mport T_690 = idxPages[UInt<5>("h014")], clk
    node T_692 = dshl(UInt<1>("h01"), T_690)
    node T_693 = bits(T_692, 5, 0)
    infer mport T_695 = idxPages[UInt<5>("h015")], clk
    node T_697 = dshl(UInt<1>("h01"), T_695)
    node T_698 = bits(T_697, 5, 0)
    infer mport T_700 = idxPages[UInt<5>("h016")], clk
    node T_702 = dshl(UInt<1>("h01"), T_700)
    node T_703 = bits(T_702, 5, 0)
    infer mport T_705 = idxPages[UInt<5>("h017")], clk
    node T_707 = dshl(UInt<1>("h01"), T_705)
    node T_708 = bits(T_707, 5, 0)
    infer mport T_710 = idxPages[UInt<5>("h018")], clk
    node T_712 = dshl(UInt<1>("h01"), T_710)
    node T_713 = bits(T_712, 5, 0)
    infer mport T_715 = idxPages[UInt<5>("h019")], clk
    node T_717 = dshl(UInt<1>("h01"), T_715)
    node T_718 = bits(T_717, 5, 0)
    infer mport T_720 = idxPages[UInt<5>("h01a")], clk
    node T_722 = dshl(UInt<1>("h01"), T_720)
    node T_723 = bits(T_722, 5, 0)
    infer mport T_725 = idxPages[UInt<5>("h01b")], clk
    node T_727 = dshl(UInt<1>("h01"), T_725)
    node T_728 = bits(T_727, 5, 0)
    infer mport T_730 = idxPages[UInt<5>("h01c")], clk
    node T_732 = dshl(UInt<1>("h01"), T_730)
    node T_733 = bits(T_732, 5, 0)
    infer mport T_735 = idxPages[UInt<5>("h01d")], clk
    node T_737 = dshl(UInt<1>("h01"), T_735)
    node T_738 = bits(T_737, 5, 0)
    infer mport T_740 = idxPages[UInt<5>("h01e")], clk
    node T_742 = dshl(UInt<1>("h01"), T_740)
    node T_743 = bits(T_742, 5, 0)
    infer mport T_745 = idxPages[UInt<5>("h01f")], clk
    node T_747 = dshl(UInt<1>("h01"), T_745)
    node T_748 = bits(T_747, 5, 0)
    infer mport T_750 = idxPages[UInt<6>("h020")], clk
    node T_752 = dshl(UInt<1>("h01"), T_750)
    node T_753 = bits(T_752, 5, 0)
    infer mport T_755 = idxPages[UInt<6>("h021")], clk
    node T_757 = dshl(UInt<1>("h01"), T_755)
    node T_758 = bits(T_757, 5, 0)
    infer mport T_760 = idxPages[UInt<6>("h022")], clk
    node T_762 = dshl(UInt<1>("h01"), T_760)
    node T_763 = bits(T_762, 5, 0)
    infer mport T_765 = idxPages[UInt<6>("h023")], clk
    node T_767 = dshl(UInt<1>("h01"), T_765)
    node T_768 = bits(T_767, 5, 0)
    infer mport T_770 = idxPages[UInt<6>("h024")], clk
    node T_772 = dshl(UInt<1>("h01"), T_770)
    node T_773 = bits(T_772, 5, 0)
    infer mport T_775 = idxPages[UInt<6>("h025")], clk
    node T_777 = dshl(UInt<1>("h01"), T_775)
    node T_778 = bits(T_777, 5, 0)
    infer mport T_780 = idxPages[UInt<6>("h026")], clk
    node T_782 = dshl(UInt<1>("h01"), T_780)
    node T_783 = bits(T_782, 5, 0)
    infer mport T_785 = idxPages[UInt<6>("h027")], clk
    node T_787 = dshl(UInt<1>("h01"), T_785)
    node T_788 = bits(T_787, 5, 0)
    infer mport T_790 = idxPages[UInt<6>("h028")], clk
    node T_792 = dshl(UInt<1>("h01"), T_790)
    node T_793 = bits(T_792, 5, 0)
    infer mport T_795 = idxPages[UInt<6>("h029")], clk
    node T_797 = dshl(UInt<1>("h01"), T_795)
    node T_798 = bits(T_797, 5, 0)
    infer mport T_800 = idxPages[UInt<6>("h02a")], clk
    node T_802 = dshl(UInt<1>("h01"), T_800)
    node T_803 = bits(T_802, 5, 0)
    infer mport T_805 = idxPages[UInt<6>("h02b")], clk
    node T_807 = dshl(UInt<1>("h01"), T_805)
    node T_808 = bits(T_807, 5, 0)
    infer mport T_810 = idxPages[UInt<6>("h02c")], clk
    node T_812 = dshl(UInt<1>("h01"), T_810)
    node T_813 = bits(T_812, 5, 0)
    infer mport T_815 = idxPages[UInt<6>("h02d")], clk
    node T_817 = dshl(UInt<1>("h01"), T_815)
    node T_818 = bits(T_817, 5, 0)
    infer mport T_820 = idxPages[UInt<6>("h02e")], clk
    node T_822 = dshl(UInt<1>("h01"), T_820)
    node T_823 = bits(T_822, 5, 0)
    infer mport T_825 = idxPages[UInt<6>("h02f")], clk
    node T_827 = dshl(UInt<1>("h01"), T_825)
    node T_828 = bits(T_827, 5, 0)
    infer mport T_830 = idxPages[UInt<6>("h030")], clk
    node T_832 = dshl(UInt<1>("h01"), T_830)
    node T_833 = bits(T_832, 5, 0)
    infer mport T_835 = idxPages[UInt<6>("h031")], clk
    node T_837 = dshl(UInt<1>("h01"), T_835)
    node T_838 = bits(T_837, 5, 0)
    infer mport T_840 = idxPages[UInt<6>("h032")], clk
    node T_842 = dshl(UInt<1>("h01"), T_840)
    node T_843 = bits(T_842, 5, 0)
    infer mport T_845 = idxPages[UInt<6>("h033")], clk
    node T_847 = dshl(UInt<1>("h01"), T_845)
    node T_848 = bits(T_847, 5, 0)
    infer mport T_850 = idxPages[UInt<6>("h034")], clk
    node T_852 = dshl(UInt<1>("h01"), T_850)
    node T_853 = bits(T_852, 5, 0)
    infer mport T_855 = idxPages[UInt<6>("h035")], clk
    node T_857 = dshl(UInt<1>("h01"), T_855)
    node T_858 = bits(T_857, 5, 0)
    infer mport T_860 = idxPages[UInt<6>("h036")], clk
    node T_862 = dshl(UInt<1>("h01"), T_860)
    node T_863 = bits(T_862, 5, 0)
    infer mport T_865 = idxPages[UInt<6>("h037")], clk
    node T_867 = dshl(UInt<1>("h01"), T_865)
    node T_868 = bits(T_867, 5, 0)
    infer mport T_870 = idxPages[UInt<6>("h038")], clk
    node T_872 = dshl(UInt<1>("h01"), T_870)
    node T_873 = bits(T_872, 5, 0)
    infer mport T_875 = idxPages[UInt<6>("h039")], clk
    node T_877 = dshl(UInt<1>("h01"), T_875)
    node T_878 = bits(T_877, 5, 0)
    infer mport T_880 = idxPages[UInt<6>("h03a")], clk
    node T_882 = dshl(UInt<1>("h01"), T_880)
    node T_883 = bits(T_882, 5, 0)
    infer mport T_885 = idxPages[UInt<6>("h03b")], clk
    node T_887 = dshl(UInt<1>("h01"), T_885)
    node T_888 = bits(T_887, 5, 0)
    infer mport T_890 = idxPages[UInt<6>("h03c")], clk
    node T_892 = dshl(UInt<1>("h01"), T_890)
    node T_893 = bits(T_892, 5, 0)
    infer mport T_895 = idxPages[UInt<6>("h03d")], clk
    node T_897 = dshl(UInt<1>("h01"), T_895)
    node T_898 = bits(T_897, 5, 0)
    infer mport T_900 = tgtPages[UInt<1>("h00")], clk
    node T_902 = dshl(UInt<1>("h01"), T_900)
    node T_903 = bits(T_902, 5, 0)
    infer mport T_905 = tgtPages[UInt<1>("h01")], clk
    node T_907 = dshl(UInt<1>("h01"), T_905)
    node T_908 = bits(T_907, 5, 0)
    infer mport T_910 = tgtPages[UInt<2>("h02")], clk
    node T_912 = dshl(UInt<1>("h01"), T_910)
    node T_913 = bits(T_912, 5, 0)
    infer mport T_915 = tgtPages[UInt<2>("h03")], clk
    node T_917 = dshl(UInt<1>("h01"), T_915)
    node T_918 = bits(T_917, 5, 0)
    infer mport T_920 = tgtPages[UInt<3>("h04")], clk
    node T_922 = dshl(UInt<1>("h01"), T_920)
    node T_923 = bits(T_922, 5, 0)
    infer mport T_925 = tgtPages[UInt<3>("h05")], clk
    node T_927 = dshl(UInt<1>("h01"), T_925)
    node T_928 = bits(T_927, 5, 0)
    infer mport T_930 = tgtPages[UInt<3>("h06")], clk
    node T_932 = dshl(UInt<1>("h01"), T_930)
    node T_933 = bits(T_932, 5, 0)
    infer mport T_935 = tgtPages[UInt<3>("h07")], clk
    node T_937 = dshl(UInt<1>("h01"), T_935)
    node T_938 = bits(T_937, 5, 0)
    infer mport T_940 = tgtPages[UInt<4>("h08")], clk
    node T_942 = dshl(UInt<1>("h01"), T_940)
    node T_943 = bits(T_942, 5, 0)
    infer mport T_945 = tgtPages[UInt<4>("h09")], clk
    node T_947 = dshl(UInt<1>("h01"), T_945)
    node T_948 = bits(T_947, 5, 0)
    infer mport T_950 = tgtPages[UInt<4>("h0a")], clk
    node T_952 = dshl(UInt<1>("h01"), T_950)
    node T_953 = bits(T_952, 5, 0)
    infer mport T_955 = tgtPages[UInt<4>("h0b")], clk
    node T_957 = dshl(UInt<1>("h01"), T_955)
    node T_958 = bits(T_957, 5, 0)
    infer mport T_960 = tgtPages[UInt<4>("h0c")], clk
    node T_962 = dshl(UInt<1>("h01"), T_960)
    node T_963 = bits(T_962, 5, 0)
    infer mport T_965 = tgtPages[UInt<4>("h0d")], clk
    node T_967 = dshl(UInt<1>("h01"), T_965)
    node T_968 = bits(T_967, 5, 0)
    infer mport T_970 = tgtPages[UInt<4>("h0e")], clk
    node T_972 = dshl(UInt<1>("h01"), T_970)
    node T_973 = bits(T_972, 5, 0)
    infer mport T_975 = tgtPages[UInt<4>("h0f")], clk
    node T_977 = dshl(UInt<1>("h01"), T_975)
    node T_978 = bits(T_977, 5, 0)
    infer mport T_980 = tgtPages[UInt<5>("h010")], clk
    node T_982 = dshl(UInt<1>("h01"), T_980)
    node T_983 = bits(T_982, 5, 0)
    infer mport T_985 = tgtPages[UInt<5>("h011")], clk
    node T_987 = dshl(UInt<1>("h01"), T_985)
    node T_988 = bits(T_987, 5, 0)
    infer mport T_990 = tgtPages[UInt<5>("h012")], clk
    node T_992 = dshl(UInt<1>("h01"), T_990)
    node T_993 = bits(T_992, 5, 0)
    infer mport T_995 = tgtPages[UInt<5>("h013")], clk
    node T_997 = dshl(UInt<1>("h01"), T_995)
    node T_998 = bits(T_997, 5, 0)
    infer mport T_1000 = tgtPages[UInt<5>("h014")], clk
    node T_1002 = dshl(UInt<1>("h01"), T_1000)
    node T_1003 = bits(T_1002, 5, 0)
    infer mport T_1005 = tgtPages[UInt<5>("h015")], clk
    node T_1007 = dshl(UInt<1>("h01"), T_1005)
    node T_1008 = bits(T_1007, 5, 0)
    infer mport T_1010 = tgtPages[UInt<5>("h016")], clk
    node T_1012 = dshl(UInt<1>("h01"), T_1010)
    node T_1013 = bits(T_1012, 5, 0)
    infer mport T_1015 = tgtPages[UInt<5>("h017")], clk
    node T_1017 = dshl(UInt<1>("h01"), T_1015)
    node T_1018 = bits(T_1017, 5, 0)
    infer mport T_1020 = tgtPages[UInt<5>("h018")], clk
    node T_1022 = dshl(UInt<1>("h01"), T_1020)
    node T_1023 = bits(T_1022, 5, 0)
    infer mport T_1025 = tgtPages[UInt<5>("h019")], clk
    node T_1027 = dshl(UInt<1>("h01"), T_1025)
    node T_1028 = bits(T_1027, 5, 0)
    infer mport T_1030 = tgtPages[UInt<5>("h01a")], clk
    node T_1032 = dshl(UInt<1>("h01"), T_1030)
    node T_1033 = bits(T_1032, 5, 0)
    infer mport T_1035 = tgtPages[UInt<5>("h01b")], clk
    node T_1037 = dshl(UInt<1>("h01"), T_1035)
    node T_1038 = bits(T_1037, 5, 0)
    infer mport T_1040 = tgtPages[UInt<5>("h01c")], clk
    node T_1042 = dshl(UInt<1>("h01"), T_1040)
    node T_1043 = bits(T_1042, 5, 0)
    infer mport T_1045 = tgtPages[UInt<5>("h01d")], clk
    node T_1047 = dshl(UInt<1>("h01"), T_1045)
    node T_1048 = bits(T_1047, 5, 0)
    infer mport T_1050 = tgtPages[UInt<5>("h01e")], clk
    node T_1052 = dshl(UInt<1>("h01"), T_1050)
    node T_1053 = bits(T_1052, 5, 0)
    infer mport T_1055 = tgtPages[UInt<5>("h01f")], clk
    node T_1057 = dshl(UInt<1>("h01"), T_1055)
    node T_1058 = bits(T_1057, 5, 0)
    infer mport T_1060 = tgtPages[UInt<6>("h020")], clk
    node T_1062 = dshl(UInt<1>("h01"), T_1060)
    node T_1063 = bits(T_1062, 5, 0)
    infer mport T_1065 = tgtPages[UInt<6>("h021")], clk
    node T_1067 = dshl(UInt<1>("h01"), T_1065)
    node T_1068 = bits(T_1067, 5, 0)
    infer mport T_1070 = tgtPages[UInt<6>("h022")], clk
    node T_1072 = dshl(UInt<1>("h01"), T_1070)
    node T_1073 = bits(T_1072, 5, 0)
    infer mport T_1075 = tgtPages[UInt<6>("h023")], clk
    node T_1077 = dshl(UInt<1>("h01"), T_1075)
    node T_1078 = bits(T_1077, 5, 0)
    infer mport T_1080 = tgtPages[UInt<6>("h024")], clk
    node T_1082 = dshl(UInt<1>("h01"), T_1080)
    node T_1083 = bits(T_1082, 5, 0)
    infer mport T_1085 = tgtPages[UInt<6>("h025")], clk
    node T_1087 = dshl(UInt<1>("h01"), T_1085)
    node T_1088 = bits(T_1087, 5, 0)
    infer mport T_1090 = tgtPages[UInt<6>("h026")], clk
    node T_1092 = dshl(UInt<1>("h01"), T_1090)
    node T_1093 = bits(T_1092, 5, 0)
    infer mport T_1095 = tgtPages[UInt<6>("h027")], clk
    node T_1097 = dshl(UInt<1>("h01"), T_1095)
    node T_1098 = bits(T_1097, 5, 0)
    infer mport T_1100 = tgtPages[UInt<6>("h028")], clk
    node T_1102 = dshl(UInt<1>("h01"), T_1100)
    node T_1103 = bits(T_1102, 5, 0)
    infer mport T_1105 = tgtPages[UInt<6>("h029")], clk
    node T_1107 = dshl(UInt<1>("h01"), T_1105)
    node T_1108 = bits(T_1107, 5, 0)
    infer mport T_1110 = tgtPages[UInt<6>("h02a")], clk
    node T_1112 = dshl(UInt<1>("h01"), T_1110)
    node T_1113 = bits(T_1112, 5, 0)
    infer mport T_1115 = tgtPages[UInt<6>("h02b")], clk
    node T_1117 = dshl(UInt<1>("h01"), T_1115)
    node T_1118 = bits(T_1117, 5, 0)
    infer mport T_1120 = tgtPages[UInt<6>("h02c")], clk
    node T_1122 = dshl(UInt<1>("h01"), T_1120)
    node T_1123 = bits(T_1122, 5, 0)
    infer mport T_1125 = tgtPages[UInt<6>("h02d")], clk
    node T_1127 = dshl(UInt<1>("h01"), T_1125)
    node T_1128 = bits(T_1127, 5, 0)
    infer mport T_1130 = tgtPages[UInt<6>("h02e")], clk
    node T_1132 = dshl(UInt<1>("h01"), T_1130)
    node T_1133 = bits(T_1132, 5, 0)
    infer mport T_1135 = tgtPages[UInt<6>("h02f")], clk
    node T_1137 = dshl(UInt<1>("h01"), T_1135)
    node T_1138 = bits(T_1137, 5, 0)
    infer mport T_1140 = tgtPages[UInt<6>("h030")], clk
    node T_1142 = dshl(UInt<1>("h01"), T_1140)
    node T_1143 = bits(T_1142, 5, 0)
    infer mport T_1145 = tgtPages[UInt<6>("h031")], clk
    node T_1147 = dshl(UInt<1>("h01"), T_1145)
    node T_1148 = bits(T_1147, 5, 0)
    infer mport T_1150 = tgtPages[UInt<6>("h032")], clk
    node T_1152 = dshl(UInt<1>("h01"), T_1150)
    node T_1153 = bits(T_1152, 5, 0)
    infer mport T_1155 = tgtPages[UInt<6>("h033")], clk
    node T_1157 = dshl(UInt<1>("h01"), T_1155)
    node T_1158 = bits(T_1157, 5, 0)
    infer mport T_1160 = tgtPages[UInt<6>("h034")], clk
    node T_1162 = dshl(UInt<1>("h01"), T_1160)
    node T_1163 = bits(T_1162, 5, 0)
    infer mport T_1165 = tgtPages[UInt<6>("h035")], clk
    node T_1167 = dshl(UInt<1>("h01"), T_1165)
    node T_1168 = bits(T_1167, 5, 0)
    infer mport T_1170 = tgtPages[UInt<6>("h036")], clk
    node T_1172 = dshl(UInt<1>("h01"), T_1170)
    node T_1173 = bits(T_1172, 5, 0)
    infer mport T_1175 = tgtPages[UInt<6>("h037")], clk
    node T_1177 = dshl(UInt<1>("h01"), T_1175)
    node T_1178 = bits(T_1177, 5, 0)
    infer mport T_1180 = tgtPages[UInt<6>("h038")], clk
    node T_1182 = dshl(UInt<1>("h01"), T_1180)
    node T_1183 = bits(T_1182, 5, 0)
    infer mport T_1185 = tgtPages[UInt<6>("h039")], clk
    node T_1187 = dshl(UInt<1>("h01"), T_1185)
    node T_1188 = bits(T_1187, 5, 0)
    infer mport T_1190 = tgtPages[UInt<6>("h03a")], clk
    node T_1192 = dshl(UInt<1>("h01"), T_1190)
    node T_1193 = bits(T_1192, 5, 0)
    infer mport T_1195 = tgtPages[UInt<6>("h03b")], clk
    node T_1197 = dshl(UInt<1>("h01"), T_1195)
    node T_1198 = bits(T_1197, 5, 0)
    infer mport T_1200 = tgtPages[UInt<6>("h03c")], clk
    node T_1202 = dshl(UInt<1>("h01"), T_1200)
    node T_1203 = bits(T_1202, 5, 0)
    infer mport T_1205 = tgtPages[UInt<6>("h03d")], clk
    node T_1207 = dshl(UInt<1>("h01"), T_1205)
    node T_1208 = bits(T_1207, 5, 0)
    reg useRAS : UInt<1>[62], clk
    reg isJump : UInt<1>[62], clk
    cmem brIdx : UInt<1>[62]
    reg T_1478 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_1478 <= io.btb_update.valid
    reg T_1479 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clk
    when io.btb_update.valid :
      T_1479 <- io.btb_update.bits
      skip
    wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}
    r_btb_update is invalid
    r_btb_update.valid <= T_1478
    r_btb_update.bits <- T_1479
    node T_1663 = shr(io.req.bits.addr, 12)
    infer mport T_1665 = pages[UInt<1>("h00")], clk
    node T_1666 = eq(T_1665, T_1663)
    infer mport T_1668 = pages[UInt<1>("h01")], clk
    node T_1669 = eq(T_1668, T_1663)
    infer mport T_1671 = pages[UInt<2>("h02")], clk
    node T_1672 = eq(T_1671, T_1663)
    infer mport T_1674 = pages[UInt<2>("h03")], clk
    node T_1675 = eq(T_1674, T_1663)
    infer mport T_1677 = pages[UInt<3>("h04")], clk
    node T_1678 = eq(T_1677, T_1663)
    infer mport T_1680 = pages[UInt<3>("h05")], clk
    node T_1681 = eq(T_1680, T_1663)
    wire T_1683 : UInt<1>[6]
    T_1683[0] <= T_1666
    T_1683[1] <= T_1669
    T_1683[2] <= T_1672
    T_1683[3] <= T_1675
    T_1683[4] <= T_1678
    T_1683[5] <= T_1681
    node T_1691 = cat(T_1683[4], T_1683[3])
    node T_1692 = cat(T_1683[5], T_1691)
    node T_1693 = cat(T_1683[1], T_1683[0])
    node T_1694 = cat(T_1683[2], T_1693)
    node T_1695 = cat(T_1692, T_1694)
    node pageHit = and(T_1695, pageValid)
    node T_1697 = bits(io.req.bits.addr, 11, 0)
    infer mport T_1699 = idxs[UInt<1>("h00")], clk
    node T_1700 = eq(T_1699, T_1697)
    infer mport T_1702 = idxs[UInt<1>("h01")], clk
    node T_1703 = eq(T_1702, T_1697)
    infer mport T_1705 = idxs[UInt<2>("h02")], clk
    node T_1706 = eq(T_1705, T_1697)
    infer mport T_1708 = idxs[UInt<2>("h03")], clk
    node T_1709 = eq(T_1708, T_1697)
    infer mport T_1711 = idxs[UInt<3>("h04")], clk
    node T_1712 = eq(T_1711, T_1697)
    infer mport T_1714 = idxs[UInt<3>("h05")], clk
    node T_1715 = eq(T_1714, T_1697)
    infer mport T_1717 = idxs[UInt<3>("h06")], clk
    node T_1718 = eq(T_1717, T_1697)
    infer mport T_1720 = idxs[UInt<3>("h07")], clk
    node T_1721 = eq(T_1720, T_1697)
    infer mport T_1723 = idxs[UInt<4>("h08")], clk
    node T_1724 = eq(T_1723, T_1697)
    infer mport T_1726 = idxs[UInt<4>("h09")], clk
    node T_1727 = eq(T_1726, T_1697)
    infer mport T_1729 = idxs[UInt<4>("h0a")], clk
    node T_1730 = eq(T_1729, T_1697)
    infer mport T_1732 = idxs[UInt<4>("h0b")], clk
    node T_1733 = eq(T_1732, T_1697)
    infer mport T_1735 = idxs[UInt<4>("h0c")], clk
    node T_1736 = eq(T_1735, T_1697)
    infer mport T_1738 = idxs[UInt<4>("h0d")], clk
    node T_1739 = eq(T_1738, T_1697)
    infer mport T_1741 = idxs[UInt<4>("h0e")], clk
    node T_1742 = eq(T_1741, T_1697)
    infer mport T_1744 = idxs[UInt<4>("h0f")], clk
    node T_1745 = eq(T_1744, T_1697)
    infer mport T_1747 = idxs[UInt<5>("h010")], clk
    node T_1748 = eq(T_1747, T_1697)
    infer mport T_1750 = idxs[UInt<5>("h011")], clk
    node T_1751 = eq(T_1750, T_1697)
    infer mport T_1753 = idxs[UInt<5>("h012")], clk
    node T_1754 = eq(T_1753, T_1697)
    infer mport T_1756 = idxs[UInt<5>("h013")], clk
    node T_1757 = eq(T_1756, T_1697)
    infer mport T_1759 = idxs[UInt<5>("h014")], clk
    node T_1760 = eq(T_1759, T_1697)
    infer mport T_1762 = idxs[UInt<5>("h015")], clk
    node T_1763 = eq(T_1762, T_1697)
    infer mport T_1765 = idxs[UInt<5>("h016")], clk
    node T_1766 = eq(T_1765, T_1697)
    infer mport T_1768 = idxs[UInt<5>("h017")], clk
    node T_1769 = eq(T_1768, T_1697)
    infer mport T_1771 = idxs[UInt<5>("h018")], clk
    node T_1772 = eq(T_1771, T_1697)
    infer mport T_1774 = idxs[UInt<5>("h019")], clk
    node T_1775 = eq(T_1774, T_1697)
    infer mport T_1777 = idxs[UInt<5>("h01a")], clk
    node T_1778 = eq(T_1777, T_1697)
    infer mport T_1780 = idxs[UInt<5>("h01b")], clk
    node T_1781 = eq(T_1780, T_1697)
    infer mport T_1783 = idxs[UInt<5>("h01c")], clk
    node T_1784 = eq(T_1783, T_1697)
    infer mport T_1786 = idxs[UInt<5>("h01d")], clk
    node T_1787 = eq(T_1786, T_1697)
    infer mport T_1789 = idxs[UInt<5>("h01e")], clk
    node T_1790 = eq(T_1789, T_1697)
    infer mport T_1792 = idxs[UInt<5>("h01f")], clk
    node T_1793 = eq(T_1792, T_1697)
    infer mport T_1795 = idxs[UInt<6>("h020")], clk
    node T_1796 = eq(T_1795, T_1697)
    infer mport T_1798 = idxs[UInt<6>("h021")], clk
    node T_1799 = eq(T_1798, T_1697)
    infer mport T_1801 = idxs[UInt<6>("h022")], clk
    node T_1802 = eq(T_1801, T_1697)
    infer mport T_1804 = idxs[UInt<6>("h023")], clk
    node T_1805 = eq(T_1804, T_1697)
    infer mport T_1807 = idxs[UInt<6>("h024")], clk
    node T_1808 = eq(T_1807, T_1697)
    infer mport T_1810 = idxs[UInt<6>("h025")], clk
    node T_1811 = eq(T_1810, T_1697)
    infer mport T_1813 = idxs[UInt<6>("h026")], clk
    node T_1814 = eq(T_1813, T_1697)
    infer mport T_1816 = idxs[UInt<6>("h027")], clk
    node T_1817 = eq(T_1816, T_1697)
    infer mport T_1819 = idxs[UInt<6>("h028")], clk
    node T_1820 = eq(T_1819, T_1697)
    infer mport T_1822 = idxs[UInt<6>("h029")], clk
    node T_1823 = eq(T_1822, T_1697)
    infer mport T_1825 = idxs[UInt<6>("h02a")], clk
    node T_1826 = eq(T_1825, T_1697)
    infer mport T_1828 = idxs[UInt<6>("h02b")], clk
    node T_1829 = eq(T_1828, T_1697)
    infer mport T_1831 = idxs[UInt<6>("h02c")], clk
    node T_1832 = eq(T_1831, T_1697)
    infer mport T_1834 = idxs[UInt<6>("h02d")], clk
    node T_1835 = eq(T_1834, T_1697)
    infer mport T_1837 = idxs[UInt<6>("h02e")], clk
    node T_1838 = eq(T_1837, T_1697)
    infer mport T_1840 = idxs[UInt<6>("h02f")], clk
    node T_1841 = eq(T_1840, T_1697)
    infer mport T_1843 = idxs[UInt<6>("h030")], clk
    node T_1844 = eq(T_1843, T_1697)
    infer mport T_1846 = idxs[UInt<6>("h031")], clk
    node T_1847 = eq(T_1846, T_1697)
    infer mport T_1849 = idxs[UInt<6>("h032")], clk
    node T_1850 = eq(T_1849, T_1697)
    infer mport T_1852 = idxs[UInt<6>("h033")], clk
    node T_1853 = eq(T_1852, T_1697)
    infer mport T_1855 = idxs[UInt<6>("h034")], clk
    node T_1856 = eq(T_1855, T_1697)
    infer mport T_1858 = idxs[UInt<6>("h035")], clk
    node T_1859 = eq(T_1858, T_1697)
    infer mport T_1861 = idxs[UInt<6>("h036")], clk
    node T_1862 = eq(T_1861, T_1697)
    infer mport T_1864 = idxs[UInt<6>("h037")], clk
    node T_1865 = eq(T_1864, T_1697)
    infer mport T_1867 = idxs[UInt<6>("h038")], clk
    node T_1868 = eq(T_1867, T_1697)
    infer mport T_1870 = idxs[UInt<6>("h039")], clk
    node T_1871 = eq(T_1870, T_1697)
    infer mport T_1873 = idxs[UInt<6>("h03a")], clk
    node T_1874 = eq(T_1873, T_1697)
    infer mport T_1876 = idxs[UInt<6>("h03b")], clk
    node T_1877 = eq(T_1876, T_1697)
    infer mport T_1879 = idxs[UInt<6>("h03c")], clk
    node T_1880 = eq(T_1879, T_1697)
    infer mport T_1882 = idxs[UInt<6>("h03d")], clk
    node T_1883 = eq(T_1882, T_1697)
    wire T_1885 : UInt<1>[62]
    T_1885[0] <= T_1700
    T_1885[1] <= T_1703
    T_1885[2] <= T_1706
    T_1885[3] <= T_1709
    T_1885[4] <= T_1712
    T_1885[5] <= T_1715
    T_1885[6] <= T_1718
    T_1885[7] <= T_1721
    T_1885[8] <= T_1724
    T_1885[9] <= T_1727
    T_1885[10] <= T_1730
    T_1885[11] <= T_1733
    T_1885[12] <= T_1736
    T_1885[13] <= T_1739
    T_1885[14] <= T_1742
    T_1885[15] <= T_1745
    T_1885[16] <= T_1748
    T_1885[17] <= T_1751
    T_1885[18] <= T_1754
    T_1885[19] <= T_1757
    T_1885[20] <= T_1760
    T_1885[21] <= T_1763
    T_1885[22] <= T_1766
    T_1885[23] <= T_1769
    T_1885[24] <= T_1772
    T_1885[25] <= T_1775
    T_1885[26] <= T_1778
    T_1885[27] <= T_1781
    T_1885[28] <= T_1784
    T_1885[29] <= T_1787
    T_1885[30] <= T_1790
    T_1885[31] <= T_1793
    T_1885[32] <= T_1796
    T_1885[33] <= T_1799
    T_1885[34] <= T_1802
    T_1885[35] <= T_1805
    T_1885[36] <= T_1808
    T_1885[37] <= T_1811
    T_1885[38] <= T_1814
    T_1885[39] <= T_1817
    T_1885[40] <= T_1820
    T_1885[41] <= T_1823
    T_1885[42] <= T_1826
    T_1885[43] <= T_1829
    T_1885[44] <= T_1832
    T_1885[45] <= T_1835
    T_1885[46] <= T_1838
    T_1885[47] <= T_1841
    T_1885[48] <= T_1844
    T_1885[49] <= T_1847
    T_1885[50] <= T_1850
    T_1885[51] <= T_1853
    T_1885[52] <= T_1856
    T_1885[53] <= T_1859
    T_1885[54] <= T_1862
    T_1885[55] <= T_1865
    T_1885[56] <= T_1868
    T_1885[57] <= T_1871
    T_1885[58] <= T_1874
    T_1885[59] <= T_1877
    T_1885[60] <= T_1880
    T_1885[61] <= T_1883
    node T_1949 = cat(T_1885[60], T_1885[59])
    node T_1950 = cat(T_1885[61], T_1949)
    node T_1951 = cat(T_1885[58], T_1885[57])
    node T_1952 = cat(T_1885[56], T_1885[55])
    node T_1953 = cat(T_1951, T_1952)
    node T_1954 = cat(T_1950, T_1953)
    node T_1955 = cat(T_1885[54], T_1885[53])
    node T_1956 = cat(T_1885[52], T_1885[51])
    node T_1957 = cat(T_1955, T_1956)
    node T_1958 = cat(T_1885[50], T_1885[49])
    node T_1959 = cat(T_1885[48], T_1885[47])
    node T_1960 = cat(T_1958, T_1959)
    node T_1961 = cat(T_1957, T_1960)
    node T_1962 = cat(T_1954, T_1961)
    node T_1963 = cat(T_1885[46], T_1885[45])
    node T_1964 = cat(T_1885[44], T_1885[43])
    node T_1965 = cat(T_1963, T_1964)
    node T_1966 = cat(T_1885[42], T_1885[41])
    node T_1967 = cat(T_1885[40], T_1885[39])
    node T_1968 = cat(T_1966, T_1967)
    node T_1969 = cat(T_1965, T_1968)
    node T_1970 = cat(T_1885[38], T_1885[37])
    node T_1971 = cat(T_1885[36], T_1885[35])
    node T_1972 = cat(T_1970, T_1971)
    node T_1973 = cat(T_1885[34], T_1885[33])
    node T_1974 = cat(T_1885[32], T_1885[31])
    node T_1975 = cat(T_1973, T_1974)
    node T_1976 = cat(T_1972, T_1975)
    node T_1977 = cat(T_1969, T_1976)
    node T_1978 = cat(T_1962, T_1977)
    node T_1979 = cat(T_1885[29], T_1885[28])
    node T_1980 = cat(T_1885[30], T_1979)
    node T_1981 = cat(T_1885[27], T_1885[26])
    node T_1982 = cat(T_1885[25], T_1885[24])
    node T_1983 = cat(T_1981, T_1982)
    node T_1984 = cat(T_1980, T_1983)
    node T_1985 = cat(T_1885[23], T_1885[22])
    node T_1986 = cat(T_1885[21], T_1885[20])
    node T_1987 = cat(T_1985, T_1986)
    node T_1988 = cat(T_1885[19], T_1885[18])
    node T_1989 = cat(T_1885[17], T_1885[16])
    node T_1990 = cat(T_1988, T_1989)
    node T_1991 = cat(T_1987, T_1990)
    node T_1992 = cat(T_1984, T_1991)
    node T_1993 = cat(T_1885[15], T_1885[14])
    node T_1994 = cat(T_1885[13], T_1885[12])
    node T_1995 = cat(T_1993, T_1994)
    node T_1996 = cat(T_1885[11], T_1885[10])
    node T_1997 = cat(T_1885[9], T_1885[8])
    node T_1998 = cat(T_1996, T_1997)
    node T_1999 = cat(T_1995, T_1998)
    node T_2000 = cat(T_1885[7], T_1885[6])
    node T_2001 = cat(T_1885[5], T_1885[4])
    node T_2002 = cat(T_2000, T_2001)
    node T_2003 = cat(T_1885[3], T_1885[2])
    node T_2004 = cat(T_1885[1], T_1885[0])
    node T_2005 = cat(T_2003, T_2004)
    node T_2006 = cat(T_2002, T_2005)
    node T_2007 = cat(T_1999, T_2006)
    node T_2008 = cat(T_1992, T_2007)
    node T_2009 = cat(T_1978, T_2008)
    node T_2010 = and(T_593, pageHit)
    node T_2011 = and(T_598, pageHit)
    node T_2012 = and(T_603, pageHit)
    node T_2013 = and(T_608, pageHit)
    node T_2014 = and(T_613, pageHit)
    node T_2015 = and(T_618, pageHit)
    node T_2016 = and(T_623, pageHit)
    node T_2017 = and(T_628, pageHit)
    node T_2018 = and(T_633, pageHit)
    node T_2019 = and(T_638, pageHit)
    node T_2020 = and(T_643, pageHit)
    node T_2021 = and(T_648, pageHit)
    node T_2022 = and(T_653, pageHit)
    node T_2023 = and(T_658, pageHit)
    node T_2024 = and(T_663, pageHit)
    node T_2025 = and(T_668, pageHit)
    node T_2026 = and(T_673, pageHit)
    node T_2027 = and(T_678, pageHit)
    node T_2028 = and(T_683, pageHit)
    node T_2029 = and(T_688, pageHit)
    node T_2030 = and(T_693, pageHit)
    node T_2031 = and(T_698, pageHit)
    node T_2032 = and(T_703, pageHit)
    node T_2033 = and(T_708, pageHit)
    node T_2034 = and(T_713, pageHit)
    node T_2035 = and(T_718, pageHit)
    node T_2036 = and(T_723, pageHit)
    node T_2037 = and(T_728, pageHit)
    node T_2038 = and(T_733, pageHit)
    node T_2039 = and(T_738, pageHit)
    node T_2040 = and(T_743, pageHit)
    node T_2041 = and(T_748, pageHit)
    node T_2042 = and(T_753, pageHit)
    node T_2043 = and(T_758, pageHit)
    node T_2044 = and(T_763, pageHit)
    node T_2045 = and(T_768, pageHit)
    node T_2046 = and(T_773, pageHit)
    node T_2047 = and(T_778, pageHit)
    node T_2048 = and(T_783, pageHit)
    node T_2049 = and(T_788, pageHit)
    node T_2050 = and(T_793, pageHit)
    node T_2051 = and(T_798, pageHit)
    node T_2052 = and(T_803, pageHit)
    node T_2053 = and(T_808, pageHit)
    node T_2054 = and(T_813, pageHit)
    node T_2055 = and(T_818, pageHit)
    node T_2056 = and(T_823, pageHit)
    node T_2057 = and(T_828, pageHit)
    node T_2058 = and(T_833, pageHit)
    node T_2059 = and(T_838, pageHit)
    node T_2060 = and(T_843, pageHit)
    node T_2061 = and(T_848, pageHit)
    node T_2062 = and(T_853, pageHit)
    node T_2063 = and(T_858, pageHit)
    node T_2064 = and(T_863, pageHit)
    node T_2065 = and(T_868, pageHit)
    node T_2066 = and(T_873, pageHit)
    node T_2067 = and(T_878, pageHit)
    node T_2068 = and(T_883, pageHit)
    node T_2069 = and(T_888, pageHit)
    node T_2070 = and(T_893, pageHit)
    node T_2071 = and(T_898, pageHit)
    node T_2073 = neq(T_2010, UInt<1>("h00"))
    node T_2075 = neq(T_2011, UInt<1>("h00"))
    node T_2077 = neq(T_2012, UInt<1>("h00"))
    node T_2079 = neq(T_2013, UInt<1>("h00"))
    node T_2081 = neq(T_2014, UInt<1>("h00"))
    node T_2083 = neq(T_2015, UInt<1>("h00"))
    node T_2085 = neq(T_2016, UInt<1>("h00"))
    node T_2087 = neq(T_2017, UInt<1>("h00"))
    node T_2089 = neq(T_2018, UInt<1>("h00"))
    node T_2091 = neq(T_2019, UInt<1>("h00"))
    node T_2093 = neq(T_2020, UInt<1>("h00"))
    node T_2095 = neq(T_2021, UInt<1>("h00"))
    node T_2097 = neq(T_2022, UInt<1>("h00"))
    node T_2099 = neq(T_2023, UInt<1>("h00"))
    node T_2101 = neq(T_2024, UInt<1>("h00"))
    node T_2103 = neq(T_2025, UInt<1>("h00"))
    node T_2105 = neq(T_2026, UInt<1>("h00"))
    node T_2107 = neq(T_2027, UInt<1>("h00"))
    node T_2109 = neq(T_2028, UInt<1>("h00"))
    node T_2111 = neq(T_2029, UInt<1>("h00"))
    node T_2113 = neq(T_2030, UInt<1>("h00"))
    node T_2115 = neq(T_2031, UInt<1>("h00"))
    node T_2117 = neq(T_2032, UInt<1>("h00"))
    node T_2119 = neq(T_2033, UInt<1>("h00"))
    node T_2121 = neq(T_2034, UInt<1>("h00"))
    node T_2123 = neq(T_2035, UInt<1>("h00"))
    node T_2125 = neq(T_2036, UInt<1>("h00"))
    node T_2127 = neq(T_2037, UInt<1>("h00"))
    node T_2129 = neq(T_2038, UInt<1>("h00"))
    node T_2131 = neq(T_2039, UInt<1>("h00"))
    node T_2133 = neq(T_2040, UInt<1>("h00"))
    node T_2135 = neq(T_2041, UInt<1>("h00"))
    node T_2137 = neq(T_2042, UInt<1>("h00"))
    node T_2139 = neq(T_2043, UInt<1>("h00"))
    node T_2141 = neq(T_2044, UInt<1>("h00"))
    node T_2143 = neq(T_2045, UInt<1>("h00"))
    node T_2145 = neq(T_2046, UInt<1>("h00"))
    node T_2147 = neq(T_2047, UInt<1>("h00"))
    node T_2149 = neq(T_2048, UInt<1>("h00"))
    node T_2151 = neq(T_2049, UInt<1>("h00"))
    node T_2153 = neq(T_2050, UInt<1>("h00"))
    node T_2155 = neq(T_2051, UInt<1>("h00"))
    node T_2157 = neq(T_2052, UInt<1>("h00"))
    node T_2159 = neq(T_2053, UInt<1>("h00"))
    node T_2161 = neq(T_2054, UInt<1>("h00"))
    node T_2163 = neq(T_2055, UInt<1>("h00"))
    node T_2165 = neq(T_2056, UInt<1>("h00"))
    node T_2167 = neq(T_2057, UInt<1>("h00"))
    node T_2169 = neq(T_2058, UInt<1>("h00"))
    node T_2171 = neq(T_2059, UInt<1>("h00"))
    node T_2173 = neq(T_2060, UInt<1>("h00"))
    node T_2175 = neq(T_2061, UInt<1>("h00"))
    node T_2177 = neq(T_2062, UInt<1>("h00"))
    node T_2179 = neq(T_2063, UInt<1>("h00"))
    node T_2181 = neq(T_2064, UInt<1>("h00"))
    node T_2183 = neq(T_2065, UInt<1>("h00"))
    node T_2185 = neq(T_2066, UInt<1>("h00"))
    node T_2187 = neq(T_2067, UInt<1>("h00"))
    node T_2189 = neq(T_2068, UInt<1>("h00"))
    node T_2191 = neq(T_2069, UInt<1>("h00"))
    node T_2193 = neq(T_2070, UInt<1>("h00"))
    node T_2195 = neq(T_2071, UInt<1>("h00"))
    wire T_2197 : UInt<1>[62]
    T_2197[0] <= T_2073
    T_2197[1] <= T_2075
    T_2197[2] <= T_2077
    T_2197[3] <= T_2079
    T_2197[4] <= T_2081
    T_2197[5] <= T_2083
    T_2197[6] <= T_2085
    T_2197[7] <= T_2087
    T_2197[8] <= T_2089
    T_2197[9] <= T_2091
    T_2197[10] <= T_2093
    T_2197[11] <= T_2095
    T_2197[12] <= T_2097
    T_2197[13] <= T_2099
    T_2197[14] <= T_2101
    T_2197[15] <= T_2103
    T_2197[16] <= T_2105
    T_2197[17] <= T_2107
    T_2197[18] <= T_2109
    T_2197[19] <= T_2111
    T_2197[20] <= T_2113
    T_2197[21] <= T_2115
    T_2197[22] <= T_2117
    T_2197[23] <= T_2119
    T_2197[24] <= T_2121
    T_2197[25] <= T_2123
    T_2197[26] <= T_2125
    T_2197[27] <= T_2127
    T_2197[28] <= T_2129
    T_2197[29] <= T_2131
    T_2197[30] <= T_2133
    T_2197[31] <= T_2135
    T_2197[32] <= T_2137
    T_2197[33] <= T_2139
    T_2197[34] <= T_2141
    T_2197[35] <= T_2143
    T_2197[36] <= T_2145
    T_2197[37] <= T_2147
    T_2197[38] <= T_2149
    T_2197[39] <= T_2151
    T_2197[40] <= T_2153
    T_2197[41] <= T_2155
    T_2197[42] <= T_2157
    T_2197[43] <= T_2159
    T_2197[44] <= T_2161
    T_2197[45] <= T_2163
    T_2197[46] <= T_2165
    T_2197[47] <= T_2167
    T_2197[48] <= T_2169
    T_2197[49] <= T_2171
    T_2197[50] <= T_2173
    T_2197[51] <= T_2175
    T_2197[52] <= T_2177
    T_2197[53] <= T_2179
    T_2197[54] <= T_2181
    T_2197[55] <= T_2183
    T_2197[56] <= T_2185
    T_2197[57] <= T_2187
    T_2197[58] <= T_2189
    T_2197[59] <= T_2191
    T_2197[60] <= T_2193
    T_2197[61] <= T_2195
    node T_2261 = cat(T_2197[60], T_2197[59])
    node T_2262 = cat(T_2197[61], T_2261)
    node T_2263 = cat(T_2197[58], T_2197[57])
    node T_2264 = cat(T_2197[56], T_2197[55])
    node T_2265 = cat(T_2263, T_2264)
    node T_2266 = cat(T_2262, T_2265)
    node T_2267 = cat(T_2197[54], T_2197[53])
    node T_2268 = cat(T_2197[52], T_2197[51])
    node T_2269 = cat(T_2267, T_2268)
    node T_2270 = cat(T_2197[50], T_2197[49])
    node T_2271 = cat(T_2197[48], T_2197[47])
    node T_2272 = cat(T_2270, T_2271)
    node T_2273 = cat(T_2269, T_2272)
    node T_2274 = cat(T_2266, T_2273)
    node T_2275 = cat(T_2197[46], T_2197[45])
    node T_2276 = cat(T_2197[44], T_2197[43])
    node T_2277 = cat(T_2275, T_2276)
    node T_2278 = cat(T_2197[42], T_2197[41])
    node T_2279 = cat(T_2197[40], T_2197[39])
    node T_2280 = cat(T_2278, T_2279)
    node T_2281 = cat(T_2277, T_2280)
    node T_2282 = cat(T_2197[38], T_2197[37])
    node T_2283 = cat(T_2197[36], T_2197[35])
    node T_2284 = cat(T_2282, T_2283)
    node T_2285 = cat(T_2197[34], T_2197[33])
    node T_2286 = cat(T_2197[32], T_2197[31])
    node T_2287 = cat(T_2285, T_2286)
    node T_2288 = cat(T_2284, T_2287)
    node T_2289 = cat(T_2281, T_2288)
    node T_2290 = cat(T_2274, T_2289)
    node T_2291 = cat(T_2197[29], T_2197[28])
    node T_2292 = cat(T_2197[30], T_2291)
    node T_2293 = cat(T_2197[27], T_2197[26])
    node T_2294 = cat(T_2197[25], T_2197[24])
    node T_2295 = cat(T_2293, T_2294)
    node T_2296 = cat(T_2292, T_2295)
    node T_2297 = cat(T_2197[23], T_2197[22])
    node T_2298 = cat(T_2197[21], T_2197[20])
    node T_2299 = cat(T_2297, T_2298)
    node T_2300 = cat(T_2197[19], T_2197[18])
    node T_2301 = cat(T_2197[17], T_2197[16])
    node T_2302 = cat(T_2300, T_2301)
    node T_2303 = cat(T_2299, T_2302)
    node T_2304 = cat(T_2296, T_2303)
    node T_2305 = cat(T_2197[15], T_2197[14])
    node T_2306 = cat(T_2197[13], T_2197[12])
    node T_2307 = cat(T_2305, T_2306)
    node T_2308 = cat(T_2197[11], T_2197[10])
    node T_2309 = cat(T_2197[9], T_2197[8])
    node T_2310 = cat(T_2308, T_2309)
    node T_2311 = cat(T_2307, T_2310)
    node T_2312 = cat(T_2197[7], T_2197[6])
    node T_2313 = cat(T_2197[5], T_2197[4])
    node T_2314 = cat(T_2312, T_2313)
    node T_2315 = cat(T_2197[3], T_2197[2])
    node T_2316 = cat(T_2197[1], T_2197[0])
    node T_2317 = cat(T_2315, T_2316)
    node T_2318 = cat(T_2314, T_2317)
    node T_2319 = cat(T_2311, T_2318)
    node T_2320 = cat(T_2304, T_2319)
    node T_2321 = cat(T_2290, T_2320)
    node T_2322 = and(idxValid, T_2009)
    node hits = and(T_2322, T_2321)
    node T_2324 = shr(r_btb_update.bits.pc, 12)
    infer mport T_2326 = pages[UInt<1>("h00")], clk
    node T_2327 = eq(T_2326, T_2324)
    infer mport T_2329 = pages[UInt<1>("h01")], clk
    node T_2330 = eq(T_2329, T_2324)
    infer mport T_2332 = pages[UInt<2>("h02")], clk
    node T_2333 = eq(T_2332, T_2324)
    infer mport T_2335 = pages[UInt<2>("h03")], clk
    node T_2336 = eq(T_2335, T_2324)
    infer mport T_2338 = pages[UInt<3>("h04")], clk
    node T_2339 = eq(T_2338, T_2324)
    infer mport T_2341 = pages[UInt<3>("h05")], clk
    node T_2342 = eq(T_2341, T_2324)
    wire T_2344 : UInt<1>[6]
    T_2344[0] <= T_2327
    T_2344[1] <= T_2330
    T_2344[2] <= T_2333
    T_2344[3] <= T_2336
    T_2344[4] <= T_2339
    T_2344[5] <= T_2342
    node T_2352 = cat(T_2344[4], T_2344[3])
    node T_2353 = cat(T_2344[5], T_2352)
    node T_2354 = cat(T_2344[1], T_2344[0])
    node T_2355 = cat(T_2344[2], T_2354)
    node T_2356 = cat(T_2353, T_2355)
    node updatePageHit = and(T_2356, pageValid)
    node T_2358 = bits(r_btb_update.bits.pc, 11, 0)
    infer mport T_2360 = idxs[UInt<1>("h00")], clk
    node T_2361 = eq(T_2360, T_2358)
    infer mport T_2363 = idxs[UInt<1>("h01")], clk
    node T_2364 = eq(T_2363, T_2358)
    infer mport T_2366 = idxs[UInt<2>("h02")], clk
    node T_2367 = eq(T_2366, T_2358)
    infer mport T_2369 = idxs[UInt<2>("h03")], clk
    node T_2370 = eq(T_2369, T_2358)
    infer mport T_2372 = idxs[UInt<3>("h04")], clk
    node T_2373 = eq(T_2372, T_2358)
    infer mport T_2375 = idxs[UInt<3>("h05")], clk
    node T_2376 = eq(T_2375, T_2358)
    infer mport T_2378 = idxs[UInt<3>("h06")], clk
    node T_2379 = eq(T_2378, T_2358)
    infer mport T_2381 = idxs[UInt<3>("h07")], clk
    node T_2382 = eq(T_2381, T_2358)
    infer mport T_2384 = idxs[UInt<4>("h08")], clk
    node T_2385 = eq(T_2384, T_2358)
    infer mport T_2387 = idxs[UInt<4>("h09")], clk
    node T_2388 = eq(T_2387, T_2358)
    infer mport T_2390 = idxs[UInt<4>("h0a")], clk
    node T_2391 = eq(T_2390, T_2358)
    infer mport T_2393 = idxs[UInt<4>("h0b")], clk
    node T_2394 = eq(T_2393, T_2358)
    infer mport T_2396 = idxs[UInt<4>("h0c")], clk
    node T_2397 = eq(T_2396, T_2358)
    infer mport T_2399 = idxs[UInt<4>("h0d")], clk
    node T_2400 = eq(T_2399, T_2358)
    infer mport T_2402 = idxs[UInt<4>("h0e")], clk
    node T_2403 = eq(T_2402, T_2358)
    infer mport T_2405 = idxs[UInt<4>("h0f")], clk
    node T_2406 = eq(T_2405, T_2358)
    infer mport T_2408 = idxs[UInt<5>("h010")], clk
    node T_2409 = eq(T_2408, T_2358)
    infer mport T_2411 = idxs[UInt<5>("h011")], clk
    node T_2412 = eq(T_2411, T_2358)
    infer mport T_2414 = idxs[UInt<5>("h012")], clk
    node T_2415 = eq(T_2414, T_2358)
    infer mport T_2417 = idxs[UInt<5>("h013")], clk
    node T_2418 = eq(T_2417, T_2358)
    infer mport T_2420 = idxs[UInt<5>("h014")], clk
    node T_2421 = eq(T_2420, T_2358)
    infer mport T_2423 = idxs[UInt<5>("h015")], clk
    node T_2424 = eq(T_2423, T_2358)
    infer mport T_2426 = idxs[UInt<5>("h016")], clk
    node T_2427 = eq(T_2426, T_2358)
    infer mport T_2429 = idxs[UInt<5>("h017")], clk
    node T_2430 = eq(T_2429, T_2358)
    infer mport T_2432 = idxs[UInt<5>("h018")], clk
    node T_2433 = eq(T_2432, T_2358)
    infer mport T_2435 = idxs[UInt<5>("h019")], clk
    node T_2436 = eq(T_2435, T_2358)
    infer mport T_2438 = idxs[UInt<5>("h01a")], clk
    node T_2439 = eq(T_2438, T_2358)
    infer mport T_2441 = idxs[UInt<5>("h01b")], clk
    node T_2442 = eq(T_2441, T_2358)
    infer mport T_2444 = idxs[UInt<5>("h01c")], clk
    node T_2445 = eq(T_2444, T_2358)
    infer mport T_2447 = idxs[UInt<5>("h01d")], clk
    node T_2448 = eq(T_2447, T_2358)
    infer mport T_2450 = idxs[UInt<5>("h01e")], clk
    node T_2451 = eq(T_2450, T_2358)
    infer mport T_2453 = idxs[UInt<5>("h01f")], clk
    node T_2454 = eq(T_2453, T_2358)
    infer mport T_2456 = idxs[UInt<6>("h020")], clk
    node T_2457 = eq(T_2456, T_2358)
    infer mport T_2459 = idxs[UInt<6>("h021")], clk
    node T_2460 = eq(T_2459, T_2358)
    infer mport T_2462 = idxs[UInt<6>("h022")], clk
    node T_2463 = eq(T_2462, T_2358)
    infer mport T_2465 = idxs[UInt<6>("h023")], clk
    node T_2466 = eq(T_2465, T_2358)
    infer mport T_2468 = idxs[UInt<6>("h024")], clk
    node T_2469 = eq(T_2468, T_2358)
    infer mport T_2471 = idxs[UInt<6>("h025")], clk
    node T_2472 = eq(T_2471, T_2358)
    infer mport T_2474 = idxs[UInt<6>("h026")], clk
    node T_2475 = eq(T_2474, T_2358)
    infer mport T_2477 = idxs[UInt<6>("h027")], clk
    node T_2478 = eq(T_2477, T_2358)
    infer mport T_2480 = idxs[UInt<6>("h028")], clk
    node T_2481 = eq(T_2480, T_2358)
    infer mport T_2483 = idxs[UInt<6>("h029")], clk
    node T_2484 = eq(T_2483, T_2358)
    infer mport T_2486 = idxs[UInt<6>("h02a")], clk
    node T_2487 = eq(T_2486, T_2358)
    infer mport T_2489 = idxs[UInt<6>("h02b")], clk
    node T_2490 = eq(T_2489, T_2358)
    infer mport T_2492 = idxs[UInt<6>("h02c")], clk
    node T_2493 = eq(T_2492, T_2358)
    infer mport T_2495 = idxs[UInt<6>("h02d")], clk
    node T_2496 = eq(T_2495, T_2358)
    infer mport T_2498 = idxs[UInt<6>("h02e")], clk
    node T_2499 = eq(T_2498, T_2358)
    infer mport T_2501 = idxs[UInt<6>("h02f")], clk
    node T_2502 = eq(T_2501, T_2358)
    infer mport T_2504 = idxs[UInt<6>("h030")], clk
    node T_2505 = eq(T_2504, T_2358)
    infer mport T_2507 = idxs[UInt<6>("h031")], clk
    node T_2508 = eq(T_2507, T_2358)
    infer mport T_2510 = idxs[UInt<6>("h032")], clk
    node T_2511 = eq(T_2510, T_2358)
    infer mport T_2513 = idxs[UInt<6>("h033")], clk
    node T_2514 = eq(T_2513, T_2358)
    infer mport T_2516 = idxs[UInt<6>("h034")], clk
    node T_2517 = eq(T_2516, T_2358)
    infer mport T_2519 = idxs[UInt<6>("h035")], clk
    node T_2520 = eq(T_2519, T_2358)
    infer mport T_2522 = idxs[UInt<6>("h036")], clk
    node T_2523 = eq(T_2522, T_2358)
    infer mport T_2525 = idxs[UInt<6>("h037")], clk
    node T_2526 = eq(T_2525, T_2358)
    infer mport T_2528 = idxs[UInt<6>("h038")], clk
    node T_2529 = eq(T_2528, T_2358)
    infer mport T_2531 = idxs[UInt<6>("h039")], clk
    node T_2532 = eq(T_2531, T_2358)
    infer mport T_2534 = idxs[UInt<6>("h03a")], clk
    node T_2535 = eq(T_2534, T_2358)
    infer mport T_2537 = idxs[UInt<6>("h03b")], clk
    node T_2538 = eq(T_2537, T_2358)
    infer mport T_2540 = idxs[UInt<6>("h03c")], clk
    node T_2541 = eq(T_2540, T_2358)
    infer mport T_2543 = idxs[UInt<6>("h03d")], clk
    node T_2544 = eq(T_2543, T_2358)
    wire T_2546 : UInt<1>[62]
    T_2546[0] <= T_2361
    T_2546[1] <= T_2364
    T_2546[2] <= T_2367
    T_2546[3] <= T_2370
    T_2546[4] <= T_2373
    T_2546[5] <= T_2376
    T_2546[6] <= T_2379
    T_2546[7] <= T_2382
    T_2546[8] <= T_2385
    T_2546[9] <= T_2388
    T_2546[10] <= T_2391
    T_2546[11] <= T_2394
    T_2546[12] <= T_2397
    T_2546[13] <= T_2400
    T_2546[14] <= T_2403
    T_2546[15] <= T_2406
    T_2546[16] <= T_2409
    T_2546[17] <= T_2412
    T_2546[18] <= T_2415
    T_2546[19] <= T_2418
    T_2546[20] <= T_2421
    T_2546[21] <= T_2424
    T_2546[22] <= T_2427
    T_2546[23] <= T_2430
    T_2546[24] <= T_2433
    T_2546[25] <= T_2436
    T_2546[26] <= T_2439
    T_2546[27] <= T_2442
    T_2546[28] <= T_2445
    T_2546[29] <= T_2448
    T_2546[30] <= T_2451
    T_2546[31] <= T_2454
    T_2546[32] <= T_2457
    T_2546[33] <= T_2460
    T_2546[34] <= T_2463
    T_2546[35] <= T_2466
    T_2546[36] <= T_2469
    T_2546[37] <= T_2472
    T_2546[38] <= T_2475
    T_2546[39] <= T_2478
    T_2546[40] <= T_2481
    T_2546[41] <= T_2484
    T_2546[42] <= T_2487
    T_2546[43] <= T_2490
    T_2546[44] <= T_2493
    T_2546[45] <= T_2496
    T_2546[46] <= T_2499
    T_2546[47] <= T_2502
    T_2546[48] <= T_2505
    T_2546[49] <= T_2508
    T_2546[50] <= T_2511
    T_2546[51] <= T_2514
    T_2546[52] <= T_2517
    T_2546[53] <= T_2520
    T_2546[54] <= T_2523
    T_2546[55] <= T_2526
    T_2546[56] <= T_2529
    T_2546[57] <= T_2532
    T_2546[58] <= T_2535
    T_2546[59] <= T_2538
    T_2546[60] <= T_2541
    T_2546[61] <= T_2544
    node T_2610 = cat(T_2546[60], T_2546[59])
    node T_2611 = cat(T_2546[61], T_2610)
    node T_2612 = cat(T_2546[58], T_2546[57])
    node T_2613 = cat(T_2546[56], T_2546[55])
    node T_2614 = cat(T_2612, T_2613)
    node T_2615 = cat(T_2611, T_2614)
    node T_2616 = cat(T_2546[54], T_2546[53])
    node T_2617 = cat(T_2546[52], T_2546[51])
    node T_2618 = cat(T_2616, T_2617)
    node T_2619 = cat(T_2546[50], T_2546[49])
    node T_2620 = cat(T_2546[48], T_2546[47])
    node T_2621 = cat(T_2619, T_2620)
    node T_2622 = cat(T_2618, T_2621)
    node T_2623 = cat(T_2615, T_2622)
    node T_2624 = cat(T_2546[46], T_2546[45])
    node T_2625 = cat(T_2546[44], T_2546[43])
    node T_2626 = cat(T_2624, T_2625)
    node T_2627 = cat(T_2546[42], T_2546[41])
    node T_2628 = cat(T_2546[40], T_2546[39])
    node T_2629 = cat(T_2627, T_2628)
    node T_2630 = cat(T_2626, T_2629)
    node T_2631 = cat(T_2546[38], T_2546[37])
    node T_2632 = cat(T_2546[36], T_2546[35])
    node T_2633 = cat(T_2631, T_2632)
    node T_2634 = cat(T_2546[34], T_2546[33])
    node T_2635 = cat(T_2546[32], T_2546[31])
    node T_2636 = cat(T_2634, T_2635)
    node T_2637 = cat(T_2633, T_2636)
    node T_2638 = cat(T_2630, T_2637)
    node T_2639 = cat(T_2623, T_2638)
    node T_2640 = cat(T_2546[29], T_2546[28])
    node T_2641 = cat(T_2546[30], T_2640)
    node T_2642 = cat(T_2546[27], T_2546[26])
    node T_2643 = cat(T_2546[25], T_2546[24])
    node T_2644 = cat(T_2642, T_2643)
    node T_2645 = cat(T_2641, T_2644)
    node T_2646 = cat(T_2546[23], T_2546[22])
    node T_2647 = cat(T_2546[21], T_2546[20])
    node T_2648 = cat(T_2646, T_2647)
    node T_2649 = cat(T_2546[19], T_2546[18])
    node T_2650 = cat(T_2546[17], T_2546[16])
    node T_2651 = cat(T_2649, T_2650)
    node T_2652 = cat(T_2648, T_2651)
    node T_2653 = cat(T_2645, T_2652)
    node T_2654 = cat(T_2546[15], T_2546[14])
    node T_2655 = cat(T_2546[13], T_2546[12])
    node T_2656 = cat(T_2654, T_2655)
    node T_2657 = cat(T_2546[11], T_2546[10])
    node T_2658 = cat(T_2546[9], T_2546[8])
    node T_2659 = cat(T_2657, T_2658)
    node T_2660 = cat(T_2656, T_2659)
    node T_2661 = cat(T_2546[7], T_2546[6])
    node T_2662 = cat(T_2546[5], T_2546[4])
    node T_2663 = cat(T_2661, T_2662)
    node T_2664 = cat(T_2546[3], T_2546[2])
    node T_2665 = cat(T_2546[1], T_2546[0])
    node T_2666 = cat(T_2664, T_2665)
    node T_2667 = cat(T_2663, T_2666)
    node T_2668 = cat(T_2660, T_2667)
    node T_2669 = cat(T_2653, T_2668)
    node T_2670 = cat(T_2639, T_2669)
    node T_2671 = and(T_593, updatePageHit)
    node T_2672 = and(T_598, updatePageHit)
    node T_2673 = and(T_603, updatePageHit)
    node T_2674 = and(T_608, updatePageHit)
    node T_2675 = and(T_613, updatePageHit)
    node T_2676 = and(T_618, updatePageHit)
    node T_2677 = and(T_623, updatePageHit)
    node T_2678 = and(T_628, updatePageHit)
    node T_2679 = and(T_633, updatePageHit)
    node T_2680 = and(T_638, updatePageHit)
    node T_2681 = and(T_643, updatePageHit)
    node T_2682 = and(T_648, updatePageHit)
    node T_2683 = and(T_653, updatePageHit)
    node T_2684 = and(T_658, updatePageHit)
    node T_2685 = and(T_663, updatePageHit)
    node T_2686 = and(T_668, updatePageHit)
    node T_2687 = and(T_673, updatePageHit)
    node T_2688 = and(T_678, updatePageHit)
    node T_2689 = and(T_683, updatePageHit)
    node T_2690 = and(T_688, updatePageHit)
    node T_2691 = and(T_693, updatePageHit)
    node T_2692 = and(T_698, updatePageHit)
    node T_2693 = and(T_703, updatePageHit)
    node T_2694 = and(T_708, updatePageHit)
    node T_2695 = and(T_713, updatePageHit)
    node T_2696 = and(T_718, updatePageHit)
    node T_2697 = and(T_723, updatePageHit)
    node T_2698 = and(T_728, updatePageHit)
    node T_2699 = and(T_733, updatePageHit)
    node T_2700 = and(T_738, updatePageHit)
    node T_2701 = and(T_743, updatePageHit)
    node T_2702 = and(T_748, updatePageHit)
    node T_2703 = and(T_753, updatePageHit)
    node T_2704 = and(T_758, updatePageHit)
    node T_2705 = and(T_763, updatePageHit)
    node T_2706 = and(T_768, updatePageHit)
    node T_2707 = and(T_773, updatePageHit)
    node T_2708 = and(T_778, updatePageHit)
    node T_2709 = and(T_783, updatePageHit)
    node T_2710 = and(T_788, updatePageHit)
    node T_2711 = and(T_793, updatePageHit)
    node T_2712 = and(T_798, updatePageHit)
    node T_2713 = and(T_803, updatePageHit)
    node T_2714 = and(T_808, updatePageHit)
    node T_2715 = and(T_813, updatePageHit)
    node T_2716 = and(T_818, updatePageHit)
    node T_2717 = and(T_823, updatePageHit)
    node T_2718 = and(T_828, updatePageHit)
    node T_2719 = and(T_833, updatePageHit)
    node T_2720 = and(T_838, updatePageHit)
    node T_2721 = and(T_843, updatePageHit)
    node T_2722 = and(T_848, updatePageHit)
    node T_2723 = and(T_853, updatePageHit)
    node T_2724 = and(T_858, updatePageHit)
    node T_2725 = and(T_863, updatePageHit)
    node T_2726 = and(T_868, updatePageHit)
    node T_2727 = and(T_873, updatePageHit)
    node T_2728 = and(T_878, updatePageHit)
    node T_2729 = and(T_883, updatePageHit)
    node T_2730 = and(T_888, updatePageHit)
    node T_2731 = and(T_893, updatePageHit)
    node T_2732 = and(T_898, updatePageHit)
    node T_2734 = neq(T_2671, UInt<1>("h00"))
    node T_2736 = neq(T_2672, UInt<1>("h00"))
    node T_2738 = neq(T_2673, UInt<1>("h00"))
    node T_2740 = neq(T_2674, UInt<1>("h00"))
    node T_2742 = neq(T_2675, UInt<1>("h00"))
    node T_2744 = neq(T_2676, UInt<1>("h00"))
    node T_2746 = neq(T_2677, UInt<1>("h00"))
    node T_2748 = neq(T_2678, UInt<1>("h00"))
    node T_2750 = neq(T_2679, UInt<1>("h00"))
    node T_2752 = neq(T_2680, UInt<1>("h00"))
    node T_2754 = neq(T_2681, UInt<1>("h00"))
    node T_2756 = neq(T_2682, UInt<1>("h00"))
    node T_2758 = neq(T_2683, UInt<1>("h00"))
    node T_2760 = neq(T_2684, UInt<1>("h00"))
    node T_2762 = neq(T_2685, UInt<1>("h00"))
    node T_2764 = neq(T_2686, UInt<1>("h00"))
    node T_2766 = neq(T_2687, UInt<1>("h00"))
    node T_2768 = neq(T_2688, UInt<1>("h00"))
    node T_2770 = neq(T_2689, UInt<1>("h00"))
    node T_2772 = neq(T_2690, UInt<1>("h00"))
    node T_2774 = neq(T_2691, UInt<1>("h00"))
    node T_2776 = neq(T_2692, UInt<1>("h00"))
    node T_2778 = neq(T_2693, UInt<1>("h00"))
    node T_2780 = neq(T_2694, UInt<1>("h00"))
    node T_2782 = neq(T_2695, UInt<1>("h00"))
    node T_2784 = neq(T_2696, UInt<1>("h00"))
    node T_2786 = neq(T_2697, UInt<1>("h00"))
    node T_2788 = neq(T_2698, UInt<1>("h00"))
    node T_2790 = neq(T_2699, UInt<1>("h00"))
    node T_2792 = neq(T_2700, UInt<1>("h00"))
    node T_2794 = neq(T_2701, UInt<1>("h00"))
    node T_2796 = neq(T_2702, UInt<1>("h00"))
    node T_2798 = neq(T_2703, UInt<1>("h00"))
    node T_2800 = neq(T_2704, UInt<1>("h00"))
    node T_2802 = neq(T_2705, UInt<1>("h00"))
    node T_2804 = neq(T_2706, UInt<1>("h00"))
    node T_2806 = neq(T_2707, UInt<1>("h00"))
    node T_2808 = neq(T_2708, UInt<1>("h00"))
    node T_2810 = neq(T_2709, UInt<1>("h00"))
    node T_2812 = neq(T_2710, UInt<1>("h00"))
    node T_2814 = neq(T_2711, UInt<1>("h00"))
    node T_2816 = neq(T_2712, UInt<1>("h00"))
    node T_2818 = neq(T_2713, UInt<1>("h00"))
    node T_2820 = neq(T_2714, UInt<1>("h00"))
    node T_2822 = neq(T_2715, UInt<1>("h00"))
    node T_2824 = neq(T_2716, UInt<1>("h00"))
    node T_2826 = neq(T_2717, UInt<1>("h00"))
    node T_2828 = neq(T_2718, UInt<1>("h00"))
    node T_2830 = neq(T_2719, UInt<1>("h00"))
    node T_2832 = neq(T_2720, UInt<1>("h00"))
    node T_2834 = neq(T_2721, UInt<1>("h00"))
    node T_2836 = neq(T_2722, UInt<1>("h00"))
    node T_2838 = neq(T_2723, UInt<1>("h00"))
    node T_2840 = neq(T_2724, UInt<1>("h00"))
    node T_2842 = neq(T_2725, UInt<1>("h00"))
    node T_2844 = neq(T_2726, UInt<1>("h00"))
    node T_2846 = neq(T_2727, UInt<1>("h00"))
    node T_2848 = neq(T_2728, UInt<1>("h00"))
    node T_2850 = neq(T_2729, UInt<1>("h00"))
    node T_2852 = neq(T_2730, UInt<1>("h00"))
    node T_2854 = neq(T_2731, UInt<1>("h00"))
    node T_2856 = neq(T_2732, UInt<1>("h00"))
    wire T_2858 : UInt<1>[62]
    T_2858[0] <= T_2734
    T_2858[1] <= T_2736
    T_2858[2] <= T_2738
    T_2858[3] <= T_2740
    T_2858[4] <= T_2742
    T_2858[5] <= T_2744
    T_2858[6] <= T_2746
    T_2858[7] <= T_2748
    T_2858[8] <= T_2750
    T_2858[9] <= T_2752
    T_2858[10] <= T_2754
    T_2858[11] <= T_2756
    T_2858[12] <= T_2758
    T_2858[13] <= T_2760
    T_2858[14] <= T_2762
    T_2858[15] <= T_2764
    T_2858[16] <= T_2766
    T_2858[17] <= T_2768
    T_2858[18] <= T_2770
    T_2858[19] <= T_2772
    T_2858[20] <= T_2774
    T_2858[21] <= T_2776
    T_2858[22] <= T_2778
    T_2858[23] <= T_2780
    T_2858[24] <= T_2782
    T_2858[25] <= T_2784
    T_2858[26] <= T_2786
    T_2858[27] <= T_2788
    T_2858[28] <= T_2790
    T_2858[29] <= T_2792
    T_2858[30] <= T_2794
    T_2858[31] <= T_2796
    T_2858[32] <= T_2798
    T_2858[33] <= T_2800
    T_2858[34] <= T_2802
    T_2858[35] <= T_2804
    T_2858[36] <= T_2806
    T_2858[37] <= T_2808
    T_2858[38] <= T_2810
    T_2858[39] <= T_2812
    T_2858[40] <= T_2814
    T_2858[41] <= T_2816
    T_2858[42] <= T_2818
    T_2858[43] <= T_2820
    T_2858[44] <= T_2822
    T_2858[45] <= T_2824
    T_2858[46] <= T_2826
    T_2858[47] <= T_2828
    T_2858[48] <= T_2830
    T_2858[49] <= T_2832
    T_2858[50] <= T_2834
    T_2858[51] <= T_2836
    T_2858[52] <= T_2838
    T_2858[53] <= T_2840
    T_2858[54] <= T_2842
    T_2858[55] <= T_2844
    T_2858[56] <= T_2846
    T_2858[57] <= T_2848
    T_2858[58] <= T_2850
    T_2858[59] <= T_2852
    T_2858[60] <= T_2854
    T_2858[61] <= T_2856
    node T_2922 = cat(T_2858[60], T_2858[59])
    node T_2923 = cat(T_2858[61], T_2922)
    node T_2924 = cat(T_2858[58], T_2858[57])
    node T_2925 = cat(T_2858[56], T_2858[55])
    node T_2926 = cat(T_2924, T_2925)
    node T_2927 = cat(T_2923, T_2926)
    node T_2928 = cat(T_2858[54], T_2858[53])
    node T_2929 = cat(T_2858[52], T_2858[51])
    node T_2930 = cat(T_2928, T_2929)
    node T_2931 = cat(T_2858[50], T_2858[49])
    node T_2932 = cat(T_2858[48], T_2858[47])
    node T_2933 = cat(T_2931, T_2932)
    node T_2934 = cat(T_2930, T_2933)
    node T_2935 = cat(T_2927, T_2934)
    node T_2936 = cat(T_2858[46], T_2858[45])
    node T_2937 = cat(T_2858[44], T_2858[43])
    node T_2938 = cat(T_2936, T_2937)
    node T_2939 = cat(T_2858[42], T_2858[41])
    node T_2940 = cat(T_2858[40], T_2858[39])
    node T_2941 = cat(T_2939, T_2940)
    node T_2942 = cat(T_2938, T_2941)
    node T_2943 = cat(T_2858[38], T_2858[37])
    node T_2944 = cat(T_2858[36], T_2858[35])
    node T_2945 = cat(T_2943, T_2944)
    node T_2946 = cat(T_2858[34], T_2858[33])
    node T_2947 = cat(T_2858[32], T_2858[31])
    node T_2948 = cat(T_2946, T_2947)
    node T_2949 = cat(T_2945, T_2948)
    node T_2950 = cat(T_2942, T_2949)
    node T_2951 = cat(T_2935, T_2950)
    node T_2952 = cat(T_2858[29], T_2858[28])
    node T_2953 = cat(T_2858[30], T_2952)
    node T_2954 = cat(T_2858[27], T_2858[26])
    node T_2955 = cat(T_2858[25], T_2858[24])
    node T_2956 = cat(T_2954, T_2955)
    node T_2957 = cat(T_2953, T_2956)
    node T_2958 = cat(T_2858[23], T_2858[22])
    node T_2959 = cat(T_2858[21], T_2858[20])
    node T_2960 = cat(T_2958, T_2959)
    node T_2961 = cat(T_2858[19], T_2858[18])
    node T_2962 = cat(T_2858[17], T_2858[16])
    node T_2963 = cat(T_2961, T_2962)
    node T_2964 = cat(T_2960, T_2963)
    node T_2965 = cat(T_2957, T_2964)
    node T_2966 = cat(T_2858[15], T_2858[14])
    node T_2967 = cat(T_2858[13], T_2858[12])
    node T_2968 = cat(T_2966, T_2967)
    node T_2969 = cat(T_2858[11], T_2858[10])
    node T_2970 = cat(T_2858[9], T_2858[8])
    node T_2971 = cat(T_2969, T_2970)
    node T_2972 = cat(T_2968, T_2971)
    node T_2973 = cat(T_2858[7], T_2858[6])
    node T_2974 = cat(T_2858[5], T_2858[4])
    node T_2975 = cat(T_2973, T_2974)
    node T_2976 = cat(T_2858[3], T_2858[2])
    node T_2977 = cat(T_2858[1], T_2858[0])
    node T_2978 = cat(T_2976, T_2977)
    node T_2979 = cat(T_2975, T_2978)
    node T_2980 = cat(T_2972, T_2979)
    node T_2981 = cat(T_2965, T_2980)
    node T_2982 = cat(T_2951, T_2981)
    node T_2983 = and(idxValid, T_2670)
    node updateHits = and(T_2983, T_2982)
    reg T_2986 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01")))
    when r_btb_update.valid :
      node T_2987 = bits(T_2986, 0, 0)
      node T_2988 = bits(T_2986, 2, 2)
      node T_2989 = xor(T_2987, T_2988)
      node T_2990 = bits(T_2986, 3, 3)
      node T_2991 = xor(T_2989, T_2990)
      node T_2992 = bits(T_2986, 5, 5)
      node T_2993 = xor(T_2991, T_2992)
      node T_2994 = bits(T_2986, 15, 1)
      node T_2995 = cat(T_2993, T_2994)
      T_2986 <= T_2995
      skip
    node T_2997 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00"))
    node T_2998 = and(r_btb_update.valid, T_2997)
    reg nextRepl : UInt<6>, clk with : (reset => (reset, UInt<6>("h00")))
    when T_2998 :
      node T_3002 = eq(nextRepl, UInt<6>("h03d"))
      node T_3004 = and(UInt<1>("h01"), T_3002)
      node T_3007 = add(nextRepl, UInt<1>("h01"))
      node T_3008 = tail(T_3007, 1)
      node T_3009 = mux(T_3004, UInt<1>("h00"), T_3008)
      nextRepl <= T_3009
      skip
    node T_3010 = and(T_2998, T_3002)
    node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00"))
    node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00"))
    wire idxPageRepl : UInt<6>
    idxPageRepl is invalid
    node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl)
    node T_3018 = bits(idxPageUpdateOH, 5, 4)
    node T_3019 = bits(idxPageUpdateOH, 3, 0)
    node T_3021 = neq(T_3018, UInt<1>("h00"))
    node T_3022 = or(T_3018, T_3019)
    node T_3023 = bits(T_3022, 3, 2)
    node T_3024 = bits(T_3022, 1, 0)
    node T_3026 = neq(T_3023, UInt<1>("h00"))
    node T_3027 = or(T_3023, T_3024)
    node T_3028 = bits(T_3027, 1, 1)
    node T_3029 = cat(T_3026, T_3028)
    node idxPageUpdate = cat(T_3021, T_3029)
    node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00"))
    node T_3033 = shr(r_btb_update.bits.pc, 12)
    node T_3034 = shr(io.req.bits.addr, 12)
    node samePage = eq(T_3033, T_3034)
    node T_3036 = not(idxPageReplEn)
    node T_3037 = and(pageHit, T_3036)
    node usePageHit = neq(T_3037, UInt<1>("h00"))
    node T_3041 = eq(samePage, UInt<1>("h00"))
    node T_3043 = eq(usePageHit, UInt<1>("h00"))
    node doTgtPageRepl = and(T_3041, T_3043)
    node T_3045 = bits(idxPageUpdateOH, 4, 0)
    node T_3046 = shl(T_3045, 1)
    node T_3047 = bits(idxPageUpdateOH, 5, 5)
    node T_3048 = or(T_3046, T_3047)
    node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3048)
    node T_3050 = mux(usePageHit, pageHit, tgtPageRepl)
    node T_3051 = bits(T_3050, 5, 4)
    node T_3052 = bits(T_3050, 3, 0)
    node T_3054 = neq(T_3051, UInt<1>("h00"))
    node T_3055 = or(T_3051, T_3052)
    node T_3056 = bits(T_3055, 3, 2)
    node T_3057 = bits(T_3055, 1, 0)
    node T_3059 = neq(T_3056, UInt<1>("h00"))
    node T_3060 = or(T_3056, T_3057)
    node T_3061 = bits(T_3060, 1, 1)
    node T_3062 = cat(T_3059, T_3061)
    node tgtPageUpdate = cat(T_3054, T_3062)
    node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00"))
    node doPageRepl = or(doIdxPageRepl, doTgtPageRepl)
    node pageReplEn = or(idxPageReplEn, tgtPageReplEn)
    node T_3068 = and(r_btb_update.valid, doPageRepl)
    reg T_3070 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    when T_3068 :
      node T_3072 = eq(T_3070, UInt<3>("h05"))
      node T_3074 = and(UInt<1>("h01"), T_3072)
      node T_3077 = add(T_3070, UInt<1>("h01"))
      node T_3078 = tail(T_3077, 1)
      node T_3079 = mux(T_3074, UInt<1>("h00"), T_3078)
      T_3070 <= T_3079
      skip
    node T_3080 = and(T_3068, T_3072)
    node T_3082 = dshl(UInt<1>("h01"), T_3070)
    idxPageRepl <= T_3082
    when r_btb_update.valid :
      node T_3083 = eq(io.req.bits.addr, r_btb_update.bits.target)
      node T_3085 = eq(reset, UInt<1>("h00"))
      when T_3085 :
        node T_3087 = eq(T_3083, UInt<1>("h00"))
        when T_3087 :
          node T_3089 = eq(reset, UInt<1>("h00"))
          when T_3089 :
            printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): BTB request != I$ target")
            skip
          stop(clk, UInt<1>(1), 1)
          skip
        skip
      node T_3090 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl)
      node T_3091 = or(T_593, T_903)
      node T_3092 = and(pageReplEn, T_3091)
      node T_3094 = neq(T_3092, UInt<1>("h00"))
      node T_3095 = or(T_598, T_908)
      node T_3096 = and(pageReplEn, T_3095)
      node T_3098 = neq(T_3096, UInt<1>("h00"))
      node T_3099 = or(T_603, T_913)
      node T_3100 = and(pageReplEn, T_3099)
      node T_3102 = neq(T_3100, UInt<1>("h00"))
      node T_3103 = or(T_608, T_918)
      node T_3104 = and(pageReplEn, T_3103)
      node T_3106 = neq(T_3104, UInt<1>("h00"))
      node T_3107 = or(T_613, T_923)
      node T_3108 = and(pageReplEn, T_3107)
      node T_3110 = neq(T_3108, UInt<1>("h00"))
      node T_3111 = or(T_618, T_928)
      node T_3112 = and(pageReplEn, T_3111)
      node T_3114 = neq(T_3112, UInt<1>("h00"))
      node T_3115 = or(T_623, T_933)
      node T_3116 = and(pageReplEn, T_3115)
      node T_3118 = neq(T_3116, UInt<1>("h00"))
      node T_3119 = or(T_628, T_938)
      node T_3120 = and(pageReplEn, T_3119)
      node T_3122 = neq(T_3120, UInt<1>("h00"))
      node T_3123 = or(T_633, T_943)
      node T_3124 = and(pageReplEn, T_3123)
      node T_3126 = neq(T_3124, UInt<1>("h00"))
      node T_3127 = or(T_638, T_948)
      node T_3128 = and(pageReplEn, T_3127)
      node T_3130 = neq(T_3128, UInt<1>("h00"))
      node T_3131 = or(T_643, T_953)
      node T_3132 = and(pageReplEn, T_3131)
      node T_3134 = neq(T_3132, UInt<1>("h00"))
      node T_3135 = or(T_648, T_958)
      node T_3136 = and(pageReplEn, T_3135)
      node T_3138 = neq(T_3136, UInt<1>("h00"))
      node T_3139 = or(T_653, T_963)
      node T_3140 = and(pageReplEn, T_3139)
      node T_3142 = neq(T_3140, UInt<1>("h00"))
      node T_3143 = or(T_658, T_968)
      node T_3144 = and(pageReplEn, T_3143)
      node T_3146 = neq(T_3144, UInt<1>("h00"))
      node T_3147 = or(T_663, T_973)
      node T_3148 = and(pageReplEn, T_3147)
      node T_3150 = neq(T_3148, UInt<1>("h00"))
      node T_3151 = or(T_668, T_978)
      node T_3152 = and(pageReplEn, T_3151)
      node T_3154 = neq(T_3152, UInt<1>("h00"))
      node T_3155 = or(T_673, T_983)
      node T_3156 = and(pageReplEn, T_3155)
      node T_3158 = neq(T_3156, UInt<1>("h00"))
      node T_3159 = or(T_678, T_988)
      node T_3160 = and(pageReplEn, T_3159)
      node T_3162 = neq(T_3160, UInt<1>("h00"))
      node T_3163 = or(T_683, T_993)
      node T_3164 = and(pageReplEn, T_3163)
      node T_3166 = neq(T_3164, UInt<1>("h00"))
      node T_3167 = or(T_688, T_998)
      node T_3168 = and(pageReplEn, T_3167)
      node T_3170 = neq(T_3168, UInt<1>("h00"))
      node T_3171 = or(T_693, T_1003)
      node T_3172 = and(pageReplEn, T_3171)
      node T_3174 = neq(T_3172, UInt<1>("h00"))
      node T_3175 = or(T_698, T_1008)
      node T_3176 = and(pageReplEn, T_3175)
      node T_3178 = neq(T_3176, UInt<1>("h00"))
      node T_3179 = or(T_703, T_1013)
      node T_3180 = and(pageReplEn, T_3179)
      node T_3182 = neq(T_3180, UInt<1>("h00"))
      node T_3183 = or(T_708, T_1018)
      node T_3184 = and(pageReplEn, T_3183)
      node T_3186 = neq(T_3184, UInt<1>("h00"))
      node T_3187 = or(T_713, T_1023)
      node T_3188 = and(pageReplEn, T_3187)
      node T_3190 = neq(T_3188, UInt<1>("h00"))
      node T_3191 = or(T_718, T_1028)
      node T_3192 = and(pageReplEn, T_3191)
      node T_3194 = neq(T_3192, UInt<1>("h00"))
      node T_3195 = or(T_723, T_1033)
      node T_3196 = and(pageReplEn, T_3195)
      node T_3198 = neq(T_3196, UInt<1>("h00"))
      node T_3199 = or(T_728, T_1038)
      node T_3200 = and(pageReplEn, T_3199)
      node T_3202 = neq(T_3200, UInt<1>("h00"))
      node T_3203 = or(T_733, T_1043)
      node T_3204 = and(pageReplEn, T_3203)
      node T_3206 = neq(T_3204, UInt<1>("h00"))
      node T_3207 = or(T_738, T_1048)
      node T_3208 = and(pageReplEn, T_3207)
      node T_3210 = neq(T_3208, UInt<1>("h00"))
      node T_3211 = or(T_743, T_1053)
      node T_3212 = and(pageReplEn, T_3211)
      node T_3214 = neq(T_3212, UInt<1>("h00"))
      node T_3215 = or(T_748, T_1058)
      node T_3216 = and(pageReplEn, T_3215)
      node T_3218 = neq(T_3216, UInt<1>("h00"))
      node T_3219 = or(T_753, T_1063)
      node T_3220 = and(pageReplEn, T_3219)
      node T_3222 = neq(T_3220, UInt<1>("h00"))
      node T_3223 = or(T_758, T_1068)
      node T_3224 = and(pageReplEn, T_3223)
      node T_3226 = neq(T_3224, UInt<1>("h00"))
      node T_3227 = or(T_763, T_1073)
      node T_3228 = and(pageReplEn, T_3227)
      node T_3230 = neq(T_3228, UInt<1>("h00"))
      node T_3231 = or(T_768, T_1078)
      node T_3232 = and(pageReplEn, T_3231)
      node T_3234 = neq(T_3232, UInt<1>("h00"))
      node T_3235 = or(T_773, T_1083)
      node T_3236 = and(pageReplEn, T_3235)
      node T_3238 = neq(T_3236, UInt<1>("h00"))
      node T_3239 = or(T_778, T_1088)
      node T_3240 = and(pageReplEn, T_3239)
      node T_3242 = neq(T_3240, UInt<1>("h00"))
      node T_3243 = or(T_783, T_1093)
      node T_3244 = and(pageReplEn, T_3243)
      node T_3246 = neq(T_3244, UInt<1>("h00"))
      node T_3247 = or(T_788, T_1098)
      node T_3248 = and(pageReplEn, T_3247)
      node T_3250 = neq(T_3248, UInt<1>("h00"))
      node T_3251 = or(T_793, T_1103)
      node T_3252 = and(pageReplEn, T_3251)
      node T_3254 = neq(T_3252, UInt<1>("h00"))
      node T_3255 = or(T_798, T_1108)
      node T_3256 = and(pageReplEn, T_3255)
      node T_3258 = neq(T_3256, UInt<1>("h00"))
      node T_3259 = or(T_803, T_1113)
      node T_3260 = and(pageReplEn, T_3259)
      node T_3262 = neq(T_3260, UInt<1>("h00"))
      node T_3263 = or(T_808, T_1118)
      node T_3264 = and(pageReplEn, T_3263)
      node T_3266 = neq(T_3264, UInt<1>("h00"))
      node T_3267 = or(T_813, T_1123)
      node T_3268 = and(pageReplEn, T_3267)
      node T_3270 = neq(T_3268, UInt<1>("h00"))
      node T_3271 = or(T_818, T_1128)
      node T_3272 = and(pageReplEn, T_3271)
      node T_3274 = neq(T_3272, UInt<1>("h00"))
      node T_3275 = or(T_823, T_1133)
      node T_3276 = and(pageReplEn, T_3275)
      node T_3278 = neq(T_3276, UInt<1>("h00"))
      node T_3279 = or(T_828, T_1138)
      node T_3280 = and(pageReplEn, T_3279)
      node T_3282 = neq(T_3280, UInt<1>("h00"))
      node T_3283 = or(T_833, T_1143)
      node T_3284 = and(pageReplEn, T_3283)
      node T_3286 = neq(T_3284, UInt<1>("h00"))
      node T_3287 = or(T_838, T_1148)
      node T_3288 = and(pageReplEn, T_3287)
      node T_3290 = neq(T_3288, UInt<1>("h00"))
      node T_3291 = or(T_843, T_1153)
      node T_3292 = and(pageReplEn, T_3291)
      node T_3294 = neq(T_3292, UInt<1>("h00"))
      node T_3295 = or(T_848, T_1158)
      node T_3296 = and(pageReplEn, T_3295)
      node T_3298 = neq(T_3296, UInt<1>("h00"))
      node T_3299 = or(T_853, T_1163)
      node T_3300 = and(pageReplEn, T_3299)
      node T_3302 = neq(T_3300, UInt<1>("h00"))
      node T_3303 = or(T_858, T_1168)
      node T_3304 = and(pageReplEn, T_3303)
      node T_3306 = neq(T_3304, UInt<1>("h00"))
      node T_3307 = or(T_863, T_1173)
      node T_3308 = and(pageReplEn, T_3307)
      node T_3310 = neq(T_3308, UInt<1>("h00"))
      node T_3311 = or(T_868, T_1178)
      node T_3312 = and(pageReplEn, T_3311)
      node T_3314 = neq(T_3312, UInt<1>("h00"))
      node T_3315 = or(T_873, T_1183)
      node T_3316 = and(pageReplEn, T_3315)
      node T_3318 = neq(T_3316, UInt<1>("h00"))
      node T_3319 = or(T_878, T_1188)
      node T_3320 = and(pageReplEn, T_3319)
      node T_3322 = neq(T_3320, UInt<1>("h00"))
      node T_3323 = or(T_883, T_1193)
      node T_3324 = and(pageReplEn, T_3323)
      node T_3326 = neq(T_3324, UInt<1>("h00"))
      node T_3327 = or(T_888, T_1198)
      node T_3328 = and(pageReplEn, T_3327)
      node T_3330 = neq(T_3328, UInt<1>("h00"))
      node T_3331 = or(T_893, T_1203)
      node T_3332 = and(pageReplEn, T_3331)
      node T_3334 = neq(T_3332, UInt<1>("h00"))
      node T_3335 = or(T_898, T_1208)
      node T_3336 = and(pageReplEn, T_3335)
      node T_3338 = neq(T_3336, UInt<1>("h00"))
      wire T_3340 : UInt<1>[62]
      T_3340[0] <= T_3094
      T_3340[1] <= T_3098
      T_3340[2] <= T_3102
      T_3340[3] <= T_3106
      T_3340[4] <= T_3110
      T_3340[5] <= T_3114
      T_3340[6] <= T_3118
      T_3340[7] <= T_3122
      T_3340[8] <= T_3126
      T_3340[9] <= T_3130
      T_3340[10] <= T_3134
      T_3340[11] <= T_3138
      T_3340[12] <= T_3142
      T_3340[13] <= T_3146
      T_3340[14] <= T_3150
      T_3340[15] <= T_3154
      T_3340[16] <= T_3158
      T_3340[17] <= T_3162
      T_3340[18] <= T_3166
      T_3340[19] <= T_3170
      T_3340[20] <= T_3174
      T_3340[21] <= T_3178
      T_3340[22] <= T_3182
      T_3340[23] <= T_3186
      T_3340[24] <= T_3190
      T_3340[25] <= T_3194
      T_3340[26] <= T_3198
      T_3340[27] <= T_3202
      T_3340[28] <= T_3206
      T_3340[29] <= T_3210
      T_3340[30] <= T_3214
      T_3340[31] <= T_3218
      T_3340[32] <= T_3222
      T_3340[33] <= T_3226
      T_3340[34] <= T_3230
      T_3340[35] <= T_3234
      T_3340[36] <= T_3238
      T_3340[37] <= T_3242
      T_3340[38] <= T_3246
      T_3340[39] <= T_3250
      T_3340[40] <= T_3254
      T_3340[41] <= T_3258
      T_3340[42] <= T_3262
      T_3340[43] <= T_3266
      T_3340[44] <= T_3270
      T_3340[45] <= T_3274
      T_3340[46] <= T_3278
      T_3340[47] <= T_3282
      T_3340[48] <= T_3286
      T_3340[49] <= T_3290
      T_3340[50] <= T_3294
      T_3340[51] <= T_3298
      T_3340[52] <= T_3302
      T_3340[53] <= T_3306
      T_3340[54] <= T_3310
      T_3340[55] <= T_3314
      T_3340[56] <= T_3318
      T_3340[57] <= T_3322
      T_3340[58] <= T_3326
      T_3340[59] <= T_3330
      T_3340[60] <= T_3334
      T_3340[61] <= T_3338
      node T_3404 = cat(T_3340[60], T_3340[59])
      node T_3405 = cat(T_3340[61], T_3404)
      node T_3406 = cat(T_3340[58], T_3340[57])
      node T_3407 = cat(T_3340[56], T_3340[55])
      node T_3408 = cat(T_3406, T_3407)
      node T_3409 = cat(T_3405, T_3408)
      node T_3410 = cat(T_3340[54], T_3340[53])
      node T_3411 = cat(T_3340[52], T_3340[51])
      node T_3412 = cat(T_3410, T_3411)
      node T_3413 = cat(T_3340[50], T_3340[49])
      node T_3414 = cat(T_3340[48], T_3340[47])
      node T_3415 = cat(T_3413, T_3414)
      node T_3416 = cat(T_3412, T_3415)
      node T_3417 = cat(T_3409, T_3416)
      node T_3418 = cat(T_3340[46], T_3340[45])
      node T_3419 = cat(T_3340[44], T_3340[43])
      node T_3420 = cat(T_3418, T_3419)
      node T_3421 = cat(T_3340[42], T_3340[41])
      node T_3422 = cat(T_3340[40], T_3340[39])
      node T_3423 = cat(T_3421, T_3422)
      node T_3424 = cat(T_3420, T_3423)
      node T_3425 = cat(T_3340[38], T_3340[37])
      node T_3426 = cat(T_3340[36], T_3340[35])
      node T_3427 = cat(T_3425, T_3426)
      node T_3428 = cat(T_3340[34], T_3340[33])
      node T_3429 = cat(T_3340[32], T_3340[31])
      node T_3430 = cat(T_3428, T_3429)
      node T_3431 = cat(T_3427, T_3430)
      node T_3432 = cat(T_3424, T_3431)
      node T_3433 = cat(T_3417, T_3432)
      node T_3434 = cat(T_3340[29], T_3340[28])
      node T_3435 = cat(T_3340[30], T_3434)
      node T_3436 = cat(T_3340[27], T_3340[26])
      node T_3437 = cat(T_3340[25], T_3340[24])
      node T_3438 = cat(T_3436, T_3437)
      node T_3439 = cat(T_3435, T_3438)
      node T_3440 = cat(T_3340[23], T_3340[22])
      node T_3441 = cat(T_3340[21], T_3340[20])
      node T_3442 = cat(T_3440, T_3441)
      node T_3443 = cat(T_3340[19], T_3340[18])
      node T_3444 = cat(T_3340[17], T_3340[16])
      node T_3445 = cat(T_3443, T_3444)
      node T_3446 = cat(T_3442, T_3445)
      node T_3447 = cat(T_3439, T_3446)
      node T_3448 = cat(T_3340[15], T_3340[14])
      node T_3449 = cat(T_3340[13], T_3340[12])
      node T_3450 = cat(T_3448, T_3449)
      node T_3451 = cat(T_3340[11], T_3340[10])
      node T_3452 = cat(T_3340[9], T_3340[8])
      node T_3453 = cat(T_3451, T_3452)
      node T_3454 = cat(T_3450, T_3453)
      node T_3455 = cat(T_3340[7], T_3340[6])
      node T_3456 = cat(T_3340[5], T_3340[4])
      node T_3457 = cat(T_3455, T_3456)
      node T_3458 = cat(T_3340[3], T_3340[2])
      node T_3459 = cat(T_3340[1], T_3340[0])
      node T_3460 = cat(T_3458, T_3459)
      node T_3461 = cat(T_3457, T_3460)
      node T_3462 = cat(T_3454, T_3461)
      node T_3463 = cat(T_3447, T_3462)
      node T_3464 = cat(T_3433, T_3463)
      node T_3466 = dshl(UInt<1>("h01"), T_3090)
      node T_3467 = not(T_3464)
      node T_3468 = and(idxValid, T_3467)
      node T_3469 = or(T_3468, T_3466)
      idxValid <= T_3469
      infer mport T_3470 = idxs[T_3090], clk
      T_3470 <= r_btb_update.bits.pc
      infer mport T_3471 = tgts[T_3090], clk
      T_3471 <= io.req.bits.addr
      infer mport T_3472 = idxPages[T_3090], clk
      T_3472 <= idxPageUpdate
      infer mport T_3473 = tgtPages[T_3090], clk
      T_3473 <= tgtPageUpdate
      useRAS[T_3090] <= r_btb_update.bits.isReturn
      isJump[T_3090] <= r_btb_update.bits.isJump
      infer mport T_3476 = brIdx[T_3090], clk
      T_3476 <= UInt<1>("h00")
      node T_3479 = cat(UInt<2>("h01"), UInt<2>("h01"))
      node T_3480 = cat(UInt<2>("h01"), T_3479)
      node T_3481 = and(idxPageUpdateOH, T_3480)
      node T_3483 = neq(T_3481, UInt<1>("h00"))
      node T_3484 = mux(T_3483, doIdxPageRepl, doTgtPageRepl)
      node T_3485 = shr(r_btb_update.bits.pc, 12)
      node T_3486 = shr(io.req.bits.addr, 12)
      node T_3487 = mux(T_3483, T_3485, T_3486)
      node T_3488 = bits(pageReplEn, 0, 0)
      node T_3489 = and(T_3484, T_3488)
      when T_3489 :
        infer mport T_3491 = pages[UInt<1>("h00")], clk
        T_3491 <= T_3487
        skip
      node T_3492 = bits(pageReplEn, 2, 2)
      node T_3493 = and(T_3484, T_3492)
      when T_3493 :
        infer mport T_3495 = pages[UInt<2>("h02")], clk
        T_3495 <= T_3487
        skip
      node T_3496 = bits(pageReplEn, 4, 4)
      node T_3497 = and(T_3484, T_3496)
      when T_3497 :
        infer mport T_3499 = pages[UInt<3>("h04")], clk
        T_3499 <= T_3487
        skip
      node T_3500 = mux(T_3483, doTgtPageRepl, doIdxPageRepl)
      node T_3501 = shr(io.req.bits.addr, 12)
      node T_3502 = shr(r_btb_update.bits.pc, 12)
      node T_3503 = mux(T_3483, T_3501, T_3502)
      node T_3504 = bits(pageReplEn, 1, 1)
      node T_3505 = and(T_3500, T_3504)
      when T_3505 :
        infer mport T_3507 = pages[UInt<1>("h01")], clk
        T_3507 <= T_3503
        skip
      node T_3508 = bits(pageReplEn, 3, 3)
      node T_3509 = and(T_3500, T_3508)
      when T_3509 :
        infer mport T_3511 = pages[UInt<2>("h03")], clk
        T_3511 <= T_3503
        skip
      node T_3512 = bits(pageReplEn, 5, 5)
      node T_3513 = and(T_3500, T_3512)
      when T_3513 :
        infer mport T_3515 = pages[UInt<3>("h05")], clk
        T_3515 <= T_3503
        skip
      when doPageRepl :
        node T_3516 = or(pageValid, pageReplEn)
        pageValid <= T_3516
        skip
      skip
    when io.invalidate :
      idxValid <= UInt<1>("h00")
      pageValid <= UInt<1>("h00")
      skip
    node T_3520 = neq(hits, UInt<1>("h00"))
    io.resp.valid <= T_3520
    io.resp.bits.taken <= io.resp.valid
    node T_3521 = bits(hits, 0, 0)
    node T_3522 = bits(hits, 1, 1)
    node T_3523 = bits(hits, 2, 2)
    node T_3524 = bits(hits, 3, 3)
    node T_3525 = bits(hits, 4, 4)
    node T_3526 = bits(hits, 5, 5)
    node T_3527 = bits(hits, 6, 6)
    node T_3528 = bits(hits, 7, 7)
    node T_3529 = bits(hits, 8, 8)
    node T_3530 = bits(hits, 9, 9)
    node T_3531 = bits(hits, 10, 10)
    node T_3532 = bits(hits, 11, 11)
    node T_3533 = bits(hits, 12, 12)
    node T_3534 = bits(hits, 13, 13)
    node T_3535 = bits(hits, 14, 14)
    node T_3536 = bits(hits, 15, 15)
    node T_3537 = bits(hits, 16, 16)
    node T_3538 = bits(hits, 17, 17)
    node T_3539 = bits(hits, 18, 18)
    node T_3540 = bits(hits, 19, 19)
    node T_3541 = bits(hits, 20, 20)
    node T_3542 = bits(hits, 21, 21)
    node T_3543 = bits(hits, 22, 22)
    node T_3544 = bits(hits, 23, 23)
    node T_3545 = bits(hits, 24, 24)
    node T_3546 = bits(hits, 25, 25)
    node T_3547 = bits(hits, 26, 26)
    node T_3548 = bits(hits, 27, 27)
    node T_3549 = bits(hits, 28, 28)
    node T_3550 = bits(hits, 29, 29)
    node T_3551 = bits(hits, 30, 30)
    node T_3552 = bits(hits, 31, 31)
    node T_3553 = bits(hits, 32, 32)
    node T_3554 = bits(hits, 33, 33)
    node T_3555 = bits(hits, 34, 34)
    node T_3556 = bits(hits, 35, 35)
    node T_3557 = bits(hits, 36, 36)
    node T_3558 = bits(hits, 37, 37)
    node T_3559 = bits(hits, 38, 38)
    node T_3560 = bits(hits, 39, 39)
    node T_3561 = bits(hits, 40, 40)
    node T_3562 = bits(hits, 41, 41)
    node T_3563 = bits(hits, 42, 42)
    node T_3564 = bits(hits, 43, 43)
    node T_3565 = bits(hits, 44, 44)
    node T_3566 = bits(hits, 45, 45)
    node T_3567 = bits(hits, 46, 46)
    node T_3568 = bits(hits, 47, 47)
    node T_3569 = bits(hits, 48, 48)
    node T_3570 = bits(hits, 49, 49)
    node T_3571 = bits(hits, 50, 50)
    node T_3572 = bits(hits, 51, 51)
    node T_3573 = bits(hits, 52, 52)
    node T_3574 = bits(hits, 53, 53)
    node T_3575 = bits(hits, 54, 54)
    node T_3576 = bits(hits, 55, 55)
    node T_3577 = bits(hits, 56, 56)
    node T_3578 = bits(hits, 57, 57)
    node T_3579 = bits(hits, 58, 58)
    node T_3580 = bits(hits, 59, 59)
    node T_3581 = bits(hits, 60, 60)
    node T_3582 = bits(hits, 61, 61)
    node T_3584 = mux(T_3521, T_903, UInt<1>("h00"))
    node T_3586 = mux(T_3522, T_908, UInt<1>("h00"))
    node T_3588 = mux(T_3523, T_913, UInt<1>("h00"))
    node T_3590 = mux(T_3524, T_918, UInt<1>("h00"))
    node T_3592 = mux(T_3525, T_923, UInt<1>("h00"))
    node T_3594 = mux(T_3526, T_928, UInt<1>("h00"))
    node T_3596 = mux(T_3527, T_933, UInt<1>("h00"))
    node T_3598 = mux(T_3528, T_938, UInt<1>("h00"))
    node T_3600 = mux(T_3529, T_943, UInt<1>("h00"))
    node T_3602 = mux(T_3530, T_948, UInt<1>("h00"))
    node T_3604 = mux(T_3531, T_953, UInt<1>("h00"))
    node T_3606 = mux(T_3532, T_958, UInt<1>("h00"))
    node T_3608 = mux(T_3533, T_963, UInt<1>("h00"))
    node T_3610 = mux(T_3534, T_968, UInt<1>("h00"))
    node T_3612 = mux(T_3535, T_973, UInt<1>("h00"))
    node T_3614 = mux(T_3536, T_978, UInt<1>("h00"))
    node T_3616 = mux(T_3537, T_983, UInt<1>("h00"))
    node T_3618 = mux(T_3538, T_988, UInt<1>("h00"))
    node T_3620 = mux(T_3539, T_993, UInt<1>("h00"))
    node T_3622 = mux(T_3540, T_998, UInt<1>("h00"))
    node T_3624 = mux(T_3541, T_1003, UInt<1>("h00"))
    node T_3626 = mux(T_3542, T_1008, UInt<1>("h00"))
    node T_3628 = mux(T_3543, T_1013, UInt<1>("h00"))
    node T_3630 = mux(T_3544, T_1018, UInt<1>("h00"))
    node T_3632 = mux(T_3545, T_1023, UInt<1>("h00"))
    node T_3634 = mux(T_3546, T_1028, UInt<1>("h00"))
    node T_3636 = mux(T_3547, T_1033, UInt<1>("h00"))
    node T_3638 = mux(T_3548, T_1038, UInt<1>("h00"))
    node T_3640 = mux(T_3549, T_1043, UInt<1>("h00"))
    node T_3642 = mux(T_3550, T_1048, UInt<1>("h00"))
    node T_3644 = mux(T_3551, T_1053, UInt<1>("h00"))
    node T_3646 = mux(T_3552, T_1058, UInt<1>("h00"))
    node T_3648 = mux(T_3553, T_1063, UInt<1>("h00"))
    node T_3650 = mux(T_3554, T_1068, UInt<1>("h00"))
    node T_3652 = mux(T_3555, T_1073, UInt<1>("h00"))
    node T_3654 = mux(T_3556, T_1078, UInt<1>("h00"))
    node T_3656 = mux(T_3557, T_1083, UInt<1>("h00"))
    node T_3658 = mux(T_3558, T_1088, UInt<1>("h00"))
    node T_3660 = mux(T_3559, T_1093, UInt<1>("h00"))
    node T_3662 = mux(T_3560, T_1098, UInt<1>("h00"))
    node T_3664 = mux(T_3561, T_1103, UInt<1>("h00"))
    node T_3666 = mux(T_3562, T_1108, UInt<1>("h00"))
    node T_3668 = mux(T_3563, T_1113, UInt<1>("h00"))
    node T_3670 = mux(T_3564, T_1118, UInt<1>("h00"))
    node T_3672 = mux(T_3565, T_1123, UInt<1>("h00"))
    node T_3674 = mux(T_3566, T_1128, UInt<1>("h00"))
    node T_3676 = mux(T_3567, T_1133, UInt<1>("h00"))
    node T_3678 = mux(T_3568, T_1138, UInt<1>("h00"))
    node T_3680 = mux(T_3569, T_1143, UInt<1>("h00"))
    node T_3682 = mux(T_3570, T_1148, UInt<1>("h00"))
    node T_3684 = mux(T_3571, T_1153, UInt<1>("h00"))
    node T_3686 = mux(T_3572, T_1158, UInt<1>("h00"))
    node T_3688 = mux(T_3573, T_1163, UInt<1>("h00"))
    node T_3690 = mux(T_3574, T_1168, UInt<1>("h00"))
    node T_3692 = mux(T_3575, T_1173, UInt<1>("h00"))
    node T_3694 = mux(T_3576, T_1178, UInt<1>("h00"))
    node T_3696 = mux(T_3577, T_1183, UInt<1>("h00"))
    node T_3698 = mux(T_3578, T_1188, UInt<1>("h00"))
    node T_3700 = mux(T_3579, T_1193, UInt<1>("h00"))
    node T_3702 = mux(T_3580, T_1198, UInt<1>("h00"))
    node T_3704 = mux(T_3581, T_1203, UInt<1>("h00"))
    node T_3706 = mux(T_3582, T_1208, UInt<1>("h00"))
    node T_3708 = or(T_3584, T_3586)
    node T_3709 = or(T_3708, T_3588)
    node T_3710 = or(T_3709, T_3590)
    node T_3711 = or(T_3710, T_3592)
    node T_3712 = or(T_3711, T_3594)
    node T_3713 = or(T_3712, T_3596)
    node T_3714 = or(T_3713, T_3598)
    node T_3715 = or(T_3714, T_3600)
    node T_3716 = or(T_3715, T_3602)
    node T_3717 = or(T_3716, T_3604)
    node T_3718 = or(T_3717, T_3606)
    node T_3719 = or(T_3718, T_3608)
    node T_3720 = or(T_3719, T_3610)
    node T_3721 = or(T_3720, T_3612)
    node T_3722 = or(T_3721, T_3614)
    node T_3723 = or(T_3722, T_3616)
    node T_3724 = or(T_3723, T_3618)
    node T_3725 = or(T_3724, T_3620)
    node T_3726 = or(T_3725, T_3622)
    node T_3727 = or(T_3726, T_3624)
    node T_3728 = or(T_3727, T_3626)
    node T_3729 = or(T_3728, T_3628)
    node T_3730 = or(T_3729, T_3630)
    node T_3731 = or(T_3730, T_3632)
    node T_3732 = or(T_3731, T_3634)
    node T_3733 = or(T_3732, T_3636)
    node T_3734 = or(T_3733, T_3638)
    node T_3735 = or(T_3734, T_3640)
    node T_3736 = or(T_3735, T_3642)
    node T_3737 = or(T_3736, T_3644)
    node T_3738 = or(T_3737, T_3646)
    node T_3739 = or(T_3738, T_3648)
    node T_3740 = or(T_3739, T_3650)
    node T_3741 = or(T_3740, T_3652)
    node T_3742 = or(T_3741, T_3654)
    node T_3743 = or(T_3742, T_3656)
    node T_3744 = or(T_3743, T_3658)
    node T_3745 = or(T_3744, T_3660)
    node T_3746 = or(T_3745, T_3662)
    node T_3747 = or(T_3746, T_3664)
    node T_3748 = or(T_3747, T_3666)
    node T_3749 = or(T_3748, T_3668)
    node T_3750 = or(T_3749, T_3670)
    node T_3751 = or(T_3750, T_3672)
    node T_3752 = or(T_3751, T_3674)
    node T_3753 = or(T_3752, T_3676)
    node T_3754 = or(T_3753, T_3678)
    node T_3755 = or(T_3754, T_3680)
    node T_3756 = or(T_3755, T_3682)
    node T_3757 = or(T_3756, T_3684)
    node T_3758 = or(T_3757, T_3686)
    node T_3759 = or(T_3758, T_3688)
    node T_3760 = or(T_3759, T_3690)
    node T_3761 = or(T_3760, T_3692)
    node T_3762 = or(T_3761, T_3694)
    node T_3763 = or(T_3762, T_3696)
    node T_3764 = or(T_3763, T_3698)
    node T_3765 = or(T_3764, T_3700)
    node T_3766 = or(T_3765, T_3702)
    node T_3767 = or(T_3766, T_3704)
    node T_3768 = or(T_3767, T_3706)
    wire T_3769 : UInt<6>
    T_3769 is invalid
    T_3769 <= T_3768
    node T_3770 = bits(T_3769, 0, 0)
    node T_3771 = bits(T_3769, 1, 1)
    node T_3772 = bits(T_3769, 2, 2)
    node T_3773 = bits(T_3769, 3, 3)
    node T_3774 = bits(T_3769, 4, 4)
    node T_3775 = bits(T_3769, 5, 5)
    infer mport T_3777 = pages[UInt<1>("h00")], clk
    infer mport T_3779 = pages[UInt<1>("h01")], clk
    infer mport T_3781 = pages[UInt<2>("h02")], clk
    infer mport T_3783 = pages[UInt<2>("h03")], clk
    infer mport T_3785 = pages[UInt<3>("h04")], clk
    infer mport T_3787 = pages[UInt<3>("h05")], clk
    node T_3789 = mux(T_3770, T_3777, UInt<1>("h00"))
    node T_3791 = mux(T_3771, T_3779, UInt<1>("h00"))
    node T_3793 = mux(T_3772, T_3781, UInt<1>("h00"))
    node T_3795 = mux(T_3773, T_3783, UInt<1>("h00"))
    node T_3797 = mux(T_3774, T_3785, UInt<1>("h00"))
    node T_3799 = mux(T_3775, T_3787, UInt<1>("h00"))
    node T_3801 = or(T_3789, T_3791)
    node T_3802 = or(T_3801, T_3793)
    node T_3803 = or(T_3802, T_3795)
    node T_3804 = or(T_3803, T_3797)
    node T_3805 = or(T_3804, T_3799)
    wire T_3806 : UInt<27>
    T_3806 is invalid
    T_3806 <= T_3805
    node T_3807 = bits(hits, 0, 0)
    node T_3808 = bits(hits, 1, 1)
    node T_3809 = bits(hits, 2, 2)
    node T_3810 = bits(hits, 3, 3)
    node T_3811 = bits(hits, 4, 4)
    node T_3812 = bits(hits, 5, 5)
    node T_3813 = bits(hits, 6, 6)
    node T_3814 = bits(hits, 7, 7)
    node T_3815 = bits(hits, 8, 8)
    node T_3816 = bits(hits, 9, 9)
    node T_3817 = bits(hits, 10, 10)
    node T_3818 = bits(hits, 11, 11)
    node T_3819 = bits(hits, 12, 12)
    node T_3820 = bits(hits, 13, 13)
    node T_3821 = bits(hits, 14, 14)
    node T_3822 = bits(hits, 15, 15)
    node T_3823 = bits(hits, 16, 16)
    node T_3824 = bits(hits, 17, 17)
    node T_3825 = bits(hits, 18, 18)
    node T_3826 = bits(hits, 19, 19)
    node T_3827 = bits(hits, 20, 20)
    node T_3828 = bits(hits, 21, 21)
    node T_3829 = bits(hits, 22, 22)
    node T_3830 = bits(hits, 23, 23)
    node T_3831 = bits(hits, 24, 24)
    node T_3832 = bits(hits, 25, 25)
    node T_3833 = bits(hits, 26, 26)
    node T_3834 = bits(hits, 27, 27)
    node T_3835 = bits(hits, 28, 28)
    node T_3836 = bits(hits, 29, 29)
    node T_3837 = bits(hits, 30, 30)
    node T_3838 = bits(hits, 31, 31)
    node T_3839 = bits(hits, 32, 32)
    node T_3840 = bits(hits, 33, 33)
    node T_3841 = bits(hits, 34, 34)
    node T_3842 = bits(hits, 35, 35)
    node T_3843 = bits(hits, 36, 36)
    node T_3844 = bits(hits, 37, 37)
    node T_3845 = bits(hits, 38, 38)
    node T_3846 = bits(hits, 39, 39)
    node T_3847 = bits(hits, 40, 40)
    node T_3848 = bits(hits, 41, 41)
    node T_3849 = bits(hits, 42, 42)
    node T_3850 = bits(hits, 43, 43)
    node T_3851 = bits(hits, 44, 44)
    node T_3852 = bits(hits, 45, 45)
    node T_3853 = bits(hits, 46, 46)
    node T_3854 = bits(hits, 47, 47)
    node T_3855 = bits(hits, 48, 48)
    node T_3856 = bits(hits, 49, 49)
    node T_3857 = bits(hits, 50, 50)
    node T_3858 = bits(hits, 51, 51)
    node T_3859 = bits(hits, 52, 52)
    node T_3860 = bits(hits, 53, 53)
    node T_3861 = bits(hits, 54, 54)
    node T_3862 = bits(hits, 55, 55)
    node T_3863 = bits(hits, 56, 56)
    node T_3864 = bits(hits, 57, 57)
    node T_3865 = bits(hits, 58, 58)
    node T_3866 = bits(hits, 59, 59)
    node T_3867 = bits(hits, 60, 60)
    node T_3868 = bits(hits, 61, 61)
    infer mport T_3870 = tgts[UInt<1>("h00")], clk
    infer mport T_3872 = tgts[UInt<1>("h01")], clk
    infer mport T_3874 = tgts[UInt<2>("h02")], clk
    infer mport T_3876 = tgts[UInt<2>("h03")], clk
    infer mport T_3878 = tgts[UInt<3>("h04")], clk
    infer mport T_3880 = tgts[UInt<3>("h05")], clk
    infer mport T_3882 = tgts[UInt<3>("h06")], clk
    infer mport T_3884 = tgts[UInt<3>("h07")], clk
    infer mport T_3886 = tgts[UInt<4>("h08")], clk
    infer mport T_3888 = tgts[UInt<4>("h09")], clk
    infer mport T_3890 = tgts[UInt<4>("h0a")], clk
    infer mport T_3892 = tgts[UInt<4>("h0b")], clk
    infer mport T_3894 = tgts[UInt<4>("h0c")], clk
    infer mport T_3896 = tgts[UInt<4>("h0d")], clk
    infer mport T_3898 = tgts[UInt<4>("h0e")], clk
    infer mport T_3900 = tgts[UInt<4>("h0f")], clk
    infer mport T_3902 = tgts[UInt<5>("h010")], clk
    infer mport T_3904 = tgts[UInt<5>("h011")], clk
    infer mport T_3906 = tgts[UInt<5>("h012")], clk
    infer mport T_3908 = tgts[UInt<5>("h013")], clk
    infer mport T_3910 = tgts[UInt<5>("h014")], clk
    infer mport T_3912 = tgts[UInt<5>("h015")], clk
    infer mport T_3914 = tgts[UInt<5>("h016")], clk
    infer mport T_3916 = tgts[UInt<5>("h017")], clk
    infer mport T_3918 = tgts[UInt<5>("h018")], clk
    infer mport T_3920 = tgts[UInt<5>("h019")], clk
    infer mport T_3922 = tgts[UInt<5>("h01a")], clk
    infer mport T_3924 = tgts[UInt<5>("h01b")], clk
    infer mport T_3926 = tgts[UInt<5>("h01c")], clk
    infer mport T_3928 = tgts[UInt<5>("h01d")], clk
    infer mport T_3930 = tgts[UInt<5>("h01e")], clk
    infer mport T_3932 = tgts[UInt<5>("h01f")], clk
    infer mport T_3934 = tgts[UInt<6>("h020")], clk
    infer mport T_3936 = tgts[UInt<6>("h021")], clk
    infer mport T_3938 = tgts[UInt<6>("h022")], clk
    infer mport T_3940 = tgts[UInt<6>("h023")], clk
    infer mport T_3942 = tgts[UInt<6>("h024")], clk
    infer mport T_3944 = tgts[UInt<6>("h025")], clk
    infer mport T_3946 = tgts[UInt<6>("h026")], clk
    infer mport T_3948 = tgts[UInt<6>("h027")], clk
    infer mport T_3950 = tgts[UInt<6>("h028")], clk
    infer mport T_3952 = tgts[UInt<6>("h029")], clk
    infer mport T_3954 = tgts[UInt<6>("h02a")], clk
    infer mport T_3956 = tgts[UInt<6>("h02b")], clk
    infer mport T_3958 = tgts[UInt<6>("h02c")], clk
    infer mport T_3960 = tgts[UInt<6>("h02d")], clk
    infer mport T_3962 = tgts[UInt<6>("h02e")], clk
    infer mport T_3964 = tgts[UInt<6>("h02f")], clk
    infer mport T_3966 = tgts[UInt<6>("h030")], clk
    infer mport T_3968 = tgts[UInt<6>("h031")], clk
    infer mport T_3970 = tgts[UInt<6>("h032")], clk
    infer mport T_3972 = tgts[UInt<6>("h033")], clk
    infer mport T_3974 = tgts[UInt<6>("h034")], clk
    infer mport T_3976 = tgts[UInt<6>("h035")], clk
    infer mport T_3978 = tgts[UInt<6>("h036")], clk
    infer mport T_3980 = tgts[UInt<6>("h037")], clk
    infer mport T_3982 = tgts[UInt<6>("h038")], clk
    infer mport T_3984 = tgts[UInt<6>("h039")], clk
    infer mport T_3986 = tgts[UInt<6>("h03a")], clk
    infer mport T_3988 = tgts[UInt<6>("h03b")], clk
    infer mport T_3990 = tgts[UInt<6>("h03c")], clk
    infer mport T_3992 = tgts[UInt<6>("h03d")], clk
    node T_3994 = mux(T_3807, T_3870, UInt<1>("h00"))
    node T_3996 = mux(T_3808, T_3872, UInt<1>("h00"))
    node T_3998 = mux(T_3809, T_3874, UInt<1>("h00"))
    node T_4000 = mux(T_3810, T_3876, UInt<1>("h00"))
    node T_4002 = mux(T_3811, T_3878, UInt<1>("h00"))
    node T_4004 = mux(T_3812, T_3880, UInt<1>("h00"))
    node T_4006 = mux(T_3813, T_3882, UInt<1>("h00"))
    node T_4008 = mux(T_3814, T_3884, UInt<1>("h00"))
    node T_4010 = mux(T_3815, T_3886, UInt<1>("h00"))
    node T_4012 = mux(T_3816, T_3888, UInt<1>("h00"))
    node T_4014 = mux(T_3817, T_3890, UInt<1>("h00"))
    node T_4016 = mux(T_3818, T_3892, UInt<1>("h00"))
    node T_4018 = mux(T_3819, T_3894, UInt<1>("h00"))
    node T_4020 = mux(T_3820, T_3896, UInt<1>("h00"))
    node T_4022 = mux(T_3821, T_3898, UInt<1>("h00"))
    node T_4024 = mux(T_3822, T_3900, UInt<1>("h00"))
    node T_4026 = mux(T_3823, T_3902, UInt<1>("h00"))
    node T_4028 = mux(T_3824, T_3904, UInt<1>("h00"))
    node T_4030 = mux(T_3825, T_3906, UInt<1>("h00"))
    node T_4032 = mux(T_3826, T_3908, UInt<1>("h00"))
    node T_4034 = mux(T_3827, T_3910, UInt<1>("h00"))
    node T_4036 = mux(T_3828, T_3912, UInt<1>("h00"))
    node T_4038 = mux(T_3829, T_3914, UInt<1>("h00"))
    node T_4040 = mux(T_3830, T_3916, UInt<1>("h00"))
    node T_4042 = mux(T_3831, T_3918, UInt<1>("h00"))
    node T_4044 = mux(T_3832, T_3920, UInt<1>("h00"))
    node T_4046 = mux(T_3833, T_3922, UInt<1>("h00"))
    node T_4048 = mux(T_3834, T_3924, UInt<1>("h00"))
    node T_4050 = mux(T_3835, T_3926, UInt<1>("h00"))
    node T_4052 = mux(T_3836, T_3928, UInt<1>("h00"))
    node T_4054 = mux(T_3837, T_3930, UInt<1>("h00"))
    node T_4056 = mux(T_3838, T_3932, UInt<1>("h00"))
    node T_4058 = mux(T_3839, T_3934, UInt<1>("h00"))
    node T_4060 = mux(T_3840, T_3936, UInt<1>("h00"))
    node T_4062 = mux(T_3841, T_3938, UInt<1>("h00"))
    node T_4064 = mux(T_3842, T_3940, UInt<1>("h00"))
    node T_4066 = mux(T_3843, T_3942, UInt<1>("h00"))
    node T_4068 = mux(T_3844, T_3944, UInt<1>("h00"))
    node T_4070 = mux(T_3845, T_3946, UInt<1>("h00"))
    node T_4072 = mux(T_3846, T_3948, UInt<1>("h00"))
    node T_4074 = mux(T_3847, T_3950, UInt<1>("h00"))
    node T_4076 = mux(T_3848, T_3952, UInt<1>("h00"))
    node T_4078 = mux(T_3849, T_3954, UInt<1>("h00"))
    node T_4080 = mux(T_3850, T_3956, UInt<1>("h00"))
    node T_4082 = mux(T_3851, T_3958, UInt<1>("h00"))
    node T_4084 = mux(T_3852, T_3960, UInt<1>("h00"))
    node T_4086 = mux(T_3853, T_3962, UInt<1>("h00"))
    node T_4088 = mux(T_3854, T_3964, UInt<1>("h00"))
    node T_4090 = mux(T_3855, T_3966, UInt<1>("h00"))
    node T_4092 = mux(T_3856, T_3968, UInt<1>("h00"))
    node T_4094 = mux(T_3857, T_3970, UInt<1>("h00"))
    node T_4096 = mux(T_3858, T_3972, UInt<1>("h00"))
    node T_4098 = mux(T_3859, T_3974, UInt<1>("h00"))
    node T_4100 = mux(T_3860, T_3976, UInt<1>("h00"))
    node T_4102 = mux(T_3861, T_3978, UInt<1>("h00"))
    node T_4104 = mux(T_3862, T_3980, UInt<1>("h00"))
    node T_4106 = mux(T_3863, T_3982, UInt<1>("h00"))
    node T_4108 = mux(T_3864, T_3984, UInt<1>("h00"))
    node T_4110 = mux(T_3865, T_3986, UInt<1>("h00"))
    node T_4112 = mux(T_3866, T_3988, UInt<1>("h00"))
    node T_4114 = mux(T_3867, T_3990, UInt<1>("h00"))
    node T_4116 = mux(T_3868, T_3992, UInt<1>("h00"))
    node T_4118 = or(T_3994, T_3996)
    node T_4119 = or(T_4118, T_3998)
    node T_4120 = or(T_4119, T_4000)
    node T_4121 = or(T_4120, T_4002)
    node T_4122 = or(T_4121, T_4004)
    node T_4123 = or(T_4122, T_4006)
    node T_4124 = or(T_4123, T_4008)
    node T_4125 = or(T_4124, T_4010)
    node T_4126 = or(T_4125, T_4012)
    node T_4127 = or(T_4126, T_4014)
    node T_4128 = or(T_4127, T_4016)
    node T_4129 = or(T_4128, T_4018)
    node T_4130 = or(T_4129, T_4020)
    node T_4131 = or(T_4130, T_4022)
    node T_4132 = or(T_4131, T_4024)
    node T_4133 = or(T_4132, T_4026)
    node T_4134 = or(T_4133, T_4028)
    node T_4135 = or(T_4134, T_4030)
    node T_4136 = or(T_4135, T_4032)
    node T_4137 = or(T_4136, T_4034)
    node T_4138 = or(T_4137, T_4036)
    node T_4139 = or(T_4138, T_4038)
    node T_4140 = or(T_4139, T_4040)
    node T_4141 = or(T_4140, T_4042)
    node T_4142 = or(T_4141, T_4044)
    node T_4143 = or(T_4142, T_4046)
    node T_4144 = or(T_4143, T_4048)
    node T_4145 = or(T_4144, T_4050)
    node T_4146 = or(T_4145, T_4052)
    node T_4147 = or(T_4146, T_4054)
    node T_4148 = or(T_4147, T_4056)
    node T_4149 = or(T_4148, T_4058)
    node T_4150 = or(T_4149, T_4060)
    node T_4151 = or(T_4150, T_4062)
    node T_4152 = or(T_4151, T_4064)
    node T_4153 = or(T_4152, T_4066)
    node T_4154 = or(T_4153, T_4068)
    node T_4155 = or(T_4154, T_4070)
    node T_4156 = or(T_4155, T_4072)
    node T_4157 = or(T_4156, T_4074)
    node T_4158 = or(T_4157, T_4076)
    node T_4159 = or(T_4158, T_4078)
    node T_4160 = or(T_4159, T_4080)
    node T_4161 = or(T_4160, T_4082)
    node T_4162 = or(T_4161, T_4084)
    node T_4163 = or(T_4162, T_4086)
    node T_4164 = or(T_4163, T_4088)
    node T_4165 = or(T_4164, T_4090)
    node T_4166 = or(T_4165, T_4092)
    node T_4167 = or(T_4166, T_4094)
    node T_4168 = or(T_4167, T_4096)
    node T_4169 = or(T_4168, T_4098)
    node T_4170 = or(T_4169, T_4100)
    node T_4171 = or(T_4170, T_4102)
    node T_4172 = or(T_4171, T_4104)
    node T_4173 = or(T_4172, T_4106)
    node T_4174 = or(T_4173, T_4108)
    node T_4175 = or(T_4174, T_4110)
    node T_4176 = or(T_4175, T_4112)
    node T_4177 = or(T_4176, T_4114)
    node T_4178 = or(T_4177, T_4116)
    wire T_4179 : UInt<12>
    T_4179 is invalid
    T_4179 <= T_4178
    node T_4180 = cat(T_3806, T_4179)
    io.resp.bits.target <= T_4180
    node T_4181 = bits(hits, 61, 32)
    node T_4182 = bits(hits, 31, 0)
    node T_4184 = neq(T_4181, UInt<1>("h00"))
    node T_4185 = or(T_4181, T_4182)
    node T_4186 = bits(T_4185, 31, 16)
    node T_4187 = bits(T_4185, 15, 0)
    node T_4189 = neq(T_4186, UInt<1>("h00"))
    node T_4190 = or(T_4186, T_4187)
    node T_4191 = bits(T_4190, 15, 8)
    node T_4192 = bits(T_4190, 7, 0)
    node T_4194 = neq(T_4191, UInt<1>("h00"))
    node T_4195 = or(T_4191, T_4192)
    node T_4196 = bits(T_4195, 7, 4)
    node T_4197 = bits(T_4195, 3, 0)
    node T_4199 = neq(T_4196, UInt<1>("h00"))
    node T_4200 = or(T_4196, T_4197)
    node T_4201 = bits(T_4200, 3, 2)
    node T_4202 = bits(T_4200, 1, 0)
    node T_4204 = neq(T_4201, UInt<1>("h00"))
    node T_4205 = or(T_4201, T_4202)
    node T_4206 = bits(T_4205, 1, 1)
    node T_4207 = cat(T_4204, T_4206)
    node T_4208 = cat(T_4199, T_4207)
    node T_4209 = cat(T_4194, T_4208)
    node T_4210 = cat(T_4189, T_4209)
    node T_4211 = cat(T_4184, T_4210)
    io.resp.bits.entry <= T_4211
    infer mport T_4212 = brIdx[io.resp.bits.entry], clk
    io.resp.bits.bridx <= T_4212
    io.resp.bits.mask <= UInt<1>("h01")
    cmem T_4216 : UInt<2>[128]
    reg T_4218 : UInt<7>, clk
    node T_4219 = bits(hits, 0, 0)
    node T_4220 = bits(hits, 1, 1)
    node T_4221 = bits(hits, 2, 2)
    node T_4222 = bits(hits, 3, 3)
    node T_4223 = bits(hits, 4, 4)
    node T_4224 = bits(hits, 5, 5)
    node T_4225 = bits(hits, 6, 6)
    node T_4226 = bits(hits, 7, 7)
    node T_4227 = bits(hits, 8, 8)
    node T_4228 = bits(hits, 9, 9)
    node T_4229 = bits(hits, 10, 10)
    node T_4230 = bits(hits, 11, 11)
    node T_4231 = bits(hits, 12, 12)
    node T_4232 = bits(hits, 13, 13)
    node T_4233 = bits(hits, 14, 14)
    node T_4234 = bits(hits, 15, 15)
    node T_4235 = bits(hits, 16, 16)
    node T_4236 = bits(hits, 17, 17)
    node T_4237 = bits(hits, 18, 18)
    node T_4238 = bits(hits, 19, 19)
    node T_4239 = bits(hits, 20, 20)
    node T_4240 = bits(hits, 21, 21)
    node T_4241 = bits(hits, 22, 22)
    node T_4242 = bits(hits, 23, 23)
    node T_4243 = bits(hits, 24, 24)
    node T_4244 = bits(hits, 25, 25)
    node T_4245 = bits(hits, 26, 26)
    node T_4246 = bits(hits, 27, 27)
    node T_4247 = bits(hits, 28, 28)
    node T_4248 = bits(hits, 29, 29)
    node T_4249 = bits(hits, 30, 30)
    node T_4250 = bits(hits, 31, 31)
    node T_4251 = bits(hits, 32, 32)
    node T_4252 = bits(hits, 33, 33)
    node T_4253 = bits(hits, 34, 34)
    node T_4254 = bits(hits, 35, 35)
    node T_4255 = bits(hits, 36, 36)
    node T_4256 = bits(hits, 37, 37)
    node T_4257 = bits(hits, 38, 38)
    node T_4258 = bits(hits, 39, 39)
    node T_4259 = bits(hits, 40, 40)
    node T_4260 = bits(hits, 41, 41)
    node T_4261 = bits(hits, 42, 42)
    node T_4262 = bits(hits, 43, 43)
    node T_4263 = bits(hits, 44, 44)
    node T_4264 = bits(hits, 45, 45)
    node T_4265 = bits(hits, 46, 46)
    node T_4266 = bits(hits, 47, 47)
    node T_4267 = bits(hits, 48, 48)
    node T_4268 = bits(hits, 49, 49)
    node T_4269 = bits(hits, 50, 50)
    node T_4270 = bits(hits, 51, 51)
    node T_4271 = bits(hits, 52, 52)
    node T_4272 = bits(hits, 53, 53)
    node T_4273 = bits(hits, 54, 54)
    node T_4274 = bits(hits, 55, 55)
    node T_4275 = bits(hits, 56, 56)
    node T_4276 = bits(hits, 57, 57)
    node T_4277 = bits(hits, 58, 58)
    node T_4278 = bits(hits, 59, 59)
    node T_4279 = bits(hits, 60, 60)
    node T_4280 = bits(hits, 61, 61)
    node T_4282 = shl(isJump[0], 0)
    node T_4283 = mux(T_4219, T_4282, UInt<1>("h00"))
    node T_4285 = shl(isJump[1], 0)
    node T_4286 = mux(T_4220, T_4285, UInt<1>("h00"))
    node T_4288 = shl(isJump[2], 0)
    node T_4289 = mux(T_4221, T_4288, UInt<1>("h00"))
    node T_4291 = shl(isJump[3], 0)
    node T_4292 = mux(T_4222, T_4291, UInt<1>("h00"))
    node T_4294 = shl(isJump[4], 0)
    node T_4295 = mux(T_4223, T_4294, UInt<1>("h00"))
    node T_4297 = shl(isJump[5], 0)
    node T_4298 = mux(T_4224, T_4297, UInt<1>("h00"))
    node T_4300 = shl(isJump[6], 0)
    node T_4301 = mux(T_4225, T_4300, UInt<1>("h00"))
    node T_4303 = shl(isJump[7], 0)
    node T_4304 = mux(T_4226, T_4303, UInt<1>("h00"))
    node T_4306 = shl(isJump[8], 0)
    node T_4307 = mux(T_4227, T_4306, UInt<1>("h00"))
    node T_4309 = shl(isJump[9], 0)
    node T_4310 = mux(T_4228, T_4309, UInt<1>("h00"))
    node T_4312 = shl(isJump[10], 0)
    node T_4313 = mux(T_4229, T_4312, UInt<1>("h00"))
    node T_4315 = shl(isJump[11], 0)
    node T_4316 = mux(T_4230, T_4315, UInt<1>("h00"))
    node T_4318 = shl(isJump[12], 0)
    node T_4319 = mux(T_4231, T_4318, UInt<1>("h00"))
    node T_4321 = shl(isJump[13], 0)
    node T_4322 = mux(T_4232, T_4321, UInt<1>("h00"))
    node T_4324 = shl(isJump[14], 0)
    node T_4325 = mux(T_4233, T_4324, UInt<1>("h00"))
    node T_4327 = shl(isJump[15], 0)
    node T_4328 = mux(T_4234, T_4327, UInt<1>("h00"))
    node T_4330 = shl(isJump[16], 0)
    node T_4331 = mux(T_4235, T_4330, UInt<1>("h00"))
    node T_4333 = shl(isJump[17], 0)
    node T_4334 = mux(T_4236, T_4333, UInt<1>("h00"))
    node T_4336 = shl(isJump[18], 0)
    node T_4337 = mux(T_4237, T_4336, UInt<1>("h00"))
    node T_4339 = shl(isJump[19], 0)
    node T_4340 = mux(T_4238, T_4339, UInt<1>("h00"))
    node T_4342 = shl(isJump[20], 0)
    node T_4343 = mux(T_4239, T_4342, UInt<1>("h00"))
    node T_4345 = shl(isJump[21], 0)
    node T_4346 = mux(T_4240, T_4345, UInt<1>("h00"))
    node T_4348 = shl(isJump[22], 0)
    node T_4349 = mux(T_4241, T_4348, UInt<1>("h00"))
    node T_4351 = shl(isJump[23], 0)
    node T_4352 = mux(T_4242, T_4351, UInt<1>("h00"))
    node T_4354 = shl(isJump[24], 0)
    node T_4355 = mux(T_4243, T_4354, UInt<1>("h00"))
    node T_4357 = shl(isJump[25], 0)
    node T_4358 = mux(T_4244, T_4357, UInt<1>("h00"))
    node T_4360 = shl(isJump[26], 0)
    node T_4361 = mux(T_4245, T_4360, UInt<1>("h00"))
    node T_4363 = shl(isJump[27], 0)
    node T_4364 = mux(T_4246, T_4363, UInt<1>("h00"))
    node T_4366 = shl(isJump[28], 0)
    node T_4367 = mux(T_4247, T_4366, UInt<1>("h00"))
    node T_4369 = shl(isJump[29], 0)
    node T_4370 = mux(T_4248, T_4369, UInt<1>("h00"))
    node T_4372 = shl(isJump[30], 0)
    node T_4373 = mux(T_4249, T_4372, UInt<1>("h00"))
    node T_4375 = shl(isJump[31], 0)
    node T_4376 = mux(T_4250, T_4375, UInt<1>("h00"))
    node T_4378 = shl(isJump[32], 0)
    node T_4379 = mux(T_4251, T_4378, UInt<1>("h00"))
    node T_4381 = shl(isJump[33], 0)
    node T_4382 = mux(T_4252, T_4381, UInt<1>("h00"))
    node T_4384 = shl(isJump[34], 0)
    node T_4385 = mux(T_4253, T_4384, UInt<1>("h00"))
    node T_4387 = shl(isJump[35], 0)
    node T_4388 = mux(T_4254, T_4387, UInt<1>("h00"))
    node T_4390 = shl(isJump[36], 0)
    node T_4391 = mux(T_4255, T_4390, UInt<1>("h00"))
    node T_4393 = shl(isJump[37], 0)
    node T_4394 = mux(T_4256, T_4393, UInt<1>("h00"))
    node T_4396 = shl(isJump[38], 0)
    node T_4397 = mux(T_4257, T_4396, UInt<1>("h00"))
    node T_4399 = shl(isJump[39], 0)
    node T_4400 = mux(T_4258, T_4399, UInt<1>("h00"))
    node T_4402 = shl(isJump[40], 0)
    node T_4403 = mux(T_4259, T_4402, UInt<1>("h00"))
    node T_4405 = shl(isJump[41], 0)
    node T_4406 = mux(T_4260, T_4405, UInt<1>("h00"))
    node T_4408 = shl(isJump[42], 0)
    node T_4409 = mux(T_4261, T_4408, UInt<1>("h00"))
    node T_4411 = shl(isJump[43], 0)
    node T_4412 = mux(T_4262, T_4411, UInt<1>("h00"))
    node T_4414 = shl(isJump[44], 0)
    node T_4415 = mux(T_4263, T_4414, UInt<1>("h00"))
    node T_4417 = shl(isJump[45], 0)
    node T_4418 = mux(T_4264, T_4417, UInt<1>("h00"))
    node T_4420 = shl(isJump[46], 0)
    node T_4421 = mux(T_4265, T_4420, UInt<1>("h00"))
    node T_4423 = shl(isJump[47], 0)
    node T_4424 = mux(T_4266, T_4423, UInt<1>("h00"))
    node T_4426 = shl(isJump[48], 0)
    node T_4427 = mux(T_4267, T_4426, UInt<1>("h00"))
    node T_4429 = shl(isJump[49], 0)
    node T_4430 = mux(T_4268, T_4429, UInt<1>("h00"))
    node T_4432 = shl(isJump[50], 0)
    node T_4433 = mux(T_4269, T_4432, UInt<1>("h00"))
    node T_4435 = shl(isJump[51], 0)
    node T_4436 = mux(T_4270, T_4435, UInt<1>("h00"))
    node T_4438 = shl(isJump[52], 0)
    node T_4439 = mux(T_4271, T_4438, UInt<1>("h00"))
    node T_4441 = shl(isJump[53], 0)
    node T_4442 = mux(T_4272, T_4441, UInt<1>("h00"))
    node T_4444 = shl(isJump[54], 0)
    node T_4445 = mux(T_4273, T_4444, UInt<1>("h00"))
    node T_4447 = shl(isJump[55], 0)
    node T_4448 = mux(T_4274, T_4447, UInt<1>("h00"))
    node T_4450 = shl(isJump[56], 0)
    node T_4451 = mux(T_4275, T_4450, UInt<1>("h00"))
    node T_4453 = shl(isJump[57], 0)
    node T_4454 = mux(T_4276, T_4453, UInt<1>("h00"))
    node T_4456 = shl(isJump[58], 0)
    node T_4457 = mux(T_4277, T_4456, UInt<1>("h00"))
    node T_4459 = shl(isJump[59], 0)
    node T_4460 = mux(T_4278, T_4459, UInt<1>("h00"))
    node T_4462 = shl(isJump[60], 0)
    node T_4463 = mux(T_4279, T_4462, UInt<1>("h00"))
    node T_4465 = shl(isJump[61], 0)
    node T_4466 = mux(T_4280, T_4465, UInt<1>("h00"))
    node T_4468 = or(T_4283, T_4286)
    node T_4469 = or(T_4468, T_4289)
    node T_4470 = or(T_4469, T_4292)
    node T_4471 = or(T_4470, T_4295)
    node T_4472 = or(T_4471, T_4298)
    node T_4473 = or(T_4472, T_4301)
    node T_4474 = or(T_4473, T_4304)
    node T_4475 = or(T_4474, T_4307)
    node T_4476 = or(T_4475, T_4310)
    node T_4477 = or(T_4476, T_4313)
    node T_4478 = or(T_4477, T_4316)
    node T_4479 = or(T_4478, T_4319)
    node T_4480 = or(T_4479, T_4322)
    node T_4481 = or(T_4480, T_4325)
    node T_4482 = or(T_4481, T_4328)
    node T_4483 = or(T_4482, T_4331)
    node T_4484 = or(T_4483, T_4334)
    node T_4485 = or(T_4484, T_4337)
    node T_4486 = or(T_4485, T_4340)
    node T_4487 = or(T_4486, T_4343)
    node T_4488 = or(T_4487, T_4346)
    node T_4489 = or(T_4488, T_4349)
    node T_4490 = or(T_4489, T_4352)
    node T_4491 = or(T_4490, T_4355)
    node T_4492 = or(T_4491, T_4358)
    node T_4493 = or(T_4492, T_4361)
    node T_4494 = or(T_4493, T_4364)
    node T_4495 = or(T_4494, T_4367)
    node T_4496 = or(T_4495, T_4370)
    node T_4497 = or(T_4496, T_4373)
    node T_4498 = or(T_4497, T_4376)
    node T_4499 = or(T_4498, T_4379)
    node T_4500 = or(T_4499, T_4382)
    node T_4501 = or(T_4500, T_4385)
    node T_4502 = or(T_4501, T_4388)
    node T_4503 = or(T_4502, T_4391)
    node T_4504 = or(T_4503, T_4394)
    node T_4505 = or(T_4504, T_4397)
    node T_4506 = or(T_4505, T_4400)
    node T_4507 = or(T_4506, T_4403)
    node T_4508 = or(T_4507, T_4406)
    node T_4509 = or(T_4508, T_4409)
    node T_4510 = or(T_4509, T_4412)
    node T_4511 = or(T_4510, T_4415)
    node T_4512 = or(T_4511, T_4418)
    node T_4513 = or(T_4512, T_4421)
    node T_4514 = or(T_4513, T_4424)
    node T_4515 = or(T_4514, T_4427)
    node T_4516 = or(T_4515, T_4430)
    node T_4517 = or(T_4516, T_4433)
    node T_4518 = or(T_4517, T_4436)
    node T_4519 = or(T_4518, T_4439)
    node T_4520 = or(T_4519, T_4442)
    node T_4521 = or(T_4520, T_4445)
    node T_4522 = or(T_4521, T_4448)
    node T_4523 = or(T_4522, T_4451)
    node T_4524 = or(T_4523, T_4454)
    node T_4525 = or(T_4524, T_4457)
    node T_4526 = or(T_4525, T_4460)
    node T_4527 = or(T_4526, T_4463)
    node T_4528 = or(T_4527, T_4466)
    wire T_4529 : UInt<1>
    T_4529 is invalid
    T_4529 <= T_4528
    node T_4531 = eq(T_4529, UInt<1>("h00"))
    node T_4532 = and(io.req.valid, io.resp.valid)
    node T_4533 = and(T_4532, T_4531)
    wire T_4537 : {history : UInt<7>, value : UInt<2>}
    T_4537 is invalid
    node T_4540 = bits(io.req.bits.addr, 8, 2)
    node T_4541 = xor(T_4540, T_4218)
    infer mport T_4542 = T_4216[T_4541], clk
    T_4537.value <= T_4542
    T_4537.history <= T_4218
    node T_4543 = bits(T_4537.value, 0, 0)
    when T_4533 :
      node T_4544 = bits(T_4218, 6, 1)
      node T_4545 = cat(T_4543, T_4544)
      T_4218 <= T_4545
      skip
    node T_4546 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid)
    when T_4546 :
      node T_4547 = bits(io.bht_update.bits.pc, 8, 2)
      node T_4548 = xor(T_4547, io.bht_update.bits.prediction.bits.bht.history)
      infer mport T_4549 = T_4216[T_4548], clk
      node T_4550 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1)
      node T_4551 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0)
      node T_4552 = and(T_4550, T_4551)
      node T_4553 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1)
      node T_4554 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0)
      node T_4555 = or(T_4553, T_4554)
      node T_4556 = and(T_4555, io.bht_update.bits.taken)
      node T_4557 = or(T_4552, T_4556)
      node T_4558 = cat(io.bht_update.bits.taken, T_4557)
      T_4549 <= T_4558
      when io.bht_update.bits.mispredict :
        node T_4559 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1)
        node T_4560 = cat(io.bht_update.bits.taken, T_4559)
        T_4218 <= T_4560
        skip
      skip
    node T_4561 = bits(T_4537.value, 0, 0)
    node T_4563 = eq(T_4561, UInt<1>("h00"))
    node T_4564 = and(T_4563, T_4531)
    when T_4564 :
      io.resp.bits.taken <= UInt<1>("h00")
      skip
    io.resp.bits.bht <- T_4537
    reg T_4567 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    reg T_4569 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_4578 : UInt[2], clk
    node T_4582 = bits(hits, 0, 0)
    node T_4583 = bits(hits, 1, 1)
    node T_4584 = bits(hits, 2, 2)
    node T_4585 = bits(hits, 3, 3)
    node T_4586 = bits(hits, 4, 4)
    node T_4587 = bits(hits, 5, 5)
    node T_4588 = bits(hits, 6, 6)
    node T_4589 = bits(hits, 7, 7)
    node T_4590 = bits(hits, 8, 8)
    node T_4591 = bits(hits, 9, 9)
    node T_4592 = bits(hits, 10, 10)
    node T_4593 = bits(hits, 11, 11)
    node T_4594 = bits(hits, 12, 12)
    node T_4595 = bits(hits, 13, 13)
    node T_4596 = bits(hits, 14, 14)
    node T_4597 = bits(hits, 15, 15)
    node T_4598 = bits(hits, 16, 16)
    node T_4599 = bits(hits, 17, 17)
    node T_4600 = bits(hits, 18, 18)
    node T_4601 = bits(hits, 19, 19)
    node T_4602 = bits(hits, 20, 20)
    node T_4603 = bits(hits, 21, 21)
    node T_4604 = bits(hits, 22, 22)
    node T_4605 = bits(hits, 23, 23)
    node T_4606 = bits(hits, 24, 24)
    node T_4607 = bits(hits, 25, 25)
    node T_4608 = bits(hits, 26, 26)
    node T_4609 = bits(hits, 27, 27)
    node T_4610 = bits(hits, 28, 28)
    node T_4611 = bits(hits, 29, 29)
    node T_4612 = bits(hits, 30, 30)
    node T_4613 = bits(hits, 31, 31)
    node T_4614 = bits(hits, 32, 32)
    node T_4615 = bits(hits, 33, 33)
    node T_4616 = bits(hits, 34, 34)
    node T_4617 = bits(hits, 35, 35)
    node T_4618 = bits(hits, 36, 36)
    node T_4619 = bits(hits, 37, 37)
    node T_4620 = bits(hits, 38, 38)
    node T_4621 = bits(hits, 39, 39)
    node T_4622 = bits(hits, 40, 40)
    node T_4623 = bits(hits, 41, 41)
    node T_4624 = bits(hits, 42, 42)
    node T_4625 = bits(hits, 43, 43)
    node T_4626 = bits(hits, 44, 44)
    node T_4627 = bits(hits, 45, 45)
    node T_4628 = bits(hits, 46, 46)
    node T_4629 = bits(hits, 47, 47)
    node T_4630 = bits(hits, 48, 48)
    node T_4631 = bits(hits, 49, 49)
    node T_4632 = bits(hits, 50, 50)
    node T_4633 = bits(hits, 51, 51)
    node T_4634 = bits(hits, 52, 52)
    node T_4635 = bits(hits, 53, 53)
    node T_4636 = bits(hits, 54, 54)
    node T_4637 = bits(hits, 55, 55)
    node T_4638 = bits(hits, 56, 56)
    node T_4639 = bits(hits, 57, 57)
    node T_4640 = bits(hits, 58, 58)
    node T_4641 = bits(hits, 59, 59)
    node T_4642 = bits(hits, 60, 60)
    node T_4643 = bits(hits, 61, 61)
    node T_4645 = shl(useRAS[0], 0)
    node T_4646 = mux(T_4582, T_4645, UInt<1>("h00"))
    node T_4648 = shl(useRAS[1], 0)
    node T_4649 = mux(T_4583, T_4648, UInt<1>("h00"))
    node T_4651 = shl(useRAS[2], 0)
    node T_4652 = mux(T_4584, T_4651, UInt<1>("h00"))
    node T_4654 = shl(useRAS[3], 0)
    node T_4655 = mux(T_4585, T_4654, UInt<1>("h00"))
    node T_4657 = shl(useRAS[4], 0)
    node T_4658 = mux(T_4586, T_4657, UInt<1>("h00"))
    node T_4660 = shl(useRAS[5], 0)
    node T_4661 = mux(T_4587, T_4660, UInt<1>("h00"))
    node T_4663 = shl(useRAS[6], 0)
    node T_4664 = mux(T_4588, T_4663, UInt<1>("h00"))
    node T_4666 = shl(useRAS[7], 0)
    node T_4667 = mux(T_4589, T_4666, UInt<1>("h00"))
    node T_4669 = shl(useRAS[8], 0)
    node T_4670 = mux(T_4590, T_4669, UInt<1>("h00"))
    node T_4672 = shl(useRAS[9], 0)
    node T_4673 = mux(T_4591, T_4672, UInt<1>("h00"))
    node T_4675 = shl(useRAS[10], 0)
    node T_4676 = mux(T_4592, T_4675, UInt<1>("h00"))
    node T_4678 = shl(useRAS[11], 0)
    node T_4679 = mux(T_4593, T_4678, UInt<1>("h00"))
    node T_4681 = shl(useRAS[12], 0)
    node T_4682 = mux(T_4594, T_4681, UInt<1>("h00"))
    node T_4684 = shl(useRAS[13], 0)
    node T_4685 = mux(T_4595, T_4684, UInt<1>("h00"))
    node T_4687 = shl(useRAS[14], 0)
    node T_4688 = mux(T_4596, T_4687, UInt<1>("h00"))
    node T_4690 = shl(useRAS[15], 0)
    node T_4691 = mux(T_4597, T_4690, UInt<1>("h00"))
    node T_4693 = shl(useRAS[16], 0)
    node T_4694 = mux(T_4598, T_4693, UInt<1>("h00"))
    node T_4696 = shl(useRAS[17], 0)
    node T_4697 = mux(T_4599, T_4696, UInt<1>("h00"))
    node T_4699 = shl(useRAS[18], 0)
    node T_4700 = mux(T_4600, T_4699, UInt<1>("h00"))
    node T_4702 = shl(useRAS[19], 0)
    node T_4703 = mux(T_4601, T_4702, UInt<1>("h00"))
    node T_4705 = shl(useRAS[20], 0)
    node T_4706 = mux(T_4602, T_4705, UInt<1>("h00"))
    node T_4708 = shl(useRAS[21], 0)
    node T_4709 = mux(T_4603, T_4708, UInt<1>("h00"))
    node T_4711 = shl(useRAS[22], 0)
    node T_4712 = mux(T_4604, T_4711, UInt<1>("h00"))
    node T_4714 = shl(useRAS[23], 0)
    node T_4715 = mux(T_4605, T_4714, UInt<1>("h00"))
    node T_4717 = shl(useRAS[24], 0)
    node T_4718 = mux(T_4606, T_4717, UInt<1>("h00"))
    node T_4720 = shl(useRAS[25], 0)
    node T_4721 = mux(T_4607, T_4720, UInt<1>("h00"))
    node T_4723 = shl(useRAS[26], 0)
    node T_4724 = mux(T_4608, T_4723, UInt<1>("h00"))
    node T_4726 = shl(useRAS[27], 0)
    node T_4727 = mux(T_4609, T_4726, UInt<1>("h00"))
    node T_4729 = shl(useRAS[28], 0)
    node T_4730 = mux(T_4610, T_4729, UInt<1>("h00"))
    node T_4732 = shl(useRAS[29], 0)
    node T_4733 = mux(T_4611, T_4732, UInt<1>("h00"))
    node T_4735 = shl(useRAS[30], 0)
    node T_4736 = mux(T_4612, T_4735, UInt<1>("h00"))
    node T_4738 = shl(useRAS[31], 0)
    node T_4739 = mux(T_4613, T_4738, UInt<1>("h00"))
    node T_4741 = shl(useRAS[32], 0)
    node T_4742 = mux(T_4614, T_4741, UInt<1>("h00"))
    node T_4744 = shl(useRAS[33], 0)
    node T_4745 = mux(T_4615, T_4744, UInt<1>("h00"))
    node T_4747 = shl(useRAS[34], 0)
    node T_4748 = mux(T_4616, T_4747, UInt<1>("h00"))
    node T_4750 = shl(useRAS[35], 0)
    node T_4751 = mux(T_4617, T_4750, UInt<1>("h00"))
    node T_4753 = shl(useRAS[36], 0)
    node T_4754 = mux(T_4618, T_4753, UInt<1>("h00"))
    node T_4756 = shl(useRAS[37], 0)
    node T_4757 = mux(T_4619, T_4756, UInt<1>("h00"))
    node T_4759 = shl(useRAS[38], 0)
    node T_4760 = mux(T_4620, T_4759, UInt<1>("h00"))
    node T_4762 = shl(useRAS[39], 0)
    node T_4763 = mux(T_4621, T_4762, UInt<1>("h00"))
    node T_4765 = shl(useRAS[40], 0)
    node T_4766 = mux(T_4622, T_4765, UInt<1>("h00"))
    node T_4768 = shl(useRAS[41], 0)
    node T_4769 = mux(T_4623, T_4768, UInt<1>("h00"))
    node T_4771 = shl(useRAS[42], 0)
    node T_4772 = mux(T_4624, T_4771, UInt<1>("h00"))
    node T_4774 = shl(useRAS[43], 0)
    node T_4775 = mux(T_4625, T_4774, UInt<1>("h00"))
    node T_4777 = shl(useRAS[44], 0)
    node T_4778 = mux(T_4626, T_4777, UInt<1>("h00"))
    node T_4780 = shl(useRAS[45], 0)
    node T_4781 = mux(T_4627, T_4780, UInt<1>("h00"))
    node T_4783 = shl(useRAS[46], 0)
    node T_4784 = mux(T_4628, T_4783, UInt<1>("h00"))
    node T_4786 = shl(useRAS[47], 0)
    node T_4787 = mux(T_4629, T_4786, UInt<1>("h00"))
    node T_4789 = shl(useRAS[48], 0)
    node T_4790 = mux(T_4630, T_4789, UInt<1>("h00"))
    node T_4792 = shl(useRAS[49], 0)
    node T_4793 = mux(T_4631, T_4792, UInt<1>("h00"))
    node T_4795 = shl(useRAS[50], 0)
    node T_4796 = mux(T_4632, T_4795, UInt<1>("h00"))
    node T_4798 = shl(useRAS[51], 0)
    node T_4799 = mux(T_4633, T_4798, UInt<1>("h00"))
    node T_4801 = shl(useRAS[52], 0)
    node T_4802 = mux(T_4634, T_4801, UInt<1>("h00"))
    node T_4804 = shl(useRAS[53], 0)
    node T_4805 = mux(T_4635, T_4804, UInt<1>("h00"))
    node T_4807 = shl(useRAS[54], 0)
    node T_4808 = mux(T_4636, T_4807, UInt<1>("h00"))
    node T_4810 = shl(useRAS[55], 0)
    node T_4811 = mux(T_4637, T_4810, UInt<1>("h00"))
    node T_4813 = shl(useRAS[56], 0)
    node T_4814 = mux(T_4638, T_4813, UInt<1>("h00"))
    node T_4816 = shl(useRAS[57], 0)
    node T_4817 = mux(T_4639, T_4816, UInt<1>("h00"))
    node T_4819 = shl(useRAS[58], 0)
    node T_4820 = mux(T_4640, T_4819, UInt<1>("h00"))
    node T_4822 = shl(useRAS[59], 0)
    node T_4823 = mux(T_4641, T_4822, UInt<1>("h00"))
    node T_4825 = shl(useRAS[60], 0)
    node T_4826 = mux(T_4642, T_4825, UInt<1>("h00"))
    node T_4828 = shl(useRAS[61], 0)
    node T_4829 = mux(T_4643, T_4828, UInt<1>("h00"))
    node T_4831 = or(T_4646, T_4649)
    node T_4832 = or(T_4831, T_4652)
    node T_4833 = or(T_4832, T_4655)
    node T_4834 = or(T_4833, T_4658)
    node T_4835 = or(T_4834, T_4661)
    node T_4836 = or(T_4835, T_4664)
    node T_4837 = or(T_4836, T_4667)
    node T_4838 = or(T_4837, T_4670)
    node T_4839 = or(T_4838, T_4673)
    node T_4840 = or(T_4839, T_4676)
    node T_4841 = or(T_4840, T_4679)
    node T_4842 = or(T_4841, T_4682)
    node T_4843 = or(T_4842, T_4685)
    node T_4844 = or(T_4843, T_4688)
    node T_4845 = or(T_4844, T_4691)
    node T_4846 = or(T_4845, T_4694)
    node T_4847 = or(T_4846, T_4697)
    node T_4848 = or(T_4847, T_4700)
    node T_4849 = or(T_4848, T_4703)
    node T_4850 = or(T_4849, T_4706)
    node T_4851 = or(T_4850, T_4709)
    node T_4852 = or(T_4851, T_4712)
    node T_4853 = or(T_4852, T_4715)
    node T_4854 = or(T_4853, T_4718)
    node T_4855 = or(T_4854, T_4721)
    node T_4856 = or(T_4855, T_4724)
    node T_4857 = or(T_4856, T_4727)
    node T_4858 = or(T_4857, T_4730)
    node T_4859 = or(T_4858, T_4733)
    node T_4860 = or(T_4859, T_4736)
    node T_4861 = or(T_4860, T_4739)
    node T_4862 = or(T_4861, T_4742)
    node T_4863 = or(T_4862, T_4745)
    node T_4864 = or(T_4863, T_4748)
    node T_4865 = or(T_4864, T_4751)
    node T_4866 = or(T_4865, T_4754)
    node T_4867 = or(T_4866, T_4757)
    node T_4868 = or(T_4867, T_4760)
    node T_4869 = or(T_4868, T_4763)
    node T_4870 = or(T_4869, T_4766)
    node T_4871 = or(T_4870, T_4769)
    node T_4872 = or(T_4871, T_4772)
    node T_4873 = or(T_4872, T_4775)
    node T_4874 = or(T_4873, T_4778)
    node T_4875 = or(T_4874, T_4781)
    node T_4876 = or(T_4875, T_4784)
    node T_4877 = or(T_4876, T_4787)
    node T_4878 = or(T_4877, T_4790)
    node T_4879 = or(T_4878, T_4793)
    node T_4880 = or(T_4879, T_4796)
    node T_4881 = or(T_4880, T_4799)
    node T_4882 = or(T_4881, T_4802)
    node T_4883 = or(T_4882, T_4805)
    node T_4884 = or(T_4883, T_4808)
    node T_4885 = or(T_4884, T_4811)
    node T_4886 = or(T_4885, T_4814)
    node T_4887 = or(T_4886, T_4817)
    node T_4888 = or(T_4887, T_4820)
    node T_4889 = or(T_4888, T_4823)
    node T_4890 = or(T_4889, T_4826)
    node T_4891 = or(T_4890, T_4829)
    wire T_4892 : UInt<1>
    T_4892 is invalid
    T_4892 <= T_4891
    node T_4894 = eq(T_4567, UInt<1>("h00"))
    node T_4896 = eq(T_4894, UInt<1>("h00"))
    node T_4897 = and(T_4896, T_4892)
    when T_4897 :
      io.resp.bits.target <= T_4578[T_4569]
      skip
    when io.ras_update.valid :
      when io.ras_update.bits.isCall :
        node T_4900 = lt(T_4567, UInt<2>("h02"))
        when T_4900 :
          node T_4902 = add(T_4567, UInt<1>("h01"))
          node T_4903 = tail(T_4902, 1)
          T_4567 <= T_4903
          skip
        node T_4906 = lt(T_4569, UInt<1>("h01"))
        node T_4907 = or(UInt<1>("h01"), T_4906)
        node T_4909 = add(T_4569, UInt<1>("h01"))
        node T_4910 = tail(T_4909, 1)
        node T_4912 = mux(T_4907, T_4910, UInt<1>("h00"))
        T_4578[T_4912] <= io.ras_update.bits.returnAddr
        T_4569 <= T_4912
        when T_4892 :
          io.resp.bits.target <= io.ras_update.bits.returnAddr
          skip
        skip
      node T_4914 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid)
      node T_4916 = eq(io.ras_update.bits.isCall, UInt<1>("h00"))
      node T_4917 = and(T_4916, T_4914)
      when T_4917 :
        node T_4919 = eq(T_4567, UInt<1>("h00"))
        node T_4921 = eq(T_4919, UInt<1>("h00"))
        when T_4921 :
          node T_4923 = sub(T_4567, UInt<1>("h01"))
          node T_4924 = tail(T_4923, 1)
          T_4567 <= T_4924
          node T_4927 = gt(T_4569, UInt<1>("h00"))
          node T_4928 = or(UInt<1>("h01"), T_4927)
          node T_4930 = sub(T_4569, UInt<1>("h01"))
          node T_4931 = tail(T_4930, 1)
          node T_4933 = mux(T_4928, T_4931, UInt<1>("h01"))
          T_4569 <= T_4933
          skip
        skip
      skip
    when io.invalidate :
      T_4567 <= UInt<1>("h00")
      skip
    
  module FlowThroughSerializer : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, cnt : UInt<1>, done : UInt<1>}
    
    io is invalid
    io.out <- io.in
    io.cnt <= UInt<1>("h00")
    io.done <= UInt<1>("h01")
    
  module ICache : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, flip invalidate : UInt<1>, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg invalidated : UInt<1>, clk
    node stall = eq(io.resp.ready, UInt<1>("h00"))
    wire rdy : UInt<1>
    rdy is invalid
    reg refill_addr : UInt<32>, clk
    wire s1_any_tag_hit : UInt<1>
    s1_any_tag_hit is invalid
    reg s1_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg s1_pgoff : UInt<12>, clk
    node s1_addr = cat(io.req.bits.ppn, s1_pgoff)
    node s1_tag = bits(s1_addr, 31, 12)
    node T_523 = and(s1_valid, stall)
    node s0_valid = or(io.req.valid, T_523)
    node T_525 = and(s1_valid, stall)
    node s0_pgoff = mux(T_525, s1_pgoff, io.req.bits.idx)
    node T_527 = and(io.req.valid, rdy)
    node T_528 = and(s1_valid, stall)
    node T_530 = eq(io.req.bits.kill, UInt<1>("h00"))
    node T_531 = and(T_528, T_530)
    node T_532 = or(T_527, T_531)
    s1_valid <= T_532
    node T_533 = and(io.req.valid, rdy)
    when T_533 :
      s1_pgoff <= io.req.bits.idx
      skip
    node T_535 = eq(io.req.bits.kill, UInt<1>("h00"))
    node T_536 = and(s1_valid, T_535)
    node T_537 = eq(state, UInt<1>("h00"))
    node out_valid = and(T_536, T_537)
    node s1_idx = bits(s1_addr, 11, 6)
    node s1_offset = bits(s1_addr, 5, 0)
    node s1_hit = and(out_valid, s1_any_tag_hit)
    node T_543 = eq(s1_any_tag_hit, UInt<1>("h00"))
    node s1_miss = and(out_valid, T_543)
    node T_545 = eq(state, UInt<1>("h00"))
    node T_547 = eq(s1_miss, UInt<1>("h00"))
    node T_548 = and(T_545, T_547)
    rdy <= T_548
    node T_549 = eq(state, UInt<1>("h00"))
    node T_550 = and(s1_valid, T_549)
    node T_551 = and(T_550, s1_miss)
    when T_551 :
      refill_addr <= s1_addr
      skip
    node refill_tag = bits(refill_addr, 31, 12)
    inst T_553 of FlowThroughSerializer
    T_553.io is invalid
    T_553.clk <= clk
    T_553.reset <= reset
    T_553.io.in.valid <= io.mem.grant.valid
    T_553.io.in.bits <- io.mem.grant.bits
    io.mem.grant.ready <= T_553.io.in.ready
    node T_554 = and(T_553.io.out.ready, T_553.io.out.valid)
    reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_554 :
      node T_558 = eq(refill_cnt, UInt<2>("h03"))
      node T_560 = and(UInt<1>("h00"), T_558)
      node T_563 = add(refill_cnt, UInt<1>("h01"))
      node T_564 = tail(T_563, 1)
      node T_565 = mux(T_560, UInt<1>("h00"), T_564)
      refill_cnt <= T_565
      skip
    node refill_wrap = and(T_554, T_558)
    node T_567 = eq(state, UInt<2>("h03"))
    node refill_done = and(T_567, refill_wrap)
    T_553.io.out.ready <= UInt<1>("h01")
    reg T_571 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01")))
    when s1_miss :
      node T_572 = bits(T_571, 0, 0)
      node T_573 = bits(T_571, 2, 2)
      node T_574 = xor(T_572, T_573)
      node T_575 = bits(T_571, 3, 3)
      node T_576 = xor(T_574, T_575)
      node T_577 = bits(T_571, 5, 5)
      node T_578 = xor(T_576, T_577)
      node T_579 = bits(T_571, 15, 1)
      node T_580 = cat(T_578, T_579)
      T_571 <= T_580
      skip
    node repl_way = bits(T_571, 1, 0)
    smem tag_array : UInt<20>[4][64]
    node T_599 = bits(s0_pgoff, 11, 6)
    node T_601 = eq(refill_done, UInt<1>("h00"))
    node T_602 = and(T_601, s0_valid)
    wire T_604 : UInt
    T_604 is invalid
    when T_602 :
      T_604 <= T_599
      skip
    read mport tag_rdata = tag_array[T_604], clk
    when refill_done :
      wire T_614 : UInt<20>[4]
      T_614[0] <= refill_tag
      T_614[1] <= refill_tag
      T_614[2] <= refill_tag
      T_614[3] <= refill_tag
      node T_621 = eq(repl_way, UInt<1>("h00"))
      node T_623 = eq(repl_way, UInt<1>("h01"))
      node T_625 = eq(repl_way, UInt<2>("h02"))
      node T_627 = eq(repl_way, UInt<2>("h03"))
      wire T_629 : UInt<1>[4]
      T_629[0] <= T_621
      T_629[1] <= T_623
      T_629[2] <= T_625
      T_629[3] <= T_627
      write mport T_637 = tag_array[s1_idx], clk
      when T_629[0] :
        T_637[0] <= T_614[0]
        skip
      when T_629[1] :
        T_637[1] <= T_614[1]
        skip
      when T_629[2] :
        T_637[2] <= T_614[2]
        skip
      when T_629[3] :
        T_637[3] <= T_614[3]
        skip
      skip
    reg vb_array : UInt<256>, clk with : (reset => (reset, UInt<256>("h00")))
    node T_646 = eq(invalidated, UInt<1>("h00"))
    node T_647 = and(refill_done, T_646)
    when T_647 :
      node T_648 = cat(repl_way, s1_idx)
      node T_651 = dshl(UInt<1>("h01"), T_648)
      node T_652 = or(vb_array, T_651)
      node T_653 = not(vb_array)
      node T_654 = or(T_653, T_651)
      node T_655 = not(T_654)
      node T_656 = mux(UInt<1>("h01"), T_652, T_655)
      vb_array <= T_656
      skip
    when io.invalidate :
      vb_array <= UInt<1>("h00")
      invalidated <= UInt<1>("h01")
      skip
    wire s1_disparity : UInt<1>[4]
    s1_disparity is invalid
    node T_675 = and(s1_valid, s1_disparity[0])
    when T_675 :
      node T_677 = cat(UInt<1>("h00"), s1_idx)
      node T_680 = dshl(UInt<1>("h01"), T_677)
      node T_681 = or(vb_array, T_680)
      node T_682 = not(vb_array)
      node T_683 = or(T_682, T_680)
      node T_684 = not(T_683)
      node T_685 = mux(UInt<1>("h00"), T_681, T_684)
      vb_array <= T_685
      skip
    node T_686 = and(s1_valid, s1_disparity[1])
    when T_686 :
      node T_688 = cat(UInt<1>("h01"), s1_idx)
      node T_691 = dshl(UInt<1>("h01"), T_688)
      node T_692 = or(vb_array, T_691)
      node T_693 = not(vb_array)
      node T_694 = or(T_693, T_691)
      node T_695 = not(T_694)
      node T_696 = mux(UInt<1>("h00"), T_692, T_695)
      vb_array <= T_696
      skip
    node T_697 = and(s1_valid, s1_disparity[2])
    when T_697 :
      node T_699 = cat(UInt<2>("h02"), s1_idx)
      node T_702 = dshl(UInt<1>("h01"), T_699)
      node T_703 = or(vb_array, T_702)
      node T_704 = not(vb_array)
      node T_705 = or(T_704, T_702)
      node T_706 = not(T_705)
      node T_707 = mux(UInt<1>("h00"), T_703, T_706)
      vb_array <= T_707
      skip
    node T_708 = and(s1_valid, s1_disparity[3])
    when T_708 :
      node T_710 = cat(UInt<2>("h03"), s1_idx)
      node T_713 = dshl(UInt<1>("h01"), T_710)
      node T_714 = or(vb_array, T_713)
      node T_715 = not(vb_array)
      node T_716 = or(T_715, T_713)
      node T_717 = not(T_716)
      node T_718 = mux(UInt<1>("h00"), T_714, T_717)
      vb_array <= T_718
      skip
    wire s1_tag_match : UInt<1>[4]
    s1_tag_match is invalid
    wire s1_tag_hit : UInt<1>[4]
    s1_tag_hit is invalid
    wire s1_dout : UInt<128>[4]
    s1_dout is invalid
    node T_768 = eq(io.invalidate, UInt<1>("h00"))
    node T_770 = bits(s1_pgoff, 11, 6)
    node T_771 = cat(UInt<1>("h00"), T_770)
    node T_772 = dshr(vb_array, T_771)
    node T_773 = bits(T_772, 0, 0)
    node T_774 = bits(T_773, 0, 0)
    node T_775 = and(T_768, T_774)
    node T_778 = or(UInt<1>("h00"), UInt<1>("h00"))
    node T_779 = and(s1_valid, rdy)
    node T_781 = eq(stall, UInt<1>("h00"))
    node T_782 = and(T_779, T_781)
    when T_782 :
      skip
    node T_783 = bits(tag_rdata[0], 19, 0)
    node T_784 = eq(T_783, s1_tag)
    s1_tag_match[0] <= T_784
    node T_785 = and(T_775, s1_tag_match[0])
    s1_tag_hit[0] <= T_785
    node T_788 = or(UInt<1>("h00"), UInt<1>("h00"))
    node T_789 = or(T_778, T_788)
    node T_790 = and(T_775, T_789)
    s1_disparity[0] <= T_790
    node T_792 = eq(io.invalidate, UInt<1>("h00"))
    node T_794 = bits(s1_pgoff, 11, 6)
    node T_795 = cat(UInt<1>("h01"), T_794)
    node T_796 = dshr(vb_array, T_795)
    node T_797 = bits(T_796, 0, 0)
    node T_798 = bits(T_797, 0, 0)
    node T_799 = and(T_792, T_798)
    node T_802 = or(UInt<1>("h00"), UInt<1>("h00"))
    node T_803 = and(s1_valid, rdy)
    node T_805 = eq(stall, UInt<1>("h00"))
    node T_806 = and(T_803, T_805)
    when T_806 :
      skip
    node T_807 = bits(tag_rdata[1], 19, 0)
    node T_808 = eq(T_807, s1_tag)
    s1_tag_match[1] <= T_808
    node T_809 = and(T_799, s1_tag_match[1])
    s1_tag_hit[1] <= T_809
    node T_812 = or(UInt<1>("h00"), UInt<1>("h00"))
    node T_813 = or(T_802, T_812)
    node T_814 = and(T_799, T_813)
    s1_disparity[1] <= T_814
    node T_816 = eq(io.invalidate, UInt<1>("h00"))
    node T_818 = bits(s1_pgoff, 11, 6)
    node T_819 = cat(UInt<2>("h02"), T_818)
    node T_820 = dshr(vb_array, T_819)
    node T_821 = bits(T_820, 0, 0)
    node T_822 = bits(T_821, 0, 0)
    node T_823 = and(T_816, T_822)
    node T_826 = or(UInt<1>("h00"), UInt<1>("h00"))
    node T_827 = and(s1_valid, rdy)
    node T_829 = eq(stall, UInt<1>("h00"))
    node T_830 = and(T_827, T_829)
    when T_830 :
      skip
    node T_831 = bits(tag_rdata[2], 19, 0)
    node T_832 = eq(T_831, s1_tag)
    s1_tag_match[2] <= T_832
    node T_833 = and(T_823, s1_tag_match[2])
    s1_tag_hit[2] <= T_833
    node T_836 = or(UInt<1>("h00"), UInt<1>("h00"))
    node T_837 = or(T_826, T_836)
    node T_838 = and(T_823, T_837)
    s1_disparity[2] <= T_838
    node T_840 = eq(io.invalidate, UInt<1>("h00"))
    node T_842 = bits(s1_pgoff, 11, 6)
    node T_843 = cat(UInt<2>("h03"), T_842)
    node T_844 = dshr(vb_array, T_843)
    node T_845 = bits(T_844, 0, 0)
    node T_846 = bits(T_845, 0, 0)
    node T_847 = and(T_840, T_846)
    node T_850 = or(UInt<1>("h00"), UInt<1>("h00"))
    node T_851 = and(s1_valid, rdy)
    node T_853 = eq(stall, UInt<1>("h00"))
    node T_854 = and(T_851, T_853)
    when T_854 :
      skip
    node T_855 = bits(tag_rdata[3], 19, 0)
    node T_856 = eq(T_855, s1_tag)
    s1_tag_match[3] <= T_856
    node T_857 = and(T_847, s1_tag_match[3])
    s1_tag_hit[3] <= T_857
    node T_860 = or(UInt<1>("h00"), UInt<1>("h00"))
    node T_861 = or(T_850, T_860)
    node T_862 = and(T_847, T_861)
    s1_disparity[3] <= T_862
    node T_863 = or(s1_tag_hit[0], s1_tag_hit[1])
    node T_864 = or(T_863, s1_tag_hit[2])
    node T_865 = or(T_864, s1_tag_hit[3])
    node T_866 = or(s1_disparity[0], s1_disparity[1])
    node T_867 = or(T_866, s1_disparity[2])
    node T_868 = or(T_867, s1_disparity[3])
    node T_870 = eq(T_868, UInt<1>("h00"))
    node T_871 = and(T_865, T_870)
    s1_any_tag_hit <= T_871
    smem T_874 : UInt<128>[256]
    node T_876 = eq(repl_way, UInt<1>("h00"))
    node T_877 = and(T_553.io.out.valid, T_876)
    when T_877 :
      node T_878 = cat(s1_idx, refill_cnt)
      write mport T_879 = T_874[T_878], clk
      T_879 <= T_553.io.out.bits.data
      skip
    node T_880 = bits(s0_pgoff, 11, 4)
    node T_882 = eq(T_877, UInt<1>("h00"))
    node T_883 = and(T_882, s0_valid)
    wire T_885 : UInt
    T_885 is invalid
    when T_883 :
      T_885 <= T_880
      skip
    read mport T_886 = T_874[T_885], clk
    s1_dout[0] <= T_886
    smem T_889 : UInt<128>[256]
    node T_891 = eq(repl_way, UInt<1>("h01"))
    node T_892 = and(T_553.io.out.valid, T_891)
    when T_892 :
      node T_893 = cat(s1_idx, refill_cnt)
      write mport T_894 = T_889[T_893], clk
      T_894 <= T_553.io.out.bits.data
      skip
    node T_895 = bits(s0_pgoff, 11, 4)
    node T_897 = eq(T_892, UInt<1>("h00"))
    node T_898 = and(T_897, s0_valid)
    wire T_900 : UInt
    T_900 is invalid
    when T_898 :
      T_900 <= T_895
      skip
    read mport T_901 = T_889[T_900], clk
    s1_dout[1] <= T_901
    smem T_904 : UInt<128>[256]
    node T_906 = eq(repl_way, UInt<2>("h02"))
    node T_907 = and(T_553.io.out.valid, T_906)
    when T_907 :
      node T_908 = cat(s1_idx, refill_cnt)
      write mport T_909 = T_904[T_908], clk
      T_909 <= T_553.io.out.bits.data
      skip
    node T_910 = bits(s0_pgoff, 11, 4)
    node T_912 = eq(T_907, UInt<1>("h00"))
    node T_913 = and(T_912, s0_valid)
    wire T_915 : UInt
    T_915 is invalid
    when T_913 :
      T_915 <= T_910
      skip
    read mport T_916 = T_904[T_915], clk
    s1_dout[2] <= T_916
    smem T_919 : UInt<128>[256]
    node T_921 = eq(repl_way, UInt<2>("h03"))
    node T_922 = and(T_553.io.out.valid, T_921)
    when T_922 :
      node T_923 = cat(s1_idx, refill_cnt)
      write mport T_924 = T_919[T_923], clk
      T_924 <= T_553.io.out.bits.data
      skip
    node T_925 = bits(s0_pgoff, 11, 4)
    node T_927 = eq(T_922, UInt<1>("h00"))
    node T_928 = and(T_927, s0_valid)
    wire T_930 : UInt
    T_930 is invalid
    when T_928 :
      T_930 <= T_925
      skip
    read mport T_931 = T_919[T_930], clk
    s1_dout[3] <= T_931
    node T_933 = mux(s1_tag_hit[0], s1_dout[0], UInt<1>("h00"))
    node T_935 = mux(s1_tag_hit[1], s1_dout[1], UInt<1>("h00"))
    node T_937 = mux(s1_tag_hit[2], s1_dout[2], UInt<1>("h00"))
    node T_939 = mux(s1_tag_hit[3], s1_dout[3], UInt<1>("h00"))
    node T_941 = or(T_933, T_935)
    node T_942 = or(T_941, T_937)
    node T_943 = or(T_942, T_939)
    wire T_944 : UInt<128>
    T_944 is invalid
    T_944 <= T_943
    io.resp.bits.datablock <= T_944
    io.resp.valid <= s1_hit
    node T_945 = eq(state, UInt<1>("h01"))
    io.mem.acquire.valid <= T_945
    node T_946 = shr(refill_addr, 6)
    node T_957 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_958 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_959 = cat(T_957, T_958)
    node T_961 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_962 = cat(UInt<3>("h07"), T_961)
    node T_964 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_966 = cat(UInt<1>("h00"), UInt<1>("h01"))
    node T_968 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_969 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_970 = cat(T_968, T_969)
    node T_972 = cat(UInt<5>("h00"), UInt<1>("h01"))
    node T_974 = cat(UInt<5>("h01"), UInt<1>("h01"))
    node T_975 = eq(UInt<3>("h06"), UInt<3>("h01"))
    node T_976 = mux(T_975, T_974, UInt<1>("h00"))
    node T_977 = eq(UInt<3>("h05"), UInt<3>("h01"))
    node T_978 = mux(T_977, T_972, T_976)
    node T_979 = eq(UInt<3>("h04"), UInt<3>("h01"))
    node T_980 = mux(T_979, T_970, T_978)
    node T_981 = eq(UInt<3>("h03"), UInt<3>("h01"))
    node T_982 = mux(T_981, T_966, T_980)
    node T_983 = eq(UInt<3>("h02"), UInt<3>("h01"))
    node T_984 = mux(T_983, T_964, T_982)
    node T_985 = eq(UInt<3>("h01"), UInt<3>("h01"))
    node T_986 = mux(T_985, T_962, T_984)
    node T_987 = eq(UInt<3>("h00"), UInt<3>("h01"))
    node T_988 = mux(T_987, T_959, T_986)
    wire T_1020 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    T_1020 is invalid
    T_1020.is_builtin_type <= UInt<1>("h01")
    T_1020.a_type <= UInt<3>("h01")
    T_1020.client_xact_id <= UInt<1>("h00")
    T_1020.addr_block <= T_946
    T_1020.addr_beat <= UInt<1>("h00")
    T_1020.data <= UInt<1>("h00")
    T_1020.union <= T_988
    io.mem.acquire.bits <- T_1020
    node T_1051 = eq(UInt<1>("h00"), state)
    when T_1051 :
      when s1_miss :
        state <= UInt<1>("h01")
        skip
      invalidated <= UInt<1>("h00")
      skip
    node T_1053 = eq(UInt<1>("h01"), state)
    when T_1053 :
      when io.mem.acquire.ready :
        state <= UInt<2>("h02")
        skip
      skip
    node T_1054 = eq(UInt<2>("h02"), state)
    when T_1054 :
      when io.mem.grant.valid :
        state <= UInt<2>("h03")
        skip
      skip
    node T_1055 = eq(UInt<2>("h03"), state)
    when T_1055 :
      when refill_done :
        state <= UInt<1>("h00")
        skip
      skip
    
  module RocketCAM : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip clear : UInt<1>, flip clear_mask : UInt<8>, flip tag : UInt<34>, hit : UInt<1>, hits : UInt<8>, valid_bits : UInt<8>, flip write : UInt<1>, flip write_tag : UInt<34>, flip write_addr : UInt<3>}
    
    io is invalid
    cmem cam_tags : UInt<34>[8]
    reg vb_array : UInt<8>, clk with : (reset => (reset, UInt<8>("h00")))
    when io.write :
      node T_21 = dshl(UInt<1>("h01"), io.write_addr)
      node T_22 = or(vb_array, T_21)
      node T_23 = not(vb_array)
      node T_24 = or(T_23, T_21)
      node T_25 = not(T_24)
      node T_26 = mux(UInt<1>("h01"), T_22, T_25)
      vb_array <= T_26
      infer mport T_27 = cam_tags[io.write_addr], clk
      T_27 <= io.write_tag
      skip
    when io.clear :
      node T_28 = not(io.clear_mask)
      node T_29 = and(vb_array, T_28)
      vb_array <= T_29
      skip
    node T_30 = bits(vb_array, 0, 0)
    infer mport T_32 = cam_tags[UInt<1>("h00")], clk
    node T_33 = eq(T_32, io.tag)
    node T_34 = and(T_30, T_33)
    node T_35 = bits(vb_array, 1, 1)
    infer mport T_37 = cam_tags[UInt<1>("h01")], clk
    node T_38 = eq(T_37, io.tag)
    node T_39 = and(T_35, T_38)
    node T_40 = bits(vb_array, 2, 2)
    infer mport T_42 = cam_tags[UInt<2>("h02")], clk
    node T_43 = eq(T_42, io.tag)
    node T_44 = and(T_40, T_43)
    node T_45 = bits(vb_array, 3, 3)
    infer mport T_47 = cam_tags[UInt<2>("h03")], clk
    node T_48 = eq(T_47, io.tag)
    node T_49 = and(T_45, T_48)
    node T_50 = bits(vb_array, 4, 4)
    infer mport T_52 = cam_tags[UInt<3>("h04")], clk
    node T_53 = eq(T_52, io.tag)
    node T_54 = and(T_50, T_53)
    node T_55 = bits(vb_array, 5, 5)
    infer mport T_57 = cam_tags[UInt<3>("h05")], clk
    node T_58 = eq(T_57, io.tag)
    node T_59 = and(T_55, T_58)
    node T_60 = bits(vb_array, 6, 6)
    infer mport T_62 = cam_tags[UInt<3>("h06")], clk
    node T_63 = eq(T_62, io.tag)
    node T_64 = and(T_60, T_63)
    node T_65 = bits(vb_array, 7, 7)
    infer mport T_67 = cam_tags[UInt<3>("h07")], clk
    node T_68 = eq(T_67, io.tag)
    node T_69 = and(T_65, T_68)
    io.valid_bits <= vb_array
    wire T_71 : UInt<1>[8]
    T_71[0] <= T_34
    T_71[1] <= T_39
    T_71[2] <= T_44
    T_71[3] <= T_49
    T_71[4] <= T_54
    T_71[5] <= T_59
    T_71[6] <= T_64
    T_71[7] <= T_69
    node T_81 = cat(T_71[7], T_71[6])
    node T_82 = cat(T_71[5], T_71[4])
    node T_83 = cat(T_81, T_82)
    node T_84 = cat(T_71[3], T_71[2])
    node T_85 = cat(T_71[1], T_71[0])
    node T_86 = cat(T_84, T_85)
    node T_87 = cat(T_83, T_86)
    io.hits <= T_87
    node T_89 = neq(io.hits, UInt<1>("h00"))
    io.hit <= T_89
    
  module TLB : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg r_refill_tag : UInt, clk
    reg r_refill_waddr : UInt, clk
    reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk
    inst tag_cam of RocketCAM
    tag_cam.io is invalid
    tag_cam.clk <= clk
    tag_cam.reset <= reset
    cmem tag_ram : UInt<20>[8]
    node lookup_tag = cat(io.req.bits.asid, io.req.bits.vpn)
    tag_cam.io.tag <= lookup_tag
    node T_176 = eq(state, UInt<2>("h02"))
    node T_177 = and(T_176, io.ptw.resp.valid)
    tag_cam.io.write <= T_177
    tag_cam.io.write_tag <= r_refill_tag
    tag_cam.io.write_addr <= r_refill_waddr
    node T_178 = bits(tag_cam.io.hits, 7, 4)
    node T_179 = bits(tag_cam.io.hits, 3, 0)
    node T_181 = neq(T_178, UInt<1>("h00"))
    node T_182 = or(T_178, T_179)
    node T_183 = bits(T_182, 3, 2)
    node T_184 = bits(T_182, 1, 0)
    node T_186 = neq(T_183, UInt<1>("h00"))
    node T_187 = or(T_183, T_184)
    node T_188 = bits(T_187, 1, 1)
    node T_189 = cat(T_186, T_188)
    node tag_hit_addr = cat(T_181, T_189)
    reg valid_array : UInt<1>[8], clk
    reg ur_array : UInt<1>[8], clk
    reg uw_array : UInt<1>[8], clk
    reg ux_array : UInt<1>[8], clk
    reg sr_array : UInt<1>[8], clk
    reg sw_array : UInt<1>[8], clk
    reg sx_array : UInt<1>[8], clk
    reg dirty_array : UInt<1>[8], clk
    when io.ptw.resp.valid :
      infer mport T_383 = tag_ram[r_refill_waddr], clk
      T_383 <= io.ptw.resp.bits.pte.ppn
      node T_386 = eq(io.ptw.resp.bits.error, UInt<1>("h00"))
      valid_array[r_refill_waddr] <= T_386
      node T_389 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02"))
      node T_390 = and(io.ptw.resp.bits.pte.v, T_389)
      node T_392 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08"))
      node T_393 = and(T_390, T_392)
      node T_395 = eq(io.ptw.resp.bits.error, UInt<1>("h00"))
      node T_396 = and(T_393, T_395)
      ur_array[r_refill_waddr] <= T_396
      node T_399 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02"))
      node T_400 = and(io.ptw.resp.bits.pte.v, T_399)
      node T_402 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08"))
      node T_403 = and(T_400, T_402)
      node T_404 = bits(io.ptw.resp.bits.pte.typ, 0, 0)
      node T_405 = and(T_403, T_404)
      node T_407 = eq(io.ptw.resp.bits.error, UInt<1>("h00"))
      node T_408 = and(T_405, T_407)
      uw_array[r_refill_waddr] <= T_408
      node T_411 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02"))
      node T_412 = and(io.ptw.resp.bits.pte.v, T_411)
      node T_414 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08"))
      node T_415 = and(T_412, T_414)
      node T_416 = bits(io.ptw.resp.bits.pte.typ, 1, 1)
      node T_417 = and(T_415, T_416)
      node T_419 = eq(io.ptw.resp.bits.error, UInt<1>("h00"))
      node T_420 = and(T_417, T_419)
      ux_array[r_refill_waddr] <= T_420
      node T_423 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02"))
      node T_424 = and(io.ptw.resp.bits.pte.v, T_423)
      node T_426 = eq(io.ptw.resp.bits.error, UInt<1>("h00"))
      node T_427 = and(T_424, T_426)
      sr_array[r_refill_waddr] <= T_427
      node T_430 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02"))
      node T_431 = and(io.ptw.resp.bits.pte.v, T_430)
      node T_432 = bits(io.ptw.resp.bits.pte.typ, 0, 0)
      node T_433 = and(T_431, T_432)
      node T_435 = eq(io.ptw.resp.bits.error, UInt<1>("h00"))
      node T_436 = and(T_433, T_435)
      sw_array[r_refill_waddr] <= T_436
      node T_439 = geq(io.ptw.resp.bits.pte.typ, UInt<3>("h04"))
      node T_440 = and(io.ptw.resp.bits.pte.v, T_439)
      node T_441 = bits(io.ptw.resp.bits.pte.typ, 1, 1)
      node T_442 = and(T_440, T_441)
      node T_444 = eq(io.ptw.resp.bits.error, UInt<1>("h00"))
      node T_445 = and(T_442, T_444)
      sx_array[r_refill_waddr] <= T_445
      dirty_array[r_refill_waddr] <= io.ptw.resp.bits.pte.d
      skip
    node T_447 = not(tag_cam.io.valid_bits)
    node T_449 = eq(T_447, UInt<1>("h00"))
    node has_invalid_entry = eq(T_449, UInt<1>("h00"))
    node T_452 = not(tag_cam.io.valid_bits)
    node T_453 = bits(T_452, 0, 0)
    node T_454 = bits(T_452, 1, 1)
    node T_455 = bits(T_452, 2, 2)
    node T_456 = bits(T_452, 3, 3)
    node T_457 = bits(T_452, 4, 4)
    node T_458 = bits(T_452, 5, 5)
    node T_459 = bits(T_452, 6, 6)
    node T_460 = bits(T_452, 7, 7)
    wire T_462 : UInt<1>[8]
    T_462[0] <= T_453
    T_462[1] <= T_454
    T_462[2] <= T_455
    T_462[3] <= T_456
    T_462[4] <= T_457
    T_462[5] <= T_458
    T_462[6] <= T_459
    T_462[7] <= T_460
    node T_480 = mux(T_462[6], UInt<3>("h06"), UInt<3>("h07"))
    node T_481 = mux(T_462[5], UInt<3>("h05"), T_480)
    node T_482 = mux(T_462[4], UInt<3>("h04"), T_481)
    node T_483 = mux(T_462[3], UInt<2>("h03"), T_482)
    node T_484 = mux(T_462[2], UInt<2>("h02"), T_483)
    node T_485 = mux(T_462[1], UInt<1>("h01"), T_484)
    node invalid_entry = mux(T_462[0], UInt<1>("h00"), T_485)
    reg T_488 : UInt<8>, clk
    node T_490 = dshr(T_488, UInt<1>("h01"))
    node T_491 = bits(T_490, 0, 0)
    node T_492 = cat(UInt<1>("h01"), T_491)
    node T_493 = dshr(T_488, T_492)
    node T_494 = bits(T_493, 0, 0)
    node T_495 = cat(T_492, T_494)
    node T_496 = dshr(T_488, T_495)
    node T_497 = bits(T_496, 0, 0)
    node T_498 = cat(T_495, T_497)
    node T_499 = bits(T_498, 2, 0)
    node repl_waddr = mux(has_invalid_entry, invalid_entry, T_499)
    node T_502 = eq(io.req.bits.instruction, UInt<1>("h00"))
    node T_503 = and(io.ptw.status.mprv, T_502)
    node priv = mux(T_503, io.ptw.status.prv1, io.ptw.status.prv)
    node priv_s = eq(priv, UInt<1>("h01"))
    node priv_uses_vm = leq(priv, UInt<1>("h01"))
    node T_510 = eq(r_req.store, UInt<1>("h00"))
    node T_511 = or(r_req.instruction, r_req.store)
    node T_513 = eq(T_511, UInt<1>("h00"))
    node T_514 = cat(r_req.store, T_513)
    node req_xwr = cat(T_510, T_514)
    node T_516 = cat(sr_array[7], sr_array[6])
    node T_517 = cat(sr_array[5], sr_array[4])
    node T_518 = cat(T_516, T_517)
    node T_519 = cat(sr_array[3], sr_array[2])
    node T_520 = cat(sr_array[1], sr_array[0])
    node T_521 = cat(T_519, T_520)
    node T_522 = cat(T_518, T_521)
    node T_523 = cat(ur_array[7], ur_array[6])
    node T_524 = cat(ur_array[5], ur_array[4])
    node T_525 = cat(T_523, T_524)
    node T_526 = cat(ur_array[3], ur_array[2])
    node T_527 = cat(ur_array[1], ur_array[0])
    node T_528 = cat(T_526, T_527)
    node T_529 = cat(T_525, T_528)
    node r_array = mux(priv_s, T_522, T_529)
    node T_531 = cat(sw_array[7], sw_array[6])
    node T_532 = cat(sw_array[5], sw_array[4])
    node T_533 = cat(T_531, T_532)
    node T_534 = cat(sw_array[3], sw_array[2])
    node T_535 = cat(sw_array[1], sw_array[0])
    node T_536 = cat(T_534, T_535)
    node T_537 = cat(T_533, T_536)
    node T_538 = cat(uw_array[7], uw_array[6])
    node T_539 = cat(uw_array[5], uw_array[4])
    node T_540 = cat(T_538, T_539)
    node T_541 = cat(uw_array[3], uw_array[2])
    node T_542 = cat(uw_array[1], uw_array[0])
    node T_543 = cat(T_541, T_542)
    node T_544 = cat(T_540, T_543)
    node w_array = mux(priv_s, T_537, T_544)
    node T_546 = cat(sx_array[7], sx_array[6])
    node T_547 = cat(sx_array[5], sx_array[4])
    node T_548 = cat(T_546, T_547)
    node T_549 = cat(sx_array[3], sx_array[2])
    node T_550 = cat(sx_array[1], sx_array[0])
    node T_551 = cat(T_549, T_550)
    node T_552 = cat(T_548, T_551)
    node T_553 = cat(ux_array[7], ux_array[6])
    node T_554 = cat(ux_array[5], ux_array[4])
    node T_555 = cat(T_553, T_554)
    node T_556 = cat(ux_array[3], ux_array[2])
    node T_557 = cat(ux_array[1], ux_array[0])
    node T_558 = cat(T_556, T_557)
    node T_559 = cat(T_555, T_558)
    node x_array = mux(priv_s, T_552, T_559)
    node T_561 = bits(io.ptw.status.vm, 3, 3)
    node T_562 = and(T_561, priv_uses_vm)
    node T_564 = eq(io.req.bits.passthrough, UInt<1>("h00"))
    node vm_enabled = and(T_562, T_564)
    node T_566 = bits(io.req.bits.vpn, 27, 27)
    node T_567 = bits(io.req.bits.vpn, 26, 26)
    node bad_va = neq(T_566, T_567)
    node T_569 = cat(dirty_array[7], dirty_array[6])
    node T_570 = cat(dirty_array[5], dirty_array[4])
    node T_571 = cat(T_569, T_570)
    node T_572 = cat(dirty_array[3], dirty_array[2])
    node T_573 = cat(dirty_array[1], dirty_array[0])
    node T_574 = cat(T_572, T_573)
    node T_575 = cat(T_571, T_574)
    node T_577 = mux(io.req.bits.store, w_array, UInt<1>("h00"))
    node T_578 = not(T_577)
    node T_579 = or(T_575, T_578)
    node tag_hits = and(tag_cam.io.hits, T_579)
    node tag_hit = neq(tag_hits, UInt<1>("h00"))
    node tlb_hit = and(vm_enabled, tag_hit)
    node T_585 = eq(tag_hit, UInt<1>("h00"))
    node T_586 = and(vm_enabled, T_585)
    node T_588 = eq(bad_va, UInt<1>("h00"))
    node tlb_miss = and(T_586, T_588)
    node T_590 = and(io.req.valid, tlb_hit)
    when T_590 :
      node T_591 = bits(tag_cam.io.hits, 7, 4)
      node T_592 = bits(tag_cam.io.hits, 3, 0)
      node T_594 = neq(T_591, UInt<1>("h00"))
      node T_595 = or(T_591, T_592)
      node T_596 = bits(T_595, 3, 2)
      node T_597 = bits(T_595, 1, 0)
      node T_599 = neq(T_596, UInt<1>("h00"))
      node T_600 = or(T_596, T_597)
      node T_601 = bits(T_600, 1, 1)
      node T_602 = cat(T_599, T_601)
      node T_603 = cat(T_594, T_602)
      node T_605 = bits(T_603, 2, 2)
      node T_607 = dshl(UInt<8>("h01"), UInt<1>("h01"))
      node T_608 = bits(T_607, 7, 0)
      node T_609 = not(T_608)
      node T_610 = and(T_488, T_609)
      node T_612 = mux(T_605, UInt<1>("h00"), T_608)
      node T_613 = or(T_610, T_612)
      node T_614 = cat(UInt<1>("h01"), T_605)
      node T_615 = bits(T_603, 1, 1)
      node T_617 = dshl(UInt<8>("h01"), T_614)
      node T_618 = bits(T_617, 7, 0)
      node T_619 = not(T_618)
      node T_620 = and(T_613, T_619)
      node T_622 = mux(T_615, UInt<1>("h00"), T_618)
      node T_623 = or(T_620, T_622)
      node T_624 = cat(T_614, T_615)
      node T_625 = bits(T_603, 0, 0)
      node T_627 = dshl(UInt<8>("h01"), T_624)
      node T_628 = bits(T_627, 7, 0)
      node T_629 = not(T_628)
      node T_630 = and(T_623, T_629)
      node T_632 = mux(T_625, UInt<1>("h00"), T_628)
      node T_633 = or(T_630, T_632)
      node T_634 = cat(T_624, T_625)
      T_488 <= T_633
      skip
    node paddr = cat(io.resp.ppn, UInt<12>("h00"))
    node T_638 = geq(paddr, UInt<1>("h00"))
    node T_640 = lt(paddr, UInt<31>("h040000000"))
    node T_641 = and(T_638, T_640)
    node T_643 = geq(paddr, UInt<31>("h040000000"))
    node T_645 = lt(paddr, UInt<31>("h040008000"))
    node T_646 = and(T_643, T_645)
    node T_648 = geq(paddr, UInt<31>("h040008000"))
    node T_650 = lt(paddr, UInt<31>("h040010000"))
    node T_651 = and(T_648, T_650)
    node T_653 = geq(paddr, UInt<31>("h040010000"))
    node T_655 = lt(paddr, UInt<31>("h040010200"))
    node T_656 = and(T_653, T_655)
    node T_658 = geq(paddr, UInt<32>("h080000000"))
    node T_660 = lt(paddr, UInt<33>("h0100000000"))
    node T_661 = and(T_658, T_660)
    node T_662 = or(T_641, T_646)
    node T_663 = or(T_662, T_651)
    node T_664 = or(T_663, T_656)
    node addr_ok = or(T_664, T_661)
    node T_667 = geq(paddr, UInt<1>("h00"))
    node T_669 = lt(paddr, UInt<31>("h040000000"))
    node T_670 = and(T_667, T_669)
    wire T_680 : {x : UInt<1>, w : UInt<1>, r : UInt<1>}
    T_680 is invalid
    T_680.r <= UInt<1>("h01")
    T_680.w <= UInt<1>("h01")
    T_680.x <= UInt<1>("h01")
    node T_688 = geq(paddr, UInt<31>("h040000000"))
    node T_690 = lt(paddr, UInt<31>("h040008000"))
    node T_691 = and(T_688, T_690)
    wire T_701 : {x : UInt<1>, w : UInt<1>, r : UInt<1>}
    T_701 is invalid
    T_701.r <= UInt<1>("h01")
    T_701.w <= UInt<1>("h00")
    T_701.x <= UInt<1>("h00")
    node T_709 = geq(paddr, UInt<31>("h040008000"))
    node T_711 = lt(paddr, UInt<31>("h040010000"))
    node T_712 = and(T_709, T_711)
    wire T_722 : {x : UInt<1>, w : UInt<1>, r : UInt<1>}
    T_722 is invalid
    T_722.r <= UInt<1>("h01")
    T_722.w <= UInt<1>("h01")
    T_722.x <= UInt<1>("h00")
    node T_730 = geq(paddr, UInt<31>("h040010000"))
    node T_732 = lt(paddr, UInt<31>("h040010200"))
    node T_733 = and(T_730, T_732)
    wire T_743 : {x : UInt<1>, w : UInt<1>, r : UInt<1>}
    T_743 is invalid
    T_743.r <= UInt<1>("h01")
    T_743.w <= UInt<1>("h01")
    T_743.x <= UInt<1>("h00")
    node T_751 = geq(paddr, UInt<32>("h080000000"))
    node T_753 = lt(paddr, UInt<33>("h0100000000"))
    node T_754 = and(T_751, T_753)
    wire T_764 : {x : UInt<1>, w : UInt<1>, r : UInt<1>}
    T_764 is invalid
    T_764.r <= UInt<1>("h01")
    T_764.w <= UInt<1>("h01")
    T_764.x <= UInt<1>("h00")
    node T_771 = cat(T_680.w, T_680.r)
    node T_772 = cat(T_680.x, T_771)
    node T_774 = mux(T_670, T_772, UInt<1>("h00"))
    node T_775 = cat(T_701.w, T_701.r)
    node T_776 = cat(T_701.x, T_775)
    node T_778 = mux(T_691, T_776, UInt<1>("h00"))
    node T_779 = cat(T_722.w, T_722.r)
    node T_780 = cat(T_722.x, T_779)
    node T_782 = mux(T_712, T_780, UInt<1>("h00"))
    node T_783 = cat(T_743.w, T_743.r)
    node T_784 = cat(T_743.x, T_783)
    node T_786 = mux(T_733, T_784, UInt<1>("h00"))
    node T_787 = cat(T_764.w, T_764.r)
    node T_788 = cat(T_764.x, T_787)
    node T_790 = mux(T_754, T_788, UInt<1>("h00"))
    node T_795 = or(T_774, T_778)
    node T_796 = or(T_795, T_782)
    node T_797 = or(T_796, T_786)
    node T_798 = or(T_797, T_790)
    wire addr_prot : {x : UInt<1>, w : UInt<1>, r : UInt<1>}
    addr_prot is invalid
    node T_807 = bits(T_798, 0, 0)
    addr_prot.r <= T_807
    node T_808 = bits(T_798, 1, 1)
    addr_prot.w <= T_808
    node T_809 = bits(T_798, 2, 2)
    addr_prot.x <= T_809
    node T_810 = eq(state, UInt<1>("h00"))
    io.req.ready <= T_810
    node T_812 = eq(addr_ok, UInt<1>("h00"))
    node T_814 = eq(addr_prot.r, UInt<1>("h00"))
    node T_815 = or(T_812, T_814)
    node T_816 = or(T_815, bad_va)
    node T_817 = and(r_array, tag_cam.io.hits)
    node T_819 = neq(T_817, UInt<1>("h00"))
    node T_821 = eq(T_819, UInt<1>("h00"))
    node T_822 = and(tlb_hit, T_821)
    node T_823 = or(T_816, T_822)
    io.resp.xcpt_ld <= T_823
    node T_825 = eq(addr_ok, UInt<1>("h00"))
    node T_827 = eq(addr_prot.w, UInt<1>("h00"))
    node T_828 = or(T_825, T_827)
    node T_829 = or(T_828, bad_va)
    node T_830 = and(w_array, tag_cam.io.hits)
    node T_832 = neq(T_830, UInt<1>("h00"))
    node T_834 = eq(T_832, UInt<1>("h00"))
    node T_835 = and(tlb_hit, T_834)
    node T_836 = or(T_829, T_835)
    io.resp.xcpt_st <= T_836
    node T_838 = eq(addr_ok, UInt<1>("h00"))
    node T_840 = eq(addr_prot.x, UInt<1>("h00"))
    node T_841 = or(T_838, T_840)
    node T_842 = or(T_841, bad_va)
    node T_843 = and(x_array, tag_cam.io.hits)
    node T_845 = neq(T_843, UInt<1>("h00"))
    node T_847 = eq(T_845, UInt<1>("h00"))
    node T_848 = and(tlb_hit, T_847)
    node T_849 = or(T_842, T_848)
    io.resp.xcpt_if <= T_849
    io.resp.miss <= tlb_miss
    node T_850 = bits(tag_cam.io.hits, 0, 0)
    node T_851 = bits(tag_cam.io.hits, 1, 1)
    node T_852 = bits(tag_cam.io.hits, 2, 2)
    node T_853 = bits(tag_cam.io.hits, 3, 3)
    node T_854 = bits(tag_cam.io.hits, 4, 4)
    node T_855 = bits(tag_cam.io.hits, 5, 5)
    node T_856 = bits(tag_cam.io.hits, 6, 6)
    node T_857 = bits(tag_cam.io.hits, 7, 7)
    infer mport T_859 = tag_ram[UInt<1>("h00")], clk
    infer mport T_861 = tag_ram[UInt<1>("h01")], clk
    infer mport T_863 = tag_ram[UInt<2>("h02")], clk
    infer mport T_865 = tag_ram[UInt<2>("h03")], clk
    infer mport T_867 = tag_ram[UInt<3>("h04")], clk
    infer mport T_869 = tag_ram[UInt<3>("h05")], clk
    infer mport T_871 = tag_ram[UInt<3>("h06")], clk
    infer mport T_873 = tag_ram[UInt<3>("h07")], clk
    node T_875 = mux(T_850, T_859, UInt<1>("h00"))
    node T_877 = mux(T_851, T_861, UInt<1>("h00"))
    node T_879 = mux(T_852, T_863, UInt<1>("h00"))
    node T_881 = mux(T_853, T_865, UInt<1>("h00"))
    node T_883 = mux(T_854, T_867, UInt<1>("h00"))
    node T_885 = mux(T_855, T_869, UInt<1>("h00"))
    node T_887 = mux(T_856, T_871, UInt<1>("h00"))
    node T_889 = mux(T_857, T_873, UInt<1>("h00"))
    node T_891 = or(T_875, T_877)
    node T_892 = or(T_891, T_879)
    node T_893 = or(T_892, T_881)
    node T_894 = or(T_893, T_883)
    node T_895 = or(T_894, T_885)
    node T_896 = or(T_895, T_887)
    node T_897 = or(T_896, T_889)
    wire T_898 : UInt<20>
    T_898 is invalid
    T_898 <= T_897
    node T_899 = bits(io.req.bits.vpn, 19, 0)
    node T_900 = mux(vm_enabled, T_898, T_899)
    io.resp.ppn <= T_900
    io.resp.hit_idx <= tag_cam.io.hits
    node T_901 = and(io.req.ready, io.req.valid)
    node T_902 = or(io.ptw.invalidate, T_901)
    tag_cam.io.clear <= T_902
    node T_903 = cat(valid_array[7], valid_array[6])
    node T_904 = cat(valid_array[5], valid_array[4])
    node T_905 = cat(T_903, T_904)
    node T_906 = cat(valid_array[3], valid_array[2])
    node T_907 = cat(valid_array[1], valid_array[0])
    node T_908 = cat(T_906, T_907)
    node T_909 = cat(T_905, T_908)
    node T_910 = not(T_909)
    node T_911 = not(tag_hits)
    node T_912 = and(tag_cam.io.hits, T_911)
    node T_913 = or(T_910, T_912)
    tag_cam.io.clear_mask <= T_913
    when io.ptw.invalidate :
      node T_915 = not(UInt<8>("h00"))
      tag_cam.io.clear_mask <= T_915
      skip
    node T_916 = eq(state, UInt<1>("h01"))
    io.ptw.req.valid <= T_916
    io.ptw.req.bits.addr <= r_refill_tag
    io.ptw.req.bits.prv <= io.ptw.status.prv
    io.ptw.req.bits.store <= r_req.store
    io.ptw.req.bits.fetch <= r_req.instruction
    node T_917 = and(io.req.ready, io.req.valid)
    node T_918 = and(T_917, tlb_miss)
    when T_918 :
      state <= UInt<1>("h01")
      r_refill_tag <= lookup_tag
      r_refill_waddr <= repl_waddr
      r_req <- io.req.bits
      skip
    node T_919 = eq(state, UInt<1>("h01"))
    when T_919 :
      when io.ptw.invalidate :
        state <= UInt<1>("h00")
        skip
      when io.ptw.req.ready :
        state <= UInt<2>("h02")
        when io.ptw.invalidate :
          state <= UInt<2>("h03")
          skip
        skip
      skip
    node T_920 = eq(state, UInt<2>("h02"))
    node T_921 = and(T_920, io.ptw.invalidate)
    when T_921 :
      state <= UInt<2>("h03")
      skip
    when io.ptw.resp.valid :
      state <= UInt<1>("h00")
      skip
    
  module Queue_92 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, count : UInt<1>}
    
    io is invalid
    cmem ram : {data : UInt<32>, datablock : UInt<128>}[1]
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_463 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_463)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_469 = and(io.enq.ready, io.enq.valid)
    node T_471 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_469, T_471)
    node T_473 = and(io.deq.ready, io.deq.valid)
    node T_475 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_473, T_475)
    when do_enq :
      infer mport T_477 = ram[UInt<1>("h00")], clk
      T_477 <- io.enq.bits
      skip
    when do_deq :
      skip
    node T_528 = neq(do_enq, do_deq)
    when T_528 :
      maybe_full <= do_enq
      skip
    node T_530 = eq(empty, UInt<1>("h00"))
    node T_532 = and(UInt<1>("h00"), io.enq.valid)
    node T_533 = or(T_530, T_532)
    io.deq.valid <= T_533
    node T_535 = eq(full, UInt<1>("h00"))
    node T_537 = and(UInt<1>("h01"), io.deq.ready)
    node T_538 = or(T_535, T_537)
    io.enq.ready <= T_538
    infer mport T_539 = ram[UInt<1>("h00")], clk
    node T_588 = mux(maybe_flow, io.enq.bits, T_539)
    io.deq.bits <- T_588
    node T_637 = sub(UInt<1>("h00"), UInt<1>("h00"))
    node ptr_diff = tail(T_637, 1)
    node T_639 = and(maybe_full, ptr_match)
    node T_640 = cat(T_639, ptr_diff)
    io.count <= T_640
    
  module Frontend : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}}
    
    io is invalid
    inst btb of BTB
    btb.io is invalid
    btb.clk <= clk
    btb.reset <= reset
    inst icache of ICache
    icache.io is invalid
    icache.clk <= clk
    icache.reset <= reset
    inst tlb of TLB
    tlb.io is invalid
    tlb.clk <= clk
    tlb.reset <= reset
    reg s1_pc_ : UInt, clk
    node T_1280 = not(s1_pc_)
    node T_1282 = or(T_1280, UInt<2>("h03"))
    node s1_pc = not(T_1282)
    reg s1_same_block : UInt<1>, clk
    reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h01")))
    reg s2_pc : UInt, clk with : (reset => (reset, UInt<10>("h0200")))
    reg s2_btb_resp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk
    reg s2_xcpt_if : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wire s2_resp_valid : UInt<1>
    s2_resp_valid <= UInt<1>("h00")
    wire s2_resp_data : UInt<128>
    s2_resp_data is invalid
    node T_1307 = bits(btb.io.resp.bits.target, 38, 38)
    node btbTarget = cat(T_1307, btb.io.resp.bits.target)
    node T_1310 = add(s1_pc, UInt<3>("h04"))
    node ntpc_0 = tail(T_1310, 1)
    node T_1312 = bits(s1_pc, 38, 38)
    node T_1313 = bits(ntpc_0, 38, 38)
    node T_1314 = and(T_1312, T_1313)
    node T_1315 = bits(ntpc_0, 38, 2)
    node T_1317 = cat(T_1315, UInt<2>("h00"))
    node ntpc = cat(T_1314, T_1317)
    node T_1320 = eq(s2_resp_valid, UInt<1>("h00"))
    node icmiss = and(s2_valid, T_1320)
    node predicted_npc = mux(btb.io.resp.bits.taken, btbTarget, ntpc)
    node npc = mux(icmiss, s2_pc, predicted_npc)
    node T_1325 = eq(icmiss, UInt<1>("h00"))
    node T_1327 = eq(io.cpu.req.valid, UInt<1>("h00"))
    node T_1328 = and(T_1325, T_1327)
    node T_1330 = eq(btb.io.resp.bits.taken, UInt<1>("h00"))
    node T_1331 = and(T_1328, T_1330)
    node T_1333 = and(ntpc, UInt<5>("h010"))
    node T_1335 = and(s1_pc, UInt<5>("h010"))
    node T_1336 = eq(T_1333, T_1335)
    node s0_same_block = and(T_1331, T_1336)
    node T_1339 = eq(io.cpu.resp.ready, UInt<1>("h00"))
    node stall = and(io.cpu.resp.valid, T_1339)
    node T_1342 = eq(stall, UInt<1>("h00"))
    when T_1342 :
      node T_1344 = eq(tlb.io.resp.miss, UInt<1>("h00"))
      node T_1345 = and(s0_same_block, T_1344)
      s1_same_block <= T_1345
      s1_pc_ <= npc
      node T_1347 = eq(icmiss, UInt<1>("h00"))
      s2_valid <= T_1347
      node T_1349 = eq(icmiss, UInt<1>("h00"))
      when T_1349 :
        s2_pc <= s1_pc
        s2_btb_resp_valid <= btb.io.resp.valid
        when btb.io.resp.valid :
          s2_btb_resp_bits <- btb.io.resp.bits
          skip
        s2_xcpt_if <= tlb.io.resp.xcpt_if
        skip
      skip
    when io.cpu.req.valid :
      s1_same_block <= UInt<1>("h00")
      s1_pc_ <= io.cpu.req.bits.pc
      s2_valid <= UInt<1>("h00")
      skip
    node T_1353 = eq(stall, UInt<1>("h00"))
    node T_1355 = eq(icmiss, UInt<1>("h00"))
    node T_1356 = and(T_1353, T_1355)
    btb.io.req.valid <= T_1356
    btb.io.req.bits.addr <= s1_pc
    btb.io.btb_update <- io.cpu.btb_update
    btb.io.bht_update <- io.cpu.bht_update
    btb.io.ras_update <- io.cpu.ras_update
    node T_1357 = or(io.cpu.invalidate, io.ptw.invalidate)
    btb.io.invalidate <= T_1357
    io.ptw <- tlb.io.ptw
    node T_1359 = eq(stall, UInt<1>("h00"))
    node T_1361 = eq(icmiss, UInt<1>("h00"))
    node T_1362 = and(T_1359, T_1361)
    tlb.io.req.valid <= T_1362
    node T_1363 = shr(s1_pc, 12)
    tlb.io.req.bits.vpn <= T_1363
    tlb.io.req.bits.asid <= UInt<1>("h00")
    tlb.io.req.bits.passthrough <= UInt<1>("h00")
    tlb.io.req.bits.instruction <= UInt<1>("h01")
    tlb.io.req.bits.store <= UInt<1>("h00")
    io.mem <- icache.io.mem
    node T_1369 = eq(stall, UInt<1>("h00"))
    node T_1371 = eq(s0_same_block, UInt<1>("h00"))
    node T_1372 = and(T_1369, T_1371)
    icache.io.req.valid <= T_1372
    icache.io.req.bits.idx <= io.cpu.npc
    icache.io.invalidate <= io.cpu.invalidate
    icache.io.req.bits.ppn <= tlb.io.resp.ppn
    node T_1373 = or(io.cpu.req.valid, tlb.io.resp.miss)
    node T_1374 = or(T_1373, tlb.io.resp.xcpt_if)
    node T_1375 = or(T_1374, icmiss)
    node T_1376 = or(T_1375, io.ptw.invalidate)
    icache.io.req.bits.kill <= T_1376
    node T_1377 = or(s2_xcpt_if, s2_resp_valid)
    node T_1378 = and(s2_valid, T_1377)
    io.cpu.resp.valid <= T_1378
    io.cpu.resp.bits.pc <= s2_pc
    node T_1379 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
    io.cpu.npc <= T_1379
    inst T_1429 of Queue_92
    T_1429.io is invalid
    T_1429.clk <= clk
    T_1429.reset <= reset
    T_1429.io.enq <- icache.io.resp
    node T_1431 = eq(stall, UInt<1>("h00"))
    node T_1433 = eq(s1_same_block, UInt<1>("h00"))
    node T_1434 = and(T_1431, T_1433)
    T_1429.io.deq.ready <= T_1434
    s2_resp_valid <= T_1429.io.deq.valid
    s2_resp_data <= T_1429.io.deq.bits.datablock
    node T_1435 = bits(s2_pc, 3, 2)
    node T_1436 = shl(T_1435, 5)
    node fetch_data = dshr(s2_resp_data, T_1436)
    node T_1438 = bits(fetch_data, 31, 0)
    io.cpu.resp.bits.data[0] <= T_1438
    node T_1440 = and(UInt<2>("h03"), s2_btb_resp_bits.mask)
    node T_1441 = mux(s2_btb_resp_valid, T_1440, UInt<2>("h03"))
    io.cpu.resp.bits.mask <= T_1441
    io.cpu.resp.bits.xcpt_if <= s2_xcpt_if
    io.cpu.btb_resp.valid <= s2_btb_resp_valid
    io.cpu.btb_resp.bits <- s2_btb_resp_bits
    
  module WritebackUnit : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip data_resp : UInt<128>, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}
    
    io is invalid
    reg active : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg r1_data_req_fired : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg r2_data_req_fired : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg data_req_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    node T_476 = not(UInt<1>("h01"))
    node beat_done = eq(T_476, UInt<1>("h00"))
    node T_479 = and(io.release.ready, io.release.valid)
    reg beat_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_479 :
      node T_483 = eq(beat_cnt, UInt<2>("h03"))
      node T_485 = and(UInt<1>("h00"), T_483)
      node T_488 = add(beat_cnt, UInt<1>("h01"))
      node T_489 = tail(T_488, 1)
      node T_490 = mux(T_485, UInt<1>("h00"), T_489)
      beat_cnt <= T_490
      skip
    node all_beats_done = and(T_479, T_483)
    reg req : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}, clk
    io.release.valid <= UInt<1>("h00")
    when active :
      r1_data_req_fired <= UInt<1>("h00")
      r2_data_req_fired <= r1_data_req_fired
      node T_556 = and(io.data_req.ready, io.data_req.valid)
      node T_557 = and(io.meta_read.ready, io.meta_read.valid)
      node T_558 = and(T_556, T_557)
      when T_558 :
        r1_data_req_fired <= UInt<1>("h01")
        node T_561 = add(data_req_cnt, UInt<1>("h01"))
        node T_562 = tail(T_561, 1)
        data_req_cnt <= T_562
        skip
      when r2_data_req_fired :
        io.release.valid <= beat_done
        when beat_done :
          node T_564 = eq(io.release.ready, UInt<1>("h00"))
          when T_564 :
            r1_data_req_fired <= UInt<1>("h00")
            r2_data_req_fired <= UInt<1>("h00")
            node T_568 = and(UInt<1>("h01"), r1_data_req_fired)
            node T_571 = mux(T_568, UInt<2>("h02"), UInt<1>("h01"))
            node T_572 = sub(data_req_cnt, T_571)
            node T_573 = tail(T_572, 1)
            data_req_cnt <= T_573
            skip
          node T_575 = eq(T_564, UInt<1>("h00"))
          when T_575 :
            skip
          skip
        node T_577 = eq(r1_data_req_fired, UInt<1>("h00"))
        when T_577 :
          node T_579 = lt(data_req_cnt, UInt<3>("h04"))
          node T_581 = eq(io.release.ready, UInt<1>("h00"))
          node T_582 = or(T_579, T_581)
          active <= T_582
          skip
        skip
      skip
    node T_583 = and(io.req.ready, io.req.valid)
    when T_583 :
      active <= UInt<1>("h01")
      data_req_cnt <= UInt<1>("h00")
      req <- io.req.bits
      skip
    node T_587 = eq(active, UInt<1>("h00"))
    io.req.ready <= T_587
    node req_idx = bits(req.addr_block, 5, 0)
    node T_590 = lt(data_req_cnt, UInt<3>("h04"))
    node fire = and(active, T_590)
    io.meta_read.valid <= fire
    io.meta_read.bits.idx <= req_idx
    node T_592 = shr(req.addr_block, 6)
    io.meta_read.bits.tag <= T_592
    io.data_req.valid <= fire
    io.data_req.bits.way_en <= req.way_en
    node T_593 = bits(data_req_cnt, 1, 0)
    node T_594 = cat(req_idx, T_593)
    node T_595 = shl(T_594, 4)
    io.data_req.bits.addr <= T_595
    io.release.bits <- req
    io.release.bits.addr_beat <= beat_cnt
    io.release.bits.data <= io.data_resp
    
  module ProbeUnit : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}}, rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, flip way_en : UInt<4>, flip mshr_rdy : UInt<1>, flip block_state : {state : UInt<2>}}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg old_coh : {state : UInt<2>}, clk
    reg way_en : UInt, clk
    reg req : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}, clk
    node tag_matches = neq(way_en, UInt<1>("h00"))
    wire miss_coh : {state : UInt<2>}
    miss_coh is invalid
    miss_coh.state <= UInt<1>("h00")
    node reply_coh = mux(tag_matches, old_coh, miss_coh)
    wire T_947 : UInt<2>[1]
    T_947[0] <= UInt<2>("h03")
    node T_950 = eq(T_947[0], reply_coh.state)
    node T_952 = or(UInt<1>("h00"), T_950)
    node T_953 = mux(T_952, UInt<1>("h00"), UInt<2>("h03"))
    node T_954 = mux(T_952, UInt<1>("h01"), UInt<3>("h04"))
    node T_955 = mux(T_952, UInt<2>("h02"), UInt<3>("h05"))
    node T_956 = eq(UInt<5>("h013"), UInt<5>("h010"))
    node T_957 = mux(T_956, T_955, UInt<3>("h05"))
    node T_958 = eq(UInt<5>("h011"), UInt<5>("h010"))
    node T_959 = mux(T_958, T_954, T_957)
    node T_960 = eq(UInt<5>("h010"), UInt<5>("h010"))
    node T_961 = mux(T_960, T_953, T_959)
    wire T_963 : UInt<2>[1]
    T_963[0] <= UInt<2>("h03")
    node T_966 = eq(T_963[0], reply_coh.state)
    node T_968 = or(UInt<1>("h00"), T_966)
    node T_969 = mux(T_968, UInt<1>("h00"), UInt<2>("h03"))
    node T_970 = mux(T_968, UInt<1>("h01"), UInt<3>("h04"))
    node T_971 = mux(T_968, UInt<2>("h02"), UInt<3>("h05"))
    node T_972 = eq(UInt<5>("h013"), UInt<5>("h011"))
    node T_973 = mux(T_972, T_971, UInt<3>("h05"))
    node T_974 = eq(UInt<5>("h011"), UInt<5>("h011"))
    node T_975 = mux(T_974, T_970, T_973)
    node T_976 = eq(UInt<5>("h010"), UInt<5>("h011"))
    node T_977 = mux(T_976, T_969, T_975)
    wire T_979 : UInt<2>[1]
    T_979[0] <= UInt<2>("h03")
    node T_982 = eq(T_979[0], reply_coh.state)
    node T_984 = or(UInt<1>("h00"), T_982)
    node T_985 = mux(T_984, UInt<1>("h00"), UInt<2>("h03"))
    node T_986 = mux(T_984, UInt<1>("h01"), UInt<3>("h04"))
    node T_987 = mux(T_984, UInt<2>("h02"), UInt<3>("h05"))
    node T_988 = eq(UInt<5>("h013"), UInt<5>("h013"))
    node T_989 = mux(T_988, T_987, UInt<3>("h05"))
    node T_990 = eq(UInt<5>("h011"), UInt<5>("h013"))
    node T_991 = mux(T_990, T_986, T_989)
    node T_992 = eq(UInt<5>("h010"), UInt<5>("h013"))
    node T_993 = mux(T_992, T_985, T_991)
    node T_994 = eq(UInt<2>("h02"), req.p_type)
    node T_995 = mux(T_994, T_993, UInt<2>("h03"))
    node T_996 = eq(UInt<1>("h01"), req.p_type)
    node T_997 = mux(T_996, T_977, T_995)
    node T_998 = eq(UInt<1>("h00"), req.p_type)
    node T_999 = mux(T_998, T_961, T_997)
    wire reply : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}
    reply is invalid
    reply.r_type <= T_999
    reply.client_xact_id <= UInt<1>("h00")
    reply.addr_block <= req.addr_block
    reply.addr_beat <= UInt<1>("h00")
    reply.data <= UInt<1>("h00")
    reply.voluntary <= UInt<1>("h00")
    node T_1061 = eq(state, UInt<1>("h00"))
    io.req.ready <= T_1061
    node T_1062 = eq(state, UInt<3>("h05"))
    io.rep.valid <= T_1062
    io.rep.bits <- reply
    node T_1064 = eq(io.rep.valid, UInt<1>("h00"))
    wire T_1066 : UInt<2>[3]
    T_1066[0] <= UInt<1>("h00")
    T_1066[1] <= UInt<1>("h01")
    T_1066[2] <= UInt<2>("h02")
    node T_1071 = eq(T_1066[0], io.rep.bits.r_type)
    node T_1072 = eq(T_1066[1], io.rep.bits.r_type)
    node T_1073 = eq(T_1066[2], io.rep.bits.r_type)
    node T_1075 = or(UInt<1>("h00"), T_1071)
    node T_1076 = or(T_1075, T_1072)
    node T_1077 = or(T_1076, T_1073)
    node T_1079 = eq(T_1077, UInt<1>("h00"))
    node T_1080 = or(T_1064, T_1079)
    node T_1082 = eq(reset, UInt<1>("h00"))
    when T_1082 :
      node T_1084 = eq(T_1080, UInt<1>("h00"))
      when T_1084 :
        node T_1086 = eq(reset, UInt<1>("h00"))
        when T_1086 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): ProbeUnit should not send releases with data")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    node T_1087 = eq(state, UInt<1>("h01"))
    io.meta_read.valid <= T_1087
    io.meta_read.bits.idx <= req.addr_block
    node T_1088 = shr(req.addr_block, 6)
    io.meta_read.bits.tag <= T_1088
    node T_1089 = eq(state, UInt<4>("h08"))
    io.meta_write.valid <= T_1089
    io.meta_write.bits.way_en <= way_en
    io.meta_write.bits.idx <= req.addr_block
    node T_1090 = shr(req.addr_block, 6)
    io.meta_write.bits.data.tag <= T_1090
    node T_1091 = eq(UInt<2>("h02"), req.p_type)
    node T_1092 = mux(T_1091, old_coh.state, old_coh.state)
    node T_1093 = eq(UInt<1>("h01"), req.p_type)
    node T_1094 = mux(T_1093, UInt<1>("h01"), T_1092)
    node T_1095 = eq(UInt<1>("h00"), req.p_type)
    node T_1096 = mux(T_1095, UInt<1>("h00"), T_1094)
    wire T_1122 : {state : UInt<2>}
    T_1122 is invalid
    T_1122.state <= T_1096
    io.meta_write.bits.data.coh <- T_1122
    node T_1147 = eq(state, UInt<3>("h06"))
    io.wb_req.valid <= T_1147
    io.wb_req.bits <- reply
    io.wb_req.bits.way_en <= way_en
    node T_1148 = and(io.req.ready, io.req.valid)
    when T_1148 :
      state <= UInt<1>("h01")
      req <- io.req.bits
      skip
    node T_1149 = and(io.meta_read.ready, io.meta_read.valid)
    when T_1149 :
      state <= UInt<2>("h02")
      skip
    node T_1150 = eq(state, UInt<2>("h02"))
    when T_1150 :
      state <= UInt<2>("h03")
      skip
    node T_1151 = eq(state, UInt<2>("h03"))
    when T_1151 :
      state <= UInt<3>("h04")
      old_coh <- io.block_state
      way_en <= io.way_en
      node T_1153 = eq(io.mshr_rdy, UInt<1>("h00"))
      when T_1153 :
        state <= UInt<1>("h01")
        skip
      skip
    node T_1154 = eq(state, UInt<3>("h04"))
    when T_1154 :
      wire T_1156 : UInt<2>[1]
      T_1156[0] <= UInt<2>("h03")
      node T_1159 = eq(T_1156[0], old_coh.state)
      node T_1161 = or(UInt<1>("h00"), T_1159)
      node T_1162 = and(tag_matches, T_1161)
      node T_1163 = mux(T_1162, UInt<3>("h06"), UInt<3>("h05"))
      state <= T_1163
      skip
    node T_1164 = eq(state, UInt<3>("h05"))
    node T_1165 = and(T_1164, io.rep.ready)
    when T_1165 :
      node T_1166 = mux(tag_matches, UInt<4>("h08"), UInt<1>("h00"))
      state <= T_1166
      skip
    node T_1167 = and(io.wb_req.ready, io.wb_req.valid)
    when T_1167 :
      state <= UInt<3>("h07")
      skip
    node T_1168 = eq(state, UInt<3>("h07"))
    node T_1169 = and(T_1168, io.wb_req.ready)
    when T_1169 :
      state <= UInt<4>("h08")
      skip
    node T_1170 = and(io.meta_write.ready, io.meta_write.valid)
    when T_1170 :
      state <= UInt<1>("h00")
      skip
    
  module Arbiter_93 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_108 : UInt<1>
    T_108 is invalid
    io.out.valid <= io.in[T_108].valid
    io.out.bits <- io.in[T_108].bits
    io.chosen <= T_108
    io.in[T_108].ready <= UInt<1>("h00")
    node T_139 = or(UInt<1>("h00"), io.in[0].valid)
    node T_141 = eq(T_139, UInt<1>("h00"))
    node T_143 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_144 = mux(UInt<1>("h00"), T_143, UInt<1>("h01"))
    node T_145 = and(T_144, io.out.ready)
    io.in[0].ready <= T_145
    node T_147 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_148 = mux(UInt<1>("h00"), T_147, T_141)
    node T_149 = and(T_148, io.out.ready)
    io.in[1].ready <= T_149
    node T_152 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_153 = mux(UInt<1>("h00"), UInt<1>("h01"), T_152)
    T_108 <= T_153
    
  module Arbiter_94 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, chosen : UInt<1>}
    
    io is invalid
    wire T_1714 : UInt<1>
    T_1714 is invalid
    io.out.valid <= io.in[T_1714].valid
    io.out.bits <- io.in[T_1714].bits
    io.chosen <= T_1714
    io.in[T_1714].ready <= UInt<1>("h00")
    node T_2183 = or(UInt<1>("h00"), io.in[0].valid)
    node T_2185 = eq(T_2183, UInt<1>("h00"))
    node T_2187 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2188 = mux(UInt<1>("h00"), T_2187, UInt<1>("h01"))
    node T_2189 = and(T_2188, io.out.ready)
    io.in[0].ready <= T_2189
    node T_2191 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_2192 = mux(UInt<1>("h00"), T_2191, T_2185)
    node T_2193 = and(T_2192, io.out.ready)
    io.in[1].ready <= T_2193
    node T_2196 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_2197 = mux(UInt<1>("h00"), UInt<1>("h01"), T_2196)
    T_1714 <= T_2197
    
  module LockingArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<2>}
    
    io is invalid
    reg T_852 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_854 : UInt, clk with : (reset => (reset, UInt<2>("h02")))
    wire T_856 : UInt<2>
    T_856 is invalid
    io.out.valid <= io.in[T_856].valid
    io.out.bits <- io.in[T_856].bits
    io.chosen <= T_856
    io.in[T_856].ready <= UInt<1>("h00")
    node T_1055 = or(UInt<1>("h00"), io.in[0].valid)
    node T_1057 = eq(T_1055, UInt<1>("h00"))
    node T_1059 = or(UInt<1>("h00"), io.in[0].valid)
    node T_1060 = or(T_1059, io.in[1].valid)
    node T_1062 = eq(T_1060, UInt<1>("h00"))
    node T_1064 = eq(T_854, UInt<1>("h00"))
    node T_1065 = mux(T_852, T_1064, UInt<1>("h01"))
    node T_1066 = and(T_1065, io.out.ready)
    io.in[0].ready <= T_1066
    node T_1068 = eq(T_854, UInt<1>("h01"))
    node T_1069 = mux(T_852, T_1068, T_1057)
    node T_1070 = and(T_1069, io.out.ready)
    io.in[1].ready <= T_1070
    node T_1072 = eq(T_854, UInt<2>("h02"))
    node T_1073 = mux(T_852, T_1072, T_1062)
    node T_1074 = and(T_1073, io.out.ready)
    io.in[2].ready <= T_1074
    reg T_1076 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_1078 = add(T_1076, UInt<1>("h01"))
    node T_1079 = tail(T_1078, 1)
    node T_1080 = and(io.out.ready, io.out.valid)
    when T_1080 :
      node T_1082 = and(UInt<1>("h01"), io.out.bits.is_builtin_type)
      wire T_1085 : UInt<3>[1]
      T_1085[0] <= UInt<3>("h03")
      node T_1088 = eq(T_1085[0], io.out.bits.a_type)
      node T_1090 = or(UInt<1>("h00"), T_1088)
      node T_1091 = and(T_1082, T_1090)
      when T_1091 :
        T_1076 <= T_1079
        node T_1093 = eq(T_852, UInt<1>("h00"))
        when T_1093 :
          T_852 <= UInt<1>("h01")
          node T_1095 = and(io.in[0].ready, io.in[0].valid)
          node T_1096 = and(io.in[1].ready, io.in[1].valid)
          node T_1097 = and(io.in[2].ready, io.in[2].valid)
          wire T_1099 : UInt<1>[3]
          T_1099[0] <= T_1095
          T_1099[1] <= T_1096
          T_1099[2] <= T_1097
          node T_1107 = mux(T_1099[1], UInt<1>("h01"), UInt<2>("h02"))
          node T_1108 = mux(T_1099[0], UInt<1>("h00"), T_1107)
          T_854 <= T_1108
          skip
        skip
      node T_1110 = eq(T_1079, UInt<1>("h00"))
      when T_1110 :
        T_852 <= UInt<1>("h00")
        skip
      skip
    node T_1114 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02"))
    node choose = mux(io.in[0].valid, UInt<1>("h00"), T_1114)
    node T_1117 = mux(T_852, T_854, choose)
    T_856 <= T_1117
    
  module Arbiter_95 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_724 : UInt<1>
    T_724 is invalid
    io.out.valid <= io.in[T_724].valid
    io.out.bits <- io.in[T_724].bits
    io.chosen <= T_724
    io.in[T_724].ready <= UInt<1>("h00")
    node T_923 = or(UInt<1>("h00"), io.in[0].valid)
    node T_925 = eq(T_923, UInt<1>("h00"))
    node T_927 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_928 = mux(UInt<1>("h00"), T_927, UInt<1>("h01"))
    node T_929 = and(T_928, io.out.ready)
    io.in[0].ready <= T_929
    node T_931 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_932 = mux(UInt<1>("h00"), T_931, T_925)
    node T_933 = and(T_932, io.out.ready)
    io.in[1].ready <= T_933
    node T_936 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_937 = mux(UInt<1>("h00"), UInt<1>("h01"), T_936)
    T_724 <= T_937
    
  module Arbiter_96 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_1230 : UInt<1>
    T_1230 is invalid
    io.out.valid <= io.in[T_1230].valid
    io.out.bits <- io.in[T_1230].bits
    io.chosen <= T_1230
    io.in[T_1230].ready <= UInt<1>("h00")
    node T_1567 = or(UInt<1>("h00"), io.in[0].valid)
    node T_1569 = eq(T_1567, UInt<1>("h00"))
    node T_1571 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_1572 = mux(UInt<1>("h00"), T_1571, UInt<1>("h01"))
    node T_1573 = and(T_1572, io.out.ready)
    io.in[0].ready <= T_1573
    node T_1575 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_1576 = mux(UInt<1>("h00"), T_1575, T_1569)
    node T_1577 = and(T_1576, io.out.ready)
    io.in[1].ready <= T_1577
    node T_1580 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_1581 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1580)
    T_1230 <= T_1581
    
  module Arbiter_97 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>}
    
    io is invalid
    wire T_64 : UInt<1>
    T_64 is invalid
    io.out.valid <= io.in[T_64].valid
    io.out.bits <= io.in[T_64].bits
    io.chosen <= T_64
    io.in[T_64].ready <= UInt<1>("h00")
    node T_83 = or(UInt<1>("h00"), io.in[0].valid)
    node T_85 = eq(T_83, UInt<1>("h00"))
    node T_87 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_88 = mux(UInt<1>("h00"), T_87, UInt<1>("h01"))
    node T_89 = and(T_88, io.out.ready)
    io.in[0].ready <= T_89
    node T_91 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_92 = mux(UInt<1>("h00"), T_91, T_85)
    node T_93 = and(T_92, io.out.ready)
    io.in[1].ready <= T_93
    node T_96 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_97 = mux(UInt<1>("h00"), UInt<1>("h01"), T_96)
    T_64 <= T_97
    
  module Queue_98 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, count : UInt<5>}
    
    io is invalid
    cmem ram : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16]
    reg T_503 : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    reg T_505 : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_503, T_505)
    node T_510 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_510)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_516 = and(io.enq.ready, io.enq.valid)
    node T_518 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_516, T_518)
    node T_520 = and(io.deq.ready, io.deq.valid)
    node T_522 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_520, T_522)
    when do_enq :
      infer mport T_524 = ram[T_503], clk
      T_524 <- io.enq.bits
      node T_579 = eq(T_503, UInt<4>("h0f"))
      node T_581 = and(UInt<1>("h00"), T_579)
      node T_584 = add(T_503, UInt<1>("h01"))
      node T_585 = tail(T_584, 1)
      node T_586 = mux(T_581, UInt<1>("h00"), T_585)
      T_503 <= T_586
      skip
    when do_deq :
      node T_588 = eq(T_505, UInt<4>("h0f"))
      node T_590 = and(UInt<1>("h00"), T_588)
      node T_593 = add(T_505, UInt<1>("h01"))
      node T_594 = tail(T_593, 1)
      node T_595 = mux(T_590, UInt<1>("h00"), T_594)
      T_505 <= T_595
      skip
    node T_596 = neq(do_enq, do_deq)
    when T_596 :
      maybe_full <= do_enq
      skip
    node T_598 = eq(empty, UInt<1>("h00"))
    node T_600 = and(UInt<1>("h00"), io.enq.valid)
    node T_601 = or(T_598, T_600)
    io.deq.valid <= T_601
    node T_603 = eq(full, UInt<1>("h00"))
    node T_605 = and(UInt<1>("h00"), io.deq.ready)
    node T_606 = or(T_603, T_605)
    io.enq.ready <= T_606
    infer mport T_607 = ram[T_505], clk
    node T_661 = mux(maybe_flow, io.enq.bits, T_607)
    io.deq.bits <- T_661
    node T_715 = sub(T_503, T_505)
    node ptr_diff = tail(T_715, 1)
    node T_717 = and(maybe_full, ptr_match)
    node T_718 = cat(T_717, ptr_diff)
    io.count <= T_718
    
  module MSHR : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_1277 : {state : UInt<2>}
    T_1277 is invalid
    T_1277.state <= UInt<1>("h00")
    reg new_coh_state : {state : UInt<2>}, clk with : (reset => (reset, T_1277))
    reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk
    node req_idx = bits(req.addr, 11, 6)
    node T_1586 = bits(io.req_bits.addr, 11, 6)
    node idx_match = eq(req_idx, T_1586)
    node T_1588 = eq(io.req_bits.cmd, UInt<5>("h01"))
    node T_1589 = eq(io.req_bits.cmd, UInt<5>("h07"))
    node T_1590 = or(T_1588, T_1589)
    node T_1591 = bits(io.req_bits.cmd, 3, 3)
    node T_1592 = eq(io.req_bits.cmd, UInt<5>("h04"))
    node T_1593 = or(T_1591, T_1592)
    node T_1594 = or(T_1590, T_1593)
    node T_1595 = eq(io.req_bits.cmd, UInt<5>("h03"))
    node T_1596 = or(T_1594, T_1595)
    node T_1597 = eq(io.req_bits.cmd, UInt<5>("h06"))
    node T_1598 = or(T_1596, T_1597)
    node T_1599 = eq(req.cmd, UInt<5>("h01"))
    node T_1600 = eq(req.cmd, UInt<5>("h07"))
    node T_1601 = or(T_1599, T_1600)
    node T_1602 = bits(req.cmd, 3, 3)
    node T_1603 = eq(req.cmd, UInt<5>("h04"))
    node T_1604 = or(T_1602, T_1603)
    node T_1605 = or(T_1601, T_1604)
    node T_1606 = eq(req.cmd, UInt<5>("h03"))
    node T_1607 = or(T_1605, T_1606)
    node T_1608 = eq(req.cmd, UInt<5>("h06"))
    node T_1609 = or(T_1607, T_1608)
    node T_1611 = eq(T_1609, UInt<1>("h00"))
    node cmd_requires_second_acquire = and(T_1598, T_1611)
    wire states_before_refill : UInt<2>[3]
    states_before_refill[0] <= UInt<1>("h01")
    states_before_refill[1] <= UInt<2>("h02")
    states_before_refill[2] <= UInt<2>("h03")
    node T_1619 = eq(states_before_refill[0], state)
    node T_1620 = eq(states_before_refill[1], state)
    node T_1621 = eq(states_before_refill[2], state)
    node T_1623 = or(UInt<1>("h00"), T_1619)
    node T_1624 = or(T_1623, T_1620)
    node T_1625 = or(T_1624, T_1621)
    wire T_1627 : UInt<3>[2]
    T_1627[0] <= UInt<3>("h04")
    T_1627[1] <= UInt<3>("h05")
    node T_1631 = eq(T_1627[0], state)
    node T_1632 = eq(T_1627[1], state)
    node T_1634 = or(UInt<1>("h00"), T_1631)
    node T_1635 = or(T_1634, T_1632)
    node T_1637 = eq(cmd_requires_second_acquire, UInt<1>("h00"))
    node T_1638 = and(T_1635, T_1637)
    node T_1639 = or(T_1625, T_1638)
    node sec_rdy = and(idx_match, T_1639)
    wire T_1644 : UInt<3>[1]
    T_1644[0] <= UInt<3>("h05")
    node T_1647 = eq(T_1644[0], io.mem_grant.bits.g_type)
    node T_1649 = or(UInt<1>("h00"), T_1647)
    wire T_1651 : UInt<1>[2]
    T_1651[0] <= UInt<1>("h00")
    T_1651[1] <= UInt<1>("h01")
    node T_1655 = eq(T_1651[0], io.mem_grant.bits.g_type)
    node T_1656 = eq(T_1651[1], io.mem_grant.bits.g_type)
    node T_1658 = or(UInt<1>("h00"), T_1655)
    node T_1659 = or(T_1658, T_1656)
    node T_1660 = mux(io.mem_grant.bits.is_builtin_type, T_1649, T_1659)
    node gnt_multi_data = and(UInt<1>("h01"), T_1660)
    node T_1662 = and(io.mem_grant.valid, gnt_multi_data)
    reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_1662 :
      node T_1666 = eq(refill_cnt, UInt<2>("h03"))
      node T_1668 = and(UInt<1>("h00"), T_1666)
      node T_1671 = add(refill_cnt, UInt<1>("h01"))
      node T_1672 = tail(T_1671, 1)
      node T_1673 = mux(T_1668, UInt<1>("h00"), T_1672)
      refill_cnt <= T_1673
      skip
    node refill_count_done = and(T_1662, T_1666)
    node T_1676 = eq(gnt_multi_data, UInt<1>("h00"))
    node T_1677 = or(T_1676, refill_count_done)
    node refill_done = and(io.mem_grant.valid, T_1677)
    inst rpq of Queue_98
    rpq.io is invalid
    rpq.clk <= clk
    rpq.reset <= reset
    node T_1734 = and(io.req_pri_val, io.req_pri_rdy)
    node T_1735 = and(io.req_sec_val, sec_rdy)
    node T_1736 = or(T_1734, T_1735)
    node T_1737 = eq(io.req_bits.cmd, UInt<5>("h02"))
    node T_1738 = eq(io.req_bits.cmd, UInt<5>("h03"))
    node T_1739 = or(T_1737, T_1738)
    node T_1741 = eq(T_1739, UInt<1>("h00"))
    node T_1742 = and(T_1736, T_1741)
    rpq.io.enq.valid <= T_1742
    rpq.io.enq.bits <- io.req_bits
    node T_1743 = eq(state, UInt<4>("h08"))
    node T_1744 = and(io.replay.ready, T_1743)
    node T_1745 = eq(state, UInt<1>("h00"))
    node T_1746 = or(T_1744, T_1745)
    rpq.io.deq.ready <= T_1746
    node T_1747 = eq(req.cmd, UInt<5>("h01"))
    node T_1748 = eq(req.cmd, UInt<5>("h07"))
    node T_1749 = or(T_1747, T_1748)
    node T_1750 = bits(req.cmd, 3, 3)
    node T_1751 = eq(req.cmd, UInt<5>("h04"))
    node T_1752 = or(T_1750, T_1751)
    node T_1753 = or(T_1749, T_1752)
    node T_1754 = mux(T_1753, UInt<2>("h03"), UInt<2>("h02"))
    node T_1755 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type)
    node T_1756 = mux(T_1755, UInt<2>("h03"), UInt<1>("h00"))
    node T_1757 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type)
    node T_1758 = mux(T_1757, T_1754, T_1756)
    node T_1759 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type)
    node T_1760 = mux(T_1759, UInt<1>("h01"), T_1758)
    node T_1761 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1760)
    wire coh_on_grant : {state : UInt<2>}
    coh_on_grant is invalid
    coh_on_grant.state <= T_1761
    node T_1812 = eq(io.req_bits.cmd, UInt<5>("h01"))
    node T_1813 = eq(io.req_bits.cmd, UInt<5>("h07"))
    node T_1814 = or(T_1812, T_1813)
    node T_1815 = bits(io.req_bits.cmd, 3, 3)
    node T_1816 = eq(io.req_bits.cmd, UInt<5>("h04"))
    node T_1817 = or(T_1815, T_1816)
    node T_1818 = or(T_1814, T_1817)
    node T_1819 = mux(T_1818, UInt<2>("h03"), io.req_bits.old_meta.coh.state)
    wire coh_on_hit : {state : UInt<2>}
    coh_on_hit is invalid
    coh_on_hit.state <= T_1819
    node T_1870 = eq(state, UInt<4>("h08"))
    node T_1872 = eq(rpq.io.deq.valid, UInt<1>("h00"))
    node T_1873 = and(T_1870, T_1872)
    when T_1873 :
      state <= UInt<1>("h00")
      skip
    node T_1874 = eq(state, UInt<3>("h07"))
    when T_1874 :
      state <= UInt<4>("h08")
      skip
    node T_1875 = eq(state, UInt<3>("h06"))
    node T_1876 = and(T_1875, io.meta_write.ready)
    when T_1876 :
      state <= UInt<3>("h07")
      skip
    node T_1877 = eq(state, UInt<3>("h05"))
    when T_1877 :
      when io.mem_grant.valid :
        new_coh_state <- coh_on_grant
        skip
      when refill_done :
        state <= UInt<3>("h06")
        skip
      skip
    node T_1878 = and(io.mem_req.ready, io.mem_req.valid)
    when T_1878 :
      state <= UInt<3>("h05")
      skip
    node T_1879 = eq(state, UInt<2>("h03"))
    node T_1880 = and(T_1879, io.meta_write.ready)
    when T_1880 :
      state <= UInt<3>("h04")
      skip
    node T_1881 = eq(state, UInt<2>("h02"))
    node T_1882 = and(T_1881, io.mem_grant.valid)
    when T_1882 :
      state <= UInt<2>("h03")
      skip
    node T_1883 = and(io.wb_req.ready, io.wb_req.valid)
    when T_1883 :
      node T_1886 = eq(UInt<1>("h00"), UInt<1>("h00"))
      node T_1887 = mux(T_1886, UInt<2>("h02"), UInt<2>("h03"))
      state <= T_1887
      skip
    node T_1888 = and(io.req_sec_val, io.req_sec_rdy)
    when T_1888 :
      when cmd_requires_second_acquire :
        req.cmd <= io.req_bits.cmd
        skip
      skip
    node T_1889 = and(io.req_pri_val, io.req_pri_rdy)
    when T_1889 :
      req <- io.req_bits
      when io.req_bits.tag_match :
        node T_1890 = eq(io.req_bits.cmd, UInt<5>("h01"))
        node T_1891 = eq(io.req_bits.cmd, UInt<5>("h07"))
        node T_1892 = or(T_1890, T_1891)
        node T_1893 = bits(io.req_bits.cmd, 3, 3)
        node T_1894 = eq(io.req_bits.cmd, UInt<5>("h04"))
        node T_1895 = or(T_1893, T_1894)
        node T_1896 = or(T_1892, T_1895)
        node T_1897 = eq(io.req_bits.cmd, UInt<5>("h03"))
        node T_1898 = or(T_1896, T_1897)
        node T_1899 = eq(io.req_bits.cmd, UInt<5>("h06"))
        node T_1900 = or(T_1898, T_1899)
        wire T_1902 : UInt<2>[2]
        T_1902[0] <= UInt<2>("h02")
        T_1902[1] <= UInt<2>("h03")
        node T_1906 = eq(T_1902[0], io.req_bits.old_meta.coh.state)
        node T_1907 = eq(T_1902[1], io.req_bits.old_meta.coh.state)
        node T_1909 = or(UInt<1>("h00"), T_1906)
        node T_1910 = or(T_1909, T_1907)
        wire T_1912 : UInt<2>[3]
        T_1912[0] <= UInt<1>("h01")
        T_1912[1] <= UInt<2>("h02")
        T_1912[2] <= UInt<2>("h03")
        node T_1917 = eq(T_1912[0], io.req_bits.old_meta.coh.state)
        node T_1918 = eq(T_1912[1], io.req_bits.old_meta.coh.state)
        node T_1919 = eq(T_1912[2], io.req_bits.old_meta.coh.state)
        node T_1921 = or(UInt<1>("h00"), T_1917)
        node T_1922 = or(T_1921, T_1918)
        node T_1923 = or(T_1922, T_1919)
        node T_1924 = mux(T_1900, T_1910, T_1923)
        when T_1924 :
          state <= UInt<3>("h06")
          new_coh_state <- coh_on_hit
          skip
        node T_1926 = eq(T_1924, UInt<1>("h00"))
        when T_1926 :
          state <= UInt<3>("h04")
          skip
        skip
      node T_1928 = eq(io.req_bits.tag_match, UInt<1>("h00"))
      when T_1928 :
        wire T_1930 : UInt<2>[1]
        T_1930[0] <= UInt<2>("h03")
        node T_1933 = eq(T_1930[0], io.req_bits.old_meta.coh.state)
        node T_1935 = or(UInt<1>("h00"), T_1933)
        node T_1936 = mux(T_1935, UInt<1>("h01"), UInt<2>("h03"))
        state <= T_1936
        skip
      skip
    node T_1937 = neq(state, UInt<1>("h00"))
    node T_1938 = and(T_1937, idx_match)
    io.idx_match <= T_1938
    io.refill.way_en <= req.way_en
    node T_1939 = cat(req_idx, refill_cnt)
    node T_1940 = shl(T_1939, 4)
    io.refill.addr <= T_1940
    node T_1941 = shr(req.addr, 12)
    io.tag <= T_1941
    node T_1942 = eq(state, UInt<1>("h00"))
    io.req_pri_rdy <= T_1942
    node T_1943 = and(sec_rdy, rpq.io.enq.ready)
    io.req_sec_rdy <= T_1943
    reg meta_hazard : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_1947 = neq(meta_hazard, UInt<1>("h00"))
    when T_1947 :
      node T_1949 = add(meta_hazard, UInt<1>("h01"))
      node T_1950 = tail(T_1949, 1)
      meta_hazard <= T_1950
      skip
    node T_1951 = and(io.meta_write.ready, io.meta_write.valid)
    when T_1951 :
      meta_hazard <= UInt<1>("h01")
      skip
    node T_1954 = eq(idx_match, UInt<1>("h00"))
    node T_1955 = eq(states_before_refill[0], state)
    node T_1956 = eq(states_before_refill[1], state)
    node T_1957 = eq(states_before_refill[2], state)
    node T_1959 = or(UInt<1>("h00"), T_1955)
    node T_1960 = or(T_1959, T_1956)
    node T_1961 = or(T_1960, T_1957)
    node T_1963 = eq(T_1961, UInt<1>("h00"))
    node T_1965 = eq(meta_hazard, UInt<1>("h00"))
    node T_1966 = and(T_1963, T_1965)
    node T_1967 = or(T_1954, T_1966)
    io.probe_rdy <= T_1967
    node T_1968 = eq(state, UInt<3>("h06"))
    node T_1969 = eq(state, UInt<2>("h03"))
    node T_1970 = or(T_1968, T_1969)
    io.meta_write.valid <= T_1970
    io.meta_write.bits.idx <= req_idx
    node T_1971 = eq(state, UInt<2>("h03"))
    wire T_1973 : UInt<2>[2]
    T_1973[0] <= UInt<2>("h02")
    T_1973[1] <= UInt<2>("h03")
    node T_1977 = eq(T_1973[0], req.old_meta.coh.state)
    node T_1978 = eq(T_1973[1], req.old_meta.coh.state)
    node T_1980 = or(UInt<1>("h00"), T_1977)
    node T_1981 = or(T_1980, T_1978)
    node T_1982 = mux(T_1981, UInt<1>("h01"), req.old_meta.coh.state)
    node T_1983 = eq(req.old_meta.coh.state, UInt<2>("h03"))
    node T_1984 = mux(T_1983, UInt<2>("h02"), req.old_meta.coh.state)
    node T_1985 = eq(UInt<5>("h013"), UInt<5>("h010"))
    node T_1986 = mux(T_1985, T_1984, req.old_meta.coh.state)
    node T_1987 = eq(UInt<5>("h011"), UInt<5>("h010"))
    node T_1988 = mux(T_1987, T_1982, T_1986)
    node T_1989 = eq(UInt<5>("h010"), UInt<5>("h010"))
    node T_1990 = mux(T_1989, UInt<1>("h00"), T_1988)
    wire T_2016 : {state : UInt<2>}
    T_2016 is invalid
    T_2016.state <= T_1990
    node T_2041 = mux(T_1971, T_2016, new_coh_state)
    io.meta_write.bits.data.coh <- T_2041
    io.meta_write.bits.data.tag <= io.tag
    io.meta_write.bits.way_en <= req.way_en
    node T_2066 = eq(state, UInt<1>("h01"))
    io.wb_req.valid <= T_2066
    node T_2068 = cat(req.old_meta.tag, req_idx)
    wire T_2073 : UInt<2>[1]
    T_2073[0] <= UInt<2>("h03")
    node T_2076 = eq(T_2073[0], req.old_meta.coh.state)
    node T_2078 = or(UInt<1>("h00"), T_2076)
    node T_2079 = mux(T_2078, UInt<1>("h00"), UInt<2>("h03"))
    node T_2080 = mux(T_2078, UInt<1>("h01"), UInt<3>("h04"))
    node T_2081 = mux(T_2078, UInt<2>("h02"), UInt<3>("h05"))
    node T_2082 = eq(UInt<5>("h013"), UInt<5>("h010"))
    node T_2083 = mux(T_2082, T_2081, UInt<3>("h05"))
    node T_2084 = eq(UInt<5>("h011"), UInt<5>("h010"))
    node T_2085 = mux(T_2084, T_2080, T_2083)
    node T_2086 = eq(UInt<5>("h010"), UInt<5>("h010"))
    node T_2087 = mux(T_2086, T_2079, T_2085)
    wire T_2118 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}
    T_2118 is invalid
    T_2118.r_type <= T_2087
    T_2118.client_xact_id <= UInt<1>("h00")
    T_2118.addr_block <= T_2068
    T_2118.addr_beat <= UInt<1>("h00")
    T_2118.data <= UInt<1>("h00")
    T_2118.voluntary <= UInt<1>("h01")
    io.wb_req.bits <- T_2118
    io.wb_req.bits.way_en <= req.way_en
    node T_2148 = eq(state, UInt<3>("h04"))
    io.mem_req.valid <= T_2148
    node T_2149 = cat(io.tag, req_idx)
    node T_2152 = eq(req.cmd, UInt<5>("h01"))
    node T_2153 = eq(req.cmd, UInt<5>("h07"))
    node T_2154 = or(T_2152, T_2153)
    node T_2155 = bits(req.cmd, 3, 3)
    node T_2156 = eq(req.cmd, UInt<5>("h04"))
    node T_2157 = or(T_2155, T_2156)
    node T_2158 = or(T_2154, T_2157)
    node T_2159 = eq(req.cmd, UInt<5>("h03"))
    node T_2160 = or(T_2158, T_2159)
    node T_2161 = eq(req.cmd, UInt<5>("h06"))
    node T_2162 = or(T_2160, T_2161)
    node T_2163 = mux(T_2162, UInt<1>("h01"), UInt<1>("h00"))
    node T_2165 = cat(req.cmd, UInt<1>("h01"))
    wire T_2199 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    T_2199 is invalid
    T_2199.is_builtin_type <= UInt<1>("h00")
    T_2199.a_type <= T_2163
    T_2199.client_xact_id <= UInt<1>("h00")
    T_2199.addr_block <= T_2149
    T_2199.addr_beat <= UInt<1>("h00")
    T_2199.data <= UInt<1>("h00")
    T_2199.union <= T_2165
    io.mem_req.bits <- T_2199
    node T_2230 = eq(state, UInt<4>("h08"))
    io.meta_read.valid <= T_2230
    io.meta_read.bits.idx <= req_idx
    io.meta_read.bits.tag <= io.tag
    node T_2231 = eq(state, UInt<4>("h08"))
    node T_2232 = and(T_2231, rpq.io.deq.valid)
    io.replay.valid <= T_2232
    io.replay.bits <- rpq.io.deq.bits
    io.replay.bits.phys <= UInt<1>("h01")
    node T_2234 = bits(rpq.io.deq.bits.addr, 5, 0)
    node T_2235 = cat(req_idx, T_2234)
    node T_2236 = cat(io.tag, T_2235)
    io.replay.bits.addr <= T_2236
    node T_2238 = eq(io.meta_read.ready, UInt<1>("h00"))
    when T_2238 :
      rpq.io.deq.ready <= UInt<1>("h00")
      io.replay.bits.cmd <= UInt<5>("h05")
      skip
    
  module MSHR_99 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    wire T_1277 : {state : UInt<2>}
    T_1277 is invalid
    T_1277.state <= UInt<1>("h00")
    reg new_coh_state : {state : UInt<2>}, clk with : (reset => (reset, T_1277))
    reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk
    node req_idx = bits(req.addr, 11, 6)
    node T_1586 = bits(io.req_bits.addr, 11, 6)
    node idx_match = eq(req_idx, T_1586)
    node T_1588 = eq(io.req_bits.cmd, UInt<5>("h01"))
    node T_1589 = eq(io.req_bits.cmd, UInt<5>("h07"))
    node T_1590 = or(T_1588, T_1589)
    node T_1591 = bits(io.req_bits.cmd, 3, 3)
    node T_1592 = eq(io.req_bits.cmd, UInt<5>("h04"))
    node T_1593 = or(T_1591, T_1592)
    node T_1594 = or(T_1590, T_1593)
    node T_1595 = eq(io.req_bits.cmd, UInt<5>("h03"))
    node T_1596 = or(T_1594, T_1595)
    node T_1597 = eq(io.req_bits.cmd, UInt<5>("h06"))
    node T_1598 = or(T_1596, T_1597)
    node T_1599 = eq(req.cmd, UInt<5>("h01"))
    node T_1600 = eq(req.cmd, UInt<5>("h07"))
    node T_1601 = or(T_1599, T_1600)
    node T_1602 = bits(req.cmd, 3, 3)
    node T_1603 = eq(req.cmd, UInt<5>("h04"))
    node T_1604 = or(T_1602, T_1603)
    node T_1605 = or(T_1601, T_1604)
    node T_1606 = eq(req.cmd, UInt<5>("h03"))
    node T_1607 = or(T_1605, T_1606)
    node T_1608 = eq(req.cmd, UInt<5>("h06"))
    node T_1609 = or(T_1607, T_1608)
    node T_1611 = eq(T_1609, UInt<1>("h00"))
    node cmd_requires_second_acquire = and(T_1598, T_1611)
    wire states_before_refill : UInt<2>[3]
    states_before_refill[0] <= UInt<1>("h01")
    states_before_refill[1] <= UInt<2>("h02")
    states_before_refill[2] <= UInt<2>("h03")
    node T_1619 = eq(states_before_refill[0], state)
    node T_1620 = eq(states_before_refill[1], state)
    node T_1621 = eq(states_before_refill[2], state)
    node T_1623 = or(UInt<1>("h00"), T_1619)
    node T_1624 = or(T_1623, T_1620)
    node T_1625 = or(T_1624, T_1621)
    wire T_1627 : UInt<3>[2]
    T_1627[0] <= UInt<3>("h04")
    T_1627[1] <= UInt<3>("h05")
    node T_1631 = eq(T_1627[0], state)
    node T_1632 = eq(T_1627[1], state)
    node T_1634 = or(UInt<1>("h00"), T_1631)
    node T_1635 = or(T_1634, T_1632)
    node T_1637 = eq(cmd_requires_second_acquire, UInt<1>("h00"))
    node T_1638 = and(T_1635, T_1637)
    node T_1639 = or(T_1625, T_1638)
    node sec_rdy = and(idx_match, T_1639)
    wire T_1644 : UInt<3>[1]
    T_1644[0] <= UInt<3>("h05")
    node T_1647 = eq(T_1644[0], io.mem_grant.bits.g_type)
    node T_1649 = or(UInt<1>("h00"), T_1647)
    wire T_1651 : UInt<1>[2]
    T_1651[0] <= UInt<1>("h00")
    T_1651[1] <= UInt<1>("h01")
    node T_1655 = eq(T_1651[0], io.mem_grant.bits.g_type)
    node T_1656 = eq(T_1651[1], io.mem_grant.bits.g_type)
    node T_1658 = or(UInt<1>("h00"), T_1655)
    node T_1659 = or(T_1658, T_1656)
    node T_1660 = mux(io.mem_grant.bits.is_builtin_type, T_1649, T_1659)
    node gnt_multi_data = and(UInt<1>("h01"), T_1660)
    node T_1662 = and(io.mem_grant.valid, gnt_multi_data)
    reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    when T_1662 :
      node T_1666 = eq(refill_cnt, UInt<2>("h03"))
      node T_1668 = and(UInt<1>("h00"), T_1666)
      node T_1671 = add(refill_cnt, UInt<1>("h01"))
      node T_1672 = tail(T_1671, 1)
      node T_1673 = mux(T_1668, UInt<1>("h00"), T_1672)
      refill_cnt <= T_1673
      skip
    node refill_count_done = and(T_1662, T_1666)
    node T_1676 = eq(gnt_multi_data, UInt<1>("h00"))
    node T_1677 = or(T_1676, refill_count_done)
    node refill_done = and(io.mem_grant.valid, T_1677)
    inst rpq of Queue_98
    rpq.io is invalid
    rpq.clk <= clk
    rpq.reset <= reset
    node T_1734 = and(io.req_pri_val, io.req_pri_rdy)
    node T_1735 = and(io.req_sec_val, sec_rdy)
    node T_1736 = or(T_1734, T_1735)
    node T_1737 = eq(io.req_bits.cmd, UInt<5>("h02"))
    node T_1738 = eq(io.req_bits.cmd, UInt<5>("h03"))
    node T_1739 = or(T_1737, T_1738)
    node T_1741 = eq(T_1739, UInt<1>("h00"))
    node T_1742 = and(T_1736, T_1741)
    rpq.io.enq.valid <= T_1742
    rpq.io.enq.bits <- io.req_bits
    node T_1743 = eq(state, UInt<4>("h08"))
    node T_1744 = and(io.replay.ready, T_1743)
    node T_1745 = eq(state, UInt<1>("h00"))
    node T_1746 = or(T_1744, T_1745)
    rpq.io.deq.ready <= T_1746
    node T_1747 = eq(req.cmd, UInt<5>("h01"))
    node T_1748 = eq(req.cmd, UInt<5>("h07"))
    node T_1749 = or(T_1747, T_1748)
    node T_1750 = bits(req.cmd, 3, 3)
    node T_1751 = eq(req.cmd, UInt<5>("h04"))
    node T_1752 = or(T_1750, T_1751)
    node T_1753 = or(T_1749, T_1752)
    node T_1754 = mux(T_1753, UInt<2>("h03"), UInt<2>("h02"))
    node T_1755 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type)
    node T_1756 = mux(T_1755, UInt<2>("h03"), UInt<1>("h00"))
    node T_1757 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type)
    node T_1758 = mux(T_1757, T_1754, T_1756)
    node T_1759 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type)
    node T_1760 = mux(T_1759, UInt<1>("h01"), T_1758)
    node T_1761 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1760)
    wire coh_on_grant : {state : UInt<2>}
    coh_on_grant is invalid
    coh_on_grant.state <= T_1761
    node T_1812 = eq(io.req_bits.cmd, UInt<5>("h01"))
    node T_1813 = eq(io.req_bits.cmd, UInt<5>("h07"))
    node T_1814 = or(T_1812, T_1813)
    node T_1815 = bits(io.req_bits.cmd, 3, 3)
    node T_1816 = eq(io.req_bits.cmd, UInt<5>("h04"))
    node T_1817 = or(T_1815, T_1816)
    node T_1818 = or(T_1814, T_1817)
    node T_1819 = mux(T_1818, UInt<2>("h03"), io.req_bits.old_meta.coh.state)
    wire coh_on_hit : {state : UInt<2>}
    coh_on_hit is invalid
    coh_on_hit.state <= T_1819
    node T_1870 = eq(state, UInt<4>("h08"))
    node T_1872 = eq(rpq.io.deq.valid, UInt<1>("h00"))
    node T_1873 = and(T_1870, T_1872)
    when T_1873 :
      state <= UInt<1>("h00")
      skip
    node T_1874 = eq(state, UInt<3>("h07"))
    when T_1874 :
      state <= UInt<4>("h08")
      skip
    node T_1875 = eq(state, UInt<3>("h06"))
    node T_1876 = and(T_1875, io.meta_write.ready)
    when T_1876 :
      state <= UInt<3>("h07")
      skip
    node T_1877 = eq(state, UInt<3>("h05"))
    when T_1877 :
      when io.mem_grant.valid :
        new_coh_state <- coh_on_grant
        skip
      when refill_done :
        state <= UInt<3>("h06")
        skip
      skip
    node T_1878 = and(io.mem_req.ready, io.mem_req.valid)
    when T_1878 :
      state <= UInt<3>("h05")
      skip
    node T_1879 = eq(state, UInt<2>("h03"))
    node T_1880 = and(T_1879, io.meta_write.ready)
    when T_1880 :
      state <= UInt<3>("h04")
      skip
    node T_1881 = eq(state, UInt<2>("h02"))
    node T_1882 = and(T_1881, io.mem_grant.valid)
    when T_1882 :
      state <= UInt<2>("h03")
      skip
    node T_1883 = and(io.wb_req.ready, io.wb_req.valid)
    when T_1883 :
      node T_1886 = eq(UInt<1>("h00"), UInt<1>("h00"))
      node T_1887 = mux(T_1886, UInt<2>("h02"), UInt<2>("h03"))
      state <= T_1887
      skip
    node T_1888 = and(io.req_sec_val, io.req_sec_rdy)
    when T_1888 :
      when cmd_requires_second_acquire :
        req.cmd <= io.req_bits.cmd
        skip
      skip
    node T_1889 = and(io.req_pri_val, io.req_pri_rdy)
    when T_1889 :
      req <- io.req_bits
      when io.req_bits.tag_match :
        node T_1890 = eq(io.req_bits.cmd, UInt<5>("h01"))
        node T_1891 = eq(io.req_bits.cmd, UInt<5>("h07"))
        node T_1892 = or(T_1890, T_1891)
        node T_1893 = bits(io.req_bits.cmd, 3, 3)
        node T_1894 = eq(io.req_bits.cmd, UInt<5>("h04"))
        node T_1895 = or(T_1893, T_1894)
        node T_1896 = or(T_1892, T_1895)
        node T_1897 = eq(io.req_bits.cmd, UInt<5>("h03"))
        node T_1898 = or(T_1896, T_1897)
        node T_1899 = eq(io.req_bits.cmd, UInt<5>("h06"))
        node T_1900 = or(T_1898, T_1899)
        wire T_1902 : UInt<2>[2]
        T_1902[0] <= UInt<2>("h02")
        T_1902[1] <= UInt<2>("h03")
        node T_1906 = eq(T_1902[0], io.req_bits.old_meta.coh.state)
        node T_1907 = eq(T_1902[1], io.req_bits.old_meta.coh.state)
        node T_1909 = or(UInt<1>("h00"), T_1906)
        node T_1910 = or(T_1909, T_1907)
        wire T_1912 : UInt<2>[3]
        T_1912[0] <= UInt<1>("h01")
        T_1912[1] <= UInt<2>("h02")
        T_1912[2] <= UInt<2>("h03")
        node T_1917 = eq(T_1912[0], io.req_bits.old_meta.coh.state)
        node T_1918 = eq(T_1912[1], io.req_bits.old_meta.coh.state)
        node T_1919 = eq(T_1912[2], io.req_bits.old_meta.coh.state)
        node T_1921 = or(UInt<1>("h00"), T_1917)
        node T_1922 = or(T_1921, T_1918)
        node T_1923 = or(T_1922, T_1919)
        node T_1924 = mux(T_1900, T_1910, T_1923)
        when T_1924 :
          state <= UInt<3>("h06")
          new_coh_state <- coh_on_hit
          skip
        node T_1926 = eq(T_1924, UInt<1>("h00"))
        when T_1926 :
          state <= UInt<3>("h04")
          skip
        skip
      node T_1928 = eq(io.req_bits.tag_match, UInt<1>("h00"))
      when T_1928 :
        wire T_1930 : UInt<2>[1]
        T_1930[0] <= UInt<2>("h03")
        node T_1933 = eq(T_1930[0], io.req_bits.old_meta.coh.state)
        node T_1935 = or(UInt<1>("h00"), T_1933)
        node T_1936 = mux(T_1935, UInt<1>("h01"), UInt<2>("h03"))
        state <= T_1936
        skip
      skip
    node T_1937 = neq(state, UInt<1>("h00"))
    node T_1938 = and(T_1937, idx_match)
    io.idx_match <= T_1938
    io.refill.way_en <= req.way_en
    node T_1939 = cat(req_idx, refill_cnt)
    node T_1940 = shl(T_1939, 4)
    io.refill.addr <= T_1940
    node T_1941 = shr(req.addr, 12)
    io.tag <= T_1941
    node T_1942 = eq(state, UInt<1>("h00"))
    io.req_pri_rdy <= T_1942
    node T_1943 = and(sec_rdy, rpq.io.enq.ready)
    io.req_sec_rdy <= T_1943
    reg meta_hazard : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_1947 = neq(meta_hazard, UInt<1>("h00"))
    when T_1947 :
      node T_1949 = add(meta_hazard, UInt<1>("h01"))
      node T_1950 = tail(T_1949, 1)
      meta_hazard <= T_1950
      skip
    node T_1951 = and(io.meta_write.ready, io.meta_write.valid)
    when T_1951 :
      meta_hazard <= UInt<1>("h01")
      skip
    node T_1954 = eq(idx_match, UInt<1>("h00"))
    node T_1955 = eq(states_before_refill[0], state)
    node T_1956 = eq(states_before_refill[1], state)
    node T_1957 = eq(states_before_refill[2], state)
    node T_1959 = or(UInt<1>("h00"), T_1955)
    node T_1960 = or(T_1959, T_1956)
    node T_1961 = or(T_1960, T_1957)
    node T_1963 = eq(T_1961, UInt<1>("h00"))
    node T_1965 = eq(meta_hazard, UInt<1>("h00"))
    node T_1966 = and(T_1963, T_1965)
    node T_1967 = or(T_1954, T_1966)
    io.probe_rdy <= T_1967
    node T_1968 = eq(state, UInt<3>("h06"))
    node T_1969 = eq(state, UInt<2>("h03"))
    node T_1970 = or(T_1968, T_1969)
    io.meta_write.valid <= T_1970
    io.meta_write.bits.idx <= req_idx
    node T_1971 = eq(state, UInt<2>("h03"))
    wire T_1973 : UInt<2>[2]
    T_1973[0] <= UInt<2>("h02")
    T_1973[1] <= UInt<2>("h03")
    node T_1977 = eq(T_1973[0], req.old_meta.coh.state)
    node T_1978 = eq(T_1973[1], req.old_meta.coh.state)
    node T_1980 = or(UInt<1>("h00"), T_1977)
    node T_1981 = or(T_1980, T_1978)
    node T_1982 = mux(T_1981, UInt<1>("h01"), req.old_meta.coh.state)
    node T_1983 = eq(req.old_meta.coh.state, UInt<2>("h03"))
    node T_1984 = mux(T_1983, UInt<2>("h02"), req.old_meta.coh.state)
    node T_1985 = eq(UInt<5>("h013"), UInt<5>("h010"))
    node T_1986 = mux(T_1985, T_1984, req.old_meta.coh.state)
    node T_1987 = eq(UInt<5>("h011"), UInt<5>("h010"))
    node T_1988 = mux(T_1987, T_1982, T_1986)
    node T_1989 = eq(UInt<5>("h010"), UInt<5>("h010"))
    node T_1990 = mux(T_1989, UInt<1>("h00"), T_1988)
    wire T_2016 : {state : UInt<2>}
    T_2016 is invalid
    T_2016.state <= T_1990
    node T_2041 = mux(T_1971, T_2016, new_coh_state)
    io.meta_write.bits.data.coh <- T_2041
    io.meta_write.bits.data.tag <= io.tag
    io.meta_write.bits.way_en <= req.way_en
    node T_2066 = eq(state, UInt<1>("h01"))
    io.wb_req.valid <= T_2066
    node T_2068 = cat(req.old_meta.tag, req_idx)
    wire T_2073 : UInt<2>[1]
    T_2073[0] <= UInt<2>("h03")
    node T_2076 = eq(T_2073[0], req.old_meta.coh.state)
    node T_2078 = or(UInt<1>("h00"), T_2076)
    node T_2079 = mux(T_2078, UInt<1>("h00"), UInt<2>("h03"))
    node T_2080 = mux(T_2078, UInt<1>("h01"), UInt<3>("h04"))
    node T_2081 = mux(T_2078, UInt<2>("h02"), UInt<3>("h05"))
    node T_2082 = eq(UInt<5>("h013"), UInt<5>("h010"))
    node T_2083 = mux(T_2082, T_2081, UInt<3>("h05"))
    node T_2084 = eq(UInt<5>("h011"), UInt<5>("h010"))
    node T_2085 = mux(T_2084, T_2080, T_2083)
    node T_2086 = eq(UInt<5>("h010"), UInt<5>("h010"))
    node T_2087 = mux(T_2086, T_2079, T_2085)
    wire T_2118 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}
    T_2118 is invalid
    T_2118.r_type <= T_2087
    T_2118.client_xact_id <= UInt<1>("h01")
    T_2118.addr_block <= T_2068
    T_2118.addr_beat <= UInt<1>("h00")
    T_2118.data <= UInt<1>("h00")
    T_2118.voluntary <= UInt<1>("h01")
    io.wb_req.bits <- T_2118
    io.wb_req.bits.way_en <= req.way_en
    node T_2148 = eq(state, UInt<3>("h04"))
    io.mem_req.valid <= T_2148
    node T_2149 = cat(io.tag, req_idx)
    node T_2152 = eq(req.cmd, UInt<5>("h01"))
    node T_2153 = eq(req.cmd, UInt<5>("h07"))
    node T_2154 = or(T_2152, T_2153)
    node T_2155 = bits(req.cmd, 3, 3)
    node T_2156 = eq(req.cmd, UInt<5>("h04"))
    node T_2157 = or(T_2155, T_2156)
    node T_2158 = or(T_2154, T_2157)
    node T_2159 = eq(req.cmd, UInt<5>("h03"))
    node T_2160 = or(T_2158, T_2159)
    node T_2161 = eq(req.cmd, UInt<5>("h06"))
    node T_2162 = or(T_2160, T_2161)
    node T_2163 = mux(T_2162, UInt<1>("h01"), UInt<1>("h00"))
    node T_2165 = cat(req.cmd, UInt<1>("h01"))
    wire T_2199 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    T_2199 is invalid
    T_2199.is_builtin_type <= UInt<1>("h00")
    T_2199.a_type <= T_2163
    T_2199.client_xact_id <= UInt<1>("h01")
    T_2199.addr_block <= T_2149
    T_2199.addr_beat <= UInt<1>("h00")
    T_2199.data <= UInt<1>("h00")
    T_2199.union <= T_2165
    io.mem_req.bits <- T_2199
    node T_2230 = eq(state, UInt<4>("h08"))
    io.meta_read.valid <= T_2230
    io.meta_read.bits.idx <= req_idx
    io.meta_read.bits.tag <= io.tag
    node T_2231 = eq(state, UInt<4>("h08"))
    node T_2232 = and(T_2231, rpq.io.deq.valid)
    io.replay.valid <= T_2232
    io.replay.bits <- rpq.io.deq.bits
    io.replay.bits.phys <= UInt<1>("h01")
    node T_2234 = bits(rpq.io.deq.bits.addr, 5, 0)
    node T_2235 = cat(req_idx, T_2234)
    node T_2236 = cat(io.tag, T_2235)
    io.replay.bits.addr <= T_2236
    node T_2238 = eq(io.meta_read.ready, UInt<1>("h00"))
    when T_2238 :
      rpq.io.deq.ready <= UInt<1>("h00")
      io.replay.bits.cmd <= UInt<5>("h05")
      skip
    
  module Arbiter_101 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>}
    
    io is invalid
    wire T_54 : UInt<1>
    T_54 is invalid
    io.out.valid <= io.in[T_54].valid
    io.out.bits <= io.in[T_54].bits
    io.chosen <= T_54
    io.in[T_54].ready <= UInt<1>("h00")
    node T_73 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_74 = mux(UInt<1>("h00"), T_73, UInt<1>("h01"))
    node T_75 = and(T_74, io.out.ready)
    io.in[0].ready <= T_75
    node T_77 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00"))
    T_54 <= T_77
    
  module Arbiter_102 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_1062 : UInt<1>
    T_1062 is invalid
    io.out.valid <= io.in[T_1062].valid
    io.out.bits <- io.in[T_1062].bits
    io.chosen <= T_1062
    io.in[T_1062].ready <= UInt<1>("h00")
    node T_1417 = eq(UInt<1>("h00"), UInt<1>("h00"))
    node T_1418 = mux(UInt<1>("h00"), T_1417, UInt<1>("h01"))
    node T_1419 = and(T_1418, io.out.ready)
    io.in[0].ready <= T_1419
    node T_1421 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00"))
    T_1062 <= T_1421
    
  module IOMSHR : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}}
    
    io is invalid
    reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk
    node req_cmd_sc = eq(req.cmd, UInt<5>("h07"))
    reg grant_word : UInt<64>, clk
    node T_861 = bits(req.typ, 1, 0)
    node T_862 = bits(req.typ, 1, 0)
    node T_863 = asSInt(req.typ)
    node T_865 = geq(T_863, asSInt(UInt<1>("h00")))
    node beat_offset = bits(req.addr, 3, 3)
    node T_868 = bits(req.addr, 0, 0)
    node T_870 = mux(T_868, UInt<1>("h01"), UInt<1>("h00"))
    node T_872 = geq(T_861, UInt<1>("h01"))
    node T_875 = mux(T_872, UInt<1>("h01"), UInt<1>("h00"))
    node T_876 = or(T_870, T_875)
    node T_877 = bits(req.addr, 0, 0)
    node T_879 = mux(T_877, UInt<1>("h00"), UInt<1>("h01"))
    node T_880 = cat(T_876, T_879)
    node T_881 = bits(req.addr, 1, 1)
    node T_883 = mux(T_881, T_880, UInt<1>("h00"))
    node T_885 = geq(T_861, UInt<2>("h02"))
    node T_888 = mux(T_885, UInt<2>("h03"), UInt<1>("h00"))
    node T_889 = or(T_883, T_888)
    node T_890 = bits(req.addr, 1, 1)
    node T_892 = mux(T_890, UInt<1>("h00"), T_880)
    node T_893 = cat(T_889, T_892)
    node T_894 = bits(req.addr, 2, 2)
    node T_896 = mux(T_894, T_893, UInt<1>("h00"))
    node T_898 = geq(T_861, UInt<2>("h03"))
    node T_901 = mux(T_898, UInt<4>("h0f"), UInt<1>("h00"))
    node T_902 = or(T_896, T_901)
    node T_903 = bits(req.addr, 2, 2)
    node T_905 = mux(T_903, UInt<1>("h00"), T_893)
    node T_906 = cat(T_902, T_905)
    node T_908 = cat(beat_offset, UInt<3>("h00"))
    node beat_mask = dshl(T_906, T_908)
    node T_911 = eq(T_861, UInt<1>("h00"))
    node T_912 = bits(req.data, 7, 0)
    node T_913 = cat(T_912, T_912)
    node T_914 = cat(T_913, T_913)
    node T_915 = cat(T_914, T_914)
    node T_917 = eq(T_861, UInt<1>("h01"))
    node T_918 = bits(req.data, 15, 0)
    node T_919 = cat(T_918, T_918)
    node T_920 = cat(T_919, T_919)
    node T_922 = eq(T_861, UInt<2>("h02"))
    node T_923 = bits(req.data, 31, 0)
    node T_924 = cat(T_923, T_923)
    node T_925 = mux(T_922, T_924, req.data)
    node T_926 = mux(T_917, T_920, T_925)
    node T_927 = mux(T_911, T_915, T_926)
    node beat_data = cat(T_927, T_927)
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    node T_935 = eq(state, UInt<1>("h00"))
    io.req.ready <= T_935
    node addr_block = bits(req.addr, 31, 6)
    node addr_beat = bits(req.addr, 5, 4)
    node addr_byte = bits(req.addr, 3, 0)
    node T_947 = cat(addr_byte, req.typ)
    node T_948 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_949 = cat(T_947, T_948)
    node T_951 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_952 = cat(req.typ, T_951)
    node T_954 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_956 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_958 = cat(addr_byte, req.typ)
    node T_959 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_960 = cat(T_958, T_959)
    node T_962 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_964 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_965 = eq(UInt<3>("h06"), UInt<3>("h00"))
    node T_966 = mux(T_965, T_964, UInt<1>("h00"))
    node T_967 = eq(UInt<3>("h05"), UInt<3>("h00"))
    node T_968 = mux(T_967, T_962, T_966)
    node T_969 = eq(UInt<3>("h04"), UInt<3>("h00"))
    node T_970 = mux(T_969, T_960, T_968)
    node T_971 = eq(UInt<3>("h03"), UInt<3>("h00"))
    node T_972 = mux(T_971, T_956, T_970)
    node T_973 = eq(UInt<3>("h02"), UInt<3>("h00"))
    node T_974 = mux(T_973, T_954, T_972)
    node T_975 = eq(UInt<3>("h01"), UInt<3>("h00"))
    node T_976 = mux(T_975, T_952, T_974)
    node T_977 = eq(UInt<3>("h00"), UInt<3>("h00"))
    node T_978 = mux(T_977, T_949, T_976)
    wire get_acquire : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    get_acquire is invalid
    get_acquire.is_builtin_type <= UInt<1>("h01")
    get_acquire.a_type <= UInt<3>("h00")
    get_acquire.client_xact_id <= UInt<2>("h02")
    get_acquire.addr_block <= addr_block
    get_acquire.addr_beat <= addr_beat
    get_acquire.data <= UInt<1>("h00")
    get_acquire.union <= T_978
    node T_1049 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1050 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_1051 = cat(T_1049, T_1050)
    node T_1053 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_1054 = cat(UInt<3>("h07"), T_1053)
    node T_1056 = cat(beat_mask, UInt<1>("h00"))
    node T_1058 = cat(beat_mask, UInt<1>("h00"))
    node T_1060 = cat(UInt<1>("h00"), UInt<3>("h07"))
    node T_1061 = cat(UInt<1>("h00"), UInt<1>("h00"))
    node T_1062 = cat(T_1060, T_1061)
    node T_1064 = cat(UInt<5>("h00"), UInt<1>("h00"))
    node T_1066 = cat(UInt<5>("h01"), UInt<1>("h00"))
    node T_1067 = eq(UInt<3>("h06"), UInt<3>("h02"))
    node T_1068 = mux(T_1067, T_1066, UInt<1>("h00"))
    node T_1069 = eq(UInt<3>("h05"), UInt<3>("h02"))
    node T_1070 = mux(T_1069, T_1064, T_1068)
    node T_1071 = eq(UInt<3>("h04"), UInt<3>("h02"))
    node T_1072 = mux(T_1071, T_1062, T_1070)
    node T_1073 = eq(UInt<3>("h03"), UInt<3>("h02"))
    node T_1074 = mux(T_1073, T_1058, T_1072)
    node T_1075 = eq(UInt<3>("h02"), UInt<3>("h02"))
    node T_1076 = mux(T_1075, T_1056, T_1074)
    node T_1077 = eq(UInt<3>("h01"), UInt<3>("h02"))
    node T_1078 = mux(T_1077, T_1054, T_1076)
    node T_1079 = eq(UInt<3>("h00"), UInt<3>("h02"))
    node T_1080 = mux(T_1079, T_1051, T_1078)
    wire put_acquire : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}
    put_acquire is invalid
    put_acquire.is_builtin_type <= UInt<1>("h01")
    put_acquire.a_type <= UInt<3>("h02")
    put_acquire.client_xact_id <= UInt<2>("h02")
    put_acquire.addr_block <= addr_block
    put_acquire.addr_beat <= addr_beat
    put_acquire.data <= beat_data
    put_acquire.union <= T_1080
    node T_1143 = eq(state, UInt<1>("h01"))
    io.acquire.valid <= T_1143
    node T_1144 = eq(req.cmd, UInt<5>("h00"))
    node T_1145 = eq(req.cmd, UInt<5>("h06"))
    node T_1146 = or(T_1144, T_1145)
    node T_1147 = eq(req.cmd, UInt<5>("h07"))
    node T_1148 = or(T_1146, T_1147)
    node T_1149 = bits(req.cmd, 3, 3)
    node T_1150 = eq(req.cmd, UInt<5>("h04"))
    node T_1151 = or(T_1149, T_1150)
    node T_1152 = or(T_1148, T_1151)
    node T_1153 = mux(T_1152, get_acquire, put_acquire)
    io.acquire.bits <- T_1153
    node T_1184 = eq(state, UInt<2>("h03"))
    io.resp.valid <= T_1184
    io.resp.bits <- req
    node T_1185 = eq(req.cmd, UInt<5>("h00"))
    node T_1186 = eq(req.cmd, UInt<5>("h06"))
    node T_1187 = or(T_1185, T_1186)
    node T_1188 = eq(req.cmd, UInt<5>("h07"))
    node T_1189 = or(T_1187, T_1188)
    node T_1190 = bits(req.cmd, 3, 3)
    node T_1191 = eq(req.cmd, UInt<5>("h04"))
    node T_1192 = or(T_1190, T_1191)
    node T_1193 = or(T_1189, T_1192)
    io.resp.bits.has_data <= T_1193
    node T_1194 = bits(req.addr, 2, 2)
    node T_1195 = bits(grant_word, 63, 32)
    node T_1196 = bits(grant_word, 31, 0)
    node T_1197 = mux(T_1194, T_1195, T_1196)
    node T_1199 = and(UInt<1>("h00"), req_cmd_sc)
    node T_1201 = mux(T_1199, UInt<1>("h00"), T_1197)
    node T_1203 = eq(T_862, UInt<2>("h02"))
    node T_1204 = or(T_1203, T_1199)
    node T_1205 = bits(T_1201, 31, 31)
    node T_1206 = and(T_865, T_1205)
    node T_1208 = sub(UInt<32>("h00"), T_1206)
    node T_1209 = tail(T_1208, 1)
    node T_1210 = bits(grant_word, 63, 32)
    node T_1211 = mux(T_1204, T_1209, T_1210)
    node T_1212 = cat(T_1211, T_1201)
    node T_1213 = bits(req.addr, 1, 1)
    node T_1214 = bits(T_1212, 31, 16)
    node T_1215 = bits(T_1212, 15, 0)
    node T_1216 = mux(T_1213, T_1214, T_1215)
    node T_1218 = and(UInt<1>("h00"), req_cmd_sc)
    node T_1220 = mux(T_1218, UInt<1>("h00"), T_1216)
    node T_1222 = eq(T_862, UInt<1>("h01"))
    node T_1223 = or(T_1222, T_1218)
    node T_1224 = bits(T_1220, 15, 15)
    node T_1225 = and(T_865, T_1224)
    node T_1227 = sub(UInt<48>("h00"), T_1225)
    node T_1228 = tail(T_1227, 1)
    node T_1229 = bits(T_1212, 63, 16)
    node T_1230 = mux(T_1223, T_1228, T_1229)
    node T_1231 = cat(T_1230, T_1220)
    node T_1232 = bits(req.addr, 0, 0)
    node T_1233 = bits(T_1231, 15, 8)
    node T_1234 = bits(T_1231, 7, 0)
    node T_1235 = mux(T_1232, T_1233, T_1234)
    node T_1237 = and(UInt<1>("h01"), req_cmd_sc)
    node T_1239 = mux(T_1237, UInt<1>("h00"), T_1235)
    node T_1241 = eq(T_862, UInt<1>("h00"))
    node T_1242 = or(T_1241, T_1237)
    node T_1243 = bits(T_1239, 7, 7)
    node T_1244 = and(T_865, T_1243)
    node T_1246 = sub(UInt<56>("h00"), T_1244)
    node T_1247 = tail(T_1246, 1)
    node T_1248 = bits(T_1231, 63, 8)
    node T_1249 = mux(T_1242, T_1247, T_1248)
    node T_1250 = cat(T_1249, T_1239)
    node T_1251 = or(T_1250, req_cmd_sc)
    io.resp.bits.data <= T_1251
    io.resp.bits.store_data <= req.data
    io.resp.bits.nack <= UInt<1>("h00")
    io.resp.bits.replay <= io.resp.valid
    node T_1253 = and(io.req.ready, io.req.valid)
    when T_1253 :
      req <- io.req.bits
      state <= UInt<1>("h01")
      skip
    node T_1254 = and(io.acquire.ready, io.acquire.valid)
    when T_1254 :
      state <= UInt<2>("h02")
      skip
    node T_1255 = eq(state, UInt<2>("h02"))
    node T_1256 = and(T_1255, io.grant.valid)
    when T_1256 :
      node T_1257 = eq(req.cmd, UInt<5>("h00"))
      node T_1258 = eq(req.cmd, UInt<5>("h06"))
      node T_1259 = or(T_1257, T_1258)
      node T_1260 = eq(req.cmd, UInt<5>("h07"))
      node T_1261 = or(T_1259, T_1260)
      node T_1262 = bits(req.cmd, 3, 3)
      node T_1263 = eq(req.cmd, UInt<5>("h04"))
      node T_1264 = or(T_1262, T_1263)
      node T_1265 = or(T_1261, T_1264)
      when T_1265 :
        node T_1266 = bits(req.addr, 3, 3)
        node T_1268 = cat(T_1266, UInt<6>("h00"))
        node T_1269 = dshr(io.grant.bits.data, T_1268)
        node T_1270 = bits(T_1269, 63, 0)
        grant_word <= T_1270
        state <= UInt<2>("h03")
        skip
      node T_1272 = eq(T_1265, UInt<1>("h00"))
      when T_1272 :
        state <= UInt<1>("h00")
        skip
      skip
    node T_1273 = and(io.resp.ready, io.resp.valid)
    when T_1273 :
      state <= UInt<1>("h00")
      skip
    
  module MSHRFile : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, secondary_miss : UInt<1>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>, fence_rdy : UInt<1>}
    
    io is invalid
    node cacheable = lt(io.req.bits.addr, UInt<31>("h040000000"))
    reg sdq_val : UInt<17>, clk with : (reset => (reset, UInt<17>("h00")))
    node T_1807 = bits(sdq_val, 16, 0)
    node T_1808 = not(T_1807)
    node T_1809 = bits(T_1808, 0, 0)
    node T_1810 = bits(T_1808, 1, 1)
    node T_1811 = bits(T_1808, 2, 2)
    node T_1812 = bits(T_1808, 3, 3)
    node T_1813 = bits(T_1808, 4, 4)
    node T_1814 = bits(T_1808, 5, 5)
    node T_1815 = bits(T_1808, 6, 6)
    node T_1816 = bits(T_1808, 7, 7)
    node T_1817 = bits(T_1808, 8, 8)
    node T_1818 = bits(T_1808, 9, 9)
    node T_1819 = bits(T_1808, 10, 10)
    node T_1820 = bits(T_1808, 11, 11)
    node T_1821 = bits(T_1808, 12, 12)
    node T_1822 = bits(T_1808, 13, 13)
    node T_1823 = bits(T_1808, 14, 14)
    node T_1824 = bits(T_1808, 15, 15)
    node T_1825 = bits(T_1808, 16, 16)
    wire T_1827 : UInt<1>[17]
    T_1827[0] <= T_1809
    T_1827[1] <= T_1810
    T_1827[2] <= T_1811
    T_1827[3] <= T_1812
    T_1827[4] <= T_1813
    T_1827[5] <= T_1814
    T_1827[6] <= T_1815
    T_1827[7] <= T_1816
    T_1827[8] <= T_1817
    T_1827[9] <= T_1818
    T_1827[10] <= T_1819
    T_1827[11] <= T_1820
    T_1827[12] <= T_1821
    T_1827[13] <= T_1822
    T_1827[14] <= T_1823
    T_1827[15] <= T_1824
    T_1827[16] <= T_1825
    node T_1863 = mux(T_1827[15], UInt<4>("h0f"), UInt<5>("h010"))
    node T_1864 = mux(T_1827[14], UInt<4>("h0e"), T_1863)
    node T_1865 = mux(T_1827[13], UInt<4>("h0d"), T_1864)
    node T_1866 = mux(T_1827[12], UInt<4>("h0c"), T_1865)
    node T_1867 = mux(T_1827[11], UInt<4>("h0b"), T_1866)
    node T_1868 = mux(T_1827[10], UInt<4>("h0a"), T_1867)
    node T_1869 = mux(T_1827[9], UInt<4>("h09"), T_1868)
    node T_1870 = mux(T_1827[8], UInt<4>("h08"), T_1869)
    node T_1871 = mux(T_1827[7], UInt<3>("h07"), T_1870)
    node T_1872 = mux(T_1827[6], UInt<3>("h06"), T_1871)
    node T_1873 = mux(T_1827[5], UInt<3>("h05"), T_1872)
    node T_1874 = mux(T_1827[4], UInt<3>("h04"), T_1873)
    node T_1875 = mux(T_1827[3], UInt<2>("h03"), T_1874)
    node T_1876 = mux(T_1827[2], UInt<2>("h02"), T_1875)
    node T_1877 = mux(T_1827[1], UInt<1>("h01"), T_1876)
    node sdq_alloc_id = mux(T_1827[0], UInt<1>("h00"), T_1877)
    node T_1879 = not(sdq_val)
    node T_1881 = eq(T_1879, UInt<1>("h00"))
    node sdq_rdy = eq(T_1881, UInt<1>("h00"))
    node T_1884 = and(io.req.valid, io.req.ready)
    node T_1885 = and(T_1884, cacheable)
    node T_1886 = eq(io.req.bits.cmd, UInt<5>("h01"))
    node T_1887 = eq(io.req.bits.cmd, UInt<5>("h07"))
    node T_1888 = or(T_1886, T_1887)
    node T_1889 = bits(io.req.bits.cmd, 3, 3)
    node T_1890 = eq(io.req.bits.cmd, UInt<5>("h04"))
    node T_1891 = or(T_1889, T_1890)
    node T_1892 = or(T_1888, T_1891)
    node sdq_enq = and(T_1885, T_1892)
    cmem sdq : UInt<64>[17]
    when sdq_enq :
      infer mport T_1896 = sdq[sdq_alloc_id], clk
      T_1896 <= io.req.bits.data
      skip
    wire idxMatch : UInt<1>[2]
    idxMatch is invalid
    wire tagList : UInt<20>[2]
    tagList is invalid
    node T_1922 = mux(idxMatch[0], tagList[0], UInt<1>("h00"))
    node T_1924 = mux(idxMatch[1], tagList[1], UInt<1>("h00"))
    node T_1926 = or(T_1922, T_1924)
    wire T_1927 : UInt<20>
    T_1927 is invalid
    T_1927 <= T_1926
    node T_1928 = shr(io.req.bits.addr, 12)
    node tag_match = eq(T_1927, T_1928)
    wire wbTagList : UInt[2]
    wbTagList is invalid
    wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2]
    refillMux is invalid
    inst meta_read_arb of Arbiter_93
    meta_read_arb.io is invalid
    meta_read_arb.clk <= clk
    meta_read_arb.reset <= reset
    inst meta_write_arb of Arbiter_94
    meta_write_arb.io is invalid
    meta_write_arb.clk <= clk
    meta_write_arb.reset <= reset
    inst mem_req_arb of LockingArbiter
    mem_req_arb.io is invalid
    mem_req_arb.clk <= clk
    mem_req_arb.reset <= reset
    inst wb_req_arb of Arbiter_95
    wb_req_arb.io is invalid
    wb_req_arb.clk <= clk
    wb_req_arb.reset <= reset
    inst replay_arb of Arbiter_96
    replay_arb.io is invalid
    replay_arb.clk <= clk
    replay_arb.reset <= reset
    inst alloc_arb of Arbiter_97
    alloc_arb.io is invalid
    alloc_arb.clk <= clk
    alloc_arb.reset <= reset
    io.fence_rdy <= UInt<1>("h01")
    io.probe_rdy <= UInt<1>("h01")
    inst T_2714 of MSHR
    T_2714.io is invalid
    T_2714.clk <= clk
    T_2714.reset <= reset
    idxMatch[0] <= T_2714.io.idx_match
    tagList[0] <= T_2714.io.tag
    node T_2715 = shr(T_2714.io.wb_req.bits.addr_block, 6)
    wbTagList[0] <= T_2715
    alloc_arb.io.in[0].valid <= T_2714.io.req_pri_rdy
    T_2714.io.req_pri_val <= alloc_arb.io.in[0].ready
    node T_2716 = and(io.req.valid, sdq_rdy)
    node T_2717 = and(T_2716, tag_match)
    T_2714.io.req_sec_val <= T_2717
    T_2714.io.req_bits <- io.req.bits
    T_2714.io.req_bits.sdq_id <= sdq_alloc_id
    meta_read_arb.io.in[0] <- T_2714.io.meta_read
    meta_write_arb.io.in[0] <- T_2714.io.meta_write
    mem_req_arb.io.in[0] <- T_2714.io.mem_req
    wb_req_arb.io.in[0] <- T_2714.io.wb_req
    replay_arb.io.in[0] <- T_2714.io.replay
    node T_2719 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h00"))
    node T_2720 = and(io.mem_grant.valid, T_2719)
    T_2714.io.mem_grant.valid <= T_2720
    T_2714.io.mem_grant.bits <- io.mem_grant.bits
    refillMux[0] <- T_2714.io.refill
    node T_2721 = or(UInt<1>("h00"), T_2714.io.req_pri_rdy)
    node T_2722 = or(UInt<1>("h00"), T_2714.io.req_sec_rdy)
    node T_2723 = or(UInt<1>("h00"), T_2714.io.idx_match)
    node T_2725 = eq(T_2714.io.req_pri_rdy, UInt<1>("h00"))
    when T_2725 :
      io.fence_rdy <= UInt<1>("h00")
      skip
    node T_2728 = eq(T_2714.io.probe_rdy, UInt<1>("h00"))
    when T_2728 :
      io.probe_rdy <= UInt<1>("h00")
      skip
    inst T_2730 of MSHR_99
    T_2730.io is invalid
    T_2730.clk <= clk
    T_2730.reset <= reset
    idxMatch[1] <= T_2730.io.idx_match
    tagList[1] <= T_2730.io.tag
    node T_2731 = shr(T_2730.io.wb_req.bits.addr_block, 6)
    wbTagList[1] <= T_2731
    alloc_arb.io.in[1].valid <= T_2730.io.req_pri_rdy
    T_2730.io.req_pri_val <= alloc_arb.io.in[1].ready
    node T_2732 = and(io.req.valid, sdq_rdy)
    node T_2733 = and(T_2732, tag_match)
    T_2730.io.req_sec_val <= T_2733
    T_2730.io.req_bits <- io.req.bits
    T_2730.io.req_bits.sdq_id <= sdq_alloc_id
    meta_read_arb.io.in[1] <- T_2730.io.meta_read
    meta_write_arb.io.in[1] <- T_2730.io.meta_write
    mem_req_arb.io.in[1] <- T_2730.io.mem_req
    wb_req_arb.io.in[1] <- T_2730.io.wb_req
    replay_arb.io.in[1] <- T_2730.io.replay
    node T_2735 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h01"))
    node T_2736 = and(io.mem_grant.valid, T_2735)
    T_2730.io.mem_grant.valid <= T_2736
    T_2730.io.mem_grant.bits <- io.mem_grant.bits
    refillMux[1] <- T_2730.io.refill
    node pri_rdy = or(T_2721, T_2730.io.req_pri_rdy)
    node sec_rdy = or(T_2722, T_2730.io.req_sec_rdy)
    node idx_match = or(T_2723, T_2730.io.idx_match)
    node T_2741 = eq(T_2730.io.req_pri_rdy, UInt<1>("h00"))
    when T_2741 :
      io.fence_rdy <= UInt<1>("h00")
      skip
    node T_2744 = eq(T_2730.io.probe_rdy, UInt<1>("h00"))
    when T_2744 :
      io.probe_rdy <= UInt<1>("h00")
      skip
    node T_2746 = and(io.req.valid, sdq_rdy)
    node T_2747 = and(T_2746, cacheable)
    node T_2749 = eq(idx_match, UInt<1>("h00"))
    node T_2750 = and(T_2747, T_2749)
    alloc_arb.io.out.ready <= T_2750
    io.meta_read <- meta_read_arb.io.out
    io.meta_write <- meta_write_arb.io.out
    io.mem_req <- mem_req_arb.io.out
    io.wb_req <- wb_req_arb.io.out
    inst mmio_alloc_arb of Arbiter_101
    mmio_alloc_arb.io is invalid
    mmio_alloc_arb.clk <= clk
    mmio_alloc_arb.reset <= reset
    inst resp_arb of Arbiter_102
    resp_arb.io is invalid
    resp_arb.clk <= clk
    resp_arb.reset <= reset
    inst T_2812 of IOMSHR
    T_2812.io is invalid
    T_2812.clk <= clk
    T_2812.reset <= reset
    mmio_alloc_arb.io.in[0].valid <= T_2812.io.req.ready
    T_2812.io.req.valid <= mmio_alloc_arb.io.in[0].ready
    T_2812.io.req.bits <- io.req.bits
    node mmio_rdy = or(UInt<1>("h00"), T_2812.io.req.ready)
    mem_req_arb.io.in[2] <- T_2812.io.acquire
    T_2812.io.grant.bits <- io.mem_grant.bits
    node T_2815 = eq(io.mem_grant.bits.client_xact_id, UInt<2>("h02"))
    node T_2816 = and(io.mem_grant.valid, T_2815)
    T_2812.io.grant.valid <= T_2816
    resp_arb.io.in[0] <- T_2812.io.resp
    node T_2818 = eq(T_2812.io.req.ready, UInt<1>("h00"))
    when T_2818 :
      io.fence_rdy <= UInt<1>("h00")
      skip
    node T_2821 = eq(cacheable, UInt<1>("h00"))
    node T_2822 = and(io.req.valid, T_2821)
    mmio_alloc_arb.io.out.ready <= T_2822
    io.resp <- resp_arb.io.out
    node T_2824 = eq(cacheable, UInt<1>("h00"))
    node T_2825 = and(tag_match, sec_rdy)
    node T_2826 = mux(idx_match, T_2825, pri_rdy)
    node T_2827 = and(T_2826, sdq_rdy)
    node T_2828 = mux(T_2824, mmio_rdy, T_2827)
    io.req.ready <= T_2828
    io.secondary_miss <= idx_match
    io.refill <- refillMux[io.mem_grant.bits.client_xact_id]
    node T_2878 = and(io.replay.ready, io.replay.valid)
    node T_2879 = eq(io.replay.bits.cmd, UInt<5>("h01"))
    node T_2880 = eq(io.replay.bits.cmd, UInt<5>("h07"))
    node T_2881 = or(T_2879, T_2880)
    node T_2882 = bits(io.replay.bits.cmd, 3, 3)
    node T_2883 = eq(io.replay.bits.cmd, UInt<5>("h04"))
    node T_2884 = or(T_2882, T_2883)
    node T_2885 = or(T_2881, T_2884)
    node free_sdq = and(T_2878, T_2885)
    reg T_2887 : UInt<5>, clk
    when free_sdq :
      T_2887 <= replay_arb.io.out.bits.sdq_id
      skip
    infer mport T_2888 = sdq[T_2887], clk
    io.replay.bits.data <= T_2888
    io.replay <- replay_arb.io.out
    node T_2889 = or(io.replay.valid, sdq_enq)
    when T_2889 :
      node T_2891 = dshl(UInt<1>("h01"), replay_arb.io.out.bits.sdq_id)
      node T_2893 = sub(UInt<17>("h00"), free_sdq)
      node T_2894 = tail(T_2893, 1)
      node T_2895 = and(T_2891, T_2894)
      node T_2896 = not(T_2895)
      node T_2897 = and(sdq_val, T_2896)
      node T_2898 = bits(sdq_val, 16, 0)
      node T_2899 = not(T_2898)
      node T_2900 = bits(T_2899, 0, 0)
      node T_2901 = bits(T_2899, 1, 1)
      node T_2902 = bits(T_2899, 2, 2)
      node T_2903 = bits(T_2899, 3, 3)
      node T_2904 = bits(T_2899, 4, 4)
      node T_2905 = bits(T_2899, 5, 5)
      node T_2906 = bits(T_2899, 6, 6)
      node T_2907 = bits(T_2899, 7, 7)
      node T_2908 = bits(T_2899, 8, 8)
      node T_2909 = bits(T_2899, 9, 9)
      node T_2910 = bits(T_2899, 10, 10)
      node T_2911 = bits(T_2899, 11, 11)
      node T_2912 = bits(T_2899, 12, 12)
      node T_2913 = bits(T_2899, 13, 13)
      node T_2914 = bits(T_2899, 14, 14)
      node T_2915 = bits(T_2899, 15, 15)
      node T_2916 = bits(T_2899, 16, 16)
      wire T_2935 : UInt<17>[17]
      T_2935[0] <= UInt<17>("h01")
      T_2935[1] <= UInt<17>("h02")
      T_2935[2] <= UInt<17>("h04")
      T_2935[3] <= UInt<17>("h08")
      T_2935[4] <= UInt<17>("h010")
      T_2935[5] <= UInt<17>("h020")
      T_2935[6] <= UInt<17>("h040")
      T_2935[7] <= UInt<17>("h080")
      T_2935[8] <= UInt<17>("h0100")
      T_2935[9] <= UInt<17>("h0200")
      T_2935[10] <= UInt<17>("h0400")
      T_2935[11] <= UInt<17>("h0800")
      T_2935[12] <= UInt<17>("h01000")
      T_2935[13] <= UInt<17>("h02000")
      T_2935[14] <= UInt<17>("h04000")
      T_2935[15] <= UInt<17>("h08000")
      T_2935[16] <= UInt<17>("h010000")
      node T_2956 = mux(T_2916, T_2935[16], UInt<17>("h00"))
      node T_2957 = mux(T_2915, T_2935[15], T_2956)
      node T_2958 = mux(T_2914, T_2935[14], T_2957)
      node T_2959 = mux(T_2913, T_2935[13], T_2958)
      node T_2960 = mux(T_2912, T_2935[12], T_2959)
      node T_2961 = mux(T_2911, T_2935[11], T_2960)
      node T_2962 = mux(T_2910, T_2935[10], T_2961)
      node T_2963 = mux(T_2909, T_2935[9], T_2962)
      node T_2964 = mux(T_2908, T_2935[8], T_2963)
      node T_2965 = mux(T_2907, T_2935[7], T_2964)
      node T_2966 = mux(T_2906, T_2935[6], T_2965)
      node T_2967 = mux(T_2905, T_2935[5], T_2966)
      node T_2968 = mux(T_2904, T_2935[4], T_2967)
      node T_2969 = mux(T_2903, T_2935[3], T_2968)
      node T_2970 = mux(T_2902, T_2935[2], T_2969)
      node T_2971 = mux(T_2901, T_2935[1], T_2970)
      node T_2972 = mux(T_2900, T_2935[0], T_2971)
      node T_2974 = sub(UInt<17>("h00"), sdq_enq)
      node T_2975 = tail(T_2974, 1)
      node T_2976 = and(T_2972, T_2975)
      node T_2977 = or(T_2897, T_2976)
      sdq_val <= T_2977
      skip
    
  module MetadataArray : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, resp : {tag : UInt<20>, coh : {state : UInt<2>}}[4]}
    
    io is invalid
    wire T_30 : {state : UInt<2>}
    T_30 is invalid
    T_30.state <= UInt<1>("h00")
    wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>}}
    rstVal is invalid
    rstVal.tag <= UInt<1>("h00")
    rstVal.coh <- T_30
    reg rst_cnt : UInt<7>, clk with : (reset => (reset, UInt<7>("h00")))
    node rst = lt(rst_cnt, UInt<7>("h040"))
    node waddr = mux(rst, rst_cnt, io.write.bits.idx)
    node T_1633 = mux(rst, rstVal, io.write.bits.data)
    node wdata = cat(T_1633.tag, T_1633.coh.state)
    node T_1708 = asSInt(io.write.bits.way_en)
    node T_1709 = mux(rst, asSInt(UInt<1>("h01")), T_1708)
    node T_1710 = bits(T_1709, 0, 0)
    node T_1711 = bits(T_1709, 1, 1)
    node T_1712 = bits(T_1709, 2, 2)
    node T_1713 = bits(T_1709, 3, 3)
    wire wmask : UInt<1>[4]
    wmask[0] <= T_1710
    wmask[1] <= T_1711
    wmask[2] <= T_1712
    wmask[3] <= T_1713
    when rst :
      node T_1722 = add(rst_cnt, UInt<1>("h01"))
      node T_1723 = tail(T_1722, 1)
      rst_cnt <= T_1723
      skip
    smem tag_arr : UInt<22>[4][64]
    node T_1741 = or(rst, io.write.valid)
    when T_1741 :
      wire T_1743 : UInt<22>[4]
      T_1743[0] <= wdata
      T_1743[1] <= wdata
      T_1743[2] <= wdata
      T_1743[3] <= wdata
      write mport T_1751 = tag_arr[waddr], clk
      when wmask[0] :
        T_1751[0] <= T_1743[0]
        skip
      when wmask[1] :
        T_1751[1] <= T_1743[1]
        skip
      when wmask[2] :
        T_1751[2] <= T_1743[2]
        skip
      when wmask[3] :
        T_1751[3] <= T_1743[3]
        skip
      skip
    wire T_1758 : UInt
    T_1758 is invalid
    when io.read.valid :
      T_1758 <= io.read.bits.idx
      skip
    read mport T_1761 = tag_arr[T_1758], clk
    node T_1767 = cat(T_1761[3], T_1761[2])
    node T_1768 = cat(T_1761[1], T_1761[0])
    node tags = cat(T_1767, T_1768)
    wire T_2428 : {tag : UInt<20>, coh : {state : UInt<2>}}[4]
    T_2428 is invalid
    node T_2794 = bits(tags, 1, 0)
    T_2428[0].coh.state <= T_2794
    node T_2795 = bits(tags, 21, 2)
    T_2428[0].tag <= T_2795
    node T_2796 = bits(tags, 23, 22)
    T_2428[1].coh.state <= T_2796
    node T_2797 = bits(tags, 43, 24)
    T_2428[1].tag <= T_2797
    node T_2798 = bits(tags, 45, 44)
    T_2428[2].coh.state <= T_2798
    node T_2799 = bits(tags, 65, 46)
    T_2428[2].tag <= T_2799
    node T_2800 = bits(tags, 67, 66)
    T_2428[3].coh.state <= T_2800
    node T_2801 = bits(tags, 87, 68)
    T_2428[3].tag <= T_2801
    io.resp <= T_2428
    node T_2803 = eq(rst, UInt<1>("h00"))
    node T_2805 = eq(io.write.valid, UInt<1>("h00"))
    node T_2806 = and(T_2803, T_2805)
    io.read.ready <= T_2806
    node T_2808 = eq(rst, UInt<1>("h00"))
    io.write.ready <= T_2808
    
  module Arbiter_105 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, chosen : UInt<3>}
    
    io is invalid
    wire T_128 : UInt<3>
    T_128 is invalid
    io.out.valid <= io.in[T_128].valid
    io.out.bits <- io.in[T_128].bits
    io.chosen <= T_128
    io.in[T_128].ready <= UInt<1>("h00")
    node T_153 = or(UInt<1>("h00"), io.in[0].valid)
    node T_155 = eq(T_153, UInt<1>("h00"))
    node T_157 = or(UInt<1>("h00"), io.in[0].valid)
    node T_158 = or(T_157, io.in[1].valid)
    node T_160 = eq(T_158, UInt<1>("h00"))
    node T_162 = or(UInt<1>("h00"), io.in[0].valid)
    node T_163 = or(T_162, io.in[1].valid)
    node T_164 = or(T_163, io.in[2].valid)
    node T_166 = eq(T_164, UInt<1>("h00"))
    node T_168 = or(UInt<1>("h00"), io.in[0].valid)
    node T_169 = or(T_168, io.in[1].valid)
    node T_170 = or(T_169, io.in[2].valid)
    node T_171 = or(T_170, io.in[3].valid)
    node T_173 = eq(T_171, UInt<1>("h00"))
    node T_175 = eq(UInt<3>("h04"), UInt<1>("h00"))
    node T_176 = mux(UInt<1>("h00"), T_175, UInt<1>("h01"))
    node T_177 = and(T_176, io.out.ready)
    io.in[0].ready <= T_177
    node T_179 = eq(UInt<3>("h04"), UInt<1>("h01"))
    node T_180 = mux(UInt<1>("h00"), T_179, T_155)
    node T_181 = and(T_180, io.out.ready)
    io.in[1].ready <= T_181
    node T_183 = eq(UInt<3>("h04"), UInt<2>("h02"))
    node T_184 = mux(UInt<1>("h00"), T_183, T_160)
    node T_185 = and(T_184, io.out.ready)
    io.in[2].ready <= T_185
    node T_187 = eq(UInt<3>("h04"), UInt<2>("h03"))
    node T_188 = mux(UInt<1>("h00"), T_187, T_166)
    node T_189 = and(T_188, io.out.ready)
    io.in[3].ready <= T_189
    node T_191 = eq(UInt<3>("h04"), UInt<3>("h04"))
    node T_192 = mux(UInt<1>("h00"), T_191, T_173)
    node T_193 = and(T_192, io.out.ready)
    io.in[4].ready <= T_193
    node T_196 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04"))
    node T_198 = mux(io.in[2].valid, UInt<2>("h02"), T_196)
    node T_200 = mux(io.in[1].valid, UInt<1>("h01"), T_198)
    node T_202 = mux(io.in[0].valid, UInt<1>("h00"), T_200)
    node T_203 = mux(UInt<1>("h00"), UInt<3>("h04"), T_202)
    T_128 <= T_203
    
  module DataArray : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, resp : UInt<128>[4]}
    
    io is invalid
    node waddr = shr(io.write.bits.addr, 4)
    node raddr = shr(io.read.bits.addr, 4)
    node T_572 = bits(io.write.bits.way_en, 1, 0)
    node T_573 = bits(io.read.bits.way_en, 1, 0)
    wire T_582 : UInt<128>[2]
    T_582 is invalid
    reg T_586 : UInt<12>, clk
    when io.read.valid :
      T_586 <= io.read.bits.addr
      skip
    smem T_599 : UInt<64>[2][256]
    node T_601 = neq(T_572, UInt<1>("h00"))
    node T_602 = and(T_601, io.write.valid)
    node T_603 = bits(io.write.bits.wmask, 0, 0)
    node T_604 = and(T_602, T_603)
    when T_604 :
      node T_605 = bits(io.write.bits.data, 63, 0)
      node T_606 = bits(io.write.bits.data, 63, 0)
      wire T_608 : UInt<64>[2]
      T_608[0] <= T_605
      T_608[1] <= T_606
      node T_612 = bits(T_572, 0, 0)
      node T_613 = bits(T_572, 1, 1)
      wire T_615 : UInt<1>[2]
      T_615[0] <= T_612
      T_615[1] <= T_613
      write mport T_621 = T_599[waddr], clk
      when T_615[0] :
        T_621[0] <= T_608[0]
        skip
      when T_615[1] :
        T_621[1] <= T_608[1]
        skip
      skip
    node T_626 = neq(T_573, UInt<1>("h00"))
    node T_627 = and(T_626, io.read.valid)
    wire T_629 : UInt
    T_629 is invalid
    when T_627 :
      T_629 <= raddr
      skip
    read mport T_632 = T_599[T_629], clk
    node T_636 = cat(T_632[1], T_632[0])
    T_582[0] <= T_636
    smem T_649 : UInt<64>[2][256]
    node T_651 = neq(T_572, UInt<1>("h00"))
    node T_652 = and(T_651, io.write.valid)
    node T_653 = bits(io.write.bits.wmask, 1, 1)
    node T_654 = and(T_652, T_653)
    when T_654 :
      node T_655 = bits(io.write.bits.data, 127, 64)
      node T_656 = bits(io.write.bits.data, 127, 64)
      wire T_658 : UInt<64>[2]
      T_658[0] <= T_655
      T_658[1] <= T_656
      node T_662 = bits(T_572, 0, 0)
      node T_663 = bits(T_572, 1, 1)
      wire T_665 : UInt<1>[2]
      T_665[0] <= T_662
      T_665[1] <= T_663
      write mport T_671 = T_649[waddr], clk
      when T_665[0] :
        T_671[0] <= T_658[0]
        skip
      when T_665[1] :
        T_671[1] <= T_658[1]
        skip
      skip
    node T_676 = neq(T_573, UInt<1>("h00"))
    node T_677 = and(T_676, io.read.valid)
    wire T_679 : UInt
    T_679 is invalid
    when T_677 :
      T_679 <= raddr
      skip
    read mport T_682 = T_649[T_679], clk
    node T_686 = cat(T_682[1], T_682[0])
    T_582[1] <= T_686
    node T_687 = bits(T_582[0], 63, 0)
    node T_688 = bits(T_582[1], 63, 0)
    wire T_690 : UInt<64>[2]
    T_690[0] <= T_687
    T_690[1] <= T_688
    node T_694 = bits(T_586, 3, 3)
    wire T_697 : UInt<64>[2]
    T_697[0] <= T_690[T_694]
    T_697[1] <= T_690[1]
    node T_701 = cat(T_697[1], T_697[0])
    io.resp[0] <= T_701
    node T_702 = bits(T_582[0], 127, 64)
    node T_703 = bits(T_582[1], 127, 64)
    wire T_705 : UInt<64>[2]
    T_705[0] <= T_702
    T_705[1] <= T_703
    node T_709 = bits(T_586, 3, 3)
    wire T_712 : UInt<64>[2]
    T_712[0] <= T_705[T_709]
    T_712[1] <= T_705[1]
    node T_716 = cat(T_712[1], T_712[0])
    io.resp[1] <= T_716
    node T_717 = bits(io.write.bits.way_en, 3, 2)
    node T_718 = bits(io.read.bits.way_en, 3, 2)
    wire T_727 : UInt<128>[2]
    T_727 is invalid
    reg T_731 : UInt<12>, clk
    when io.read.valid :
      T_731 <= io.read.bits.addr
      skip
    smem T_744 : UInt<64>[2][256]
    node T_746 = neq(T_717, UInt<1>("h00"))
    node T_747 = and(T_746, io.write.valid)
    node T_748 = bits(io.write.bits.wmask, 0, 0)
    node T_749 = and(T_747, T_748)
    when T_749 :
      node T_750 = bits(io.write.bits.data, 63, 0)
      node T_751 = bits(io.write.bits.data, 63, 0)
      wire T_753 : UInt<64>[2]
      T_753[0] <= T_750
      T_753[1] <= T_751
      node T_757 = bits(T_717, 0, 0)
      node T_758 = bits(T_717, 1, 1)
      wire T_760 : UInt<1>[2]
      T_760[0] <= T_757
      T_760[1] <= T_758
      write mport T_766 = T_744[waddr], clk
      when T_760[0] :
        T_766[0] <= T_753[0]
        skip
      when T_760[1] :
        T_766[1] <= T_753[1]
        skip
      skip
    node T_771 = neq(T_718, UInt<1>("h00"))
    node T_772 = and(T_771, io.read.valid)
    wire T_774 : UInt
    T_774 is invalid
    when T_772 :
      T_774 <= raddr
      skip
    read mport T_777 = T_744[T_774], clk
    node T_781 = cat(T_777[1], T_777[0])
    T_727[0] <= T_781
    smem T_794 : UInt<64>[2][256]
    node T_796 = neq(T_717, UInt<1>("h00"))
    node T_797 = and(T_796, io.write.valid)
    node T_798 = bits(io.write.bits.wmask, 1, 1)
    node T_799 = and(T_797, T_798)
    when T_799 :
      node T_800 = bits(io.write.bits.data, 127, 64)
      node T_801 = bits(io.write.bits.data, 127, 64)
      wire T_803 : UInt<64>[2]
      T_803[0] <= T_800
      T_803[1] <= T_801
      node T_807 = bits(T_717, 0, 0)
      node T_808 = bits(T_717, 1, 1)
      wire T_810 : UInt<1>[2]
      T_810[0] <= T_807
      T_810[1] <= T_808
      write mport T_816 = T_794[waddr], clk
      when T_810[0] :
        T_816[0] <= T_803[0]
        skip
      when T_810[1] :
        T_816[1] <= T_803[1]
        skip
      skip
    node T_821 = neq(T_718, UInt<1>("h00"))
    node T_822 = and(T_821, io.read.valid)
    wire T_824 : UInt
    T_824 is invalid
    when T_822 :
      T_824 <= raddr
      skip
    read mport T_827 = T_794[T_824], clk
    node T_831 = cat(T_827[1], T_827[0])
    T_727[1] <= T_831
    node T_832 = bits(T_727[0], 63, 0)
    node T_833 = bits(T_727[1], 63, 0)
    wire T_835 : UInt<64>[2]
    T_835[0] <= T_832
    T_835[1] <= T_833
    node T_839 = bits(T_731, 3, 3)
    wire T_842 : UInt<64>[2]
    T_842[0] <= T_835[T_839]
    T_842[1] <= T_835[1]
    node T_846 = cat(T_842[1], T_842[0])
    io.resp[2] <= T_846
    node T_847 = bits(T_727[0], 127, 64)
    node T_848 = bits(T_727[1], 127, 64)
    wire T_850 : UInt<64>[2]
    T_850[0] <= T_847
    T_850[1] <= T_848
    node T_854 = bits(T_731, 3, 3)
    wire T_857 : UInt<64>[2]
    T_857[0] <= T_850[T_854]
    T_857[1] <= T_850[1]
    node T_861 = cat(T_857[1], T_857[0])
    io.resp[3] <= T_861
    io.read.ready <= UInt<1>("h01")
    io.write.ready <= UInt<1>("h01")
    
  module Arbiter_107 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, chosen : UInt<2>}
    
    io is invalid
    wire T_1524 : UInt<2>
    T_1524 is invalid
    io.out.valid <= io.in[T_1524].valid
    io.out.bits <- io.in[T_1524].bits
    io.chosen <= T_1524
    io.in[T_1524].ready <= UInt<1>("h00")
    node T_1831 = or(UInt<1>("h00"), io.in[0].valid)
    node T_1833 = eq(T_1831, UInt<1>("h00"))
    node T_1835 = or(UInt<1>("h00"), io.in[0].valid)
    node T_1836 = or(T_1835, io.in[1].valid)
    node T_1838 = eq(T_1836, UInt<1>("h00"))
    node T_1840 = or(UInt<1>("h00"), io.in[0].valid)
    node T_1841 = or(T_1840, io.in[1].valid)
    node T_1842 = or(T_1841, io.in[2].valid)
    node T_1844 = eq(T_1842, UInt<1>("h00"))
    node T_1846 = eq(UInt<2>("h03"), UInt<1>("h00"))
    node T_1847 = mux(UInt<1>("h00"), T_1846, UInt<1>("h01"))
    node T_1848 = and(T_1847, io.out.ready)
    io.in[0].ready <= T_1848
    node T_1850 = eq(UInt<2>("h03"), UInt<1>("h01"))
    node T_1851 = mux(UInt<1>("h00"), T_1850, T_1833)
    node T_1852 = and(T_1851, io.out.ready)
    io.in[1].ready <= T_1852
    node T_1854 = eq(UInt<2>("h03"), UInt<2>("h02"))
    node T_1855 = mux(UInt<1>("h00"), T_1854, T_1838)
    node T_1856 = and(T_1855, io.out.ready)
    io.in[2].ready <= T_1856
    node T_1858 = eq(UInt<2>("h03"), UInt<2>("h03"))
    node T_1859 = mux(UInt<1>("h00"), T_1858, T_1844)
    node T_1860 = and(T_1859, io.out.ready)
    io.in[3].ready <= T_1860
    node T_1863 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03"))
    node T_1865 = mux(io.in[1].valid, UInt<1>("h01"), T_1863)
    node T_1867 = mux(io.in[0].valid, UInt<1>("h00"), T_1865)
    node T_1868 = mux(UInt<1>("h00"), UInt<2>("h03"), T_1867)
    T_1524 <= T_1868
    
  module Arbiter_108 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_1164 : UInt<1>
    T_1164 is invalid
    io.out.valid <= io.in[T_1164].valid
    io.out.bits <- io.in[T_1164].bits
    io.chosen <= T_1164
    io.in[T_1164].ready <= UInt<1>("h00")
    node T_1483 = or(UInt<1>("h00"), io.in[0].valid)
    node T_1485 = eq(T_1483, UInt<1>("h00"))
    node T_1487 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_1488 = mux(UInt<1>("h00"), T_1487, UInt<1>("h01"))
    node T_1489 = and(T_1488, io.out.ready)
    io.in[0].ready <= T_1489
    node T_1491 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_1492 = mux(UInt<1>("h00"), T_1491, T_1485)
    node T_1493 = and(T_1492, io.out.ready)
    io.in[1].ready <= T_1493
    node T_1496 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_1497 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1496)
    T_1164 <= T_1497
    
  module AMOALU : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip addr : UInt<6>, flip cmd : UInt<5>, flip typ : UInt<3>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>}
    
    io is invalid
    node T_10 = bits(io.typ, 1, 0)
    node T_12 = eq(T_10, UInt<2>("h02"))
    node T_13 = bits(io.rhs, 31, 0)
    node T_14 = cat(T_13, T_13)
    node rhs = mux(T_12, T_14, io.rhs)
    node T_16 = eq(io.cmd, UInt<5>("h0c"))
    node T_17 = eq(io.cmd, UInt<5>("h0d"))
    node sgned = or(T_16, T_17)
    node T_19 = eq(io.cmd, UInt<5>("h0d"))
    node T_20 = eq(io.cmd, UInt<5>("h0f"))
    node max = or(T_19, T_20)
    node T_22 = eq(io.cmd, UInt<5>("h0c"))
    node T_23 = eq(io.cmd, UInt<5>("h0e"))
    node min = or(T_22, T_23)
    node T_25 = eq(io.typ, UInt<3>("h02"))
    node T_26 = eq(io.typ, UInt<3>("h06"))
    node T_27 = or(T_25, T_26)
    node T_28 = eq(io.typ, UInt<3>("h00"))
    node T_29 = or(T_27, T_28)
    node T_30 = eq(io.typ, UInt<3>("h04"))
    node word = or(T_29, T_30)
    node T_33 = not(UInt<64>("h00"))
    node T_34 = bits(io.addr, 2, 2)
    node T_35 = shl(T_34, 31)
    node mask = xor(T_33, T_35)
    node T_37 = and(io.lhs, mask)
    node T_38 = and(rhs, mask)
    node T_39 = add(T_37, T_38)
    node adder_out = tail(T_39, 1)
    node T_41 = bits(io.addr, 2, 2)
    node T_43 = eq(T_41, UInt<1>("h00"))
    node T_44 = and(word, T_43)
    node T_45 = bits(io.lhs, 31, 31)
    node T_46 = bits(io.lhs, 63, 63)
    node cmp_lhs = mux(T_44, T_45, T_46)
    node T_48 = bits(io.addr, 2, 2)
    node T_50 = eq(T_48, UInt<1>("h00"))
    node T_51 = and(word, T_50)
    node T_52 = bits(rhs, 31, 31)
    node T_53 = bits(rhs, 63, 63)
    node cmp_rhs = mux(T_51, T_52, T_53)
    node T_55 = bits(io.lhs, 31, 0)
    node T_56 = bits(rhs, 31, 0)
    node lt_lo = lt(T_55, T_56)
    node T_58 = bits(io.lhs, 63, 32)
    node T_59 = bits(rhs, 63, 32)
    node lt_hi = lt(T_58, T_59)
    node T_61 = bits(io.lhs, 63, 32)
    node T_62 = bits(rhs, 63, 32)
    node eq_hi = eq(T_61, T_62)
    node T_64 = bits(io.addr, 2, 2)
    node T_65 = mux(T_64, lt_hi, lt_lo)
    node T_66 = and(eq_hi, lt_lo)
    node T_67 = or(lt_hi, T_66)
    node lt = mux(word, T_65, T_67)
    node T_69 = eq(cmp_lhs, cmp_rhs)
    node T_70 = mux(sgned, cmp_lhs, cmp_rhs)
    node less = mux(T_69, lt, T_70)
    node T_72 = eq(io.cmd, UInt<5>("h08"))
    node T_73 = eq(io.cmd, UInt<5>("h0b"))
    node T_74 = and(io.lhs, rhs)
    node T_75 = eq(io.cmd, UInt<5>("h0a"))
    node T_76 = or(io.lhs, rhs)
    node T_77 = eq(io.cmd, UInt<5>("h09"))
    node T_78 = xor(io.lhs, rhs)
    node T_79 = mux(less, min, max)
    node T_81 = eq(T_10, UInt<1>("h00"))
    node T_82 = bits(io.rhs, 7, 0)
    node T_83 = cat(T_82, T_82)
    node T_84 = cat(T_83, T_83)
    node T_85 = cat(T_84, T_84)
    node T_87 = eq(T_10, UInt<1>("h01"))
    node T_88 = bits(io.rhs, 15, 0)
    node T_89 = cat(T_88, T_88)
    node T_90 = cat(T_89, T_89)
    node T_92 = eq(T_10, UInt<2>("h02"))
    node T_93 = bits(io.rhs, 31, 0)
    node T_94 = cat(T_93, T_93)
    node T_95 = mux(T_92, T_94, io.rhs)
    node T_96 = mux(T_87, T_90, T_95)
    node T_97 = mux(T_81, T_85, T_96)
    node T_98 = mux(T_79, io.lhs, T_97)
    node T_99 = mux(T_77, T_78, T_98)
    node T_100 = mux(T_75, T_76, T_99)
    node T_101 = mux(T_73, T_74, T_100)
    node out = mux(T_72, adder_out, T_101)
    node T_104 = bits(io.addr, 0, 0)
    node T_106 = mux(T_104, UInt<1>("h01"), UInt<1>("h00"))
    node T_108 = geq(T_10, UInt<1>("h01"))
    node T_111 = mux(T_108, UInt<1>("h01"), UInt<1>("h00"))
    node T_112 = or(T_106, T_111)
    node T_113 = bits(io.addr, 0, 0)
    node T_115 = mux(T_113, UInt<1>("h00"), UInt<1>("h01"))
    node T_116 = cat(T_112, T_115)
    node T_117 = bits(io.addr, 1, 1)
    node T_119 = mux(T_117, T_116, UInt<1>("h00"))
    node T_121 = geq(T_10, UInt<2>("h02"))
    node T_124 = mux(T_121, UInt<2>("h03"), UInt<1>("h00"))
    node T_125 = or(T_119, T_124)
    node T_126 = bits(io.addr, 1, 1)
    node T_128 = mux(T_126, UInt<1>("h00"), T_116)
    node T_129 = cat(T_125, T_128)
    node T_130 = bits(io.addr, 2, 2)
    node T_132 = mux(T_130, T_129, UInt<1>("h00"))
    node T_134 = geq(T_10, UInt<2>("h03"))
    node T_137 = mux(T_134, UInt<4>("h0f"), UInt<1>("h00"))
    node T_138 = or(T_132, T_137)
    node T_139 = bits(io.addr, 2, 2)
    node T_141 = mux(T_139, UInt<1>("h00"), T_129)
    node T_142 = cat(T_138, T_141)
    node T_143 = bits(T_142, 0, 0)
    node T_144 = bits(T_142, 1, 1)
    node T_145 = bits(T_142, 2, 2)
    node T_146 = bits(T_142, 3, 3)
    node T_147 = bits(T_142, 4, 4)
    node T_148 = bits(T_142, 5, 5)
    node T_149 = bits(T_142, 6, 6)
    node T_150 = bits(T_142, 7, 7)
    wire T_152 : UInt<1>[8]
    T_152[0] <= T_143
    T_152[1] <= T_144
    T_152[2] <= T_145
    T_152[3] <= T_146
    T_152[4] <= T_147
    T_152[5] <= T_148
    T_152[6] <= T_149
    T_152[7] <= T_150
    node T_163 = sub(UInt<8>("h00"), T_152[0])
    node T_164 = tail(T_163, 1)
    node T_166 = sub(UInt<8>("h00"), T_152[1])
    node T_167 = tail(T_166, 1)
    node T_169 = sub(UInt<8>("h00"), T_152[2])
    node T_170 = tail(T_169, 1)
    node T_172 = sub(UInt<8>("h00"), T_152[3])
    node T_173 = tail(T_172, 1)
    node T_175 = sub(UInt<8>("h00"), T_152[4])
    node T_176 = tail(T_175, 1)
    node T_178 = sub(UInt<8>("h00"), T_152[5])
    node T_179 = tail(T_178, 1)
    node T_181 = sub(UInt<8>("h00"), T_152[6])
    node T_182 = tail(T_181, 1)
    node T_184 = sub(UInt<8>("h00"), T_152[7])
    node T_185 = tail(T_184, 1)
    wire T_187 : UInt<8>[8]
    T_187[0] <= T_164
    T_187[1] <= T_167
    T_187[2] <= T_170
    T_187[3] <= T_173
    T_187[4] <= T_176
    T_187[5] <= T_179
    T_187[6] <= T_182
    T_187[7] <= T_185
    node T_197 = cat(T_187[7], T_187[6])
    node T_198 = cat(T_187[5], T_187[4])
    node T_199 = cat(T_197, T_198)
    node T_200 = cat(T_187[3], T_187[2])
    node T_201 = cat(T_187[1], T_187[0])
    node T_202 = cat(T_200, T_201)
    node wmask = cat(T_199, T_202)
    node T_204 = and(wmask, out)
    node T_205 = not(wmask)
    node T_206 = and(T_205, io.lhs)
    node T_207 = or(T_204, T_206)
    io.out <= T_207
    
  module LockingArbiter_109 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, chosen : UInt<1>}
    
    io is invalid
    reg T_700 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_702 : UInt, clk with : (reset => (reset, UInt<1>("h01")))
    wire T_704 : UInt<1>
    T_704 is invalid
    io.out.valid <= io.in[T_704].valid
    io.out.bits <- io.in[T_704].bits
    io.chosen <= T_704
    io.in[T_704].ready <= UInt<1>("h00")
    node T_897 = or(UInt<1>("h00"), io.in[0].valid)
    node T_899 = eq(T_897, UInt<1>("h00"))
    node T_901 = eq(T_702, UInt<1>("h00"))
    node T_902 = mux(T_700, T_901, UInt<1>("h01"))
    node T_903 = and(T_902, io.out.ready)
    io.in[0].ready <= T_903
    node T_905 = eq(T_702, UInt<1>("h01"))
    node T_906 = mux(T_700, T_905, T_899)
    node T_907 = and(T_906, io.out.ready)
    io.in[1].ready <= T_907
    reg T_909 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    node T_911 = add(T_909, UInt<1>("h01"))
    node T_912 = tail(T_911, 1)
    node T_913 = and(io.out.ready, io.out.valid)
    when T_913 :
      wire T_916 : UInt<2>[3]
      T_916[0] <= UInt<1>("h00")
      T_916[1] <= UInt<1>("h01")
      T_916[2] <= UInt<2>("h02")
      node T_921 = eq(T_916[0], io.out.bits.r_type)
      node T_922 = eq(T_916[1], io.out.bits.r_type)
      node T_923 = eq(T_916[2], io.out.bits.r_type)
      node T_925 = or(UInt<1>("h00"), T_921)
      node T_926 = or(T_925, T_922)
      node T_927 = or(T_926, T_923)
      node T_928 = and(UInt<1>("h01"), T_927)
      when T_928 :
        T_909 <= T_912
        node T_930 = eq(T_700, UInt<1>("h00"))
        when T_930 :
          T_700 <= UInt<1>("h01")
          node T_932 = and(io.in[0].ready, io.in[0].valid)
          node T_933 = and(io.in[1].ready, io.in[1].valid)
          wire T_935 : UInt<1>[2]
          T_935[0] <= T_932
          T_935[1] <= T_933
          node T_941 = mux(T_935[0], UInt<1>("h00"), UInt<1>("h01"))
          T_702 <= T_941
          skip
        skip
      node T_943 = eq(T_912, UInt<1>("h00"))
      when T_943 :
        T_700 <= UInt<1>("h00")
        skip
      skip
    node choose = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_948 = mux(T_700, T_702, choose)
    T_704 <= T_948
    
  module HellaCache : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}
    
    io is invalid
    inst wb of WritebackUnit
    wb.io is invalid
    wb.clk <= clk
    wb.reset <= reset
    inst prober of ProbeUnit
    prober.io is invalid
    prober.clk <= clk
    prober.reset <= reset
    inst mshrs of MSHRFile
    mshrs.io is invalid
    mshrs.clk <= clk
    mshrs.reset <= reset
    io.cpu.req.ready <= UInt<1>("h01")
    node T_1622 = and(io.cpu.req.ready, io.cpu.req.valid)
    reg s1_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    s1_valid <= T_1622
    reg s1_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk
    node T_1680 = eq(io.cpu.req.bits.kill, UInt<1>("h00"))
    node s1_valid_masked = and(s1_valid, T_1680)
    reg s1_replay : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg s1_clk_en : UInt<1>, clk
    reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    s2_valid <= s1_valid_masked
    node T_1688 = and(s1_valid, io.cpu.req.bits.kill)
    reg s2_killed : UInt<1>, clk
    s2_killed <= T_1688
    reg s2_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk
    reg T_1745 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_1745 <= s1_replay
    node T_1746 = neq(s2_req.cmd, UInt<5>("h05"))
    node s2_replay = and(T_1745, T_1746)
    wire s2_recycle : UInt<1>
    s2_recycle is invalid
    wire s2_valid_masked : UInt<1>
    s2_valid_masked is invalid
    reg s3_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg s3_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk
    reg s3_way : UInt, clk
    reg s1_recycled : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    when s1_clk_en :
      s1_recycled <= s2_recycle
      skip
    node T_1812 = eq(s1_req.cmd, UInt<5>("h00"))
    node T_1813 = eq(s1_req.cmd, UInt<5>("h06"))
    node T_1814 = or(T_1812, T_1813)
    node T_1815 = eq(s1_req.cmd, UInt<5>("h07"))
    node T_1816 = or(T_1814, T_1815)
    node T_1817 = bits(s1_req.cmd, 3, 3)
    node T_1818 = eq(s1_req.cmd, UInt<5>("h04"))
    node T_1819 = or(T_1817, T_1818)
    node s1_read = or(T_1816, T_1819)
    node T_1821 = eq(s1_req.cmd, UInt<5>("h01"))
    node T_1822 = eq(s1_req.cmd, UInt<5>("h07"))
    node T_1823 = or(T_1821, T_1822)
    node T_1824 = bits(s1_req.cmd, 3, 3)
    node T_1825 = eq(s1_req.cmd, UInt<5>("h04"))
    node T_1826 = or(T_1824, T_1825)
    node s1_write = or(T_1823, T_1826)
    node T_1828 = or(s1_read, s1_write)
    node T_1829 = eq(s1_req.cmd, UInt<5>("h02"))
    node T_1830 = eq(s1_req.cmd, UInt<5>("h03"))
    node T_1831 = or(T_1829, T_1830)
    node s1_readwrite = or(T_1828, T_1831)
    inst dtlb of TLB
    dtlb.io is invalid
    dtlb.clk <= clk
    dtlb.reset <= reset
    io.ptw <- dtlb.io.ptw
    node T_1834 = and(s1_valid_masked, s1_readwrite)
    node T_1836 = eq(s1_req.phys, UInt<1>("h00"))
    node T_1837 = and(T_1834, T_1836)
    dtlb.io.req.valid <= T_1837
    dtlb.io.req.bits.passthrough <= s1_req.phys
    dtlb.io.req.bits.asid <= UInt<1>("h00")
    node T_1839 = shr(s1_req.addr, 12)
    dtlb.io.req.bits.vpn <= T_1839
    dtlb.io.req.bits.instruction <= UInt<1>("h00")
    dtlb.io.req.bits.store <= s1_write
    node T_1842 = eq(dtlb.io.req.ready, UInt<1>("h00"))
    node T_1844 = eq(io.cpu.req.bits.phys, UInt<1>("h00"))
    node T_1845 = and(T_1842, T_1844)
    when T_1845 :
      io.cpu.req.ready <= UInt<1>("h00")
      skip
    when io.cpu.req.valid :
      s1_req <- io.cpu.req.bits
      skip
    when wb.io.meta_read.valid :
      node T_1847 = cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx)
      node T_1848 = shl(T_1847, 6)
      s1_req.addr <= T_1848
      s1_req.phys <= UInt<1>("h01")
      skip
    when prober.io.meta_read.valid :
      node T_1850 = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx)
      node T_1851 = shl(T_1850, 6)
      s1_req.addr <= T_1851
      s1_req.phys <= UInt<1>("h01")
      skip
    when mshrs.io.replay.valid :
      s1_req <- mshrs.io.replay.bits
      skip
    when s2_recycle :
      s1_req <- s2_req
      skip
    node T_1853 = bits(s1_req.addr, 11, 0)
    node s1_addr = cat(dtlb.io.resp.ppn, T_1853)
    when s1_clk_en :
      s2_req.kill <= s1_req.kill
      s2_req.typ <= s1_req.typ
      s2_req.phys <= s1_req.phys
      s2_req.addr <= s1_addr
      when s1_write :
        node T_1855 = mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.req.bits.data)
        s2_req.data <= T_1855
        skip
      when s1_recycled :
        s2_req.data <= s1_req.data
        skip
      s2_req.tag <= s1_req.tag
      s2_req.cmd <= s1_req.cmd
      skip
    node T_1857 = bits(s1_req.typ, 1, 0)
    node T_1859 = dshl(UInt<1>("h01"), T_1857)
    node T_1861 = sub(T_1859, UInt<1>("h01"))
    node T_1862 = tail(T_1861, 1)
    node T_1863 = bits(T_1862, 2, 0)
    node T_1864 = and(s1_req.addr, T_1863)
    node misaligned = neq(T_1864, UInt<1>("h00"))
    node T_1867 = and(s1_read, misaligned)
    io.cpu.xcpt.ma.ld <= T_1867
    node T_1868 = and(s1_write, misaligned)
    io.cpu.xcpt.ma.st <= T_1868
    node T_1869 = and(s1_read, dtlb.io.resp.xcpt_ld)
    io.cpu.xcpt.pf.ld <= T_1869
    node T_1870 = and(s1_write, dtlb.io.resp.xcpt_st)
    io.cpu.xcpt.pf.st <= T_1870
    node T_1871 = or(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st)
    node T_1872 = or(T_1871, io.cpu.xcpt.pf.ld)
    node T_1873 = or(T_1872, io.cpu.xcpt.pf.st)
    reg T_1874 : UInt<1>, clk
    T_1874 <= T_1873
    node T_1875 = and(T_1874, io.cpu.resp.valid)
    node T_1877 = eq(T_1875, UInt<1>("h00"))
    node T_1879 = eq(reset, UInt<1>("h00"))
    when T_1879 :
      node T_1881 = eq(T_1877, UInt<1>("h00"))
      when T_1881 :
        node T_1883 = eq(reset, UInt<1>("h00"))
        when T_1883 :
          printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): DCache exception occurred - cache response not killed.")
          skip
        stop(clk, UInt<1>(1), 1)
        skip
      skip
    inst meta of MetadataArray
    meta.io is invalid
    meta.clk <= clk
    meta.reset <= reset
    inst metaReadArb of Arbiter_105
    metaReadArb.io is invalid
    metaReadArb.clk <= clk
    metaReadArb.reset <= reset
    inst metaWriteArb of Arbiter_94
    metaWriteArb.io is invalid
    metaWriteArb.clk <= clk
    metaWriteArb.reset <= reset
    meta.io.read <- metaReadArb.io.out
    meta.io.write <- metaWriteArb.io.out
    inst data of DataArray
    data.io is invalid
    data.clk <= clk
    data.reset <= reset
    inst readArb of Arbiter_107
    readArb.io is invalid
    readArb.clk <= clk
    readArb.reset <= reset
    inst writeArb of Arbiter_108
    writeArb.io is invalid
    writeArb.clk <= clk
    writeArb.reset <= reset
    data.io.write.valid <= writeArb.io.out.valid
    writeArb.io.out.ready <= data.io.write.ready
    data.io.write.bits <- writeArb.io.out.bits
    node T_2141 = bits(writeArb.io.out.bits.data, 63, 0)
    node T_2142 = bits(writeArb.io.out.bits.data, 127, 64)
    wire T_2144 : UInt<64>[2]
    T_2144[0] <= T_2141
    T_2144[1] <= T_2142
    node T_2148 = cat(T_2144[1], T_2144[0])
    data.io.write.bits.data <= T_2148
    metaReadArb.io.in[4].valid <= io.cpu.req.valid
    node T_2149 = shr(io.cpu.req.bits.addr, 6)
    metaReadArb.io.in[4].bits.idx <= T_2149
    node T_2151 = eq(metaReadArb.io.in[4].ready, UInt<1>("h00"))
    when T_2151 :
      io.cpu.req.ready <= UInt<1>("h00")
      skip
    readArb.io.in[3].valid <= io.cpu.req.valid
    readArb.io.in[3].bits.addr <= io.cpu.req.bits.addr
    node T_2154 = not(UInt<4>("h00"))
    readArb.io.in[3].bits.way_en <= T_2154
    node T_2156 = eq(readArb.io.in[3].ready, UInt<1>("h00"))
    when T_2156 :
      io.cpu.req.ready <= UInt<1>("h00")
      skip
    metaReadArb.io.in[0].valid <= s2_recycle
    node T_2158 = shr(s2_req.addr, 6)
    metaReadArb.io.in[0].bits.idx <= T_2158
    readArb.io.in[0].valid <= s2_recycle
    readArb.io.in[0].bits.addr <= s2_req.addr
    node T_2160 = not(UInt<4>("h00"))
    readArb.io.in[0].bits.way_en <= T_2160
    node T_2161 = shr(s1_addr, 12)
    node T_2162 = eq(meta.io.resp[0].tag, T_2161)
    node T_2163 = shr(s1_addr, 12)
    node T_2164 = eq(meta.io.resp[1].tag, T_2163)
    node T_2165 = shr(s1_addr, 12)
    node T_2166 = eq(meta.io.resp[2].tag, T_2165)
    node T_2167 = shr(s1_addr, 12)
    node T_2168 = eq(meta.io.resp[3].tag, T_2167)
    wire T_2170 : UInt<1>[4]
    T_2170[0] <= T_2162
    T_2170[1] <= T_2164
    T_2170[2] <= T_2166
    T_2170[3] <= T_2168
    node T_2176 = cat(T_2170[3], T_2170[2])
    node T_2177 = cat(T_2170[1], T_2170[0])
    node s1_tag_eq_way = cat(T_2176, T_2177)
    node T_2179 = bits(s1_tag_eq_way, 0, 0)
    node T_2180 = neq(meta.io.resp[0].coh.state, UInt<1>("h00"))
    node T_2181 = and(T_2179, T_2180)
    node T_2182 = bits(s1_tag_eq_way, 1, 1)
    node T_2183 = neq(meta.io.resp[1].coh.state, UInt<1>("h00"))
    node T_2184 = and(T_2182, T_2183)
    node T_2185 = bits(s1_tag_eq_way, 2, 2)
    node T_2186 = neq(meta.io.resp[2].coh.state, UInt<1>("h00"))
    node T_2187 = and(T_2185, T_2186)
    node T_2188 = bits(s1_tag_eq_way, 3, 3)
    node T_2189 = neq(meta.io.resp[3].coh.state, UInt<1>("h00"))
    node T_2190 = and(T_2188, T_2189)
    wire T_2192 : UInt<1>[4]
    T_2192[0] <= T_2181
    T_2192[1] <= T_2184
    T_2192[2] <= T_2187
    T_2192[3] <= T_2190
    node T_2198 = cat(T_2192[3], T_2192[2])
    node T_2199 = cat(T_2192[1], T_2192[0])
    node s1_tag_match_way = cat(T_2198, T_2199)
    s1_clk_en <= metaReadArb.io.out.valid
    node T_2202 = eq(s1_valid, UInt<1>("h00"))
    node T_2203 = and(s1_clk_en, T_2202)
    node T_2205 = eq(s1_replay, UInt<1>("h00"))
    node s1_writeback = and(T_2203, T_2205)
    reg s2_tag_match_way : UInt<4>, clk
    when s1_clk_en :
      s2_tag_match_way <= s1_tag_match_way
      skip
    node s2_tag_match = neq(s2_tag_match_way, UInt<1>("h00"))
    reg T_2210 : {state : UInt<2>}, clk
    when s1_clk_en :
      T_2210 <- meta.io.resp[0].coh
      skip
    reg T_2235 : {state : UInt<2>}, clk
    when s1_clk_en :
      T_2235 <- meta.io.resp[1].coh
      skip
    reg T_2260 : {state : UInt<2>}, clk
    when s1_clk_en :
      T_2260 <- meta.io.resp[2].coh
      skip
    reg T_2285 : {state : UInt<2>}, clk
    when s1_clk_en :
      T_2285 <- meta.io.resp[3].coh
      skip
    wire T_2335 : {state : UInt<2>}[4]
    T_2335[0] <- T_2210
    T_2335[1] <- T_2235
    T_2335[2] <- T_2260
    T_2335[3] <- T_2285
    node T_2461 = bits(s2_tag_match_way, 0, 0)
    node T_2462 = bits(s2_tag_match_way, 1, 1)
    node T_2463 = bits(s2_tag_match_way, 2, 2)
    node T_2464 = bits(s2_tag_match_way, 3, 3)
    node T_2466 = mux(T_2461, T_2335[0].state, UInt<1>("h00"))
    node T_2468 = mux(T_2462, T_2335[1].state, UInt<1>("h00"))
    node T_2470 = mux(T_2463, T_2335[2].state, UInt<1>("h00"))
    node T_2472 = mux(T_2464, T_2335[3].state, UInt<1>("h00"))
    node T_2498 = or(T_2466, T_2468)
    node T_2499 = or(T_2498, T_2470)
    node T_2500 = or(T_2499, T_2472)
    wire s2_hit_state : {state : UInt<2>}
    s2_hit_state is invalid
    node T_2551 = bits(T_2500, 1, 0)
    s2_hit_state.state <= T_2551
    node T_2552 = eq(s2_req.cmd, UInt<5>("h01"))
    node T_2553 = eq(s2_req.cmd, UInt<5>("h07"))
    node T_2554 = or(T_2552, T_2553)
    node T_2555 = bits(s2_req.cmd, 3, 3)
    node T_2556 = eq(s2_req.cmd, UInt<5>("h04"))
    node T_2557 = or(T_2555, T_2556)
    node T_2558 = or(T_2554, T_2557)
    node T_2559 = eq(s2_req.cmd, UInt<5>("h03"))
    node T_2560 = or(T_2558, T_2559)
    node T_2561 = eq(s2_req.cmd, UInt<5>("h06"))
    node T_2562 = or(T_2560, T_2561)
    wire T_2564 : UInt<2>[2]
    T_2564[0] <= UInt<2>("h02")
    T_2564[1] <= UInt<2>("h03")
    node T_2568 = eq(T_2564[0], s2_hit_state.state)
    node T_2569 = eq(T_2564[1], s2_hit_state.state)
    node T_2571 = or(UInt<1>("h00"), T_2568)
    node T_2572 = or(T_2571, T_2569)
    wire T_2574 : UInt<2>[3]
    T_2574[0] <= UInt<1>("h01")
    T_2574[1] <= UInt<2>("h02")
    T_2574[2] <= UInt<2>("h03")
    node T_2579 = eq(T_2574[0], s2_hit_state.state)
    node T_2580 = eq(T_2574[1], s2_hit_state.state)
    node T_2581 = eq(T_2574[2], s2_hit_state.state)
    node T_2583 = or(UInt<1>("h00"), T_2579)
    node T_2584 = or(T_2583, T_2580)
    node T_2585 = or(T_2584, T_2581)
    node T_2586 = mux(T_2562, T_2572, T_2585)
    node T_2587 = and(s2_tag_match, T_2586)
    node T_2588 = eq(s2_req.cmd, UInt<5>("h01"))
    node T_2589 = eq(s2_req.cmd, UInt<5>("h07"))
    node T_2590 = or(T_2588, T_2589)
    node T_2591 = bits(s2_req.cmd, 3, 3)
    node T_2592 = eq(s2_req.cmd, UInt<5>("h04"))
    node T_2593 = or(T_2591, T_2592)
    node T_2594 = or(T_2590, T_2593)
    node T_2595 = mux(T_2594, UInt<2>("h03"), s2_hit_state.state)
    wire T_2621 : {state : UInt<2>}
    T_2621 is invalid
    T_2621.state <= T_2595
    node T_2646 = eq(s2_hit_state.state, T_2621.state)
    node s2_hit = and(T_2587, T_2646)
    reg lrsc_count : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    node lrsc_valid = neq(lrsc_count, UInt<1>("h00"))
    reg lrsc_addr : UInt, clk
    node s2_lr = eq(s2_req.cmd, UInt<5>("h06"))
    node s2_sc = eq(s2_req.cmd, UInt<5>("h07"))
    node T_2656 = shr(s2_req.addr, 6)
    node T_2657 = eq(lrsc_addr, T_2656)
    node s2_lrsc_addr_match = and(lrsc_valid, T_2657)
    node T_2660 = eq(s2_lrsc_addr_match, UInt<1>("h00"))
    node s2_sc_fail = and(s2_sc, T_2660)
    when lrsc_valid :
      node T_2663 = sub(lrsc_count, UInt<1>("h01"))
      node T_2664 = tail(T_2663, 1)
      lrsc_count <= T_2664
      skip
    node T_2665 = and(s2_valid_masked, s2_hit)
    node T_2666 = or(T_2665, s2_replay)
    when T_2666 :
      when s2_lr :
        node T_2668 = eq(lrsc_valid, UInt<1>("h00"))
        when T_2668 :
          lrsc_count <= UInt<5>("h01f")
          skip
        node T_2670 = shr(s2_req.addr, 6)
        lrsc_addr <= T_2670
        skip
      when s2_sc :
        lrsc_count <= UInt<1>("h00")
        skip
      skip
    when io.cpu.invalidate_lr :
      lrsc_count <= UInt<1>("h00")
      skip
    wire s2_data : UInt<128>[4]
    s2_data is invalid
    reg T_2697 : UInt<64>[2], clk
    node T_2701 = bits(s1_tag_eq_way, 0, 0)
    node T_2702 = and(s1_clk_en, T_2701)
    node T_2706 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2707 = or(UInt<1>("h01"), T_2706)
    node T_2708 = or(T_2707, s1_writeback)
    node T_2709 = and(T_2702, T_2708)
    when T_2709 :
      node T_2710 = shr(data.io.resp[0], 0)
      T_2697[0] <= T_2710
      skip
    node T_2714 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2715 = or(UInt<1>("h00"), T_2714)
    node T_2716 = or(T_2715, s1_writeback)
    node T_2717 = and(T_2702, T_2716)
    when T_2717 :
      node T_2718 = shr(data.io.resp[0], 64)
      T_2697[1] <= T_2718
      skip
    node T_2719 = cat(T_2697[1], T_2697[0])
    s2_data[0] <= T_2719
    reg T_2728 : UInt<64>[2], clk
    node T_2732 = bits(s1_tag_eq_way, 1, 1)
    node T_2733 = and(s1_clk_en, T_2732)
    node T_2737 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2738 = or(UInt<1>("h01"), T_2737)
    node T_2739 = or(T_2738, s1_writeback)
    node T_2740 = and(T_2733, T_2739)
    when T_2740 :
      node T_2741 = shr(data.io.resp[1], 0)
      T_2728[0] <= T_2741
      skip
    node T_2745 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2746 = or(UInt<1>("h00"), T_2745)
    node T_2747 = or(T_2746, s1_writeback)
    node T_2748 = and(T_2733, T_2747)
    when T_2748 :
      node T_2749 = shr(data.io.resp[1], 64)
      T_2728[1] <= T_2749
      skip
    node T_2750 = cat(T_2728[1], T_2728[0])
    s2_data[1] <= T_2750
    reg T_2759 : UInt<64>[2], clk
    node T_2763 = bits(s1_tag_eq_way, 2, 2)
    node T_2764 = and(s1_clk_en, T_2763)
    node T_2768 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2769 = or(UInt<1>("h01"), T_2768)
    node T_2770 = or(T_2769, s1_writeback)
    node T_2771 = and(T_2764, T_2770)
    when T_2771 :
      node T_2772 = shr(data.io.resp[2], 0)
      T_2759[0] <= T_2772
      skip
    node T_2776 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2777 = or(UInt<1>("h00"), T_2776)
    node T_2778 = or(T_2777, s1_writeback)
    node T_2779 = and(T_2764, T_2778)
    when T_2779 :
      node T_2780 = shr(data.io.resp[2], 64)
      T_2759[1] <= T_2780
      skip
    node T_2781 = cat(T_2759[1], T_2759[0])
    s2_data[2] <= T_2781
    reg T_2790 : UInt<64>[2], clk
    node T_2794 = bits(s1_tag_eq_way, 3, 3)
    node T_2795 = and(s1_clk_en, T_2794)
    node T_2799 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2800 = or(UInt<1>("h01"), T_2799)
    node T_2801 = or(T_2800, s1_writeback)
    node T_2802 = and(T_2795, T_2801)
    when T_2802 :
      node T_2803 = shr(data.io.resp[3], 0)
      T_2790[0] <= T_2803
      skip
    node T_2807 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_2808 = or(UInt<1>("h00"), T_2807)
    node T_2809 = or(T_2808, s1_writeback)
    node T_2810 = and(T_2795, T_2809)
    when T_2810 :
      node T_2811 = shr(data.io.resp[3], 64)
      T_2790[1] <= T_2811
      skip
    node T_2812 = cat(T_2790[1], T_2790[0])
    s2_data[3] <= T_2812
    node T_2813 = bits(s2_tag_match_way, 0, 0)
    node T_2814 = bits(s2_tag_match_way, 1, 1)
    node T_2815 = bits(s2_tag_match_way, 2, 2)
    node T_2816 = bits(s2_tag_match_way, 3, 3)
    node T_2818 = mux(T_2813, s2_data[0], UInt<1>("h00"))
    node T_2820 = mux(T_2814, s2_data[1], UInt<1>("h00"))
    node T_2822 = mux(T_2815, s2_data[2], UInt<1>("h00"))
    node T_2824 = mux(T_2816, s2_data[3], UInt<1>("h00"))
    node T_2826 = or(T_2818, T_2820)
    node T_2827 = or(T_2826, T_2822)
    node T_2828 = or(T_2827, T_2824)
    wire s2_data_muxed : UInt<128>
    s2_data_muxed is invalid
    s2_data_muxed <= T_2828
    node T_2830 = bits(s2_data_muxed, 63, 0)
    node T_2831 = bits(s2_data_muxed, 127, 64)
    wire T_2833 : UInt<64>[2]
    T_2833[0] <= T_2830
    T_2833[1] <= T_2831
    node s2_data_corrected = cat(T_2833[1], T_2833[0])
    wire T_2839 : UInt<64>[2]
    T_2839[0] <= T_2830
    T_2839[1] <= T_2831
    node s2_data_uncorrected = cat(T_2839[1], T_2839[0])
    wire T_2848 : UInt<1>[2]
    T_2848[0] <= UInt<1>("h00")
    T_2848[1] <= UInt<1>("h00")
    node T_2852 = cat(T_2848[1], T_2848[0])
    node T_2853 = dshr(T_2852, UInt<1>("h00"))
    node s2_data_correctable = bits(T_2853, 0, 0)
    node T_2855 = and(s2_valid_masked, s2_hit)
    node T_2856 = or(T_2855, s2_replay)
    node T_2858 = eq(s2_sc_fail, UInt<1>("h00"))
    node T_2859 = and(T_2856, T_2858)
    node T_2860 = eq(s2_req.cmd, UInt<5>("h01"))
    node T_2861 = eq(s2_req.cmd, UInt<5>("h07"))
    node T_2862 = or(T_2860, T_2861)
    node T_2863 = bits(s2_req.cmd, 3, 3)
    node T_2864 = eq(s2_req.cmd, UInt<5>("h04"))
    node T_2865 = or(T_2863, T_2864)
    node T_2866 = or(T_2862, T_2865)
    node T_2867 = and(T_2859, T_2866)
    s3_valid <= T_2867
    inst amoalu of AMOALU
    amoalu.io is invalid
    amoalu.clk <= clk
    amoalu.reset <= reset
    node T_2869 = or(s2_valid, s2_replay)
    node T_2870 = eq(s2_req.cmd, UInt<5>("h01"))
    node T_2871 = eq(s2_req.cmd, UInt<5>("h07"))
    node T_2872 = or(T_2870, T_2871)
    node T_2873 = bits(s2_req.cmd, 3, 3)
    node T_2874 = eq(s2_req.cmd, UInt<5>("h04"))
    node T_2875 = or(T_2873, T_2874)
    node T_2876 = or(T_2872, T_2875)
    node T_2877 = or(T_2876, s2_data_correctable)
    node T_2878 = and(T_2869, T_2877)
    when T_2878 :
      s3_req <- s2_req
      node T_2879 = mux(s2_data_correctable, s2_data_corrected, amoalu.io.out)
      s3_req.data <= T_2879
      s3_way <= s2_tag_match_way
      skip
    writeArb.io.in[0].bits.addr <= s3_req.addr
    node rowIdx = bits(s3_req.addr, 3, 3)
    node rowWMask = dshl(UInt<1>("h01"), rowIdx)
    writeArb.io.in[0].bits.wmask <= rowWMask
    node T_2883 = cat(s3_req.data, s3_req.data)
    writeArb.io.in[0].bits.data <= T_2883
    writeArb.io.in[0].valid <= s3_valid
    writeArb.io.in[0].bits.way_en <= s3_way
    wire T_2885 : UInt<1>
    T_2885 is invalid
    T_2885 <= UInt<1>("h00")
    reg T_2888 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01")))
    when T_2885 :
      node T_2889 = bits(T_2888, 0, 0)
      node T_2890 = bits(T_2888, 2, 2)
      node T_2891 = xor(T_2889, T_2890)
      node T_2892 = bits(T_2888, 3, 3)
      node T_2893 = xor(T_2891, T_2892)
      node T_2894 = bits(T_2888, 5, 5)
      node T_2895 = xor(T_2893, T_2894)
      node T_2896 = bits(T_2888, 15, 1)
      node T_2897 = cat(T_2895, T_2896)
      T_2888 <= T_2897
      skip
    node T_2898 = bits(T_2888, 1, 0)
    node s1_replaced_way_en = dshl(UInt<1>("h01"), T_2898)
    node T_2901 = bits(T_2888, 1, 0)
    reg T_2902 : UInt<2>, clk
    when s1_clk_en :
      T_2902 <= T_2901
      skip
    node s2_replaced_way_en = dshl(UInt<1>("h01"), T_2902)
    node T_2905 = bits(s1_replaced_way_en, 0, 0)
    node T_2906 = and(s1_clk_en, T_2905)
    reg T_2907 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk
    when T_2906 :
      T_2907 <- meta.io.resp[0]
      skip
    node T_2980 = bits(s1_replaced_way_en, 1, 1)
    node T_2981 = and(s1_clk_en, T_2980)
    reg T_2982 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk
    when T_2981 :
      T_2982 <- meta.io.resp[1]
      skip
    node T_3055 = bits(s1_replaced_way_en, 2, 2)
    node T_3056 = and(s1_clk_en, T_3055)
    reg T_3057 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk
    when T_3056 :
      T_3057 <- meta.io.resp[2]
      skip
    node T_3130 = bits(s1_replaced_way_en, 3, 3)
    node T_3131 = and(s1_clk_en, T_3130)
    reg T_3132 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk
    when T_3131 :
      T_3132 <- meta.io.resp[3]
      skip
    wire T_3278 : {tag : UInt<20>, coh : {state : UInt<2>}}[4]
    T_3278[0] <- T_2907
    T_3278[1] <- T_2982
    T_3278[2] <- T_3057
    T_3278[3] <- T_3132
    node T_3644 = bits(s2_replaced_way_en, 0, 0)
    node T_3645 = bits(s2_replaced_way_en, 1, 1)
    node T_3646 = bits(s2_replaced_way_en, 2, 2)
    node T_3647 = bits(s2_replaced_way_en, 3, 3)
    node T_3648 = cat(T_3278[0].tag, T_3278[0].coh.state)
    node T_3650 = mux(T_3644, T_3648, UInt<1>("h00"))
    node T_3651 = cat(T_3278[1].tag, T_3278[1].coh.state)
    node T_3653 = mux(T_3645, T_3651, UInt<1>("h00"))
    node T_3654 = cat(T_3278[2].tag, T_3278[2].coh.state)
    node T_3656 = mux(T_3646, T_3654, UInt<1>("h00"))
    node T_3657 = cat(T_3278[3].tag, T_3278[3].coh.state)
    node T_3659 = mux(T_3647, T_3657, UInt<1>("h00"))
    node T_3733 = or(T_3650, T_3653)
    node T_3734 = or(T_3733, T_3656)
    node T_3735 = or(T_3734, T_3659)
    wire s2_repl_meta : {tag : UInt<20>, coh : {state : UInt<2>}}
    s2_repl_meta is invalid
    node T_3882 = bits(T_3735, 1, 0)
    s2_repl_meta.coh.state <= T_3882
    node T_3883 = bits(T_3735, 21, 2)
    s2_repl_meta.tag <= T_3883
    node T_3885 = eq(s2_hit, UInt<1>("h00"))
    node T_3886 = and(s2_valid_masked, T_3885)
    node T_3887 = eq(s2_req.cmd, UInt<5>("h02"))
    node T_3888 = eq(s2_req.cmd, UInt<5>("h03"))
    node T_3889 = or(T_3887, T_3888)
    node T_3890 = eq(s2_req.cmd, UInt<5>("h00"))
    node T_3891 = eq(s2_req.cmd, UInt<5>("h06"))
    node T_3892 = or(T_3890, T_3891)
    node T_3893 = eq(s2_req.cmd, UInt<5>("h07"))
    node T_3894 = or(T_3892, T_3893)
    node T_3895 = bits(s2_req.cmd, 3, 3)
    node T_3896 = eq(s2_req.cmd, UInt<5>("h04"))
    node T_3897 = or(T_3895, T_3896)
    node T_3898 = or(T_3894, T_3897)
    node T_3899 = or(T_3889, T_3898)
    node T_3900 = eq(s2_req.cmd, UInt<5>("h01"))
    node T_3901 = eq(s2_req.cmd, UInt<5>("h07"))
    node T_3902 = or(T_3900, T_3901)
    node T_3903 = bits(s2_req.cmd, 3, 3)
    node T_3904 = eq(s2_req.cmd, UInt<5>("h04"))
    node T_3905 = or(T_3903, T_3904)
    node T_3906 = or(T_3902, T_3905)
    node T_3907 = or(T_3899, T_3906)
    node T_3908 = and(T_3886, T_3907)
    mshrs.io.req.valid <= T_3908
    mshrs.io.req.bits <- s2_req
    mshrs.io.req.bits.tag_match <= s2_tag_match
    wire T_3982 : {tag : UInt<20>, coh : {state : UInt<2>}}
    T_3982 is invalid
    T_3982.tag <= s2_repl_meta.tag
    T_3982.coh <- s2_hit_state
    node T_4055 = mux(s2_tag_match, T_3982, s2_repl_meta)
    mshrs.io.req.bits.old_meta <- T_4055
    node T_4128 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
    mshrs.io.req.bits.way_en <= T_4128
    mshrs.io.req.bits.data <= s2_req.data
    node T_4129 = and(mshrs.io.req.ready, mshrs.io.req.valid)
    when T_4129 :
      T_2885 <= UInt<1>("h01")
      skip
    io.mem.acquire <- mshrs.io.mem_req
    readArb.io.in[1].valid <= mshrs.io.replay.valid
    readArb.io.in[1].bits <- mshrs.io.replay.bits
    node T_4132 = not(UInt<4>("h00"))
    readArb.io.in[1].bits.way_en <= T_4132
    mshrs.io.replay.ready <= readArb.io.in[1].ready
    node T_4133 = and(mshrs.io.replay.valid, readArb.io.in[1].ready)
    s1_replay <= T_4133
    metaReadArb.io.in[1] <- mshrs.io.meta_read
    metaWriteArb.io.in[0] <- mshrs.io.meta_write
    inst releaseArb of LockingArbiter_109
    releaseArb.io is invalid
    releaseArb.clk <= clk
    releaseArb.reset <= reset
    io.mem.release <- releaseArb.io.out
    node T_4166 = eq(lrsc_valid, UInt<1>("h00"))
    node T_4167 = and(io.mem.probe.valid, T_4166)
    prober.io.req.valid <= T_4167
    node T_4169 = eq(lrsc_valid, UInt<1>("h00"))
    node T_4170 = and(prober.io.req.ready, T_4169)
    io.mem.probe.ready <= T_4170
    prober.io.req.bits <- io.mem.probe.bits
    releaseArb.io.in[1] <- prober.io.rep
    prober.io.way_en <= s2_tag_match_way
    prober.io.block_state <- s2_hit_state
    metaReadArb.io.in[2] <- prober.io.meta_read
    metaWriteArb.io.in[1] <- prober.io.meta_write
    prober.io.mshr_rdy <= mshrs.io.probe_rdy
    inst T_4171 of FlowThroughSerializer
    T_4171.io is invalid
    T_4171.clk <= clk
    T_4171.reset <= reset
    T_4171.io.in.valid <= io.mem.grant.valid
    T_4171.io.in.bits <- io.mem.grant.bits
    io.mem.grant.ready <= T_4171.io.in.ready
    node T_4172 = and(T_4171.io.out.ready, T_4171.io.out.valid)
    mshrs.io.mem_grant.valid <= T_4172
    mshrs.io.mem_grant.bits <- T_4171.io.out.bits
    wire T_4176 : UInt<3>[2]
    T_4176[0] <= UInt<3>("h05")
    T_4176[1] <= UInt<3>("h04")
    node T_4180 = eq(T_4176[0], T_4171.io.out.bits.g_type)
    node T_4181 = eq(T_4176[1], T_4171.io.out.bits.g_type)
    node T_4183 = or(UInt<1>("h00"), T_4180)
    node T_4184 = or(T_4183, T_4181)
    wire T_4186 : UInt<1>[2]
    T_4186[0] <= UInt<1>("h00")
    T_4186[1] <= UInt<1>("h01")
    node T_4190 = eq(T_4186[0], T_4171.io.out.bits.g_type)
    node T_4191 = eq(T_4186[1], T_4171.io.out.bits.g_type)
    node T_4193 = or(UInt<1>("h00"), T_4190)
    node T_4194 = or(T_4193, T_4191)
    node T_4195 = mux(T_4171.io.out.bits.is_builtin_type, T_4184, T_4194)
    node T_4197 = eq(T_4195, UInt<1>("h00"))
    node T_4198 = or(writeArb.io.in[1].ready, T_4197)
    T_4171.io.out.ready <= T_4198
    wire T_4202 : UInt<3>[2]
    T_4202[0] <= UInt<3>("h05")
    T_4202[1] <= UInt<3>("h04")
    node T_4206 = eq(T_4202[0], T_4171.io.out.bits.g_type)
    node T_4207 = eq(T_4202[1], T_4171.io.out.bits.g_type)
    node T_4209 = or(UInt<1>("h00"), T_4206)
    node T_4210 = or(T_4209, T_4207)
    wire T_4212 : UInt<1>[2]
    T_4212[0] <= UInt<1>("h00")
    T_4212[1] <= UInt<1>("h01")
    node T_4216 = eq(T_4212[0], T_4171.io.out.bits.g_type)
    node T_4217 = eq(T_4212[1], T_4171.io.out.bits.g_type)
    node T_4219 = or(UInt<1>("h00"), T_4216)
    node T_4220 = or(T_4219, T_4217)
    node T_4221 = mux(T_4171.io.out.bits.is_builtin_type, T_4210, T_4220)
    node T_4222 = and(T_4171.io.out.valid, T_4221)
    node T_4224 = lt(T_4171.io.out.bits.client_xact_id, UInt<2>("h02"))
    node T_4225 = and(T_4222, T_4224)
    writeArb.io.in[1].valid <= T_4225
    writeArb.io.in[1].bits.addr <= mshrs.io.refill.addr
    writeArb.io.in[1].bits.way_en <= mshrs.io.refill.way_en
    node T_4227 = not(UInt<2>("h00"))
    writeArb.io.in[1].bits.wmask <= T_4227
    node T_4228 = bits(T_4171.io.out.bits.data, 127, 0)
    writeArb.io.in[1].bits.data <= T_4228
    data.io.read <- readArb.io.out
    node T_4230 = eq(T_4171.io.out.valid, UInt<1>("h00"))
    node T_4231 = or(T_4230, T_4171.io.out.ready)
    readArb.io.out.ready <= T_4231
    inst wbArb of Arbiter_95
    wbArb.io is invalid
    wbArb.clk <= clk
    wbArb.reset <= reset
    wbArb.io.in[0] <- prober.io.wb_req
    wbArb.io.in[1] <- mshrs.io.wb_req
    wb.io.req <- wbArb.io.out
    metaReadArb.io.in[3] <- wb.io.meta_read
    readArb.io.in[2] <- wb.io.data_req
    wb.io.data_resp <= s2_data_corrected
    releaseArb.io.in[0] <- wb.io.release
    reg s4_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    s4_valid <= s3_valid
    node T_4266 = and(s3_valid, metaReadArb.io.out.valid)
    reg s4_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk
    when T_4266 :
      s4_req <- s3_req
      skip
    node T_4321 = or(s2_valid_masked, s2_replay)
    node T_4323 = eq(s2_sc_fail, UInt<1>("h00"))
    node T_4324 = and(T_4321, T_4323)
    node T_4325 = shr(s1_addr, 3)
    node T_4326 = shr(s2_req.addr, 3)
    node T_4327 = eq(T_4325, T_4326)
    node T_4328 = and(T_4324, T_4327)
    node T_4329 = eq(s2_req.cmd, UInt<5>("h01"))
    node T_4330 = eq(s2_req.cmd, UInt<5>("h07"))
    node T_4331 = or(T_4329, T_4330)
    node T_4332 = bits(s2_req.cmd, 3, 3)
    node T_4333 = eq(s2_req.cmd, UInt<5>("h04"))
    node T_4334 = or(T_4332, T_4333)
    node T_4335 = or(T_4331, T_4334)
    node T_4336 = and(T_4328, T_4335)
    node T_4337 = shr(s1_addr, 3)
    node T_4338 = shr(s3_req.addr, 3)
    node T_4339 = eq(T_4337, T_4338)
    node T_4340 = and(s3_valid, T_4339)
    node T_4341 = eq(s3_req.cmd, UInt<5>("h01"))
    node T_4342 = eq(s3_req.cmd, UInt<5>("h07"))
    node T_4343 = or(T_4341, T_4342)
    node T_4344 = bits(s3_req.cmd, 3, 3)
    node T_4345 = eq(s3_req.cmd, UInt<5>("h04"))
    node T_4346 = or(T_4344, T_4345)
    node T_4347 = or(T_4343, T_4346)
    node T_4348 = and(T_4340, T_4347)
    node T_4349 = shr(s1_addr, 3)
    node T_4350 = shr(s4_req.addr, 3)
    node T_4351 = eq(T_4349, T_4350)
    node T_4352 = and(s4_valid, T_4351)
    node T_4353 = eq(s4_req.cmd, UInt<5>("h01"))
    node T_4354 = eq(s4_req.cmd, UInt<5>("h07"))
    node T_4355 = or(T_4353, T_4354)
    node T_4356 = bits(s4_req.cmd, 3, 3)
    node T_4357 = eq(s4_req.cmd, UInt<5>("h04"))
    node T_4358 = or(T_4356, T_4357)
    node T_4359 = or(T_4355, T_4358)
    node T_4360 = and(T_4352, T_4359)
    reg s2_store_bypass_data : UInt<64>, clk
    reg s2_store_bypass : UInt<1>, clk
    when s1_clk_en :
      s2_store_bypass <= UInt<1>("h00")
      node T_4366 = or(T_4336, T_4348)
      node T_4367 = or(T_4366, T_4360)
      when T_4367 :
        node T_4368 = mux(T_4348, s3_req.data, s4_req.data)
        node T_4369 = mux(T_4336, amoalu.io.out, T_4368)
        s2_store_bypass_data <= T_4369
        s2_store_bypass <= UInt<1>("h01")
        skip
      skip
    node T_4372 = cat(UInt<1>("h00"), UInt<6>("h00"))
    node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_4372)
    node s2_data_word = mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
    node T_4375 = bits(s2_req.typ, 1, 0)
    node T_4376 = asSInt(s2_req.typ)
    node T_4378 = geq(T_4376, asSInt(UInt<1>("h00")))
    amoalu.io.addr <= s2_req.addr
    amoalu.io.cmd <= s2_req.cmd
    amoalu.io.typ <= s2_req.typ
    amoalu.io.lhs <= s2_data_word
    amoalu.io.rhs <= s2_req.data
    node T_4379 = and(dtlb.io.req.valid, dtlb.io.resp.miss)
    node T_4380 = bits(s1_req.addr, 11, 6)
    node T_4381 = eq(T_4380, prober.io.meta_write.bits.idx)
    node T_4383 = eq(prober.io.req.ready, UInt<1>("h00"))
    node T_4384 = and(T_4381, T_4383)
    node s1_nack = or(T_4379, T_4384)
    node T_4386 = or(s1_valid, s1_replay)
    reg s2_nack_hit : UInt<1>, clk
    when T_4386 :
      s2_nack_hit <= s1_nack
      skip
    when s2_nack_hit :
      mshrs.io.req.valid <= UInt<1>("h00")
      skip
    node s2_nack_victim = and(s2_hit, mshrs.io.secondary_miss)
    node T_4391 = eq(s2_hit, UInt<1>("h00"))
    node T_4393 = eq(mshrs.io.req.ready, UInt<1>("h00"))
    node s2_nack_miss = and(T_4391, T_4393)
    node T_4395 = or(s2_nack_hit, s2_nack_victim)
    node s2_nack = or(T_4395, s2_nack_miss)
    node T_4398 = eq(s2_nack, UInt<1>("h00"))
    node T_4399 = and(s2_valid, T_4398)
    s2_valid_masked <= T_4399
    node T_4400 = or(s2_valid, s2_replay)
    node T_4401 = and(T_4400, s2_hit)
    node s2_recycle_ecc = and(T_4401, s2_data_correctable)
    reg s2_recycle_next : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_4405 = or(s1_valid, s1_replay)
    when T_4405 :
      s2_recycle_next <= s2_recycle_ecc
      skip
    node T_4406 = or(s2_recycle_ecc, s2_recycle_next)
    s2_recycle <= T_4406
    reg block_miss : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_4409 = or(s2_valid, block_miss)
    node T_4410 = and(T_4409, s2_nack_miss)
    block_miss <= T_4410
    when block_miss :
      io.cpu.req.ready <= UInt<1>("h00")
      skip
    wire cache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}
    cache_resp is invalid
    node T_4701 = and(s2_valid_masked, s2_hit)
    node T_4702 = or(s2_replay, T_4701)
    node T_4704 = eq(s2_data_correctable, UInt<1>("h00"))
    node T_4705 = and(T_4702, T_4704)
    cache_resp.valid <= T_4705
    cache_resp.bits <- s2_req
    node T_4706 = eq(s2_req.cmd, UInt<5>("h00"))
    node T_4707 = eq(s2_req.cmd, UInt<5>("h06"))
    node T_4708 = or(T_4706, T_4707)
    node T_4709 = eq(s2_req.cmd, UInt<5>("h07"))
    node T_4710 = or(T_4708, T_4709)
    node T_4711 = bits(s2_req.cmd, 3, 3)
    node T_4712 = eq(s2_req.cmd, UInt<5>("h04"))
    node T_4713 = or(T_4711, T_4712)
    node T_4714 = or(T_4710, T_4713)
    cache_resp.bits.has_data <= T_4714
    node T_4715 = bits(s2_req.addr, 2, 2)
    node T_4716 = bits(s2_data_word, 63, 32)
    node T_4717 = bits(s2_data_word, 31, 0)
    node T_4718 = mux(T_4715, T_4716, T_4717)
    node T_4720 = and(UInt<1>("h00"), s2_sc)
    node T_4722 = mux(T_4720, UInt<1>("h00"), T_4718)
    node T_4724 = eq(T_4375, UInt<2>("h02"))
    node T_4725 = or(T_4724, T_4720)
    node T_4726 = bits(T_4722, 31, 31)
    node T_4727 = and(T_4378, T_4726)
    node T_4729 = sub(UInt<32>("h00"), T_4727)
    node T_4730 = tail(T_4729, 1)
    node T_4731 = bits(s2_data_word, 63, 32)
    node T_4732 = mux(T_4725, T_4730, T_4731)
    node T_4733 = cat(T_4732, T_4722)
    node T_4734 = bits(s2_req.addr, 1, 1)
    node T_4735 = bits(T_4733, 31, 16)
    node T_4736 = bits(T_4733, 15, 0)
    node T_4737 = mux(T_4734, T_4735, T_4736)
    node T_4739 = and(UInt<1>("h00"), s2_sc)
    node T_4741 = mux(T_4739, UInt<1>("h00"), T_4737)
    node T_4743 = eq(T_4375, UInt<1>("h01"))
    node T_4744 = or(T_4743, T_4739)
    node T_4745 = bits(T_4741, 15, 15)
    node T_4746 = and(T_4378, T_4745)
    node T_4748 = sub(UInt<48>("h00"), T_4746)
    node T_4749 = tail(T_4748, 1)
    node T_4750 = bits(T_4733, 63, 16)
    node T_4751 = mux(T_4744, T_4749, T_4750)
    node T_4752 = cat(T_4751, T_4741)
    node T_4753 = bits(s2_req.addr, 0, 0)
    node T_4754 = bits(T_4752, 15, 8)
    node T_4755 = bits(T_4752, 7, 0)
    node T_4756 = mux(T_4753, T_4754, T_4755)
    node T_4758 = and(UInt<1>("h01"), s2_sc)
    node T_4760 = mux(T_4758, UInt<1>("h00"), T_4756)
    node T_4762 = eq(T_4375, UInt<1>("h00"))
    node T_4763 = or(T_4762, T_4758)
    node T_4764 = bits(T_4760, 7, 7)
    node T_4765 = and(T_4378, T_4764)
    node T_4767 = sub(UInt<56>("h00"), T_4765)
    node T_4768 = tail(T_4767, 1)
    node T_4769 = bits(T_4752, 63, 8)
    node T_4770 = mux(T_4763, T_4768, T_4769)
    node T_4771 = cat(T_4770, T_4760)
    node T_4772 = or(T_4771, s2_sc_fail)
    cache_resp.bits.data <= T_4772
    cache_resp.bits.store_data <= s2_req.data
    node T_4773 = and(s2_valid, s2_nack)
    cache_resp.bits.nack <= T_4773
    cache_resp.bits.replay <= s2_replay
    wire uncache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}
    uncache_resp is invalid
    uncache_resp.bits <- mshrs.io.resp.bits
    uncache_resp.valid <= mshrs.io.resp.valid
    node T_5063 = or(s2_valid, s2_killed)
    node cache_pass = or(T_5063, s2_replay)
    node T_5066 = eq(cache_pass, UInt<1>("h00"))
    mshrs.io.resp.ready <= T_5066
    node T_5067 = mux(cache_pass, cache_resp, uncache_resp)
    io.cpu.resp <- T_5067
    node T_5183 = bits(s2_req.addr, 2, 2)
    node T_5184 = bits(s2_data_word, 63, 32)
    node T_5185 = bits(s2_data_word, 31, 0)
    node T_5186 = mux(T_5183, T_5184, T_5185)
    node T_5188 = and(UInt<1>("h00"), s2_sc)
    node T_5190 = mux(T_5188, UInt<1>("h00"), T_5186)
    node T_5192 = eq(T_4375, UInt<2>("h02"))
    node T_5193 = or(T_5192, T_5188)
    node T_5194 = bits(T_5190, 31, 31)
    node T_5195 = and(T_4378, T_5194)
    node T_5197 = sub(UInt<32>("h00"), T_5195)
    node T_5198 = tail(T_5197, 1)
    node T_5199 = bits(s2_data_word, 63, 32)
    node T_5200 = mux(T_5193, T_5198, T_5199)
    node T_5201 = cat(T_5200, T_5190)
    io.cpu.resp.bits.data_word_bypass <= T_5201
    node T_5203 = eq(s1_valid, UInt<1>("h00"))
    node T_5204 = and(mshrs.io.fence_rdy, T_5203)
    node T_5206 = eq(s2_valid, UInt<1>("h00"))
    node T_5207 = and(T_5204, T_5206)
    io.cpu.ordered <= T_5207
    node T_5208 = and(s1_replay, s1_read)
    io.cpu.replay_next.valid <= T_5208
    io.cpu.replay_next.bits <= s1_req.tag
    
  module RRArbiter_112 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>}
    
    io is invalid
    wire T_152 : UInt<1>
    T_152 is invalid
    io.out.valid <= io.in[T_152].valid
    io.out.bits <- io.in[T_152].bits
    io.chosen <= T_152
    io.in[T_152].ready <= UInt<1>("h00")
    reg T_195 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node T_196 = gt(UInt<1>("h00"), T_195)
    node T_197 = and(io.in[0].valid, T_196)
    node T_199 = gt(UInt<1>("h01"), T_195)
    node T_200 = and(io.in[1].valid, T_199)
    node T_203 = or(UInt<1>("h00"), T_197)
    node T_205 = eq(T_203, UInt<1>("h00"))
    node T_207 = or(UInt<1>("h00"), T_197)
    node T_208 = or(T_207, T_200)
    node T_210 = eq(T_208, UInt<1>("h00"))
    node T_212 = or(UInt<1>("h00"), T_197)
    node T_213 = or(T_212, T_200)
    node T_214 = or(T_213, io.in[0].valid)
    node T_216 = eq(T_214, UInt<1>("h00"))
    node T_218 = gt(UInt<1>("h00"), T_195)
    node T_219 = and(UInt<1>("h01"), T_218)
    node T_220 = or(T_219, T_210)
    node T_222 = gt(UInt<1>("h01"), T_195)
    node T_223 = and(T_205, T_222)
    node T_224 = or(T_223, T_216)
    node T_226 = eq(UInt<1>("h01"), UInt<1>("h00"))
    node T_227 = mux(UInt<1>("h00"), T_226, T_220)
    node T_228 = and(T_227, io.out.ready)
    io.in[0].ready <= T_228
    node T_230 = eq(UInt<1>("h01"), UInt<1>("h01"))
    node T_231 = mux(UInt<1>("h00"), T_230, T_224)
    node T_232 = and(T_231, io.out.ready)
    io.in[1].ready <= T_232
    node T_235 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01"))
    node T_237 = gt(UInt<1>("h01"), T_195)
    node T_238 = and(io.in[1].valid, T_237)
    node T_240 = mux(T_238, UInt<1>("h01"), T_235)
    node T_241 = mux(UInt<1>("h00"), UInt<1>("h01"), T_240)
    T_152 <= T_241
    node T_242 = and(io.out.ready, io.out.valid)
    when T_242 :
      T_195 <= T_152
      skip
    
  module PTW : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}}
    
    io is invalid
    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
    reg count : UInt<2>, clk
    reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clk
    reg r_req_dest : UInt, clk
    reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clk
    node T_1590 = shr(r_req.addr, 18)
    node T_1591 = bits(T_1590, 8, 0)
    node T_1592 = shr(r_req.addr, 9)
    node T_1593 = bits(T_1592, 8, 0)
    node T_1594 = shr(r_req.addr, 0)
    node T_1595 = bits(T_1594, 8, 0)
    wire T_1597 : UInt<9>[3]
    T_1597[0] <= T_1591
    T_1597[1] <= T_1593
    T_1597[2] <= T_1595
    inst arb of RRArbiter_112
    arb.io is invalid
    arb.clk <= clk
    arb.reset <= reset
    arb.io.in[0] <- io.requestor[0].req
    arb.io.in[1] <- io.requestor[1].req
    node T_1609 = eq(state, UInt<1>("h00"))
    arb.io.out.ready <= T_1609
    wire pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}
    pte is invalid
    node T_1631 = bits(io.mem.resp.bits.data, 0, 0)
    pte.v <= T_1631
    node T_1632 = bits(io.mem.resp.bits.data, 4, 1)
    pte.typ <= T_1632
    node T_1633 = bits(io.mem.resp.bits.data, 5, 5)
    pte.r <= T_1633
    node T_1634 = bits(io.mem.resp.bits.data, 6, 6)
    pte.d <= T_1634
    node T_1635 = bits(io.mem.resp.bits.data, 9, 7)
    pte.reserved_for_software <= T_1635
    node T_1636 = bits(io.mem.resp.bits.data, 29, 10)
    pte.ppn <= T_1636
    node T_1637 = cat(r_pte.ppn, T_1597[count])
    node pte_addr = shl(T_1637, 3)
    node T_1639 = and(arb.io.out.ready, arb.io.out.valid)
    when T_1639 :
      r_req <- arb.io.out.bits
      r_req_dest <= arb.io.chosen
      node T_1640 = bits(io.dpath.ptbr, 31, 12)
      r_pte.ppn <= T_1640
      skip
    reg T_1642 : UInt<3>, clk
    reg T_1652 : UInt<1>[3], clk
    node T_1657 = cat(T_1652[1], T_1652[0])
    node T_1658 = cat(T_1652[2], T_1657)
    cmem T_1661 : UInt<32>[3]
    cmem T_1664 : UInt<20>[3]
    infer mport T_1666 = T_1661[UInt<1>("h00")], clk
    node T_1667 = eq(T_1666, pte_addr)
    infer mport T_1669 = T_1661[UInt<1>("h01")], clk
    node T_1670 = eq(T_1669, pte_addr)
    infer mport T_1672 = T_1661[UInt<2>("h02")], clk
    node T_1673 = eq(T_1672, pte_addr)
    wire T_1675 : UInt<1>[3]
    T_1675[0] <= T_1667
    T_1675[1] <= T_1670
    T_1675[2] <= T_1673
    node T_1680 = cat(T_1675[1], T_1675[0])
    node T_1681 = cat(T_1675[2], T_1680)
    node T_1682 = and(T_1681, T_1658)
    node pte_cache_hit = neq(T_1682, UInt<1>("h00"))
    node T_1686 = lt(pte.typ, UInt<2>("h02"))
    node T_1687 = and(pte.v, T_1686)
    node T_1688 = and(io.mem.resp.valid, T_1687)
    node T_1690 = eq(pte_cache_hit, UInt<1>("h00"))
    node T_1691 = and(T_1688, T_1690)
    when T_1691 :
      node T_1692 = not(T_1658)
      node T_1694 = eq(T_1692, UInt<1>("h00"))
      node T_1696 = dshr(T_1642, UInt<1>("h01"))
      node T_1697 = bits(T_1696, 0, 0)
      node T_1698 = cat(UInt<1>("h01"), T_1697)
      node T_1699 = dshr(T_1642, T_1698)
      node T_1700 = bits(T_1699, 0, 0)
      node T_1701 = cat(T_1698, T_1700)
      node T_1702 = bits(T_1701, 1, 0)
      node T_1703 = not(T_1658)
      node T_1704 = bits(T_1703, 0, 0)
      node T_1705 = bits(T_1703, 1, 1)
      node T_1706 = bits(T_1703, 2, 2)
      wire T_1708 : UInt<1>[3]
      T_1708[0] <= T_1704
      T_1708[1] <= T_1705
      T_1708[2] <= T_1706
      node T_1716 = mux(T_1708[1], UInt<1>("h01"), UInt<2>("h02"))
      node T_1717 = mux(T_1708[0], UInt<1>("h00"), T_1716)
      node T_1718 = mux(T_1694, T_1702, T_1717)
      T_1652[T_1718] <= UInt<1>("h01")
      infer mport T_1721 = T_1661[T_1718], clk
      T_1721 <= pte_addr
      infer mport T_1722 = T_1664[T_1718], clk
      T_1722 <= pte.ppn
      skip
    node T_1723 = eq(state, UInt<1>("h01"))
    node T_1724 = and(pte_cache_hit, T_1723)
    when T_1724 :
      node T_1725 = bits(T_1682, 2, 2)
      node T_1726 = bits(T_1682, 1, 0)
      node T_1728 = neq(T_1725, UInt<1>("h00"))
      node T_1729 = or(T_1725, T_1726)
      node T_1730 = bits(T_1729, 1, 1)
      node T_1731 = cat(T_1728, T_1730)
      node T_1733 = bits(T_1731, 1, 1)
      node T_1735 = dshl(UInt<3>("h01"), UInt<1>("h01"))
      node T_1736 = bits(T_1735, 2, 0)
      node T_1737 = not(T_1736)
      node T_1738 = and(T_1642, T_1737)
      node T_1740 = mux(T_1733, UInt<1>("h00"), T_1736)
      node T_1741 = or(T_1738, T_1740)
      node T_1742 = cat(UInt<1>("h01"), T_1733)
      node T_1743 = bits(T_1731, 0, 0)
      node T_1745 = dshl(UInt<3>("h01"), T_1742)
      node T_1746 = bits(T_1745, 2, 0)
      node T_1747 = not(T_1746)
      node T_1748 = and(T_1741, T_1747)
      node T_1750 = mux(T_1743, UInt<1>("h00"), T_1746)
      node T_1751 = or(T_1748, T_1750)
      node T_1752 = cat(T_1742, T_1743)
      T_1642 <= T_1751
      skip
    node T_1753 = or(reset, io.dpath.invalidate)
    when T_1753 :
      T_1652[0] <= UInt<1>("h00")
      T_1652[1] <= UInt<1>("h00")
      T_1652[2] <= UInt<1>("h00")
      skip
    node T_1757 = bits(T_1682, 0, 0)
    node T_1758 = bits(T_1682, 1, 1)
    node T_1759 = bits(T_1682, 2, 2)
    infer mport T_1761 = T_1664[UInt<1>("h00")], clk
    infer mport T_1763 = T_1664[UInt<1>("h01")], clk
    infer mport T_1765 = T_1664[UInt<2>("h02")], clk
    node T_1767 = mux(T_1757, T_1761, UInt<1>("h00"))
    node T_1769 = mux(T_1758, T_1763, UInt<1>("h00"))
    node T_1771 = mux(T_1759, T_1765, UInt<1>("h00"))
    node T_1773 = or(T_1767, T_1769)
    node T_1774 = or(T_1773, T_1771)
    wire pte_cache_data : UInt<20>
    pte_cache_data is invalid
    pte_cache_data <= T_1774
    node T_1776 = bits(r_req.prv, 0, 0)
    node T_1778 = geq(pte.typ, UInt<3>("h04"))
    node T_1779 = and(pte.v, T_1778)
    node T_1780 = bits(pte.typ, 1, 1)
    node T_1781 = and(T_1779, T_1780)
    node T_1783 = geq(pte.typ, UInt<2>("h02"))
    node T_1784 = and(pte.v, T_1783)
    node T_1785 = bits(pte.typ, 0, 0)
    node T_1786 = and(T_1784, T_1785)
    node T_1788 = geq(pte.typ, UInt<2>("h02"))
    node T_1789 = and(pte.v, T_1788)
    node T_1790 = mux(r_req.store, T_1786, T_1789)
    node T_1791 = mux(r_req.fetch, T_1781, T_1790)
    node T_1793 = geq(pte.typ, UInt<2>("h02"))
    node T_1794 = and(pte.v, T_1793)
    node T_1796 = lt(pte.typ, UInt<4>("h08"))
    node T_1797 = and(T_1794, T_1796)
    node T_1798 = bits(pte.typ, 1, 1)
    node T_1799 = and(T_1797, T_1798)
    node T_1801 = geq(pte.typ, UInt<2>("h02"))
    node T_1802 = and(pte.v, T_1801)
    node T_1804 = lt(pte.typ, UInt<4>("h08"))
    node T_1805 = and(T_1802, T_1804)
    node T_1806 = bits(pte.typ, 0, 0)
    node T_1807 = and(T_1805, T_1806)
    node T_1809 = geq(pte.typ, UInt<2>("h02"))
    node T_1810 = and(pte.v, T_1809)
    node T_1812 = lt(pte.typ, UInt<4>("h08"))
    node T_1813 = and(T_1810, T_1812)
    node T_1814 = mux(r_req.store, T_1807, T_1813)
    node T_1815 = mux(r_req.fetch, T_1799, T_1814)
    node perm_ok = mux(T_1776, T_1791, T_1815)
    node T_1818 = eq(pte.r, UInt<1>("h00"))
    node T_1820 = eq(pte.d, UInt<1>("h00"))
    node T_1821 = and(r_req.store, T_1820)
    node T_1822 = or(T_1818, T_1821)
    node set_dirty_bit = and(perm_ok, T_1822)
    node T_1824 = eq(state, UInt<2>("h02"))
    node T_1825 = and(io.mem.resp.valid, T_1824)
    node T_1827 = eq(set_dirty_bit, UInt<1>("h00"))
    node T_1828 = and(T_1825, T_1827)
    when T_1828 :
      r_pte <- pte
      skip
    wire T_1844 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}
    T_1844 is invalid
    T_1844.v <= UInt<1>("h00")
    T_1844.typ <= UInt<4>("h00")
    T_1844.r <= UInt<1>("h00")
    T_1844.d <= UInt<1>("h00")
    T_1844.reserved_for_software <= UInt<3>("h00")
    T_1844.ppn <= UInt<20>("h00")
    wire pte_wdata : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}
    pte_wdata <- T_1844
    pte_wdata.r <= UInt<1>("h01")
    pte_wdata.d <= r_req.store
    node T_1865 = eq(state, UInt<1>("h01"))
    node T_1866 = eq(state, UInt<2>("h03"))
    node T_1867 = or(T_1865, T_1866)
    io.mem.req.valid <= T_1867
    io.mem.req.bits.phys <= UInt<1>("h01")
    node T_1869 = eq(state, UInt<2>("h03"))
    node T_1870 = mux(T_1869, UInt<5>("h0a"), UInt<5>("h00"))
    io.mem.req.bits.cmd <= T_1870
    io.mem.req.bits.typ <= UInt<3>("h03")
    io.mem.req.bits.addr <= pte_addr
    io.mem.req.bits.kill <= UInt<1>("h00")
    node T_1872 = cat(pte_wdata.reserved_for_software, pte_wdata.d)
    node T_1873 = cat(pte_wdata.ppn, T_1872)
    node T_1874 = cat(pte_wdata.typ, pte_wdata.v)
    node T_1875 = cat(pte_wdata.r, T_1874)
    node T_1876 = cat(T_1873, T_1875)
    io.mem.req.bits.data <= T_1876
    node resp_err = eq(state, UInt<3>("h06"))
    node T_1878 = eq(state, UInt<3>("h05"))
    node resp_val = or(T_1878, resp_err)
    node r_resp_ppn = shr(io.mem.req.bits.addr, 12)
    node T_1881 = shr(r_resp_ppn, 18)
    node T_1882 = bits(r_req.addr, 17, 0)
    node T_1883 = cat(T_1881, T_1882)
    node T_1884 = shr(r_resp_ppn, 9)
    node T_1885 = bits(r_req.addr, 8, 0)
    node T_1886 = cat(T_1884, T_1885)
    wire T_1888 : UInt<28>[3]
    T_1888[0] <= T_1883
    T_1888[1] <= T_1886
    T_1888[2] <= r_resp_ppn
    node T_1895 = eq(r_req_dest, UInt<1>("h00"))
    node T_1896 = and(resp_val, T_1895)
    io.requestor[0].resp.valid <= T_1896
    io.requestor[0].resp.bits.error <= resp_err
    io.requestor[0].resp.bits.pte <- r_pte
    io.requestor[0].resp.bits.pte.ppn <= T_1888[count]
    io.requestor[0].invalidate <= io.dpath.invalidate
    io.requestor[0].status <- io.dpath.status
    node T_1898 = eq(r_req_dest, UInt<1>("h01"))
    node T_1899 = and(resp_val, T_1898)
    io.requestor[1].resp.valid <= T_1899
    io.requestor[1].resp.bits.error <= resp_err
    io.requestor[1].resp.bits.pte <- r_pte
    io.requestor[1].resp.bits.pte.ppn <= T_1888[count]
    io.requestor[1].invalidate <= io.dpath.invalidate
    io.requestor[1].status <- io.dpath.status
    node T_1900 = eq(UInt<1>("h00"), state)
    when T_1900 :
      when arb.io.out.valid :
        state <= UInt<1>("h01")
        skip
      count <= UInt<1>("h00")
      skip
    node T_1902 = eq(UInt<1>("h01"), state)
    when T_1902 :
      node T_1904 = lt(count, UInt<2>("h02"))
      node T_1905 = and(pte_cache_hit, T_1904)
      when T_1905 :
        io.mem.req.valid <= UInt<1>("h00")
        state <= UInt<1>("h01")
        node T_1908 = add(count, UInt<1>("h01"))
        node T_1909 = tail(T_1908, 1)
        count <= T_1909
        r_pte.ppn <= pte_cache_data
        skip
      node T_1911 = eq(T_1905, UInt<1>("h00"))
      node T_1912 = and(T_1911, io.mem.req.ready)
      when T_1912 :
        state <= UInt<2>("h02")
        skip
      skip
    node T_1913 = eq(UInt<2>("h02"), state)
    when T_1913 :
      when io.mem.resp.bits.nack :
        state <= UInt<1>("h01")
        skip
      when io.mem.resp.valid :
        state <= UInt<3>("h06")
        node T_1915 = lt(pte.typ, UInt<2>("h02"))
        node T_1916 = and(pte.v, T_1915)
        node T_1918 = lt(count, UInt<2>("h02"))
        node T_1919 = and(T_1916, T_1918)
        when T_1919 :
          state <= UInt<1>("h01")
          node T_1921 = add(count, UInt<1>("h01"))
          node T_1922 = tail(T_1921, 1)
          count <= T_1922
          skip
        node T_1924 = geq(pte.typ, UInt<2>("h02"))
        node T_1925 = and(pte.v, T_1924)
        when T_1925 :
          node T_1926 = mux(set_dirty_bit, UInt<2>("h03"), UInt<3>("h05"))
          state <= T_1926
          skip
        skip
      skip
    node T_1927 = eq(UInt<2>("h03"), state)
    when T_1927 :
      when io.mem.req.ready :
        state <= UInt<3>("h04")
        skip
      skip
    node T_1928 = eq(UInt<3>("h04"), state)
    when T_1928 :
      when io.mem.resp.bits.nack :
        state <= UInt<2>("h03")
        skip
      when io.mem.resp.valid :
        state <= UInt<1>("h01")
        skip
      skip
    node T_1929 = eq(UInt<3>("h05"), state)
    when T_1929 :
      state <= UInt<1>("h00")
      skip
    node T_1930 = eq(UInt<3>("h06"), state)
    when T_1930 :
      state <= UInt<1>("h00")
      skip
    
  module HellaCacheArbiter : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}}
    
    io is invalid
    reg T_5286 : UInt<1>, clk
    T_5286 <= io.requestor[0].req.valid
    reg T_5287 : UInt<1>, clk
    T_5287 <= io.requestor[1].req.valid
    node T_5288 = or(io.requestor[0].req.valid, io.requestor[1].req.valid)
    io.mem.req.valid <= T_5288
    io.requestor[0].req.ready <= io.mem.req.ready
    node T_5290 = eq(io.requestor[0].req.valid, UInt<1>("h00"))
    node T_5291 = and(io.requestor[0].req.ready, T_5290)
    io.requestor[1].req.ready <= T_5291
    io.mem.req.bits <- io.requestor[1].req.bits
    node T_5293 = cat(io.requestor[1].req.bits.tag, UInt<1>("h01"))
    io.mem.req.bits.tag <= T_5293
    when io.requestor[0].req.valid :
      io.mem.req.bits.cmd <= io.requestor[0].req.bits.cmd
      io.mem.req.bits.typ <= io.requestor[0].req.bits.typ
      io.mem.req.bits.addr <= io.requestor[0].req.bits.addr
      io.mem.req.bits.phys <= io.requestor[0].req.bits.phys
      node T_5295 = cat(io.requestor[0].req.bits.tag, UInt<1>("h00"))
      io.mem.req.bits.tag <= T_5295
      skip
    when T_5286 :
      io.mem.req.bits.kill <= io.requestor[0].req.bits.kill
      io.mem.req.bits.data <= io.requestor[0].req.bits.data
      skip
    node T_5296 = bits(io.mem.resp.bits.tag, 0, 0)
    node T_5298 = eq(T_5296, UInt<1>("h00"))
    node T_5299 = and(io.mem.resp.valid, T_5298)
    io.requestor[0].resp.valid <= T_5299
    io.requestor[0].xcpt <- io.mem.xcpt
    io.requestor[0].ordered <= io.mem.ordered
    io.requestor[0].resp.bits <- io.mem.resp.bits
    node T_5300 = shr(io.mem.resp.bits.tag, 1)
    io.requestor[0].resp.bits.tag <= T_5300
    node T_5301 = and(io.mem.resp.bits.nack, T_5298)
    io.requestor[0].resp.bits.nack <= T_5301
    node T_5302 = and(io.mem.resp.bits.replay, T_5298)
    io.requestor[0].resp.bits.replay <= T_5302
    node T_5303 = bits(io.mem.replay_next.bits, 0, 0)
    node T_5305 = eq(T_5303, UInt<1>("h00"))
    node T_5306 = and(io.mem.replay_next.valid, T_5305)
    io.requestor[0].replay_next.valid <= T_5306
    node T_5307 = shr(io.mem.replay_next.bits, 1)
    io.requestor[0].replay_next.bits <= T_5307
    node T_5308 = bits(io.mem.resp.bits.tag, 0, 0)
    node T_5310 = eq(T_5308, UInt<1>("h01"))
    node T_5311 = and(io.mem.resp.valid, T_5310)
    io.requestor[1].resp.valid <= T_5311
    io.requestor[1].xcpt <- io.mem.xcpt
    io.requestor[1].ordered <= io.mem.ordered
    io.requestor[1].resp.bits <- io.mem.resp.bits
    node T_5312 = shr(io.mem.resp.bits.tag, 1)
    io.requestor[1].resp.bits.tag <= T_5312
    node T_5313 = and(io.mem.resp.bits.nack, T_5310)
    io.requestor[1].resp.bits.nack <= T_5313
    node T_5314 = and(io.mem.resp.bits.replay, T_5310)
    io.requestor[1].resp.bits.replay <= T_5314
    node T_5315 = bits(io.mem.replay_next.bits, 0, 0)
    node T_5317 = eq(T_5315, UInt<1>("h01"))
    node T_5318 = and(io.mem.replay_next.valid, T_5317)
    io.requestor[1].replay_next.valid <= T_5318
    node T_5319 = shr(io.mem.replay_next.bits, 1)
    io.requestor[1].replay_next.bits <= T_5319
    
  module FPUDecoder : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}}
    
    io is invalid
    node T_42 = and(io.inst, UInt<32>("h04"))
    node T_44 = eq(T_42, UInt<32>("h04"))
    node T_46 = and(io.inst, UInt<32>("h08000010"))
    node T_48 = eq(T_46, UInt<32>("h08000010"))
    node T_50 = or(UInt<1>("h00"), T_44)
    node T_51 = or(T_50, T_48)
    node T_53 = and(io.inst, UInt<32>("h08"))
    node T_55 = eq(T_53, UInt<32>("h08"))
    node T_57 = and(io.inst, UInt<32>("h010000010"))
    node T_59 = eq(T_57, UInt<32>("h010000010"))
    node T_61 = or(UInt<1>("h00"), T_55)
    node T_62 = or(T_61, T_59)
    node T_64 = and(io.inst, UInt<32>("h040"))
    node T_66 = eq(T_64, UInt<32>("h00"))
    node T_68 = and(io.inst, UInt<32>("h020000000"))
    node T_70 = eq(T_68, UInt<32>("h020000000"))
    node T_72 = or(UInt<1>("h00"), T_66)
    node T_73 = or(T_72, T_70)
    node T_75 = and(io.inst, UInt<32>("h040000000"))
    node T_77 = eq(T_75, UInt<32>("h040000000"))
    node T_79 = or(UInt<1>("h00"), T_66)
    node T_80 = or(T_79, T_77)
    node T_82 = and(io.inst, UInt<32>("h010"))
    node T_84 = eq(T_82, UInt<32>("h00"))
    node T_86 = or(UInt<1>("h00"), T_84)
    node T_87 = cat(T_62, T_51)
    node T_88 = cat(T_73, T_87)
    node T_89 = cat(T_80, T_88)
    node T_90 = cat(T_86, T_89)
    node T_92 = or(UInt<1>("h00"), T_66)
    node T_94 = and(io.inst, UInt<32>("h080000020"))
    node T_96 = eq(T_94, UInt<32>("h00"))
    node T_98 = and(io.inst, UInt<32>("h030"))
    node T_100 = eq(T_98, UInt<32>("h00"))
    node T_102 = and(io.inst, UInt<32>("h010000020"))
    node T_104 = eq(T_102, UInt<32>("h010000000"))
    node T_106 = or(UInt<1>("h00"), T_96)
    node T_107 = or(T_106, T_100)
    node T_108 = or(T_107, T_104)
    node T_110 = and(io.inst, UInt<32>("h080000004"))
    node T_112 = eq(T_110, UInt<32>("h00"))
    node T_114 = and(io.inst, UInt<32>("h010000004"))
    node T_116 = eq(T_114, UInt<32>("h00"))
    node T_118 = and(io.inst, UInt<32>("h050"))
    node T_120 = eq(T_118, UInt<32>("h040"))
    node T_122 = or(UInt<1>("h00"), T_112)
    node T_123 = or(T_122, T_116)
    node T_124 = or(T_123, T_120)
    node T_126 = and(io.inst, UInt<32>("h040000004"))
    node T_128 = eq(T_126, UInt<32>("h00"))
    node T_130 = and(io.inst, UInt<32>("h020"))
    node T_132 = eq(T_130, UInt<32>("h020"))
    node T_134 = or(UInt<1>("h00"), T_128)
    node T_135 = or(T_134, T_132)
    node T_136 = or(T_135, T_120)
    node T_138 = or(UInt<1>("h00"), T_120)
    node T_140 = and(io.inst, UInt<32>("h050000010"))
    node T_142 = eq(T_140, UInt<32>("h050000010"))
    node T_144 = or(UInt<1>("h00"), T_66)
    node T_145 = or(T_144, T_142)
    node T_147 = and(io.inst, UInt<32>("h030000010"))
    node T_149 = eq(T_147, UInt<32>("h010"))
    node T_151 = or(UInt<1>("h00"), T_149)
    node T_153 = and(io.inst, UInt<32>("h01040"))
    node T_155 = eq(T_153, UInt<32>("h00"))
    node T_157 = and(io.inst, UInt<32>("h02000040"))
    node T_159 = eq(T_157, UInt<32>("h040"))
    node T_161 = or(UInt<1>("h00"), T_155)
    node T_162 = or(T_161, T_159)
    node T_164 = and(io.inst, UInt<32>("h090000010"))
    node T_166 = eq(T_164, UInt<32>("h090000010"))
    node T_168 = or(UInt<1>("h00"), T_166)
    node T_170 = and(io.inst, UInt<32>("h090000010"))
    node T_172 = eq(T_170, UInt<32>("h080000010"))
    node T_174 = or(UInt<1>("h00"), T_132)
    node T_175 = or(T_174, T_172)
    node T_177 = and(io.inst, UInt<32>("h0a0000010"))
    node T_179 = eq(T_177, UInt<32>("h020000010"))
    node T_181 = and(io.inst, UInt<32>("h0d0000010"))
    node T_183 = eq(T_181, UInt<32>("h040000010"))
    node T_185 = or(UInt<1>("h00"), T_179)
    node T_186 = or(T_185, T_183)
    node T_188 = and(io.inst, UInt<32>("h070000004"))
    node T_190 = eq(T_188, UInt<32>("h00"))
    node T_192 = and(io.inst, UInt<32>("h068000004"))
    node T_194 = eq(T_192, UInt<32>("h00"))
    node T_196 = or(UInt<1>("h00"), T_190)
    node T_197 = or(T_196, T_194)
    node T_198 = or(T_197, T_120)
    node T_200 = and(io.inst, UInt<32>("h058000010"))
    node T_202 = eq(T_200, UInt<32>("h018000010"))
    node T_204 = or(UInt<1>("h00"), T_202)
    node T_206 = and(io.inst, UInt<32>("h0d0000010"))
    node T_208 = eq(T_206, UInt<32>("h050000010"))
    node T_210 = or(UInt<1>("h00"), T_208)
    node T_212 = and(io.inst, UInt<32>("h020000004"))
    node T_214 = eq(T_212, UInt<32>("h00"))
    node T_216 = and(io.inst, UInt<32>("h040002000"))
    node T_218 = eq(T_216, UInt<32>("h040000000"))
    node T_220 = or(UInt<1>("h00"), T_214)
    node T_221 = or(T_220, T_120)
    node T_222 = or(T_221, T_218)
    node T_224 = and(io.inst, UInt<32>("h08002000"))
    node T_226 = eq(T_224, UInt<32>("h08000000"))
    node T_228 = and(io.inst, UInt<32>("h0c0000004"))
    node T_230 = eq(T_228, UInt<32>("h080000000"))
    node T_232 = or(UInt<1>("h00"), T_214)
    node T_233 = or(T_232, T_120)
    node T_234 = or(T_233, T_226)
    node T_235 = or(T_234, T_230)
    io.sigs.cmd <= T_90
    io.sigs.ldst <= T_92
    io.sigs.wen <= T_108
    io.sigs.ren1 <= T_124
    io.sigs.ren2 <= T_136
    io.sigs.ren3 <= T_138
    io.sigs.swap12 <= T_145
    io.sigs.swap23 <= T_151
    io.sigs.single <= T_162
    io.sigs.fromint <= T_168
    io.sigs.toint <= T_175
    io.sigs.fastpipe <= T_186
    io.sigs.fma <= T_198
    io.sigs.div <= T_204
    io.sigs.sqrt <= T_210
    io.sigs.round <= T_222
    io.sigs.wflags <= T_235
    
  module MulAddRecFN_preMul : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}}
    
    io is invalid
    node signA = bits(io.a, 32, 32)
    node expA = bits(io.a, 31, 23)
    node fractA = bits(io.a, 22, 0)
    node T_50 = bits(expA, 8, 6)
    node isZeroA = eq(T_50, UInt<1>("h00"))
    node T_54 = eq(isZeroA, UInt<1>("h00"))
    node sigA = cat(T_54, fractA)
    node signB = bits(io.b, 32, 32)
    node expB = bits(io.b, 31, 23)
    node fractB = bits(io.b, 22, 0)
    node T_59 = bits(expB, 8, 6)
    node isZeroB = eq(T_59, UInt<1>("h00"))
    node T_63 = eq(isZeroB, UInt<1>("h00"))
    node sigB = cat(T_63, fractB)
    node T_65 = bits(io.c, 32, 32)
    node T_66 = bits(io.op, 0, 0)
    node opSignC = xor(T_65, T_66)
    node expC = bits(io.c, 31, 23)
    node fractC = bits(io.c, 22, 0)
    node T_70 = bits(expC, 8, 6)
    node isZeroC = eq(T_70, UInt<1>("h00"))
    node T_74 = eq(isZeroC, UInt<1>("h00"))
    node sigC = cat(T_74, fractC)
    node T_76 = xor(signA, signB)
    node T_77 = bits(io.op, 1, 1)
    node signProd = xor(T_76, T_77)
    node isZeroProd = or(isZeroA, isZeroB)
    node T_80 = bits(expB, 8, 8)
    node T_82 = eq(T_80, UInt<1>("h00"))
    node T_84 = sub(UInt<3>("h00"), T_82)
    node T_85 = tail(T_84, 1)
    node T_86 = bits(expB, 7, 0)
    node T_87 = cat(T_85, T_86)
    node T_88 = add(expA, T_87)
    node T_89 = tail(T_88, 1)
    node T_91 = add(T_89, UInt<5>("h01b"))
    node sExpAlignedProd = tail(T_91, 1)
    node doSubMags = xor(signProd, opSignC)
    node T_94 = sub(sExpAlignedProd, expC)
    node sNatCAlignDist = tail(T_94, 1)
    node T_96 = bits(sNatCAlignDist, 10, 10)
    node CAlignDist_floor = or(isZeroProd, T_96)
    node T_98 = bits(sNatCAlignDist, 9, 0)
    node T_100 = eq(T_98, UInt<1>("h00"))
    node CAlignDist_0 = or(CAlignDist_floor, T_100)
    node T_103 = eq(isZeroC, UInt<1>("h00"))
    node T_104 = bits(sNatCAlignDist, 9, 0)
    node T_106 = lt(T_104, UInt<5>("h019"))
    node T_107 = or(CAlignDist_floor, T_106)
    node isCDominant = and(T_103, T_107)
    node T_110 = bits(sNatCAlignDist, 9, 0)
    node T_112 = lt(T_110, UInt<7>("h04a"))
    node T_113 = bits(sNatCAlignDist, 6, 0)
    node T_115 = mux(T_112, T_113, UInt<7>("h04a"))
    node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_115)
    node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd)
    node T_119 = dshr(asSInt(UInt<129>("h0100000000000000000000000000000000")), CAlignDist)
    node T_120 = bits(T_119, 77, 54)
    node T_121 = bits(T_120, 15, 0)
    node T_124 = shl(UInt<8>("h0ff"), 8)
    node T_125 = xor(UInt<16>("h0ffff"), T_124)
    node T_126 = shr(T_121, 8)
    node T_127 = and(T_126, T_125)
    node T_128 = bits(T_121, 7, 0)
    node T_129 = shl(T_128, 8)
    node T_130 = not(T_125)
    node T_131 = and(T_129, T_130)
    node T_132 = or(T_127, T_131)
    node T_133 = bits(T_125, 11, 0)
    node T_134 = shl(T_133, 4)
    node T_135 = xor(T_125, T_134)
    node T_136 = shr(T_132, 4)
    node T_137 = and(T_136, T_135)
    node T_138 = bits(T_132, 11, 0)
    node T_139 = shl(T_138, 4)
    node T_140 = not(T_135)
    node T_141 = and(T_139, T_140)
    node T_142 = or(T_137, T_141)
    node T_143 = bits(T_135, 13, 0)
    node T_144 = shl(T_143, 2)
    node T_145 = xor(T_135, T_144)
    node T_146 = shr(T_142, 2)
    node T_147 = and(T_146, T_145)
    node T_148 = bits(T_142, 13, 0)
    node T_149 = shl(T_148, 2)
    node T_150 = not(T_145)
    node T_151 = and(T_149, T_150)
    node T_152 = or(T_147, T_151)
    node T_153 = bits(T_145, 14, 0)
    node T_154 = shl(T_153, 1)
    node T_155 = xor(T_145, T_154)
    node T_156 = shr(T_152, 1)
    node T_157 = and(T_156, T_155)
    node T_158 = bits(T_152, 14, 0)
    node T_159 = shl(T_158, 1)
    node T_160 = not(T_155)
    node T_161 = and(T_159, T_160)
    node T_162 = or(T_157, T_161)
    node T_163 = bits(T_120, 23, 16)
    node T_166 = shl(UInt<4>("h0f"), 4)
    node T_167 = xor(UInt<8>("h0ff"), T_166)
    node T_168 = shr(T_163, 4)
    node T_169 = and(T_168, T_167)
    node T_170 = bits(T_163, 3, 0)
    node T_171 = shl(T_170, 4)
    node T_172 = not(T_167)
    node T_173 = and(T_171, T_172)
    node T_174 = or(T_169, T_173)
    node T_175 = bits(T_167, 5, 0)
    node T_176 = shl(T_175, 2)
    node T_177 = xor(T_167, T_176)
    node T_178 = shr(T_174, 2)
    node T_179 = and(T_178, T_177)
    node T_180 = bits(T_174, 5, 0)
    node T_181 = shl(T_180, 2)
    node T_182 = not(T_177)
    node T_183 = and(T_181, T_182)
    node T_184 = or(T_179, T_183)
    node T_185 = bits(T_177, 6, 0)
    node T_186 = shl(T_185, 1)
    node T_187 = xor(T_177, T_186)
    node T_188 = shr(T_184, 1)
    node T_189 = and(T_188, T_187)
    node T_190 = bits(T_184, 6, 0)
    node T_191 = shl(T_190, 1)
    node T_192 = not(T_187)
    node T_193 = and(T_191, T_192)
    node T_194 = or(T_189, T_193)
    node CExtraMask = cat(T_162, T_194)
    node T_196 = not(sigC)
    node negSigC = mux(doSubMags, T_196, sigC)
    node T_199 = sub(UInt<50>("h00"), doSubMags)
    node T_200 = tail(T_199, 1)
    node T_201 = cat(negSigC, T_200)
    node T_202 = cat(doSubMags, T_201)
    node T_203 = asSInt(T_202)
    node T_204 = dshr(T_203, CAlignDist)
    node T_205 = and(sigC, CExtraMask)
    node T_207 = neq(T_205, UInt<1>("h00"))
    node T_208 = xor(T_207, doSubMags)
    node T_209 = asUInt(T_204)
    node T_210 = cat(T_209, T_208)
    node alignedNegSigC = bits(T_210, 74, 0)
    io.mulAddA <= sigA
    io.mulAddB <= sigB
    node T_212 = bits(alignedNegSigC, 48, 1)
    io.mulAddC <= T_212
    node T_213 = bits(expA, 8, 6)
    io.toPostMul.highExpA <= T_213
    node T_214 = bits(fractA, 22, 22)
    io.toPostMul.isNaN_isQuietNaNA <= T_214
    node T_215 = bits(expB, 8, 6)
    io.toPostMul.highExpB <= T_215
    node T_216 = bits(fractB, 22, 22)
    io.toPostMul.isNaN_isQuietNaNB <= T_216
    io.toPostMul.signProd <= signProd
    io.toPostMul.isZeroProd <= isZeroProd
    io.toPostMul.opSignC <= opSignC
    node T_217 = bits(expC, 8, 6)
    io.toPostMul.highExpC <= T_217
    node T_218 = bits(fractC, 22, 22)
    io.toPostMul.isNaN_isQuietNaNC <= T_218
    io.toPostMul.isCDominant <= isCDominant
    io.toPostMul.CAlignDist_0 <= CAlignDist_0
    io.toPostMul.CAlignDist <= CAlignDist
    node T_219 = bits(alignedNegSigC, 0, 0)
    io.toPostMul.bit0AlignedNegSigC <= T_219
    node T_220 = bits(alignedNegSigC, 74, 49)
    io.toPostMul.highAlignedNegSigC <= T_220
    io.toPostMul.sExpSum <= sExpSum
    io.toPostMul.roundingMode <= io.roundingMode
    
  module MulAddRecFN_postMul : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>}
    
    io is invalid
    node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00"))
    node T_44 = bits(io.fromPreMul.highExpA, 2, 1)
    node isSpecialA = eq(T_44, UInt<2>("h03"))
    node T_47 = bits(io.fromPreMul.highExpA, 0, 0)
    node T_49 = eq(T_47, UInt<1>("h00"))
    node isInfA = and(isSpecialA, T_49)
    node T_51 = bits(io.fromPreMul.highExpA, 0, 0)
    node isNaNA = and(isSpecialA, T_51)
    node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00"))
    node isSigNaNA = and(isNaNA, T_54)
    node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00"))
    node T_58 = bits(io.fromPreMul.highExpB, 2, 1)
    node isSpecialB = eq(T_58, UInt<2>("h03"))
    node T_61 = bits(io.fromPreMul.highExpB, 0, 0)
    node T_63 = eq(T_61, UInt<1>("h00"))
    node isInfB = and(isSpecialB, T_63)
    node T_65 = bits(io.fromPreMul.highExpB, 0, 0)
    node isNaNB = and(isSpecialB, T_65)
    node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00"))
    node isSigNaNB = and(isNaNB, T_68)
    node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00"))
    node T_72 = bits(io.fromPreMul.highExpC, 2, 1)
    node isSpecialC = eq(T_72, UInt<2>("h03"))
    node T_75 = bits(io.fromPreMul.highExpC, 0, 0)
    node T_77 = eq(T_75, UInt<1>("h00"))
    node isInfC = and(isSpecialC, T_77)
    node T_79 = bits(io.fromPreMul.highExpC, 0, 0)
    node isNaNC = and(isSpecialC, T_79)
    node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00"))
    node isSigNaNC = and(isNaNC, T_82)
    node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00"))
    node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01"))
    node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02"))
    node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03"))
    node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00"))
    node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC)
    node T_96 = bits(io.mulAddResult, 48, 48)
    node T_98 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01"))
    node T_99 = tail(T_98, 1)
    node T_100 = mux(T_96, T_99, io.fromPreMul.highAlignedNegSigC)
    node T_101 = bits(io.mulAddResult, 47, 0)
    node T_102 = cat(T_101, io.fromPreMul.bit0AlignedNegSigC)
    node sigSum = cat(T_100, T_102)
    node T_105 = bits(sigSum, 50, 1)
    node T_106 = xor(UInt<50>("h00"), T_105)
    node T_107 = or(UInt<50>("h00"), T_105)
    node T_108 = shl(T_107, 1)
    node T_109 = xor(T_106, T_108)
    node T_111 = bits(T_109, 49, 0)
    node T_112 = bits(T_111, 49, 49)
    node T_114 = bits(T_111, 48, 48)
    node T_116 = bits(T_111, 47, 47)
    node T_118 = bits(T_111, 46, 46)
    node T_120 = bits(T_111, 45, 45)
    node T_122 = bits(T_111, 44, 44)
    node T_124 = bits(T_111, 43, 43)
    node T_126 = bits(T_111, 42, 42)
    node T_128 = bits(T_111, 41, 41)
    node T_130 = bits(T_111, 40, 40)
    node T_132 = bits(T_111, 39, 39)
    node T_134 = bits(T_111, 38, 38)
    node T_136 = bits(T_111, 37, 37)
    node T_138 = bits(T_111, 36, 36)
    node T_140 = bits(T_111, 35, 35)
    node T_142 = bits(T_111, 34, 34)
    node T_144 = bits(T_111, 33, 33)
    node T_146 = bits(T_111, 32, 32)
    node T_148 = bits(T_111, 31, 31)
    node T_150 = bits(T_111, 30, 30)
    node T_152 = bits(T_111, 29, 29)
    node T_154 = bits(T_111, 28, 28)
    node T_156 = bits(T_111, 27, 27)
    node T_158 = bits(T_111, 26, 26)
    node T_160 = bits(T_111, 25, 25)
    node T_162 = bits(T_111, 24, 24)
    node T_164 = bits(T_111, 23, 23)
    node T_166 = bits(T_111, 22, 22)
    node T_168 = bits(T_111, 21, 21)
    node T_170 = bits(T_111, 20, 20)
    node T_172 = bits(T_111, 19, 19)
    node T_174 = bits(T_111, 18, 18)
    node T_176 = bits(T_111, 17, 17)
    node T_178 = bits(T_111, 16, 16)
    node T_180 = bits(T_111, 15, 15)
    node T_182 = bits(T_111, 14, 14)
    node T_184 = bits(T_111, 13, 13)
    node T_186 = bits(T_111, 12, 12)
    node T_188 = bits(T_111, 11, 11)
    node T_190 = bits(T_111, 10, 10)
    node T_192 = bits(T_111, 9, 9)
    node T_194 = bits(T_111, 8, 8)
    node T_196 = bits(T_111, 7, 7)
    node T_198 = bits(T_111, 6, 6)
    node T_200 = bits(T_111, 5, 5)
    node T_202 = bits(T_111, 4, 4)
    node T_204 = bits(T_111, 3, 3)
    node T_206 = bits(T_111, 2, 2)
    node T_208 = bits(T_111, 1, 1)
    node T_209 = shl(T_208, 0)
    node T_210 = mux(T_206, UInt<2>("h02"), T_209)
    node T_211 = mux(T_204, UInt<2>("h03"), T_210)
    node T_212 = mux(T_202, UInt<3>("h04"), T_211)
    node T_213 = mux(T_200, UInt<3>("h05"), T_212)
    node T_214 = mux(T_198, UInt<3>("h06"), T_213)
    node T_215 = mux(T_196, UInt<3>("h07"), T_214)
    node T_216 = mux(T_194, UInt<4>("h08"), T_215)
    node T_217 = mux(T_192, UInt<4>("h09"), T_216)
    node T_218 = mux(T_190, UInt<4>("h0a"), T_217)
    node T_219 = mux(T_188, UInt<4>("h0b"), T_218)
    node T_220 = mux(T_186, UInt<4>("h0c"), T_219)
    node T_221 = mux(T_184, UInt<4>("h0d"), T_220)
    node T_222 = mux(T_182, UInt<4>("h0e"), T_221)
    node T_223 = mux(T_180, UInt<4>("h0f"), T_222)
    node T_224 = mux(T_178, UInt<5>("h010"), T_223)
    node T_225 = mux(T_176, UInt<5>("h011"), T_224)
    node T_226 = mux(T_174, UInt<5>("h012"), T_225)
    node T_227 = mux(T_172, UInt<5>("h013"), T_226)
    node T_228 = mux(T_170, UInt<5>("h014"), T_227)
    node T_229 = mux(T_168, UInt<5>("h015"), T_228)
    node T_230 = mux(T_166, UInt<5>("h016"), T_229)
    node T_231 = mux(T_164, UInt<5>("h017"), T_230)
    node T_232 = mux(T_162, UInt<5>("h018"), T_231)
    node T_233 = mux(T_160, UInt<5>("h019"), T_232)
    node T_234 = mux(T_158, UInt<5>("h01a"), T_233)
    node T_235 = mux(T_156, UInt<5>("h01b"), T_234)
    node T_236 = mux(T_154, UInt<5>("h01c"), T_235)
    node T_237 = mux(T_152, UInt<5>("h01d"), T_236)
    node T_238 = mux(T_150, UInt<5>("h01e"), T_237)
    node T_239 = mux(T_148, UInt<5>("h01f"), T_238)
    node T_240 = mux(T_146, UInt<6>("h020"), T_239)
    node T_241 = mux(T_144, UInt<6>("h021"), T_240)
    node T_242 = mux(T_142, UInt<6>("h022"), T_241)
    node T_243 = mux(T_140, UInt<6>("h023"), T_242)
    node T_244 = mux(T_138, UInt<6>("h024"), T_243)
    node T_245 = mux(T_136, UInt<6>("h025"), T_244)
    node T_246 = mux(T_134, UInt<6>("h026"), T_245)
    node T_247 = mux(T_132, UInt<6>("h027"), T_246)
    node T_248 = mux(T_130, UInt<6>("h028"), T_247)
    node T_249 = mux(T_128, UInt<6>("h029"), T_248)
    node T_250 = mux(T_126, UInt<6>("h02a"), T_249)
    node T_251 = mux(T_124, UInt<6>("h02b"), T_250)
    node T_252 = mux(T_122, UInt<6>("h02c"), T_251)
    node T_253 = mux(T_120, UInt<6>("h02d"), T_252)
    node T_254 = mux(T_118, UInt<6>("h02e"), T_253)
    node T_255 = mux(T_116, UInt<6>("h02f"), T_254)
    node T_256 = mux(T_114, UInt<6>("h030"), T_255)
    node T_257 = mux(T_112, UInt<6>("h031"), T_256)
    node T_258 = sub(UInt<7>("h049"), T_257)
    node estNormPos_dist = tail(T_258, 1)
    node T_260 = bits(sigSum, 33, 18)
    node T_262 = neq(T_260, UInt<1>("h00"))
    node T_263 = bits(sigSum, 17, 0)
    node T_265 = neq(T_263, UInt<1>("h00"))
    node firstReduceSigSum = cat(T_262, T_265)
    node notSigSum = not(sigSum)
    node T_268 = bits(notSigSum, 33, 18)
    node T_270 = neq(T_268, UInt<1>("h00"))
    node T_271 = bits(notSigSum, 17, 0)
    node T_273 = neq(T_271, UInt<1>("h00"))
    node firstReduceNotSigSum = cat(T_270, T_273)
    node T_275 = or(io.fromPreMul.CAlignDist_0, doSubMags)
    node T_277 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01"))
    node T_278 = tail(T_277, 1)
    node T_279 = bits(T_278, 4, 0)
    node CDom_estNormDist = mux(T_275, io.fromPreMul.CAlignDist, T_279)
    node T_281 = not(doSubMags)
    node T_282 = bits(CDom_estNormDist, 4, 4)
    node T_283 = not(T_282)
    node T_284 = and(T_281, T_283)
    node T_285 = asSInt(T_284)
    node T_286 = bits(sigSum, 74, 34)
    node T_288 = neq(firstReduceSigSum, UInt<1>("h00"))
    node T_289 = cat(T_286, T_288)
    node T_290 = asSInt(T_289)
    node T_291 = and(T_285, T_290)
    node T_292 = asSInt(T_291)
    node T_293 = not(doSubMags)
    node T_294 = bits(CDom_estNormDist, 4, 4)
    node T_295 = and(T_293, T_294)
    node T_296 = asSInt(T_295)
    node T_297 = bits(sigSum, 58, 18)
    node T_298 = bits(firstReduceSigSum, 0, 0)
    node T_299 = cat(T_297, T_298)
    node T_300 = asSInt(T_299)
    node T_301 = and(T_296, T_300)
    node T_302 = asSInt(T_301)
    node T_303 = or(T_292, T_302)
    node T_304 = asSInt(T_303)
    node T_305 = bits(CDom_estNormDist, 4, 4)
    node T_306 = not(T_305)
    node T_307 = and(doSubMags, T_306)
    node T_308 = asSInt(T_307)
    node T_309 = bits(notSigSum, 74, 34)
    node T_311 = neq(firstReduceNotSigSum, UInt<1>("h00"))
    node T_312 = cat(T_309, T_311)
    node T_313 = asSInt(T_312)
    node T_314 = and(T_308, T_313)
    node T_315 = asSInt(T_314)
    node T_316 = or(T_304, T_315)
    node T_317 = asSInt(T_316)
    node T_318 = bits(CDom_estNormDist, 4, 4)
    node T_319 = and(doSubMags, T_318)
    node T_320 = asSInt(T_319)
    node T_321 = bits(notSigSum, 58, 18)
    node T_322 = bits(firstReduceNotSigSum, 0, 0)
    node T_323 = cat(T_321, T_322)
    node T_324 = asSInt(T_323)
    node T_325 = and(T_320, T_324)
    node T_326 = asSInt(T_325)
    node T_327 = or(T_317, T_326)
    node T_328 = asSInt(T_327)
    node CDom_firstNormAbsSigSum = asUInt(T_328)
    node T_330 = bits(sigSum, 50, 18)
    node T_331 = bits(firstReduceNotSigSum, 0, 0)
    node T_332 = not(T_331)
    node T_333 = bits(firstReduceSigSum, 0, 0)
    node T_334 = mux(doSubMags, T_332, T_333)
    node T_335 = cat(T_330, T_334)
    node T_336 = bits(sigSum, 42, 1)
    node T_337 = bits(estNormPos_dist, 5, 5)
    node T_338 = bits(estNormPos_dist, 4, 4)
    node T_339 = bits(sigSum, 26, 1)
    node T_341 = sub(UInt<16>("h00"), doSubMags)
    node T_342 = tail(T_341, 1)
    node T_343 = cat(T_339, T_342)
    node T_344 = mux(T_338, T_343, T_336)
    node T_345 = bits(estNormPos_dist, 4, 4)
    node T_346 = bits(sigSum, 10, 1)
    node T_348 = sub(UInt<32>("h00"), doSubMags)
    node T_349 = tail(T_348, 1)
    node T_350 = cat(T_346, T_349)
    node T_351 = mux(T_345, T_335, T_350)
    node notCDom_pos_firstNormAbsSigSum = mux(T_337, T_344, T_351)
    node T_353 = bits(notSigSum, 49, 18)
    node T_354 = bits(firstReduceNotSigSum, 0, 0)
    node T_355 = cat(T_353, T_354)
    node T_356 = bits(notSigSum, 42, 1)
    node T_357 = bits(estNormPos_dist, 5, 5)
    node T_358 = bits(estNormPos_dist, 4, 4)
    node T_359 = bits(notSigSum, 27, 1)
    node T_361 = dshl(T_359, UInt<5>("h010"))
    node T_362 = mux(T_358, T_361, T_356)
    node T_363 = bits(estNormPos_dist, 4, 4)
    node T_364 = bits(notSigSum, 11, 1)
    node T_366 = dshl(T_364, UInt<6>("h020"))
    node T_367 = mux(T_363, T_355, T_366)
    node notCDom_neg_cFirstNormAbsSigSum = mux(T_357, T_362, T_367)
    node notCDom_signSigSum = bits(sigSum, 51, 51)
    node T_370 = not(isZeroC)
    node T_371 = and(doSubMags, T_370)
    node doNegSignSum = mux(io.fromPreMul.isCDominant, T_371, notCDom_signSigSum)
    node T_373 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist)
    node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_373)
    node T_375 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum)
    node T_376 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum)
    node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_375, T_376)
    node T_378 = not(io.fromPreMul.isCDominant)
    node T_379 = not(notCDom_signSigSum)
    node T_380 = and(T_378, T_379)
    node doIncrSig = and(T_380, doSubMags)
    node estNormDist_5 = bits(estNormDist, 3, 0)
    node normTo2ShiftDist = not(estNormDist_5)
    node T_385 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist)
    node T_386 = bits(T_385, 15, 1)
    node T_387 = bits(T_386, 7, 0)
    node T_390 = shl(UInt<4>("h0f"), 4)
    node T_391 = xor(UInt<8>("h0ff"), T_390)
    node T_392 = shr(T_387, 4)
    node T_393 = and(T_392, T_391)
    node T_394 = bits(T_387, 3, 0)
    node T_395 = shl(T_394, 4)
    node T_396 = not(T_391)
    node T_397 = and(T_395, T_396)
    node T_398 = or(T_393, T_397)
    node T_399 = bits(T_391, 5, 0)
    node T_400 = shl(T_399, 2)
    node T_401 = xor(T_391, T_400)
    node T_402 = shr(T_398, 2)
    node T_403 = and(T_402, T_401)
    node T_404 = bits(T_398, 5, 0)
    node T_405 = shl(T_404, 2)
    node T_406 = not(T_401)
    node T_407 = and(T_405, T_406)
    node T_408 = or(T_403, T_407)
    node T_409 = bits(T_401, 6, 0)
    node T_410 = shl(T_409, 1)
    node T_411 = xor(T_401, T_410)
    node T_412 = shr(T_408, 1)
    node T_413 = and(T_412, T_411)
    node T_414 = bits(T_408, 6, 0)
    node T_415 = shl(T_414, 1)
    node T_416 = not(T_411)
    node T_417 = and(T_415, T_416)
    node T_418 = or(T_413, T_417)
    node T_419 = bits(T_386, 14, 8)
    node T_420 = bits(T_419, 3, 0)
    node T_421 = bits(T_420, 1, 0)
    node T_422 = bits(T_421, 0, 0)
    node T_423 = bits(T_421, 1, 1)
    node T_424 = cat(T_422, T_423)
    node T_425 = bits(T_420, 3, 2)
    node T_426 = bits(T_425, 0, 0)
    node T_427 = bits(T_425, 1, 1)
    node T_428 = cat(T_426, T_427)
    node T_429 = cat(T_424, T_428)
    node T_430 = bits(T_419, 6, 4)
    node T_431 = bits(T_430, 1, 0)
    node T_432 = bits(T_431, 0, 0)
    node T_433 = bits(T_431, 1, 1)
    node T_434 = cat(T_432, T_433)
    node T_435 = bits(T_430, 2, 2)
    node T_436 = cat(T_434, T_435)
    node T_437 = cat(T_429, T_436)
    node T_438 = cat(T_418, T_437)
    node absSigSumExtraMask = cat(T_438, UInt<1>("h01"))
    node T_441 = bits(cFirstNormAbsSigSum, 42, 1)
    node T_442 = dshr(T_441, normTo2ShiftDist)
    node T_443 = bits(cFirstNormAbsSigSum, 15, 0)
    node T_444 = not(T_443)
    node T_445 = and(T_444, absSigSumExtraMask)
    node T_447 = eq(T_445, UInt<1>("h00"))
    node T_448 = bits(cFirstNormAbsSigSum, 15, 0)
    node T_449 = and(T_448, absSigSumExtraMask)
    node T_451 = neq(T_449, UInt<1>("h00"))
    node T_452 = mux(doIncrSig, T_447, T_451)
    node T_453 = cat(T_442, T_452)
    node sigX3 = bits(T_453, 27, 0)
    node T_455 = bits(sigX3, 27, 26)
    node sigX3Shift1 = eq(T_455, UInt<1>("h00"))
    node T_458 = sub(io.fromPreMul.sExpSum, estNormDist)
    node sExpX3 = tail(T_458, 1)
    node T_460 = bits(sigX3, 27, 25)
    node isZeroY = eq(T_460, UInt<1>("h00"))
    node T_463 = xor(io.fromPreMul.signProd, doNegSignSum)
    node signY = mux(isZeroY, signZeroNotEqOpSigns, T_463)
    node sExpX3_13 = bits(sExpX3, 9, 0)
    node T_466 = bits(sExpX3, 10, 10)
    node T_468 = sub(UInt<27>("h00"), T_466)
    node T_469 = tail(T_468, 1)
    node T_470 = not(sExpX3_13)
    node T_472 = dshr(asSInt(UInt<1025>("h010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_470)
    node T_473 = bits(T_472, 131, 107)
    node T_474 = bits(T_473, 15, 0)
    node T_477 = shl(UInt<8>("h0ff"), 8)
    node T_478 = xor(UInt<16>("h0ffff"), T_477)
    node T_479 = shr(T_474, 8)
    node T_480 = and(T_479, T_478)
    node T_481 = bits(T_474, 7, 0)
    node T_482 = shl(T_481, 8)
    node T_483 = not(T_478)
    node T_484 = and(T_482, T_483)
    node T_485 = or(T_480, T_484)
    node T_486 = bits(T_478, 11, 0)
    node T_487 = shl(T_486, 4)
    node T_488 = xor(T_478, T_487)
    node T_489 = shr(T_485, 4)
    node T_490 = and(T_489, T_488)
    node T_491 = bits(T_485, 11, 0)
    node T_492 = shl(T_491, 4)
    node T_493 = not(T_488)
    node T_494 = and(T_492, T_493)
    node T_495 = or(T_490, T_494)
    node T_496 = bits(T_488, 13, 0)
    node T_497 = shl(T_496, 2)
    node T_498 = xor(T_488, T_497)
    node T_499 = shr(T_495, 2)
    node T_500 = and(T_499, T_498)
    node T_501 = bits(T_495, 13, 0)
    node T_502 = shl(T_501, 2)
    node T_503 = not(T_498)
    node T_504 = and(T_502, T_503)
    node T_505 = or(T_500, T_504)
    node T_506 = bits(T_498, 14, 0)
    node T_507 = shl(T_506, 1)
    node T_508 = xor(T_498, T_507)
    node T_509 = shr(T_505, 1)
    node T_510 = and(T_509, T_508)
    node T_511 = bits(T_505, 14, 0)
    node T_512 = shl(T_511, 1)
    node T_513 = not(T_508)
    node T_514 = and(T_512, T_513)
    node T_515 = or(T_510, T_514)
    node T_516 = bits(T_473, 24, 16)
    node T_517 = bits(T_516, 7, 0)
    node T_520 = shl(UInt<4>("h0f"), 4)
    node T_521 = xor(UInt<8>("h0ff"), T_520)
    node T_522 = shr(T_517, 4)
    node T_523 = and(T_522, T_521)
    node T_524 = bits(T_517, 3, 0)
    node T_525 = shl(T_524, 4)
    node T_526 = not(T_521)
    node T_527 = and(T_525, T_526)
    node T_528 = or(T_523, T_527)
    node T_529 = bits(T_521, 5, 0)
    node T_530 = shl(T_529, 2)
    node T_531 = xor(T_521, T_530)
    node T_532 = shr(T_528, 2)
    node T_533 = and(T_532, T_531)
    node T_534 = bits(T_528, 5, 0)
    node T_535 = shl(T_534, 2)
    node T_536 = not(T_531)
    node T_537 = and(T_535, T_536)
    node T_538 = or(T_533, T_537)
    node T_539 = bits(T_531, 6, 0)
    node T_540 = shl(T_539, 1)
    node T_541 = xor(T_531, T_540)
    node T_542 = shr(T_538, 1)
    node T_543 = and(T_542, T_541)
    node T_544 = bits(T_538, 6, 0)
    node T_545 = shl(T_544, 1)
    node T_546 = not(T_541)
    node T_547 = and(T_545, T_546)
    node T_548 = or(T_543, T_547)
    node T_549 = bits(T_516, 8, 8)
    node T_550 = cat(T_548, T_549)
    node T_551 = cat(T_515, T_550)
    node T_552 = bits(sigX3, 26, 26)
    node T_553 = or(T_551, T_552)
    node T_555 = cat(T_553, UInt<2>("h03"))
    node roundMask = or(T_469, T_555)
    node T_557 = shr(roundMask, 1)
    node T_558 = not(T_557)
    node roundPosMask = and(T_558, roundMask)
    node T_560 = and(sigX3, roundPosMask)
    node roundPosBit = neq(T_560, UInt<1>("h00"))
    node T_563 = shr(roundMask, 1)
    node T_564 = and(sigX3, T_563)
    node anyRoundExtra = neq(T_564, UInt<1>("h00"))
    node T_567 = not(sigX3)
    node T_568 = shr(roundMask, 1)
    node T_569 = and(T_567, T_568)
    node allRoundExtra = eq(T_569, UInt<1>("h00"))
    node anyRound = or(roundPosBit, anyRoundExtra)
    node allRound = and(roundPosBit, allRoundExtra)
    node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max)
    node T_575 = not(doIncrSig)
    node T_576 = and(T_575, roundingMode_nearest_even)
    node T_577 = and(T_576, roundPosBit)
    node T_578 = and(T_577, anyRoundExtra)
    node T_579 = not(doIncrSig)
    node T_580 = and(T_579, roundDirectUp)
    node T_581 = and(T_580, anyRound)
    node T_582 = or(T_578, T_581)
    node T_583 = and(doIncrSig, allRound)
    node T_584 = or(T_582, T_583)
    node T_585 = and(doIncrSig, roundingMode_nearest_even)
    node T_586 = and(T_585, roundPosBit)
    node T_587 = or(T_584, T_586)
    node T_588 = and(doIncrSig, roundDirectUp)
    node T_590 = and(T_588, UInt<1>("h01"))
    node roundUp = or(T_587, T_590)
    node T_592 = not(roundPosBit)
    node T_593 = and(roundingMode_nearest_even, T_592)
    node T_594 = and(T_593, allRoundExtra)
    node T_595 = and(roundingMode_nearest_even, roundPosBit)
    node T_596 = not(anyRoundExtra)
    node T_597 = and(T_595, T_596)
    node roundEven = mux(doIncrSig, T_594, T_597)
    node T_599 = not(allRound)
    node roundInexact = mux(doIncrSig, T_599, anyRound)
    node T_601 = or(sigX3, roundMask)
    node T_602 = shr(T_601, 2)
    node T_604 = add(T_602, UInt<1>("h01"))
    node T_605 = tail(T_604, 1)
    node roundUp_sigY3 = bits(T_605, 25, 0)
    node T_607 = not(roundUp)
    node T_608 = not(roundEven)
    node T_609 = and(T_607, T_608)
    node T_610 = bits(T_609, 0, 0)
    node T_611 = not(roundMask)
    node T_612 = and(sigX3, T_611)
    node T_613 = shr(T_612, 2)
    node T_615 = mux(T_610, T_613, UInt<1>("h00"))
    node T_616 = bits(roundUp, 0, 0)
    node T_618 = mux(T_616, roundUp_sigY3, UInt<1>("h00"))
    node T_619 = or(T_615, T_618)
    node T_620 = shr(roundMask, 1)
    node T_621 = not(T_620)
    node T_622 = and(roundUp_sigY3, T_621)
    node T_624 = mux(roundEven, T_622, UInt<1>("h00"))
    node sigY3 = or(T_619, T_624)
    node T_626 = bits(sigY3, 25, 25)
    node T_628 = add(sExpX3, UInt<1>("h01"))
    node T_629 = tail(T_628, 1)
    node T_631 = mux(T_626, T_629, UInt<1>("h00"))
    node T_632 = bits(sigY3, 24, 24)
    node T_634 = mux(T_632, sExpX3, UInt<1>("h00"))
    node T_635 = or(T_631, T_634)
    node T_636 = bits(sigY3, 25, 24)
    node T_638 = eq(T_636, UInt<1>("h00"))
    node T_640 = sub(sExpX3, UInt<1>("h01"))
    node T_641 = tail(T_640, 1)
    node T_643 = mux(T_638, T_641, UInt<1>("h00"))
    node sExpY = or(T_635, T_643)
    node expY = bits(sExpY, 8, 0)
    node T_646 = bits(sigY3, 22, 0)
    node T_647 = bits(sigY3, 23, 1)
    node fractY = mux(sigX3Shift1, T_646, T_647)
    node T_649 = bits(sExpY, 9, 7)
    node overflowY = eq(T_649, UInt<2>("h03"))
    node T_652 = not(isZeroY)
    node T_653 = bits(sExpY, 9, 9)
    node T_654 = bits(sExpY, 8, 0)
    node T_656 = lt(T_654, UInt<7>("h06b"))
    node T_657 = or(T_653, T_656)
    node totalUnderflowY = and(T_652, T_657)
    node T_659 = bits(sExpX3, 10, 10)
    node T_662 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081"))
    node T_663 = leq(sExpX3_13, T_662)
    node T_664 = or(T_659, T_663)
    node underflowY = and(roundInexact, T_664)
    node T_666 = and(roundingMode_min, signY)
    node T_667 = not(signY)
    node T_668 = and(roundingMode_max, T_667)
    node roundMagUp = or(T_666, T_668)
    node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp)
    node mulSpecial = or(isSpecialA, isSpecialB)
    node addSpecial = or(mulSpecial, isSpecialC)
    node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC)
    node T_674 = not(addSpecial)
    node T_675 = not(notSpecial_addZeros)
    node commonCase = and(T_674, T_675)
    node T_677 = and(isInfA, isZeroB)
    node T_678 = and(isZeroA, isInfB)
    node T_679 = or(T_677, T_678)
    node T_680 = not(isNaNA)
    node T_681 = not(isNaNB)
    node T_682 = and(T_680, T_681)
    node T_683 = or(isInfA, isInfB)
    node T_684 = and(T_682, T_683)
    node T_685 = and(T_684, isInfC)
    node T_686 = and(T_685, doSubMags)
    node notSigNaN_invalid = or(T_679, T_686)
    node T_688 = or(isSigNaNA, isSigNaNB)
    node T_689 = or(T_688, isSigNaNC)
    node invalid = or(T_689, notSigNaN_invalid)
    node overflow = and(commonCase, overflowY)
    node underflow = and(commonCase, underflowY)
    node T_693 = and(commonCase, roundInexact)
    node inexact = or(overflow, T_693)
    node T_695 = or(notSpecial_addZeros, isZeroY)
    node notSpecial_isZeroOut = or(T_695, totalUnderflowY)
    node T_697 = and(commonCase, totalUnderflowY)
    node pegMinFiniteMagOut = and(T_697, roundMagUp)
    node T_699 = not(overflowY_roundMagUp)
    node pegMaxFiniteMagOut = and(overflow, T_699)
    node T_701 = or(isInfA, isInfB)
    node T_702 = or(T_701, isInfC)
    node T_703 = and(overflow, overflowY_roundMagUp)
    node notNaN_isInfOut = or(T_702, T_703)
    node T_705 = or(isNaNA, isNaNB)
    node T_706 = or(T_705, isNaNC)
    node isNaNOut = or(T_706, notSigNaN_invalid)
    node T_709 = eq(doSubMags, UInt<1>("h00"))
    node T_710 = and(T_709, io.fromPreMul.opSignC)
    node T_712 = eq(isSpecialC, UInt<1>("h00"))
    node T_713 = and(mulSpecial, T_712)
    node T_714 = and(T_713, io.fromPreMul.signProd)
    node T_715 = or(T_710, T_714)
    node T_717 = eq(mulSpecial, UInt<1>("h00"))
    node T_718 = and(T_717, isSpecialC)
    node T_719 = and(T_718, io.fromPreMul.opSignC)
    node T_720 = or(T_715, T_719)
    node T_722 = eq(mulSpecial, UInt<1>("h00"))
    node T_723 = and(T_722, notSpecial_addZeros)
    node T_724 = and(T_723, doSubMags)
    node T_725 = and(T_724, signZeroNotEqOpSigns)
    node uncommonCaseSignOut = or(T_720, T_725)
    node T_728 = eq(isNaNOut, UInt<1>("h00"))
    node T_729 = and(T_728, uncommonCaseSignOut)
    node T_730 = and(commonCase, signY)
    node signOut = or(T_729, T_730)
    node T_734 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00"))
    node T_735 = not(T_734)
    node T_736 = and(expY, T_735)
    node T_738 = not(UInt<9>("h06b"))
    node T_740 = mux(pegMinFiniteMagOut, T_738, UInt<9>("h00"))
    node T_741 = not(T_740)
    node T_742 = and(T_736, T_741)
    node T_745 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<9>("h00"))
    node T_746 = not(T_745)
    node T_747 = and(T_742, T_746)
    node T_750 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00"))
    node T_751 = not(T_750)
    node T_752 = and(T_747, T_751)
    node T_755 = mux(pegMinFiniteMagOut, UInt<7>("h06b"), UInt<9>("h00"))
    node T_756 = or(T_752, T_755)
    node T_759 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<9>("h00"))
    node T_760 = or(T_756, T_759)
    node T_763 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00"))
    node T_764 = or(T_760, T_763)
    node T_767 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00"))
    node expOut = or(T_764, T_767)
    node T_769 = and(totalUnderflowY, roundMagUp)
    node T_770 = or(T_769, isNaNOut)
    node T_772 = mux(T_770, UInt<1>("h00"), fractY)
    node T_773 = shl(isNaNOut, 22)
    node T_774 = or(T_772, T_773)
    node T_776 = sub(UInt<23>("h00"), pegMaxFiniteMagOut)
    node T_777 = tail(T_776, 1)
    node fractOut = or(T_774, T_777)
    node T_779 = cat(expOut, fractOut)
    node T_780 = cat(signOut, T_779)
    io.out <= T_780
    node T_782 = cat(invalid, UInt<1>("h00"))
    node T_783 = cat(underflow, inexact)
    node T_784 = cat(overflow, T_783)
    node T_785 = cat(T_782, T_784)
    io.exceptionFlags <= T_785
    
  module MulAddRecFN : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>}
    
    io is invalid
    inst mulAddRecFN_preMul of MulAddRecFN_preMul
    mulAddRecFN_preMul.io is invalid
    mulAddRecFN_preMul.clk <= clk
    mulAddRecFN_preMul.reset <= reset
    inst mulAddRecFN_postMul of MulAddRecFN_postMul
    mulAddRecFN_postMul.io is invalid
    mulAddRecFN_postMul.clk <= clk
    mulAddRecFN_postMul.reset <= reset
    mulAddRecFN_preMul.io.op <= io.op
    mulAddRecFN_preMul.io.a <= io.a
    mulAddRecFN_preMul.io.b <= io.b
    mulAddRecFN_preMul.io.c <= io.c
    mulAddRecFN_preMul.io.roundingMode <= io.roundingMode
    mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul
    node T_14 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB)
    node T_16 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC)
    node T_17 = add(T_14, T_16)
    node T_18 = tail(T_17, 1)
    mulAddRecFN_postMul.io.mulAddResult <= T_18
    io.out <= mulAddRecFN_postMul.io.out
    io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags
    
  module FPUFMAPipe : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}
    
    io is invalid
    node one = shl(UInt<1>("h01"), 31)
    node T_136 = bits(io.in.bits.in1, 32, 32)
    node T_137 = bits(io.in.bits.in2, 32, 32)
    node T_138 = xor(T_136, T_137)
    node zero = shl(T_138, 32)
    reg valid : UInt<1>, clk
    valid <= io.in.valid
    reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk
    when io.in.valid :
      in <- io.in.bits
      node T_187 = bits(io.in.bits.cmd, 1, 1)
      node T_188 = or(io.in.bits.ren3, io.in.bits.swap23)
      node T_189 = and(T_187, T_188)
      node T_190 = bits(io.in.bits.cmd, 0, 0)
      node T_191 = cat(T_189, T_190)
      in.cmd <= T_191
      when io.in.bits.swap23 :
        in.in2 <= one
        skip
      node T_192 = or(io.in.bits.ren3, io.in.bits.swap23)
      node T_194 = eq(T_192, UInt<1>("h00"))
      when T_194 :
        in.in3 <= zero
        skip
      skip
    inst fma of MulAddRecFN
    fma.io is invalid
    fma.clk <= clk
    fma.reset <= reset
    fma.io.op <= in.cmd
    fma.io.roundingMode <= in.rm
    fma.io.a <= in.in1
    fma.io.b <= in.in2
    fma.io.c <= in.in3
    wire res : {data : UInt<65>, exc : UInt<5>}
    res is invalid
    node T_203 = asUInt(asSInt(UInt<32>("h0ffffffff")))
    node T_204 = cat(T_203, fma.io.out)
    res.data <= T_204
    res.exc <= fma.io.exceptionFlags
    reg T_207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_207 <= valid
    reg T_208 : {data : UInt<65>, exc : UInt<5>}, clk
    when valid :
      T_208 <- res
      skip
    wire T_219 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}
    T_219 is invalid
    T_219.valid <= T_207
    T_219.bits <- T_208
    io.out <- T_219
    
  module MulAddRecFN_preMul_115 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}}
    
    io is invalid
    node signA = bits(io.a, 64, 64)
    node expA = bits(io.a, 63, 52)
    node fractA = bits(io.a, 51, 0)
    node T_50 = bits(expA, 11, 9)
    node isZeroA = eq(T_50, UInt<1>("h00"))
    node T_54 = eq(isZeroA, UInt<1>("h00"))
    node sigA = cat(T_54, fractA)
    node signB = bits(io.b, 64, 64)
    node expB = bits(io.b, 63, 52)
    node fractB = bits(io.b, 51, 0)
    node T_59 = bits(expB, 11, 9)
    node isZeroB = eq(T_59, UInt<1>("h00"))
    node T_63 = eq(isZeroB, UInt<1>("h00"))
    node sigB = cat(T_63, fractB)
    node T_65 = bits(io.c, 64, 64)
    node T_66 = bits(io.op, 0, 0)
    node opSignC = xor(T_65, T_66)
    node expC = bits(io.c, 63, 52)
    node fractC = bits(io.c, 51, 0)
    node T_70 = bits(expC, 11, 9)
    node isZeroC = eq(T_70, UInt<1>("h00"))
    node T_74 = eq(isZeroC, UInt<1>("h00"))
    node sigC = cat(T_74, fractC)
    node T_76 = xor(signA, signB)
    node T_77 = bits(io.op, 1, 1)
    node signProd = xor(T_76, T_77)
    node isZeroProd = or(isZeroA, isZeroB)
    node T_80 = bits(expB, 11, 11)
    node T_82 = eq(T_80, UInt<1>("h00"))
    node T_84 = sub(UInt<3>("h00"), T_82)
    node T_85 = tail(T_84, 1)
    node T_86 = bits(expB, 10, 0)
    node T_87 = cat(T_85, T_86)
    node T_88 = add(expA, T_87)
    node T_89 = tail(T_88, 1)
    node T_91 = add(T_89, UInt<6>("h038"))
    node sExpAlignedProd = tail(T_91, 1)
    node doSubMags = xor(signProd, opSignC)
    node T_94 = sub(sExpAlignedProd, expC)
    node sNatCAlignDist = tail(T_94, 1)
    node T_96 = bits(sNatCAlignDist, 13, 13)
    node CAlignDist_floor = or(isZeroProd, T_96)
    node T_98 = bits(sNatCAlignDist, 12, 0)
    node T_100 = eq(T_98, UInt<1>("h00"))
    node CAlignDist_0 = or(CAlignDist_floor, T_100)
    node T_103 = eq(isZeroC, UInt<1>("h00"))
    node T_104 = bits(sNatCAlignDist, 12, 0)
    node T_106 = lt(T_104, UInt<6>("h036"))
    node T_107 = or(CAlignDist_floor, T_106)
    node isCDominant = and(T_103, T_107)
    node T_110 = bits(sNatCAlignDist, 12, 0)
    node T_112 = lt(T_110, UInt<8>("h0a1"))
    node T_113 = bits(sNatCAlignDist, 7, 0)
    node T_115 = mux(T_112, T_113, UInt<8>("h0a1"))
    node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_115)
    node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd)
    node T_119 = dshr(asSInt(UInt<257>("h010000000000000000000000000000000000000000000000000000000000000000")), CAlignDist)
    node T_120 = bits(T_119, 147, 95)
    node T_121 = bits(T_120, 31, 0)
    node T_124 = shl(UInt<16>("h0ffff"), 16)
    node T_125 = xor(UInt<32>("h0ffffffff"), T_124)
    node T_126 = shr(T_121, 16)
    node T_127 = and(T_126, T_125)
    node T_128 = bits(T_121, 15, 0)
    node T_129 = shl(T_128, 16)
    node T_130 = not(T_125)
    node T_131 = and(T_129, T_130)
    node T_132 = or(T_127, T_131)
    node T_133 = bits(T_125, 23, 0)
    node T_134 = shl(T_133, 8)
    node T_135 = xor(T_125, T_134)
    node T_136 = shr(T_132, 8)
    node T_137 = and(T_136, T_135)
    node T_138 = bits(T_132, 23, 0)
    node T_139 = shl(T_138, 8)
    node T_140 = not(T_135)
    node T_141 = and(T_139, T_140)
    node T_142 = or(T_137, T_141)
    node T_143 = bits(T_135, 27, 0)
    node T_144 = shl(T_143, 4)
    node T_145 = xor(T_135, T_144)
    node T_146 = shr(T_142, 4)
    node T_147 = and(T_146, T_145)
    node T_148 = bits(T_142, 27, 0)
    node T_149 = shl(T_148, 4)
    node T_150 = not(T_145)
    node T_151 = and(T_149, T_150)
    node T_152 = or(T_147, T_151)
    node T_153 = bits(T_145, 29, 0)
    node T_154 = shl(T_153, 2)
    node T_155 = xor(T_145, T_154)
    node T_156 = shr(T_152, 2)
    node T_157 = and(T_156, T_155)
    node T_158 = bits(T_152, 29, 0)
    node T_159 = shl(T_158, 2)
    node T_160 = not(T_155)
    node T_161 = and(T_159, T_160)
    node T_162 = or(T_157, T_161)
    node T_163 = bits(T_155, 30, 0)
    node T_164 = shl(T_163, 1)
    node T_165 = xor(T_155, T_164)
    node T_166 = shr(T_162, 1)
    node T_167 = and(T_166, T_165)
    node T_168 = bits(T_162, 30, 0)
    node T_169 = shl(T_168, 1)
    node T_170 = not(T_165)
    node T_171 = and(T_169, T_170)
    node T_172 = or(T_167, T_171)
    node T_173 = bits(T_120, 52, 32)
    node T_174 = bits(T_173, 15, 0)
    node T_177 = shl(UInt<8>("h0ff"), 8)
    node T_178 = xor(UInt<16>("h0ffff"), T_177)
    node T_179 = shr(T_174, 8)
    node T_180 = and(T_179, T_178)
    node T_181 = bits(T_174, 7, 0)
    node T_182 = shl(T_181, 8)
    node T_183 = not(T_178)
    node T_184 = and(T_182, T_183)
    node T_185 = or(T_180, T_184)
    node T_186 = bits(T_178, 11, 0)
    node T_187 = shl(T_186, 4)
    node T_188 = xor(T_178, T_187)
    node T_189 = shr(T_185, 4)
    node T_190 = and(T_189, T_188)
    node T_191 = bits(T_185, 11, 0)
    node T_192 = shl(T_191, 4)
    node T_193 = not(T_188)
    node T_194 = and(T_192, T_193)
    node T_195 = or(T_190, T_194)
    node T_196 = bits(T_188, 13, 0)
    node T_197 = shl(T_196, 2)
    node T_198 = xor(T_188, T_197)
    node T_199 = shr(T_195, 2)
    node T_200 = and(T_199, T_198)
    node T_201 = bits(T_195, 13, 0)
    node T_202 = shl(T_201, 2)
    node T_203 = not(T_198)
    node T_204 = and(T_202, T_203)
    node T_205 = or(T_200, T_204)
    node T_206 = bits(T_198, 14, 0)
    node T_207 = shl(T_206, 1)
    node T_208 = xor(T_198, T_207)
    node T_209 = shr(T_205, 1)
    node T_210 = and(T_209, T_208)
    node T_211 = bits(T_205, 14, 0)
    node T_212 = shl(T_211, 1)
    node T_213 = not(T_208)
    node T_214 = and(T_212, T_213)
    node T_215 = or(T_210, T_214)
    node T_216 = bits(T_173, 20, 16)
    node T_217 = bits(T_216, 3, 0)
    node T_218 = bits(T_217, 1, 0)
    node T_219 = bits(T_218, 0, 0)
    node T_220 = bits(T_218, 1, 1)
    node T_221 = cat(T_219, T_220)
    node T_222 = bits(T_217, 3, 2)
    node T_223 = bits(T_222, 0, 0)
    node T_224 = bits(T_222, 1, 1)
    node T_225 = cat(T_223, T_224)
    node T_226 = cat(T_221, T_225)
    node T_227 = bits(T_216, 4, 4)
    node T_228 = cat(T_226, T_227)
    node T_229 = cat(T_215, T_228)
    node CExtraMask = cat(T_172, T_229)
    node T_231 = not(sigC)
    node negSigC = mux(doSubMags, T_231, sigC)
    node T_234 = sub(UInt<108>("h00"), doSubMags)
    node T_235 = tail(T_234, 1)
    node T_236 = cat(negSigC, T_235)
    node T_237 = cat(doSubMags, T_236)
    node T_238 = asSInt(T_237)
    node T_239 = dshr(T_238, CAlignDist)
    node T_240 = and(sigC, CExtraMask)
    node T_242 = neq(T_240, UInt<1>("h00"))
    node T_243 = xor(T_242, doSubMags)
    node T_244 = asUInt(T_239)
    node T_245 = cat(T_244, T_243)
    node alignedNegSigC = bits(T_245, 161, 0)
    io.mulAddA <= sigA
    io.mulAddB <= sigB
    node T_247 = bits(alignedNegSigC, 106, 1)
    io.mulAddC <= T_247
    node T_248 = bits(expA, 11, 9)
    io.toPostMul.highExpA <= T_248
    node T_249 = bits(fractA, 51, 51)
    io.toPostMul.isNaN_isQuietNaNA <= T_249
    node T_250 = bits(expB, 11, 9)
    io.toPostMul.highExpB <= T_250
    node T_251 = bits(fractB, 51, 51)
    io.toPostMul.isNaN_isQuietNaNB <= T_251
    io.toPostMul.signProd <= signProd
    io.toPostMul.isZeroProd <= isZeroProd
    io.toPostMul.opSignC <= opSignC
    node T_252 = bits(expC, 11, 9)
    io.toPostMul.highExpC <= T_252
    node T_253 = bits(fractC, 51, 51)
    io.toPostMul.isNaN_isQuietNaNC <= T_253
    io.toPostMul.isCDominant <= isCDominant
    io.toPostMul.CAlignDist_0 <= CAlignDist_0
    io.toPostMul.CAlignDist <= CAlignDist
    node T_254 = bits(alignedNegSigC, 0, 0)
    io.toPostMul.bit0AlignedNegSigC <= T_254
    node T_255 = bits(alignedNegSigC, 161, 107)
    io.toPostMul.highAlignedNegSigC <= T_255
    io.toPostMul.sExpSum <= sExpSum
    io.toPostMul.roundingMode <= io.roundingMode
    
  module MulAddRecFN_postMul_116 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>}
    
    io is invalid
    node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00"))
    node T_44 = bits(io.fromPreMul.highExpA, 2, 1)
    node isSpecialA = eq(T_44, UInt<2>("h03"))
    node T_47 = bits(io.fromPreMul.highExpA, 0, 0)
    node T_49 = eq(T_47, UInt<1>("h00"))
    node isInfA = and(isSpecialA, T_49)
    node T_51 = bits(io.fromPreMul.highExpA, 0, 0)
    node isNaNA = and(isSpecialA, T_51)
    node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00"))
    node isSigNaNA = and(isNaNA, T_54)
    node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00"))
    node T_58 = bits(io.fromPreMul.highExpB, 2, 1)
    node isSpecialB = eq(T_58, UInt<2>("h03"))
    node T_61 = bits(io.fromPreMul.highExpB, 0, 0)
    node T_63 = eq(T_61, UInt<1>("h00"))
    node isInfB = and(isSpecialB, T_63)
    node T_65 = bits(io.fromPreMul.highExpB, 0, 0)
    node isNaNB = and(isSpecialB, T_65)
    node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00"))
    node isSigNaNB = and(isNaNB, T_68)
    node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00"))
    node T_72 = bits(io.fromPreMul.highExpC, 2, 1)
    node isSpecialC = eq(T_72, UInt<2>("h03"))
    node T_75 = bits(io.fromPreMul.highExpC, 0, 0)
    node T_77 = eq(T_75, UInt<1>("h00"))
    node isInfC = and(isSpecialC, T_77)
    node T_79 = bits(io.fromPreMul.highExpC, 0, 0)
    node isNaNC = and(isSpecialC, T_79)
    node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00"))
    node isSigNaNC = and(isNaNC, T_82)
    node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00"))
    node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01"))
    node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02"))
    node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03"))
    node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00"))
    node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC)
    node T_92 = bits(io.mulAddResult, 106, 106)
    node T_94 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01"))
    node T_95 = tail(T_94, 1)
    node T_96 = mux(T_92, T_95, io.fromPreMul.highAlignedNegSigC)
    node T_97 = bits(io.mulAddResult, 105, 0)
    node T_98 = cat(T_97, io.fromPreMul.bit0AlignedNegSigC)
    node sigSum = cat(T_96, T_98)
    node T_101 = bits(sigSum, 108, 1)
    node T_102 = xor(UInt<108>("h00"), T_101)
    node T_103 = or(UInt<108>("h00"), T_101)
    node T_104 = shl(T_103, 1)
    node T_105 = xor(T_102, T_104)
    node T_107 = bits(T_105, 107, 0)
    node T_108 = bits(T_107, 107, 107)
    node T_110 = bits(T_107, 106, 106)
    node T_112 = bits(T_107, 105, 105)
    node T_114 = bits(T_107, 104, 104)
    node T_116 = bits(T_107, 103, 103)
    node T_118 = bits(T_107, 102, 102)
    node T_120 = bits(T_107, 101, 101)
    node T_122 = bits(T_107, 100, 100)
    node T_124 = bits(T_107, 99, 99)
    node T_126 = bits(T_107, 98, 98)
    node T_128 = bits(T_107, 97, 97)
    node T_130 = bits(T_107, 96, 96)
    node T_132 = bits(T_107, 95, 95)
    node T_134 = bits(T_107, 94, 94)
    node T_136 = bits(T_107, 93, 93)
    node T_138 = bits(T_107, 92, 92)
    node T_140 = bits(T_107, 91, 91)
    node T_142 = bits(T_107, 90, 90)
    node T_144 = bits(T_107, 89, 89)
    node T_146 = bits(T_107, 88, 88)
    node T_148 = bits(T_107, 87, 87)
    node T_150 = bits(T_107, 86, 86)
    node T_152 = bits(T_107, 85, 85)
    node T_154 = bits(T_107, 84, 84)
    node T_156 = bits(T_107, 83, 83)
    node T_158 = bits(T_107, 82, 82)
    node T_160 = bits(T_107, 81, 81)
    node T_162 = bits(T_107, 80, 80)
    node T_164 = bits(T_107, 79, 79)
    node T_166 = bits(T_107, 78, 78)
    node T_168 = bits(T_107, 77, 77)
    node T_170 = bits(T_107, 76, 76)
    node T_172 = bits(T_107, 75, 75)
    node T_174 = bits(T_107, 74, 74)
    node T_176 = bits(T_107, 73, 73)
    node T_178 = bits(T_107, 72, 72)
    node T_180 = bits(T_107, 71, 71)
    node T_182 = bits(T_107, 70, 70)
    node T_184 = bits(T_107, 69, 69)
    node T_186 = bits(T_107, 68, 68)
    node T_188 = bits(T_107, 67, 67)
    node T_190 = bits(T_107, 66, 66)
    node T_192 = bits(T_107, 65, 65)
    node T_194 = bits(T_107, 64, 64)
    node T_196 = bits(T_107, 63, 63)
    node T_198 = bits(T_107, 62, 62)
    node T_200 = bits(T_107, 61, 61)
    node T_202 = bits(T_107, 60, 60)
    node T_204 = bits(T_107, 59, 59)
    node T_206 = bits(T_107, 58, 58)
    node T_208 = bits(T_107, 57, 57)
    node T_210 = bits(T_107, 56, 56)
    node T_212 = bits(T_107, 55, 55)
    node T_214 = bits(T_107, 54, 54)
    node T_216 = bits(T_107, 53, 53)
    node T_218 = bits(T_107, 52, 52)
    node T_220 = bits(T_107, 51, 51)
    node T_222 = bits(T_107, 50, 50)
    node T_224 = bits(T_107, 49, 49)
    node T_226 = bits(T_107, 48, 48)
    node T_228 = bits(T_107, 47, 47)
    node T_230 = bits(T_107, 46, 46)
    node T_232 = bits(T_107, 45, 45)
    node T_234 = bits(T_107, 44, 44)
    node T_236 = bits(T_107, 43, 43)
    node T_238 = bits(T_107, 42, 42)
    node T_240 = bits(T_107, 41, 41)
    node T_242 = bits(T_107, 40, 40)
    node T_244 = bits(T_107, 39, 39)
    node T_246 = bits(T_107, 38, 38)
    node T_248 = bits(T_107, 37, 37)
    node T_250 = bits(T_107, 36, 36)
    node T_252 = bits(T_107, 35, 35)
    node T_254 = bits(T_107, 34, 34)
    node T_256 = bits(T_107, 33, 33)
    node T_258 = bits(T_107, 32, 32)
    node T_260 = bits(T_107, 31, 31)
    node T_262 = bits(T_107, 30, 30)
    node T_264 = bits(T_107, 29, 29)
    node T_266 = bits(T_107, 28, 28)
    node T_268 = bits(T_107, 27, 27)
    node T_270 = bits(T_107, 26, 26)
    node T_272 = bits(T_107, 25, 25)
    node T_274 = bits(T_107, 24, 24)
    node T_276 = bits(T_107, 23, 23)
    node T_278 = bits(T_107, 22, 22)
    node T_280 = bits(T_107, 21, 21)
    node T_282 = bits(T_107, 20, 20)
    node T_284 = bits(T_107, 19, 19)
    node T_286 = bits(T_107, 18, 18)
    node T_288 = bits(T_107, 17, 17)
    node T_290 = bits(T_107, 16, 16)
    node T_292 = bits(T_107, 15, 15)
    node T_294 = bits(T_107, 14, 14)
    node T_296 = bits(T_107, 13, 13)
    node T_298 = bits(T_107, 12, 12)
    node T_300 = bits(T_107, 11, 11)
    node T_302 = bits(T_107, 10, 10)
    node T_304 = bits(T_107, 9, 9)
    node T_306 = bits(T_107, 8, 8)
    node T_308 = bits(T_107, 7, 7)
    node T_310 = bits(T_107, 6, 6)
    node T_312 = bits(T_107, 5, 5)
    node T_314 = bits(T_107, 4, 4)
    node T_316 = bits(T_107, 3, 3)
    node T_318 = bits(T_107, 2, 2)
    node T_320 = bits(T_107, 1, 1)
    node T_321 = shl(T_320, 0)
    node T_322 = mux(T_318, UInt<2>("h02"), T_321)
    node T_323 = mux(T_316, UInt<2>("h03"), T_322)
    node T_324 = mux(T_314, UInt<3>("h04"), T_323)
    node T_325 = mux(T_312, UInt<3>("h05"), T_324)
    node T_326 = mux(T_310, UInt<3>("h06"), T_325)
    node T_327 = mux(T_308, UInt<3>("h07"), T_326)
    node T_328 = mux(T_306, UInt<4>("h08"), T_327)
    node T_329 = mux(T_304, UInt<4>("h09"), T_328)
    node T_330 = mux(T_302, UInt<4>("h0a"), T_329)
    node T_331 = mux(T_300, UInt<4>("h0b"), T_330)
    node T_332 = mux(T_298, UInt<4>("h0c"), T_331)
    node T_333 = mux(T_296, UInt<4>("h0d"), T_332)
    node T_334 = mux(T_294, UInt<4>("h0e"), T_333)
    node T_335 = mux(T_292, UInt<4>("h0f"), T_334)
    node T_336 = mux(T_290, UInt<5>("h010"), T_335)
    node T_337 = mux(T_288, UInt<5>("h011"), T_336)
    node T_338 = mux(T_286, UInt<5>("h012"), T_337)
    node T_339 = mux(T_284, UInt<5>("h013"), T_338)
    node T_340 = mux(T_282, UInt<5>("h014"), T_339)
    node T_341 = mux(T_280, UInt<5>("h015"), T_340)
    node T_342 = mux(T_278, UInt<5>("h016"), T_341)
    node T_343 = mux(T_276, UInt<5>("h017"), T_342)
    node T_344 = mux(T_274, UInt<5>("h018"), T_343)
    node T_345 = mux(T_272, UInt<5>("h019"), T_344)
    node T_346 = mux(T_270, UInt<5>("h01a"), T_345)
    node T_347 = mux(T_268, UInt<5>("h01b"), T_346)
    node T_348 = mux(T_266, UInt<5>("h01c"), T_347)
    node T_349 = mux(T_264, UInt<5>("h01d"), T_348)
    node T_350 = mux(T_262, UInt<5>("h01e"), T_349)
    node T_351 = mux(T_260, UInt<5>("h01f"), T_350)
    node T_352 = mux(T_258, UInt<6>("h020"), T_351)
    node T_353 = mux(T_256, UInt<6>("h021"), T_352)
    node T_354 = mux(T_254, UInt<6>("h022"), T_353)
    node T_355 = mux(T_252, UInt<6>("h023"), T_354)
    node T_356 = mux(T_250, UInt<6>("h024"), T_355)
    node T_357 = mux(T_248, UInt<6>("h025"), T_356)
    node T_358 = mux(T_246, UInt<6>("h026"), T_357)
    node T_359 = mux(T_244, UInt<6>("h027"), T_358)
    node T_360 = mux(T_242, UInt<6>("h028"), T_359)
    node T_361 = mux(T_240, UInt<6>("h029"), T_360)
    node T_362 = mux(T_238, UInt<6>("h02a"), T_361)
    node T_363 = mux(T_236, UInt<6>("h02b"), T_362)
    node T_364 = mux(T_234, UInt<6>("h02c"), T_363)
    node T_365 = mux(T_232, UInt<6>("h02d"), T_364)
    node T_366 = mux(T_230, UInt<6>("h02e"), T_365)
    node T_367 = mux(T_228, UInt<6>("h02f"), T_366)
    node T_368 = mux(T_226, UInt<6>("h030"), T_367)
    node T_369 = mux(T_224, UInt<6>("h031"), T_368)
    node T_370 = mux(T_222, UInt<6>("h032"), T_369)
    node T_371 = mux(T_220, UInt<6>("h033"), T_370)
    node T_372 = mux(T_218, UInt<6>("h034"), T_371)
    node T_373 = mux(T_216, UInt<6>("h035"), T_372)
    node T_374 = mux(T_214, UInt<6>("h036"), T_373)
    node T_375 = mux(T_212, UInt<6>("h037"), T_374)
    node T_376 = mux(T_210, UInt<6>("h038"), T_375)
    node T_377 = mux(T_208, UInt<6>("h039"), T_376)
    node T_378 = mux(T_206, UInt<6>("h03a"), T_377)
    node T_379 = mux(T_204, UInt<6>("h03b"), T_378)
    node T_380 = mux(T_202, UInt<6>("h03c"), T_379)
    node T_381 = mux(T_200, UInt<6>("h03d"), T_380)
    node T_382 = mux(T_198, UInt<6>("h03e"), T_381)
    node T_383 = mux(T_196, UInt<6>("h03f"), T_382)
    node T_384 = mux(T_194, UInt<7>("h040"), T_383)
    node T_385 = mux(T_192, UInt<7>("h041"), T_384)
    node T_386 = mux(T_190, UInt<7>("h042"), T_385)
    node T_387 = mux(T_188, UInt<7>("h043"), T_386)
    node T_388 = mux(T_186, UInt<7>("h044"), T_387)
    node T_389 = mux(T_184, UInt<7>("h045"), T_388)
    node T_390 = mux(T_182, UInt<7>("h046"), T_389)
    node T_391 = mux(T_180, UInt<7>("h047"), T_390)
    node T_392 = mux(T_178, UInt<7>("h048"), T_391)
    node T_393 = mux(T_176, UInt<7>("h049"), T_392)
    node T_394 = mux(T_174, UInt<7>("h04a"), T_393)
    node T_395 = mux(T_172, UInt<7>("h04b"), T_394)
    node T_396 = mux(T_170, UInt<7>("h04c"), T_395)
    node T_397 = mux(T_168, UInt<7>("h04d"), T_396)
    node T_398 = mux(T_166, UInt<7>("h04e"), T_397)
    node T_399 = mux(T_164, UInt<7>("h04f"), T_398)
    node T_400 = mux(T_162, UInt<7>("h050"), T_399)
    node T_401 = mux(T_160, UInt<7>("h051"), T_400)
    node T_402 = mux(T_158, UInt<7>("h052"), T_401)
    node T_403 = mux(T_156, UInt<7>("h053"), T_402)
    node T_404 = mux(T_154, UInt<7>("h054"), T_403)
    node T_405 = mux(T_152, UInt<7>("h055"), T_404)
    node T_406 = mux(T_150, UInt<7>("h056"), T_405)
    node T_407 = mux(T_148, UInt<7>("h057"), T_406)
    node T_408 = mux(T_146, UInt<7>("h058"), T_407)
    node T_409 = mux(T_144, UInt<7>("h059"), T_408)
    node T_410 = mux(T_142, UInt<7>("h05a"), T_409)
    node T_411 = mux(T_140, UInt<7>("h05b"), T_410)
    node T_412 = mux(T_138, UInt<7>("h05c"), T_411)
    node T_413 = mux(T_136, UInt<7>("h05d"), T_412)
    node T_414 = mux(T_134, UInt<7>("h05e"), T_413)
    node T_415 = mux(T_132, UInt<7>("h05f"), T_414)
    node T_416 = mux(T_130, UInt<7>("h060"), T_415)
    node T_417 = mux(T_128, UInt<7>("h061"), T_416)
    node T_418 = mux(T_126, UInt<7>("h062"), T_417)
    node T_419 = mux(T_124, UInt<7>("h063"), T_418)
    node T_420 = mux(T_122, UInt<7>("h064"), T_419)
    node T_421 = mux(T_120, UInt<7>("h065"), T_420)
    node T_422 = mux(T_118, UInt<7>("h066"), T_421)
    node T_423 = mux(T_116, UInt<7>("h067"), T_422)
    node T_424 = mux(T_114, UInt<7>("h068"), T_423)
    node T_425 = mux(T_112, UInt<7>("h069"), T_424)
    node T_426 = mux(T_110, UInt<7>("h06a"), T_425)
    node T_427 = mux(T_108, UInt<7>("h06b"), T_426)
    node T_428 = sub(UInt<8>("h0a0"), T_427)
    node estNormPos_dist = tail(T_428, 1)
    node T_430 = bits(sigSum, 75, 44)
    node T_432 = neq(T_430, UInt<1>("h00"))
    node T_433 = bits(sigSum, 43, 0)
    node T_435 = neq(T_433, UInt<1>("h00"))
    node firstReduceSigSum = cat(T_432, T_435)
    node notSigSum = not(sigSum)
    node T_438 = bits(notSigSum, 75, 44)
    node T_440 = neq(T_438, UInt<1>("h00"))
    node T_441 = bits(notSigSum, 43, 0)
    node T_443 = neq(T_441, UInt<1>("h00"))
    node firstReduceNotSigSum = cat(T_440, T_443)
    node T_445 = or(io.fromPreMul.CAlignDist_0, doSubMags)
    node T_447 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01"))
    node T_448 = tail(T_447, 1)
    node T_449 = bits(T_448, 5, 0)
    node CDom_estNormDist = mux(T_445, io.fromPreMul.CAlignDist, T_449)
    node T_451 = not(doSubMags)
    node T_452 = bits(CDom_estNormDist, 5, 5)
    node T_453 = not(T_452)
    node T_454 = and(T_451, T_453)
    node T_455 = asSInt(T_454)
    node T_456 = bits(sigSum, 161, 76)
    node T_458 = neq(firstReduceSigSum, UInt<1>("h00"))
    node T_459 = cat(T_456, T_458)
    node T_460 = asSInt(T_459)
    node T_461 = and(T_455, T_460)
    node T_462 = asSInt(T_461)
    node T_463 = not(doSubMags)
    node T_464 = bits(CDom_estNormDist, 5, 5)
    node T_465 = and(T_463, T_464)
    node T_466 = asSInt(T_465)
    node T_467 = bits(sigSum, 129, 44)
    node T_468 = bits(firstReduceSigSum, 0, 0)
    node T_469 = cat(T_467, T_468)
    node T_470 = asSInt(T_469)
    node T_471 = and(T_466, T_470)
    node T_472 = asSInt(T_471)
    node T_473 = or(T_462, T_472)
    node T_474 = asSInt(T_473)
    node T_475 = bits(CDom_estNormDist, 5, 5)
    node T_476 = not(T_475)
    node T_477 = and(doSubMags, T_476)
    node T_478 = asSInt(T_477)
    node T_479 = bits(notSigSum, 161, 76)
    node T_481 = neq(firstReduceNotSigSum, UInt<1>("h00"))
    node T_482 = cat(T_479, T_481)
    node T_483 = asSInt(T_482)
    node T_484 = and(T_478, T_483)
    node T_485 = asSInt(T_484)
    node T_486 = or(T_474, T_485)
    node T_487 = asSInt(T_486)
    node T_488 = bits(CDom_estNormDist, 5, 5)
    node T_489 = and(doSubMags, T_488)
    node T_490 = asSInt(T_489)
    node T_491 = bits(notSigSum, 129, 44)
    node T_492 = bits(firstReduceNotSigSum, 0, 0)
    node T_493 = cat(T_491, T_492)
    node T_494 = asSInt(T_493)
    node T_495 = and(T_490, T_494)
    node T_496 = asSInt(T_495)
    node T_497 = or(T_487, T_496)
    node T_498 = asSInt(T_497)
    node CDom_firstNormAbsSigSum = asUInt(T_498)
    node T_500 = bits(sigSum, 108, 44)
    node T_501 = bits(firstReduceNotSigSum, 0, 0)
    node T_502 = not(T_501)
    node T_503 = bits(firstReduceSigSum, 0, 0)
    node T_504 = mux(doSubMags, T_502, T_503)
    node T_505 = cat(T_500, T_504)
    node T_506 = bits(sigSum, 97, 1)
    node T_507 = bits(estNormPos_dist, 4, 4)
    node T_508 = bits(sigSum, 1, 1)
    node T_510 = sub(UInt<86>("h00"), doSubMags)
    node T_511 = tail(T_510, 1)
    node T_512 = cat(T_508, T_511)
    node T_513 = mux(T_507, T_505, T_512)
    node T_514 = bits(sigSum, 97, 12)
    node T_515 = bits(notSigSum, 11, 1)
    node T_517 = eq(T_515, UInt<1>("h00"))
    node T_518 = bits(sigSum, 11, 1)
    node T_520 = neq(T_518, UInt<1>("h00"))
    node T_521 = mux(doSubMags, T_517, T_520)
    node T_522 = cat(T_514, T_521)
    node T_523 = bits(estNormPos_dist, 6, 6)
    node T_524 = bits(estNormPos_dist, 5, 5)
    node T_525 = bits(sigSum, 65, 1)
    node T_527 = sub(UInt<22>("h00"), doSubMags)
    node T_528 = tail(T_527, 1)
    node T_529 = cat(T_525, T_528)
    node T_530 = mux(T_524, T_529, T_522)
    node T_531 = bits(estNormPos_dist, 5, 5)
    node T_532 = bits(sigSum, 33, 1)
    node T_534 = sub(UInt<54>("h00"), doSubMags)
    node T_535 = tail(T_534, 1)
    node T_536 = cat(T_532, T_535)
    node T_537 = mux(T_531, T_513, T_536)
    node notCDom_pos_firstNormAbsSigSum = mux(T_523, T_530, T_537)
    node T_539 = bits(notSigSum, 107, 44)
    node T_540 = bits(firstReduceNotSigSum, 0, 0)
    node T_541 = cat(T_539, T_540)
    node T_542 = bits(notSigSum, 97, 1)
    node T_543 = bits(estNormPos_dist, 4, 4)
    node T_544 = bits(notSigSum, 2, 1)
    node T_546 = dshl(T_544, UInt<7>("h056"))
    node T_547 = mux(T_543, T_541, T_546)
    node T_548 = bits(notSigSum, 98, 12)
    node T_549 = bits(notSigSum, 11, 1)
    node T_551 = neq(T_549, UInt<1>("h00"))
    node T_552 = cat(T_548, T_551)
    node T_553 = bits(estNormPos_dist, 6, 6)
    node T_554 = bits(estNormPos_dist, 5, 5)
    node T_555 = bits(notSigSum, 66, 1)
    node T_557 = dshl(T_555, UInt<5>("h016"))
    node T_558 = mux(T_554, T_557, T_552)
    node T_559 = bits(estNormPos_dist, 5, 5)
    node T_560 = bits(notSigSum, 34, 1)
    node T_562 = dshl(T_560, UInt<6>("h036"))
    node T_563 = mux(T_559, T_547, T_562)
    node notCDom_neg_cFirstNormAbsSigSum = mux(T_553, T_558, T_563)
    node notCDom_signSigSum = bits(sigSum, 109, 109)
    node T_566 = not(isZeroC)
    node T_567 = and(doSubMags, T_566)
    node doNegSignSum = mux(io.fromPreMul.isCDominant, T_567, notCDom_signSigSum)
    node T_569 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist)
    node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_569)
    node T_571 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum)
    node T_572 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum)
    node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_571, T_572)
    node T_574 = not(io.fromPreMul.isCDominant)
    node T_575 = not(notCDom_signSigSum)
    node T_576 = and(T_574, T_575)
    node doIncrSig = and(T_576, doSubMags)
    node estNormDist_5 = bits(estNormDist, 4, 0)
    node normTo2ShiftDist = not(estNormDist_5)
    node T_581 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist)
    node T_582 = bits(T_581, 31, 1)
    node T_583 = bits(T_582, 15, 0)
    node T_586 = shl(UInt<8>("h0ff"), 8)
    node T_587 = xor(UInt<16>("h0ffff"), T_586)
    node T_588 = shr(T_583, 8)
    node T_589 = and(T_588, T_587)
    node T_590 = bits(T_583, 7, 0)
    node T_591 = shl(T_590, 8)
    node T_592 = not(T_587)
    node T_593 = and(T_591, T_592)
    node T_594 = or(T_589, T_593)
    node T_595 = bits(T_587, 11, 0)
    node T_596 = shl(T_595, 4)
    node T_597 = xor(T_587, T_596)
    node T_598 = shr(T_594, 4)
    node T_599 = and(T_598, T_597)
    node T_600 = bits(T_594, 11, 0)
    node T_601 = shl(T_600, 4)
    node T_602 = not(T_597)
    node T_603 = and(T_601, T_602)
    node T_604 = or(T_599, T_603)
    node T_605 = bits(T_597, 13, 0)
    node T_606 = shl(T_605, 2)
    node T_607 = xor(T_597, T_606)
    node T_608 = shr(T_604, 2)
    node T_609 = and(T_608, T_607)
    node T_610 = bits(T_604, 13, 0)
    node T_611 = shl(T_610, 2)
    node T_612 = not(T_607)
    node T_613 = and(T_611, T_612)
    node T_614 = or(T_609, T_613)
    node T_615 = bits(T_607, 14, 0)
    node T_616 = shl(T_615, 1)
    node T_617 = xor(T_607, T_616)
    node T_618 = shr(T_614, 1)
    node T_619 = and(T_618, T_617)
    node T_620 = bits(T_614, 14, 0)
    node T_621 = shl(T_620, 1)
    node T_622 = not(T_617)
    node T_623 = and(T_621, T_622)
    node T_624 = or(T_619, T_623)
    node T_625 = bits(T_582, 30, 16)
    node T_626 = bits(T_625, 7, 0)
    node T_629 = shl(UInt<4>("h0f"), 4)
    node T_630 = xor(UInt<8>("h0ff"), T_629)
    node T_631 = shr(T_626, 4)
    node T_632 = and(T_631, T_630)
    node T_633 = bits(T_626, 3, 0)
    node T_634 = shl(T_633, 4)
    node T_635 = not(T_630)
    node T_636 = and(T_634, T_635)
    node T_637 = or(T_632, T_636)
    node T_638 = bits(T_630, 5, 0)
    node T_639 = shl(T_638, 2)
    node T_640 = xor(T_630, T_639)
    node T_641 = shr(T_637, 2)
    node T_642 = and(T_641, T_640)
    node T_643 = bits(T_637, 5, 0)
    node T_644 = shl(T_643, 2)
    node T_645 = not(T_640)
    node T_646 = and(T_644, T_645)
    node T_647 = or(T_642, T_646)
    node T_648 = bits(T_640, 6, 0)
    node T_649 = shl(T_648, 1)
    node T_650 = xor(T_640, T_649)
    node T_651 = shr(T_647, 1)
    node T_652 = and(T_651, T_650)
    node T_653 = bits(T_647, 6, 0)
    node T_654 = shl(T_653, 1)
    node T_655 = not(T_650)
    node T_656 = and(T_654, T_655)
    node T_657 = or(T_652, T_656)
    node T_658 = bits(T_625, 14, 8)
    node T_659 = bits(T_658, 3, 0)
    node T_660 = bits(T_659, 1, 0)
    node T_661 = bits(T_660, 0, 0)
    node T_662 = bits(T_660, 1, 1)
    node T_663 = cat(T_661, T_662)
    node T_664 = bits(T_659, 3, 2)
    node T_665 = bits(T_664, 0, 0)
    node T_666 = bits(T_664, 1, 1)
    node T_667 = cat(T_665, T_666)
    node T_668 = cat(T_663, T_667)
    node T_669 = bits(T_658, 6, 4)
    node T_670 = bits(T_669, 1, 0)
    node T_671 = bits(T_670, 0, 0)
    node T_672 = bits(T_670, 1, 1)
    node T_673 = cat(T_671, T_672)
    node T_674 = bits(T_669, 2, 2)
    node T_675 = cat(T_673, T_674)
    node T_676 = cat(T_668, T_675)
    node T_677 = cat(T_657, T_676)
    node T_678 = cat(T_624, T_677)
    node absSigSumExtraMask = cat(T_678, UInt<1>("h01"))
    node T_681 = bits(cFirstNormAbsSigSum, 87, 1)
    node T_682 = dshr(T_681, normTo2ShiftDist)
    node T_683 = bits(cFirstNormAbsSigSum, 31, 0)
    node T_684 = not(T_683)
    node T_685 = and(T_684, absSigSumExtraMask)
    node T_687 = eq(T_685, UInt<1>("h00"))
    node T_688 = bits(cFirstNormAbsSigSum, 31, 0)
    node T_689 = and(T_688, absSigSumExtraMask)
    node T_691 = neq(T_689, UInt<1>("h00"))
    node T_692 = mux(doIncrSig, T_687, T_691)
    node T_693 = cat(T_682, T_692)
    node sigX3 = bits(T_693, 56, 0)
    node T_695 = bits(sigX3, 56, 55)
    node sigX3Shift1 = eq(T_695, UInt<1>("h00"))
    node T_698 = sub(io.fromPreMul.sExpSum, estNormDist)
    node sExpX3 = tail(T_698, 1)
    node T_700 = bits(sigX3, 56, 54)
    node isZeroY = eq(T_700, UInt<1>("h00"))
    node T_703 = xor(io.fromPreMul.signProd, doNegSignSum)
    node signY = mux(isZeroY, signZeroNotEqOpSigns, T_703)
    node sExpX3_13 = bits(sExpX3, 12, 0)
    node T_706 = bits(sExpX3, 13, 13)
    node T_708 = sub(UInt<56>("h00"), T_706)
    node T_709 = tail(T_708, 1)
    node T_710 = not(sExpX3_13)
    node T_712 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_710)
    node T_713 = bits(T_712, 1027, 974)
    node T_714 = bits(T_713, 31, 0)
    node T_717 = shl(UInt<16>("h0ffff"), 16)
    node T_718 = xor(UInt<32>("h0ffffffff"), T_717)
    node T_719 = shr(T_714, 16)
    node T_720 = and(T_719, T_718)
    node T_721 = bits(T_714, 15, 0)
    node T_722 = shl(T_721, 16)
    node T_723 = not(T_718)
    node T_724 = and(T_722, T_723)
    node T_725 = or(T_720, T_724)
    node T_726 = bits(T_718, 23, 0)
    node T_727 = shl(T_726, 8)
    node T_728 = xor(T_718, T_727)
    node T_729 = shr(T_725, 8)
    node T_730 = and(T_729, T_728)
    node T_731 = bits(T_725, 23, 0)
    node T_732 = shl(T_731, 8)
    node T_733 = not(T_728)
    node T_734 = and(T_732, T_733)
    node T_735 = or(T_730, T_734)
    node T_736 = bits(T_728, 27, 0)
    node T_737 = shl(T_736, 4)
    node T_738 = xor(T_728, T_737)
    node T_739 = shr(T_735, 4)
    node T_740 = and(T_739, T_738)
    node T_741 = bits(T_735, 27, 0)
    node T_742 = shl(T_741, 4)
    node T_743 = not(T_738)
    node T_744 = and(T_742, T_743)
    node T_745 = or(T_740, T_744)
    node T_746 = bits(T_738, 29, 0)
    node T_747 = shl(T_746, 2)
    node T_748 = xor(T_738, T_747)
    node T_749 = shr(T_745, 2)
    node T_750 = and(T_749, T_748)
    node T_751 = bits(T_745, 29, 0)
    node T_752 = shl(T_751, 2)
    node T_753 = not(T_748)
    node T_754 = and(T_752, T_753)
    node T_755 = or(T_750, T_754)
    node T_756 = bits(T_748, 30, 0)
    node T_757 = shl(T_756, 1)
    node T_758 = xor(T_748, T_757)
    node T_759 = shr(T_755, 1)
    node T_760 = and(T_759, T_758)
    node T_761 = bits(T_755, 30, 0)
    node T_762 = shl(T_761, 1)
    node T_763 = not(T_758)
    node T_764 = and(T_762, T_763)
    node T_765 = or(T_760, T_764)
    node T_766 = bits(T_713, 53, 32)
    node T_767 = bits(T_766, 15, 0)
    node T_770 = shl(UInt<8>("h0ff"), 8)
    node T_771 = xor(UInt<16>("h0ffff"), T_770)
    node T_772 = shr(T_767, 8)
    node T_773 = and(T_772, T_771)
    node T_774 = bits(T_767, 7, 0)
    node T_775 = shl(T_774, 8)
    node T_776 = not(T_771)
    node T_777 = and(T_775, T_776)
    node T_778 = or(T_773, T_777)
    node T_779 = bits(T_771, 11, 0)
    node T_780 = shl(T_779, 4)
    node T_781 = xor(T_771, T_780)
    node T_782 = shr(T_778, 4)
    node T_783 = and(T_782, T_781)
    node T_784 = bits(T_778, 11, 0)
    node T_785 = shl(T_784, 4)
    node T_786 = not(T_781)
    node T_787 = and(T_785, T_786)
    node T_788 = or(T_783, T_787)
    node T_789 = bits(T_781, 13, 0)
    node T_790 = shl(T_789, 2)
    node T_791 = xor(T_781, T_790)
    node T_792 = shr(T_788, 2)
    node T_793 = and(T_792, T_791)
    node T_794 = bits(T_788, 13, 0)
    node T_795 = shl(T_794, 2)
    node T_796 = not(T_791)
    node T_797 = and(T_795, T_796)
    node T_798 = or(T_793, T_797)
    node T_799 = bits(T_791, 14, 0)
    node T_800 = shl(T_799, 1)
    node T_801 = xor(T_791, T_800)
    node T_802 = shr(T_798, 1)
    node T_803 = and(T_802, T_801)
    node T_804 = bits(T_798, 14, 0)
    node T_805 = shl(T_804, 1)
    node T_806 = not(T_801)
    node T_807 = and(T_805, T_806)
    node T_808 = or(T_803, T_807)
    node T_809 = bits(T_766, 21, 16)
    node T_810 = bits(T_809, 3, 0)
    node T_811 = bits(T_810, 1, 0)
    node T_812 = bits(T_811, 0, 0)
    node T_813 = bits(T_811, 1, 1)
    node T_814 = cat(T_812, T_813)
    node T_815 = bits(T_810, 3, 2)
    node T_816 = bits(T_815, 0, 0)
    node T_817 = bits(T_815, 1, 1)
    node T_818 = cat(T_816, T_817)
    node T_819 = cat(T_814, T_818)
    node T_820 = bits(T_809, 5, 4)
    node T_821 = bits(T_820, 0, 0)
    node T_822 = bits(T_820, 1, 1)
    node T_823 = cat(T_821, T_822)
    node T_824 = cat(T_819, T_823)
    node T_825 = cat(T_808, T_824)
    node T_826 = cat(T_765, T_825)
    node T_827 = bits(sigX3, 55, 55)
    node T_828 = or(T_826, T_827)
    node T_830 = cat(T_828, UInt<2>("h03"))
    node roundMask = or(T_709, T_830)
    node T_832 = shr(roundMask, 1)
    node T_833 = not(T_832)
    node roundPosMask = and(T_833, roundMask)
    node T_835 = and(sigX3, roundPosMask)
    node roundPosBit = neq(T_835, UInt<1>("h00"))
    node T_838 = shr(roundMask, 1)
    node T_839 = and(sigX3, T_838)
    node anyRoundExtra = neq(T_839, UInt<1>("h00"))
    node T_842 = not(sigX3)
    node T_843 = shr(roundMask, 1)
    node T_844 = and(T_842, T_843)
    node allRoundExtra = eq(T_844, UInt<1>("h00"))
    node anyRound = or(roundPosBit, anyRoundExtra)
    node allRound = and(roundPosBit, allRoundExtra)
    node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max)
    node T_850 = not(doIncrSig)
    node T_851 = and(T_850, roundingMode_nearest_even)
    node T_852 = and(T_851, roundPosBit)
    node T_853 = and(T_852, anyRoundExtra)
    node T_854 = not(doIncrSig)
    node T_855 = and(T_854, roundDirectUp)
    node T_856 = and(T_855, anyRound)
    node T_857 = or(T_853, T_856)
    node T_858 = and(doIncrSig, allRound)
    node T_859 = or(T_857, T_858)
    node T_860 = and(doIncrSig, roundingMode_nearest_even)
    node T_861 = and(T_860, roundPosBit)
    node T_862 = or(T_859, T_861)
    node T_863 = and(doIncrSig, roundDirectUp)
    node T_865 = and(T_863, UInt<1>("h01"))
    node roundUp = or(T_862, T_865)
    node T_867 = not(roundPosBit)
    node T_868 = and(roundingMode_nearest_even, T_867)
    node T_869 = and(T_868, allRoundExtra)
    node T_870 = and(roundingMode_nearest_even, roundPosBit)
    node T_871 = not(anyRoundExtra)
    node T_872 = and(T_870, T_871)
    node roundEven = mux(doIncrSig, T_869, T_872)
    node T_874 = not(allRound)
    node roundInexact = mux(doIncrSig, T_874, anyRound)
    node T_876 = or(sigX3, roundMask)
    node T_877 = shr(T_876, 2)
    node T_879 = add(T_877, UInt<1>("h01"))
    node T_880 = tail(T_879, 1)
    node roundUp_sigY3 = bits(T_880, 54, 0)
    node T_882 = not(roundUp)
    node T_883 = not(roundEven)
    node T_884 = and(T_882, T_883)
    node T_885 = bits(T_884, 0, 0)
    node T_886 = not(roundMask)
    node T_887 = and(sigX3, T_886)
    node T_888 = shr(T_887, 2)
    node T_890 = mux(T_885, T_888, UInt<1>("h00"))
    node T_891 = bits(roundUp, 0, 0)
    node T_893 = mux(T_891, roundUp_sigY3, UInt<1>("h00"))
    node T_894 = or(T_890, T_893)
    node T_895 = shr(roundMask, 1)
    node T_896 = not(T_895)
    node T_897 = and(roundUp_sigY3, T_896)
    node T_899 = mux(roundEven, T_897, UInt<1>("h00"))
    node sigY3 = or(T_894, T_899)
    node T_901 = bits(sigY3, 54, 54)
    node T_903 = add(sExpX3, UInt<1>("h01"))
    node T_904 = tail(T_903, 1)
    node T_906 = mux(T_901, T_904, UInt<1>("h00"))
    node T_907 = bits(sigY3, 53, 53)
    node T_909 = mux(T_907, sExpX3, UInt<1>("h00"))
    node T_910 = or(T_906, T_909)
    node T_911 = bits(sigY3, 54, 53)
    node T_913 = eq(T_911, UInt<1>("h00"))
    node T_915 = sub(sExpX3, UInt<1>("h01"))
    node T_916 = tail(T_915, 1)
    node T_918 = mux(T_913, T_916, UInt<1>("h00"))
    node sExpY = or(T_910, T_918)
    node expY = bits(sExpY, 11, 0)
    node T_921 = bits(sigY3, 51, 0)
    node T_922 = bits(sigY3, 52, 1)
    node fractY = mux(sigX3Shift1, T_921, T_922)
    node T_924 = bits(sExpY, 12, 10)
    node overflowY = eq(T_924, UInt<2>("h03"))
    node T_927 = not(isZeroY)
    node T_928 = bits(sExpY, 12, 12)
    node T_929 = bits(sExpY, 11, 0)
    node T_931 = lt(T_929, UInt<10>("h03ce"))
    node T_932 = or(T_928, T_931)
    node totalUnderflowY = and(T_927, T_932)
    node T_934 = bits(sExpX3, 13, 13)
    node T_937 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401"))
    node T_938 = leq(sExpX3_13, T_937)
    node T_939 = or(T_934, T_938)
    node underflowY = and(roundInexact, T_939)
    node T_941 = and(roundingMode_min, signY)
    node T_942 = not(signY)
    node T_943 = and(roundingMode_max, T_942)
    node roundMagUp = or(T_941, T_943)
    node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp)
    node mulSpecial = or(isSpecialA, isSpecialB)
    node addSpecial = or(mulSpecial, isSpecialC)
    node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC)
    node T_949 = not(addSpecial)
    node T_950 = not(notSpecial_addZeros)
    node commonCase = and(T_949, T_950)
    node T_952 = and(isInfA, isZeroB)
    node T_953 = and(isZeroA, isInfB)
    node T_954 = or(T_952, T_953)
    node T_955 = not(isNaNA)
    node T_956 = not(isNaNB)
    node T_957 = and(T_955, T_956)
    node T_958 = or(isInfA, isInfB)
    node T_959 = and(T_957, T_958)
    node T_960 = and(T_959, isInfC)
    node T_961 = and(T_960, doSubMags)
    node notSigNaN_invalid = or(T_954, T_961)
    node T_963 = or(isSigNaNA, isSigNaNB)
    node T_964 = or(T_963, isSigNaNC)
    node invalid = or(T_964, notSigNaN_invalid)
    node overflow = and(commonCase, overflowY)
    node underflow = and(commonCase, underflowY)
    node T_968 = and(commonCase, roundInexact)
    node inexact = or(overflow, T_968)
    node T_970 = or(notSpecial_addZeros, isZeroY)
    node notSpecial_isZeroOut = or(T_970, totalUnderflowY)
    node T_972 = and(commonCase, totalUnderflowY)
    node pegMinFiniteMagOut = and(T_972, roundMagUp)
    node T_974 = not(overflowY_roundMagUp)
    node pegMaxFiniteMagOut = and(overflow, T_974)
    node T_976 = or(isInfA, isInfB)
    node T_977 = or(T_976, isInfC)
    node T_978 = and(overflow, overflowY_roundMagUp)
    node notNaN_isInfOut = or(T_977, T_978)
    node T_980 = or(isNaNA, isNaNB)
    node T_981 = or(T_980, isNaNC)
    node isNaNOut = or(T_981, notSigNaN_invalid)
    node T_984 = eq(doSubMags, UInt<1>("h00"))
    node T_985 = and(T_984, io.fromPreMul.opSignC)
    node T_987 = eq(isSpecialC, UInt<1>("h00"))
    node T_988 = and(mulSpecial, T_987)
    node T_989 = and(T_988, io.fromPreMul.signProd)
    node T_990 = or(T_985, T_989)
    node T_992 = eq(mulSpecial, UInt<1>("h00"))
    node T_993 = and(T_992, isSpecialC)
    node T_994 = and(T_993, io.fromPreMul.opSignC)
    node T_995 = or(T_990, T_994)
    node T_997 = eq(mulSpecial, UInt<1>("h00"))
    node T_998 = and(T_997, notSpecial_addZeros)
    node T_999 = and(T_998, doSubMags)
    node T_1000 = and(T_999, signZeroNotEqOpSigns)
    node uncommonCaseSignOut = or(T_995, T_1000)
    node T_1003 = eq(isNaNOut, UInt<1>("h00"))
    node T_1004 = and(T_1003, uncommonCaseSignOut)
    node T_1005 = and(commonCase, signY)
    node signOut = or(T_1004, T_1005)
    node T_1009 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00"))
    node T_1010 = not(T_1009)
    node T_1011 = and(expY, T_1010)
    node T_1013 = not(UInt<12>("h03ce"))
    node T_1015 = mux(pegMinFiniteMagOut, T_1013, UInt<12>("h00"))
    node T_1016 = not(T_1015)
    node T_1017 = and(T_1011, T_1016)
    node T_1020 = mux(pegMaxFiniteMagOut, UInt<12>("h0400"), UInt<12>("h00"))
    node T_1021 = not(T_1020)
    node T_1022 = and(T_1017, T_1021)
    node T_1025 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00"))
    node T_1026 = not(T_1025)
    node T_1027 = and(T_1022, T_1026)
    node T_1030 = mux(pegMinFiniteMagOut, UInt<10>("h03ce"), UInt<12>("h00"))
    node T_1031 = or(T_1027, T_1030)
    node T_1034 = mux(pegMaxFiniteMagOut, UInt<12>("h0bff"), UInt<12>("h00"))
    node T_1035 = or(T_1031, T_1034)
    node T_1038 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00"))
    node T_1039 = or(T_1035, T_1038)
    node T_1042 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00"))
    node expOut = or(T_1039, T_1042)
    node T_1044 = and(totalUnderflowY, roundMagUp)
    node T_1045 = or(T_1044, isNaNOut)
    node T_1047 = mux(T_1045, UInt<1>("h00"), fractY)
    node T_1048 = shl(isNaNOut, 51)
    node T_1049 = or(T_1047, T_1048)
    node T_1051 = sub(UInt<52>("h00"), pegMaxFiniteMagOut)
    node T_1052 = tail(T_1051, 1)
    node fractOut = or(T_1049, T_1052)
    node T_1054 = cat(expOut, fractOut)
    node T_1055 = cat(signOut, T_1054)
    io.out <= T_1055
    node T_1057 = cat(invalid, UInt<1>("h00"))
    node T_1058 = cat(underflow, inexact)
    node T_1059 = cat(overflow, T_1058)
    node T_1060 = cat(T_1057, T_1059)
    io.exceptionFlags <= T_1060
    
  module MulAddRecFN_114 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>}
    
    io is invalid
    inst mulAddRecFN_preMul of MulAddRecFN_preMul_115
    mulAddRecFN_preMul.io is invalid
    mulAddRecFN_preMul.clk <= clk
    mulAddRecFN_preMul.reset <= reset
    inst mulAddRecFN_postMul of MulAddRecFN_postMul_116
    mulAddRecFN_postMul.io is invalid
    mulAddRecFN_postMul.clk <= clk
    mulAddRecFN_postMul.reset <= reset
    mulAddRecFN_preMul.io.op <= io.op
    mulAddRecFN_preMul.io.a <= io.a
    mulAddRecFN_preMul.io.b <= io.b
    mulAddRecFN_preMul.io.c <= io.c
    mulAddRecFN_preMul.io.roundingMode <= io.roundingMode
    mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul
    node T_14 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB)
    node T_16 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC)
    node T_17 = add(T_14, T_16)
    node T_18 = tail(T_17, 1)
    mulAddRecFN_postMul.io.mulAddResult <= T_18
    io.out <= mulAddRecFN_postMul.io.out
    io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags
    
  module FPUFMAPipe_113 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}
    
    io is invalid
    node one = shl(UInt<1>("h01"), 63)
    node T_136 = bits(io.in.bits.in1, 64, 64)
    node T_137 = bits(io.in.bits.in2, 64, 64)
    node T_138 = xor(T_136, T_137)
    node zero = shl(T_138, 64)
    reg valid : UInt<1>, clk
    valid <= io.in.valid
    reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk
    when io.in.valid :
      in <- io.in.bits
      node T_187 = bits(io.in.bits.cmd, 1, 1)
      node T_188 = or(io.in.bits.ren3, io.in.bits.swap23)
      node T_189 = and(T_187, T_188)
      node T_190 = bits(io.in.bits.cmd, 0, 0)
      node T_191 = cat(T_189, T_190)
      in.cmd <= T_191
      when io.in.bits.swap23 :
        in.in2 <= one
        skip
      node T_192 = or(io.in.bits.ren3, io.in.bits.swap23)
      node T_194 = eq(T_192, UInt<1>("h00"))
      when T_194 :
        in.in3 <= zero
        skip
      skip
    inst fma of MulAddRecFN_114
    fma.io is invalid
    fma.clk <= clk
    fma.reset <= reset
    fma.io.op <= in.cmd
    fma.io.roundingMode <= in.rm
    fma.io.a <= in.in1
    fma.io.b <= in.in2
    fma.io.c <= in.in3
    wire res : {data : UInt<65>, exc : UInt<5>}
    res is invalid
    node T_203 = asUInt(asSInt(UInt<32>("h0ffffffff")))
    node T_204 = cat(T_203, fma.io.out)
    res.data <= T_204
    res.exc <= fma.io.exceptionFlags
    reg T_207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_207 <= valid
    reg T_208 : {data : UInt<65>, exc : UInt<5>}, clk
    when valid :
      T_208 <- res
      skip
    reg T_213 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_213 <= T_207
    reg T_214 : {data : UInt<65>, exc : UInt<5>}, clk
    when T_207 :
      T_214 <- T_208
      skip
    wire T_225 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}
    T_225 is invalid
    T_225.valid <= T_213
    T_225.bits <- T_214
    io.out <- T_225
    
  module RecFNToRecFN : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>}
    
    io is invalid
    node T_8 = bits(io.in, 31, 23)
    node T_9 = bits(T_8, 8, 7)
    node T_11 = eq(T_9, UInt<2>("h03"))
    wire T_19 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}
    T_19 is invalid
    node T_26 = bits(io.in, 32, 32)
    T_19.sign <= T_26
    node T_27 = bits(T_8, 6, 6)
    node T_28 = and(T_11, T_27)
    T_19.isNaN <= T_28
    node T_29 = bits(T_8, 6, 6)
    node T_31 = eq(T_29, UInt<1>("h00"))
    node T_32 = and(T_11, T_31)
    T_19.isInf <= T_32
    node T_33 = bits(T_8, 8, 6)
    node T_35 = eq(T_33, UInt<1>("h00"))
    T_19.isZero <= T_35
    node T_36 = cvt(T_8)
    T_19.sExp <= T_36
    node T_38 = bits(io.in, 22, 0)
    node T_40 = cat(T_38, UInt<2>("h00"))
    node T_41 = cat(UInt<2>("h01"), T_40)
    T_19.sig <= T_41
    node T_43 = add(T_19.sExp, asSInt(UInt<12>("h0700")))
    node T_44 = tail(T_43, 1)
    node T_45 = asSInt(T_44)
    wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>}
    outRawFloat is invalid
    outRawFloat.sign <= T_19.sign
    outRawFloat.isNaN <= T_19.isNaN
    outRawFloat.isInf <= T_19.isInf
    outRawFloat.isZero <= T_19.isZero
    outRawFloat.sExp <= T_45
    node T_60 = shl(T_19.sig, 29)
    outRawFloat.sig <= T_60
    node T_61 = bits(outRawFloat.sig, 53, 53)
    node T_63 = eq(T_61, UInt<1>("h00"))
    node invalidExc = and(outRawFloat.isNaN, T_63)
    node T_65 = not(outRawFloat.isNaN)
    node T_66 = and(outRawFloat.sign, T_65)
    node T_67 = bits(outRawFloat.sExp, 11, 0)
    node T_70 = mux(outRawFloat.isZero, UInt<12>("h0c00"), UInt<1>("h00"))
    node T_71 = not(T_70)
    node T_72 = and(T_67, T_71)
    node T_73 = or(outRawFloat.isZero, outRawFloat.isInf)
    node T_76 = mux(T_73, UInt<12>("h0200"), UInt<1>("h00"))
    node T_77 = not(T_76)
    node T_78 = and(T_72, T_77)
    node T_81 = mux(outRawFloat.isInf, UInt<12>("h0c00"), UInt<1>("h00"))
    node T_82 = or(T_78, T_81)
    node T_85 = mux(outRawFloat.isNaN, UInt<12>("h0e00"), UInt<1>("h00"))
    node T_86 = or(T_82, T_85)
    node T_88 = bits(outRawFloat.sig, 53, 2)
    node T_89 = mux(outRawFloat.isNaN, UInt<52>("h08000000000000"), T_88)
    node T_90 = cat(T_86, T_89)
    node T_91 = cat(T_66, T_90)
    io.out <= T_91
    node T_93 = cat(invalidExc, UInt<4>("h00"))
    io.exceptionFlags <= T_93
    
  module CompareRecFN : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>}
    
    io is invalid
    node T_11 = bits(io.a, 63, 52)
    node T_12 = bits(T_11, 11, 10)
    node T_14 = eq(T_12, UInt<2>("h03"))
    wire rawA : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>}
    rawA is invalid
    node T_29 = bits(io.a, 64, 64)
    rawA.sign <= T_29
    node T_30 = bits(T_11, 9, 9)
    node T_31 = and(T_14, T_30)
    rawA.isNaN <= T_31
    node T_32 = bits(T_11, 9, 9)
    node T_34 = eq(T_32, UInt<1>("h00"))
    node T_35 = and(T_14, T_34)
    rawA.isInf <= T_35
    node T_36 = bits(T_11, 11, 9)
    node T_38 = eq(T_36, UInt<1>("h00"))
    rawA.isZero <= T_38
    node T_39 = cvt(T_11)
    rawA.sExp <= T_39
    node T_41 = bits(io.a, 51, 0)
    node T_43 = cat(T_41, UInt<2>("h00"))
    node T_44 = cat(UInt<2>("h01"), T_43)
    rawA.sig <= T_44
    node T_45 = bits(io.b, 63, 52)
    node T_46 = bits(T_45, 11, 10)
    node T_48 = eq(T_46, UInt<2>("h03"))
    wire rawB : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>}
    rawB is invalid
    node T_63 = bits(io.b, 64, 64)
    rawB.sign <= T_63
    node T_64 = bits(T_45, 9, 9)
    node T_65 = and(T_48, T_64)
    rawB.isNaN <= T_65
    node T_66 = bits(T_45, 9, 9)
    node T_68 = eq(T_66, UInt<1>("h00"))
    node T_69 = and(T_48, T_68)
    rawB.isInf <= T_69
    node T_70 = bits(T_45, 11, 9)
    node T_72 = eq(T_70, UInt<1>("h00"))
    rawB.isZero <= T_72
    node T_73 = cvt(T_45)
    rawB.sExp <= T_73
    node T_75 = bits(io.b, 51, 0)
    node T_77 = cat(T_75, UInt<2>("h00"))
    node T_78 = cat(UInt<2>("h01"), T_77)
    rawB.sig <= T_78
    node T_79 = not(rawA.isNaN)
    node T_80 = not(rawB.isNaN)
    node ordered = and(T_79, T_80)
    node bothInfs = and(rawA.isInf, rawB.isInf)
    node bothZeros = and(rawA.isZero, rawB.isZero)
    node eqExps = eq(rawA.sExp, rawB.sExp)
    node T_85 = lt(rawA.sExp, rawB.sExp)
    node T_86 = lt(rawA.sig, rawB.sig)
    node T_87 = and(eqExps, T_86)
    node common_ltMags = or(T_85, T_87)
    node T_89 = eq(rawA.sig, rawB.sig)
    node common_eqMags = and(eqExps, T_89)
    node T_91 = not(bothZeros)
    node T_92 = not(rawB.sign)
    node T_93 = and(rawA.sign, T_92)
    node T_94 = not(bothInfs)
    node T_95 = not(common_ltMags)
    node T_96 = and(rawA.sign, T_95)
    node T_97 = not(common_eqMags)
    node T_98 = and(T_96, T_97)
    node T_99 = not(rawB.sign)
    node T_100 = and(T_99, common_ltMags)
    node T_101 = or(T_98, T_100)
    node T_102 = and(T_94, T_101)
    node T_103 = or(T_93, T_102)
    node ordered_lt = and(T_91, T_103)
    node T_105 = eq(rawA.sign, rawB.sign)
    node T_106 = or(bothInfs, common_eqMags)
    node T_107 = and(T_105, T_106)
    node ordered_eq = or(bothZeros, T_107)
    node T_109 = bits(rawA.sig, 53, 53)
    node T_111 = eq(T_109, UInt<1>("h00"))
    node T_112 = and(rawA.isNaN, T_111)
    node T_113 = bits(rawB.sig, 53, 53)
    node T_115 = eq(T_113, UInt<1>("h00"))
    node T_116 = and(rawB.isNaN, T_115)
    node T_117 = or(T_112, T_116)
    node T_118 = not(ordered)
    node T_119 = and(io.signaling, T_118)
    node invalid = or(T_117, T_119)
    node T_121 = and(ordered, ordered_lt)
    io.lt <= T_121
    node T_122 = and(ordered, ordered_eq)
    io.eq <= T_122
    node T_123 = not(ordered_lt)
    node T_124 = and(ordered, T_123)
    node T_125 = not(ordered_eq)
    node T_126 = and(T_124, T_125)
    io.gt <= T_126
    node T_128 = cat(invalid, UInt<4>("h00"))
    io.exceptionFlags <= T_128
    
  module RecFNToIN : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>}
    
    io is invalid
    node sign = bits(io.in, 64, 64)
    node exp = bits(io.in, 63, 52)
    node fract = bits(io.in, 51, 0)
    node T_12 = bits(exp, 11, 9)
    node isZero = eq(T_12, UInt<1>("h00"))
    node T_15 = bits(exp, 11, 10)
    node T_16 = not(T_15)
    node isSpecial = eq(T_16, UInt<1>("h00"))
    node T_19 = bits(exp, 9, 9)
    node isNaN = and(isSpecial, T_19)
    node notSpecial_magGeOne = bits(exp, 11, 11)
    node T_22 = cat(notSpecial_magGeOne, fract)
    node T_23 = bits(exp, 5, 0)
    node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h00"))
    node shiftedSig = dshl(T_22, T_25)
    node unroundedInt = bits(shiftedSig, 115, 52)
    node T_28 = bits(shiftedSig, 52, 51)
    node T_29 = bits(shiftedSig, 50, 0)
    node T_31 = neq(T_29, UInt<1>("h00"))
    node roundBits = cat(T_28, T_31)
    node T_33 = bits(roundBits, 1, 0)
    node T_35 = neq(T_33, UInt<1>("h00"))
    node T_37 = eq(isZero, UInt<1>("h00"))
    node roundInexact = mux(notSpecial_magGeOne, T_35, T_37)
    node T_39 = bits(roundBits, 2, 1)
    node T_40 = not(T_39)
    node T_42 = eq(T_40, UInt<1>("h00"))
    node T_43 = bits(roundBits, 1, 0)
    node T_44 = not(T_43)
    node T_46 = eq(T_44, UInt<1>("h00"))
    node T_47 = or(T_42, T_46)
    node T_48 = bits(exp, 10, 0)
    node T_49 = not(T_48)
    node T_51 = eq(T_49, UInt<1>("h00"))
    node T_52 = bits(roundBits, 1, 0)
    node T_54 = neq(T_52, UInt<1>("h00"))
    node T_56 = mux(T_51, T_54, UInt<1>("h00"))
    node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_47, T_56)
    node T_58 = eq(io.roundingMode, UInt<2>("h00"))
    node T_59 = and(T_58, roundIncr_nearestEven)
    node T_60 = eq(io.roundingMode, UInt<2>("h02"))
    node T_61 = and(sign, roundInexact)
    node T_62 = and(T_60, T_61)
    node T_63 = or(T_59, T_62)
    node T_64 = eq(io.roundingMode, UInt<2>("h03"))
    node T_66 = eq(sign, UInt<1>("h00"))
    node T_67 = and(T_66, roundInexact)
    node T_68 = and(T_64, T_67)
    node roundIncr = or(T_63, T_68)
    node T_70 = not(unroundedInt)
    node onesCompUnroundedInt = mux(sign, T_70, unroundedInt)
    node T_72 = xor(roundIncr, sign)
    node T_74 = add(onesCompUnroundedInt, UInt<1>("h01"))
    node T_75 = tail(T_74, 1)
    node roundedInt = mux(T_72, T_75, onesCompUnroundedInt)
    node T_77 = bits(unroundedInt, 61, 0)
    node T_78 = not(T_77)
    node T_80 = eq(T_78, UInt<1>("h00"))
    node roundCarryBut2 = and(T_80, roundIncr)
    node posExp = bits(exp, 10, 0)
    node T_84 = geq(posExp, UInt<7>("h040"))
    node T_86 = eq(posExp, UInt<6>("h03f"))
    node T_88 = eq(sign, UInt<1>("h00"))
    node T_89 = bits(unroundedInt, 62, 0)
    node T_91 = neq(T_89, UInt<1>("h00"))
    node T_92 = or(T_88, T_91)
    node T_93 = or(T_92, roundIncr)
    node T_94 = and(T_86, T_93)
    node T_95 = or(T_84, T_94)
    node T_97 = eq(sign, UInt<1>("h00"))
    node T_99 = eq(posExp, UInt<6>("h03e"))
    node T_100 = and(T_97, T_99)
    node T_101 = and(T_100, roundCarryBut2)
    node T_102 = or(T_95, T_101)
    node overflow_signed = mux(notSpecial_magGeOne, T_102, UInt<1>("h00"))
    node T_106 = geq(posExp, UInt<7>("h040"))
    node T_107 = or(sign, T_106)
    node T_109 = eq(posExp, UInt<6>("h03f"))
    node T_110 = bits(unroundedInt, 62, 62)
    node T_111 = and(T_109, T_110)
    node T_112 = and(T_111, roundCarryBut2)
    node T_113 = or(T_107, T_112)
    node T_114 = and(sign, roundIncr)
    node overflow_unsigned = mux(notSpecial_magGeOne, T_113, T_114)
    node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned)
    node T_118 = eq(isNaN, UInt<1>("h00"))
    node excSign = and(sign, T_118)
    node T_120 = and(io.signedOut, excSign)
    node T_123 = mux(T_120, UInt<64>("h08000000000000000"), UInt<1>("h00"))
    node T_125 = eq(excSign, UInt<1>("h00"))
    node T_126 = and(io.signedOut, T_125)
    node T_129 = mux(T_126, UInt<63>("h07fffffffffffffff"), UInt<1>("h00"))
    node T_130 = or(T_123, T_129)
    node T_132 = eq(io.signedOut, UInt<1>("h00"))
    node T_135 = mux(T_132, UInt<64>("h0ffffffffffffffff"), UInt<1>("h00"))
    node excValue = or(T_130, T_135)
    node T_138 = eq(isSpecial, UInt<1>("h00"))
    node T_139 = and(roundInexact, T_138)
    node T_141 = eq(overflow, UInt<1>("h00"))
    node inexact = and(T_139, T_141)
    node T_143 = or(isSpecial, overflow)
    node T_144 = mux(T_143, excValue, roundedInt)
    io.out <= T_144
    node T_145 = cat(overflow, inexact)
    node T_146 = cat(isSpecial, T_145)
    io.intExceptionFlags <= T_146
    
  module RecFNToIN_118 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>}
    
    io is invalid
    node sign = bits(io.in, 64, 64)
    node exp = bits(io.in, 63, 52)
    node fract = bits(io.in, 51, 0)
    node T_12 = bits(exp, 11, 9)
    node isZero = eq(T_12, UInt<1>("h00"))
    node T_15 = bits(exp, 11, 10)
    node T_16 = not(T_15)
    node isSpecial = eq(T_16, UInt<1>("h00"))
    node T_19 = bits(exp, 9, 9)
    node isNaN = and(isSpecial, T_19)
    node notSpecial_magGeOne = bits(exp, 11, 11)
    node T_22 = cat(notSpecial_magGeOne, fract)
    node T_23 = bits(exp, 4, 0)
    node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h00"))
    node shiftedSig = dshl(T_22, T_25)
    node unroundedInt = bits(shiftedSig, 83, 52)
    node T_28 = bits(shiftedSig, 52, 51)
    node T_29 = bits(shiftedSig, 50, 0)
    node T_31 = neq(T_29, UInt<1>("h00"))
    node roundBits = cat(T_28, T_31)
    node T_33 = bits(roundBits, 1, 0)
    node T_35 = neq(T_33, UInt<1>("h00"))
    node T_37 = eq(isZero, UInt<1>("h00"))
    node roundInexact = mux(notSpecial_magGeOne, T_35, T_37)
    node T_39 = bits(roundBits, 2, 1)
    node T_40 = not(T_39)
    node T_42 = eq(T_40, UInt<1>("h00"))
    node T_43 = bits(roundBits, 1, 0)
    node T_44 = not(T_43)
    node T_46 = eq(T_44, UInt<1>("h00"))
    node T_47 = or(T_42, T_46)
    node T_48 = bits(exp, 10, 0)
    node T_49 = not(T_48)
    node T_51 = eq(T_49, UInt<1>("h00"))
    node T_52 = bits(roundBits, 1, 0)
    node T_54 = neq(T_52, UInt<1>("h00"))
    node T_56 = mux(T_51, T_54, UInt<1>("h00"))
    node roundIncr_nearestEven = mux(notSpecial_magGeOne, T_47, T_56)
    node T_58 = eq(io.roundingMode, UInt<2>("h00"))
    node T_59 = and(T_58, roundIncr_nearestEven)
    node T_60 = eq(io.roundingMode, UInt<2>("h02"))
    node T_61 = and(sign, roundInexact)
    node T_62 = and(T_60, T_61)
    node T_63 = or(T_59, T_62)
    node T_64 = eq(io.roundingMode, UInt<2>("h03"))
    node T_66 = eq(sign, UInt<1>("h00"))
    node T_67 = and(T_66, roundInexact)
    node T_68 = and(T_64, T_67)
    node roundIncr = or(T_63, T_68)
    node T_70 = not(unroundedInt)
    node onesCompUnroundedInt = mux(sign, T_70, unroundedInt)
    node T_72 = xor(roundIncr, sign)
    node T_74 = add(onesCompUnroundedInt, UInt<1>("h01"))
    node T_75 = tail(T_74, 1)
    node roundedInt = mux(T_72, T_75, onesCompUnroundedInt)
    node T_77 = bits(unroundedInt, 29, 0)
    node T_78 = not(T_77)
    node T_80 = eq(T_78, UInt<1>("h00"))
    node roundCarryBut2 = and(T_80, roundIncr)
    node posExp = bits(exp, 10, 0)
    node T_84 = geq(posExp, UInt<6>("h020"))
    node T_86 = eq(posExp, UInt<5>("h01f"))
    node T_88 = eq(sign, UInt<1>("h00"))
    node T_89 = bits(unroundedInt, 30, 0)
    node T_91 = neq(T_89, UInt<1>("h00"))
    node T_92 = or(T_88, T_91)
    node T_93 = or(T_92, roundIncr)
    node T_94 = and(T_86, T_93)
    node T_95 = or(T_84, T_94)
    node T_97 = eq(sign, UInt<1>("h00"))
    node T_99 = eq(posExp, UInt<5>("h01e"))
    node T_100 = and(T_97, T_99)
    node T_101 = and(T_100, roundCarryBut2)
    node T_102 = or(T_95, T_101)
    node overflow_signed = mux(notSpecial_magGeOne, T_102, UInt<1>("h00"))
    node T_106 = geq(posExp, UInt<6>("h020"))
    node T_107 = or(sign, T_106)
    node T_109 = eq(posExp, UInt<5>("h01f"))
    node T_110 = bits(unroundedInt, 30, 30)
    node T_111 = and(T_109, T_110)
    node T_112 = and(T_111, roundCarryBut2)
    node T_113 = or(T_107, T_112)
    node T_114 = and(sign, roundIncr)
    node overflow_unsigned = mux(notSpecial_magGeOne, T_113, T_114)
    node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned)
    node T_118 = eq(isNaN, UInt<1>("h00"))
    node excSign = and(sign, T_118)
    node T_120 = and(io.signedOut, excSign)
    node T_123 = mux(T_120, UInt<32>("h080000000"), UInt<1>("h00"))
    node T_125 = eq(excSign, UInt<1>("h00"))
    node T_126 = and(io.signedOut, T_125)
    node T_129 = mux(T_126, UInt<31>("h07fffffff"), UInt<1>("h00"))
    node T_130 = or(T_123, T_129)
    node T_132 = eq(io.signedOut, UInt<1>("h00"))
    node T_135 = mux(T_132, UInt<32>("h0ffffffff"), UInt<1>("h00"))
    node excValue = or(T_130, T_135)
    node T_138 = eq(isSpecial, UInt<1>("h00"))
    node T_139 = and(roundInexact, T_138)
    node T_141 = eq(overflow, UInt<1>("h00"))
    node inexact = and(T_139, T_141)
    node T_143 = or(isSpecial, overflow)
    node T_144 = mux(T_143, excValue, roundedInt)
    io.out <= T_144
    node T_145 = cat(overflow, inexact)
    node T_146 = cat(isSpecial, T_145)
    io.intExceptionFlags <= T_146
    
  module FPToInt : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}}
    
    io is invalid
    reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk
    reg valid : UInt<1>, clk
    valid <= io.in.valid
    inst T_233 of RecFNToRecFN
    T_233.io is invalid
    T_233.clk <= clk
    T_233.reset <= reset
    T_233.io.in <= io.in.bits.in1
    T_233.io.roundingMode <= UInt<1>("h00")
    inst T_235 of RecFNToRecFN
    T_235.io is invalid
    T_235.clk <= clk
    T_235.reset <= reset
    T_235.io.in <= io.in.bits.in2
    T_235.io.roundingMode <= UInt<1>("h00")
    when io.in.valid :
      in <- io.in.bits
      node T_238 = eq(io.in.bits.ldst, UInt<1>("h00"))
      node T_239 = and(io.in.bits.single, T_238)
      node T_242 = and(io.in.bits.cmd, UInt<4>("h0c"))
      node T_243 = eq(UInt<4>("h0c"), T_242)
      node T_245 = eq(T_243, UInt<1>("h00"))
      node T_246 = and(T_239, T_245)
      when T_246 :
        in.in1 <= T_233.io.out
        in.in2 <= T_235.io.out
        skip
      skip
    node T_247 = bits(in.in1, 32, 32)
    node T_248 = bits(in.in1, 31, 23)
    node T_249 = bits(in.in1, 22, 0)
    node T_250 = bits(T_248, 6, 0)
    node T_252 = lt(T_250, UInt<2>("h02"))
    node T_253 = bits(T_248, 8, 6)
    node T_255 = eq(T_253, UInt<1>("h01"))
    node T_256 = bits(T_248, 8, 7)
    node T_258 = eq(T_256, UInt<1>("h01"))
    node T_259 = and(T_258, T_252)
    node T_260 = or(T_255, T_259)
    node T_261 = bits(T_248, 8, 7)
    node T_263 = eq(T_261, UInt<1>("h01"))
    node T_265 = eq(T_252, UInt<1>("h00"))
    node T_266 = and(T_263, T_265)
    node T_267 = bits(T_248, 8, 7)
    node T_269 = eq(T_267, UInt<2>("h02"))
    node T_270 = or(T_266, T_269)
    node T_271 = bits(T_248, 8, 7)
    node T_273 = eq(T_271, UInt<2>("h03"))
    node T_274 = bits(T_248, 6, 6)
    node T_275 = and(T_273, T_274)
    node T_277 = bits(T_248, 4, 0)
    node T_278 = sub(UInt<2>("h02"), T_277)
    node T_279 = tail(T_278, 1)
    node T_281 = cat(UInt<1>("h01"), T_249)
    node T_282 = dshr(T_281, T_279)
    node T_283 = bits(T_282, 22, 0)
    node T_284 = bits(T_248, 7, 0)
    node T_286 = sub(T_284, UInt<8>("h081"))
    node T_287 = tail(T_286, 1)
    node T_289 = sub(UInt<8>("h00"), T_273)
    node T_290 = tail(T_289, 1)
    node T_291 = mux(T_270, T_287, T_290)
    node T_292 = or(T_270, T_275)
    node T_294 = mux(T_260, T_283, UInt<1>("h00"))
    node T_295 = mux(T_292, T_249, T_294)
    node T_296 = cat(T_291, T_295)
    node unrec_s = cat(T_247, T_296)
    node T_298 = bits(in.in1, 64, 64)
    node T_299 = bits(in.in1, 63, 52)
    node T_300 = bits(in.in1, 51, 0)
    node T_301 = bits(T_299, 9, 0)
    node T_303 = lt(T_301, UInt<2>("h02"))
    node T_304 = bits(T_299, 11, 9)
    node T_306 = eq(T_304, UInt<1>("h01"))
    node T_307 = bits(T_299, 11, 10)
    node T_309 = eq(T_307, UInt<1>("h01"))
    node T_310 = and(T_309, T_303)
    node T_311 = or(T_306, T_310)
    node T_312 = bits(T_299, 11, 10)
    node T_314 = eq(T_312, UInt<1>("h01"))
    node T_316 = eq(T_303, UInt<1>("h00"))
    node T_317 = and(T_314, T_316)
    node T_318 = bits(T_299, 11, 10)
    node T_320 = eq(T_318, UInt<2>("h02"))
    node T_321 = or(T_317, T_320)
    node T_322 = bits(T_299, 11, 10)
    node T_324 = eq(T_322, UInt<2>("h03"))
    node T_325 = bits(T_299, 9, 9)
    node T_326 = and(T_324, T_325)
    node T_328 = bits(T_299, 5, 0)
    node T_329 = sub(UInt<2>("h02"), T_328)
    node T_330 = tail(T_329, 1)
    node T_332 = cat(UInt<1>("h01"), T_300)
    node T_333 = dshr(T_332, T_330)
    node T_334 = bits(T_333, 51, 0)
    node T_335 = bits(T_299, 10, 0)
    node T_337 = sub(T_335, UInt<11>("h0401"))
    node T_338 = tail(T_337, 1)
    node T_340 = sub(UInt<11>("h00"), T_324)
    node T_341 = tail(T_340, 1)
    node T_342 = mux(T_321, T_338, T_341)
    node T_343 = or(T_321, T_326)
    node T_345 = mux(T_311, T_334, UInt<1>("h00"))
    node T_346 = mux(T_343, T_300, T_345)
    node T_347 = cat(T_342, T_346)
    node unrec_d = cat(T_298, T_347)
    node T_349 = bits(unrec_s, 31, 31)
    node T_351 = sub(UInt<32>("h00"), T_349)
    node T_352 = tail(T_351, 1)
    node T_353 = cat(T_352, unrec_s)
    node unrec_out = mux(in.single, T_353, unrec_d)
    node T_355 = bits(in.in1, 32, 32)
    node T_356 = bits(in.in1, 31, 23)
    node T_357 = bits(in.in1, 22, 0)
    node T_358 = bits(T_356, 8, 6)
    node T_359 = bits(T_358, 2, 1)
    node T_361 = eq(T_359, UInt<2>("h03"))
    node T_362 = bits(T_356, 6, 0)
    node T_364 = lt(T_362, UInt<2>("h02"))
    node T_366 = eq(T_358, UInt<1>("h01"))
    node T_368 = eq(T_359, UInt<1>("h01"))
    node T_369 = and(T_368, T_364)
    node T_370 = or(T_366, T_369)
    node T_372 = eq(T_359, UInt<1>("h01"))
    node T_374 = eq(T_364, UInt<1>("h00"))
    node T_375 = and(T_372, T_374)
    node T_377 = eq(T_359, UInt<2>("h02"))
    node T_378 = or(T_375, T_377)
    node T_380 = eq(T_358, UInt<1>("h00"))
    node T_381 = bits(T_356, 6, 6)
    node T_383 = eq(T_381, UInt<1>("h00"))
    node T_384 = and(T_361, T_383)
    node T_385 = not(T_358)
    node T_387 = eq(T_385, UInt<1>("h00"))
    node T_388 = bits(T_357, 22, 22)
    node T_390 = eq(T_388, UInt<1>("h00"))
    node T_391 = and(T_387, T_390)
    node T_392 = bits(T_357, 22, 22)
    node T_393 = and(T_387, T_392)
    node T_395 = eq(T_355, UInt<1>("h00"))
    node T_396 = and(T_384, T_395)
    node T_398 = eq(T_355, UInt<1>("h00"))
    node T_399 = and(T_378, T_398)
    node T_401 = eq(T_355, UInt<1>("h00"))
    node T_402 = and(T_370, T_401)
    node T_404 = eq(T_355, UInt<1>("h00"))
    node T_405 = and(T_380, T_404)
    node T_406 = and(T_380, T_355)
    node T_407 = and(T_370, T_355)
    node T_408 = and(T_378, T_355)
    node T_409 = and(T_384, T_355)
    node T_410 = cat(T_393, T_391)
    node T_411 = cat(T_399, T_402)
    node T_412 = cat(T_396, T_411)
    node T_413 = cat(T_410, T_412)
    node T_414 = cat(T_405, T_406)
    node T_415 = cat(T_408, T_409)
    node T_416 = cat(T_407, T_415)
    node T_417 = cat(T_414, T_416)
    node classify_s = cat(T_413, T_417)
    node T_419 = bits(in.in1, 64, 64)
    node T_420 = bits(in.in1, 63, 52)
    node T_421 = bits(in.in1, 51, 0)
    node T_422 = bits(T_420, 11, 9)
    node T_423 = bits(T_422, 2, 1)
    node T_425 = eq(T_423, UInt<2>("h03"))
    node T_426 = bits(T_420, 9, 0)
    node T_428 = lt(T_426, UInt<2>("h02"))
    node T_430 = eq(T_422, UInt<1>("h01"))
    node T_432 = eq(T_423, UInt<1>("h01"))
    node T_433 = and(T_432, T_428)
    node T_434 = or(T_430, T_433)
    node T_436 = eq(T_423, UInt<1>("h01"))
    node T_438 = eq(T_428, UInt<1>("h00"))
    node T_439 = and(T_436, T_438)
    node T_441 = eq(T_423, UInt<2>("h02"))
    node T_442 = or(T_439, T_441)
    node T_444 = eq(T_422, UInt<1>("h00"))
    node T_445 = bits(T_420, 9, 9)
    node T_447 = eq(T_445, UInt<1>("h00"))
    node T_448 = and(T_425, T_447)
    node T_449 = not(T_422)
    node T_451 = eq(T_449, UInt<1>("h00"))
    node T_452 = bits(T_421, 51, 51)
    node T_454 = eq(T_452, UInt<1>("h00"))
    node T_455 = and(T_451, T_454)
    node T_456 = bits(T_421, 51, 51)
    node T_457 = and(T_451, T_456)
    node T_459 = eq(T_419, UInt<1>("h00"))
    node T_460 = and(T_448, T_459)
    node T_462 = eq(T_419, UInt<1>("h00"))
    node T_463 = and(T_442, T_462)
    node T_465 = eq(T_419, UInt<1>("h00"))
    node T_466 = and(T_434, T_465)
    node T_468 = eq(T_419, UInt<1>("h00"))
    node T_469 = and(T_444, T_468)
    node T_470 = and(T_444, T_419)
    node T_471 = and(T_434, T_419)
    node T_472 = and(T_442, T_419)
    node T_473 = and(T_448, T_419)
    node T_474 = cat(T_457, T_455)
    node T_475 = cat(T_463, T_466)
    node T_476 = cat(T_460, T_475)
    node T_477 = cat(T_474, T_476)
    node T_478 = cat(T_469, T_470)
    node T_479 = cat(T_472, T_473)
    node T_480 = cat(T_471, T_479)
    node T_481 = cat(T_478, T_480)
    node classify_d = cat(T_477, T_481)
    node classify_out = mux(in.single, classify_s, classify_d)
    inst dcmp of CompareRecFN
    dcmp.io is invalid
    dcmp.clk <= clk
    dcmp.reset <= reset
    dcmp.io.a <= in.in1
    dcmp.io.b <= in.in2
    dcmp.io.signaling <= UInt<1>("h01")
    node T_486 = not(in.rm)
    node T_487 = cat(dcmp.io.lt, dcmp.io.eq)
    node T_488 = and(T_486, T_487)
    node dcmp_out = neq(T_488, UInt<1>("h00"))
    inst d2l of RecFNToIN
    d2l.io is invalid
    d2l.clk <= clk
    d2l.reset <= reset
    inst d2w of RecFNToIN_118
    d2w.io is invalid
    d2w.clk <= clk
    d2w.reset <= reset
    d2l.io.in <= in.in1
    d2l.io.roundingMode <= in.rm
    node T_493 = bits(in.typ, 0, 0)
    node T_494 = not(T_493)
    d2l.io.signedOut <= T_494
    d2w.io.in <= in.in1
    d2w.io.roundingMode <= in.rm
    node T_495 = bits(in.typ, 0, 0)
    node T_496 = not(T_495)
    d2w.io.signedOut <= T_496
    node T_497 = bits(in.rm, 0, 0)
    node T_498 = mux(T_497, classify_out, unrec_out)
    io.out.bits.toint <= T_498
    io.out.bits.store <= unrec_out
    io.out.bits.exc <= UInt<1>("h00")
    node T_502 = and(in.cmd, UInt<4>("h0c"))
    node T_503 = eq(UInt<3>("h04"), T_502)
    when T_503 :
      io.out.bits.toint <= dcmp_out
      io.out.bits.exc <= dcmp.io.exceptionFlags
      skip
    node T_506 = and(in.cmd, UInt<4>("h0c"))
    node T_507 = eq(UInt<4>("h08"), T_506)
    when T_507 :
      node T_508 = bits(in.typ, 1, 1)
      node T_509 = asSInt(d2l.io.out)
      node T_510 = asSInt(d2w.io.out)
      node T_511 = mux(T_508, T_509, T_510)
      node T_512 = asUInt(T_511)
      io.out.bits.toint <= T_512
      node T_513 = bits(in.typ, 1, 1)
      node T_514 = mux(T_513, d2l.io.intExceptionFlags, d2w.io.intExceptionFlags)
      node T_515 = bits(T_514, 2, 1)
      node T_517 = neq(T_515, UInt<1>("h00"))
      node T_519 = bits(T_514, 0, 0)
      node T_520 = cat(UInt<3>("h00"), T_519)
      node T_521 = cat(T_517, T_520)
      io.out.bits.exc <= T_521
      skip
    io.out.valid <= valid
    io.out.bits.lt <= dcmp.io.lt
    io.as_double <- in
    
  module INToRecFN : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>}
    
    io is invalid
    node T_9 = bits(io.in, 63, 63)
    node sign = and(io.signedIn, T_9)
    node T_12 = sub(UInt<1>("h00"), io.in)
    node T_13 = tail(T_12, 1)
    node absIn = mux(sign, T_13, io.in)
    node T_15 = shl(absIn, 0)
    node T_16 = bits(T_15, 63, 63)
    node T_18 = bits(T_15, 62, 62)
    node T_20 = bits(T_15, 61, 61)
    node T_22 = bits(T_15, 60, 60)
    node T_24 = bits(T_15, 59, 59)
    node T_26 = bits(T_15, 58, 58)
    node T_28 = bits(T_15, 57, 57)
    node T_30 = bits(T_15, 56, 56)
    node T_32 = bits(T_15, 55, 55)
    node T_34 = bits(T_15, 54, 54)
    node T_36 = bits(T_15, 53, 53)
    node T_38 = bits(T_15, 52, 52)
    node T_40 = bits(T_15, 51, 51)
    node T_42 = bits(T_15, 50, 50)
    node T_44 = bits(T_15, 49, 49)
    node T_46 = bits(T_15, 48, 48)
    node T_48 = bits(T_15, 47, 47)
    node T_50 = bits(T_15, 46, 46)
    node T_52 = bits(T_15, 45, 45)
    node T_54 = bits(T_15, 44, 44)
    node T_56 = bits(T_15, 43, 43)
    node T_58 = bits(T_15, 42, 42)
    node T_60 = bits(T_15, 41, 41)
    node T_62 = bits(T_15, 40, 40)
    node T_64 = bits(T_15, 39, 39)
    node T_66 = bits(T_15, 38, 38)
    node T_68 = bits(T_15, 37, 37)
    node T_70 = bits(T_15, 36, 36)
    node T_72 = bits(T_15, 35, 35)
    node T_74 = bits(T_15, 34, 34)
    node T_76 = bits(T_15, 33, 33)
    node T_78 = bits(T_15, 32, 32)
    node T_80 = bits(T_15, 31, 31)
    node T_82 = bits(T_15, 30, 30)
    node T_84 = bits(T_15, 29, 29)
    node T_86 = bits(T_15, 28, 28)
    node T_88 = bits(T_15, 27, 27)
    node T_90 = bits(T_15, 26, 26)
    node T_92 = bits(T_15, 25, 25)
    node T_94 = bits(T_15, 24, 24)
    node T_96 = bits(T_15, 23, 23)
    node T_98 = bits(T_15, 22, 22)
    node T_100 = bits(T_15, 21, 21)
    node T_102 = bits(T_15, 20, 20)
    node T_104 = bits(T_15, 19, 19)
    node T_106 = bits(T_15, 18, 18)
    node T_108 = bits(T_15, 17, 17)
    node T_110 = bits(T_15, 16, 16)
    node T_112 = bits(T_15, 15, 15)
    node T_114 = bits(T_15, 14, 14)
    node T_116 = bits(T_15, 13, 13)
    node T_118 = bits(T_15, 12, 12)
    node T_120 = bits(T_15, 11, 11)
    node T_122 = bits(T_15, 10, 10)
    node T_124 = bits(T_15, 9, 9)
    node T_126 = bits(T_15, 8, 8)
    node T_128 = bits(T_15, 7, 7)
    node T_130 = bits(T_15, 6, 6)
    node T_132 = bits(T_15, 5, 5)
    node T_134 = bits(T_15, 4, 4)
    node T_136 = bits(T_15, 3, 3)
    node T_138 = bits(T_15, 2, 2)
    node T_140 = bits(T_15, 1, 1)
    node T_141 = shl(T_140, 0)
    node T_142 = mux(T_138, UInt<2>("h02"), T_141)
    node T_143 = mux(T_136, UInt<2>("h03"), T_142)
    node T_144 = mux(T_134, UInt<3>("h04"), T_143)
    node T_145 = mux(T_132, UInt<3>("h05"), T_144)
    node T_146 = mux(T_130, UInt<3>("h06"), T_145)
    node T_147 = mux(T_128, UInt<3>("h07"), T_146)
    node T_148 = mux(T_126, UInt<4>("h08"), T_147)
    node T_149 = mux(T_124, UInt<4>("h09"), T_148)
    node T_150 = mux(T_122, UInt<4>("h0a"), T_149)
    node T_151 = mux(T_120, UInt<4>("h0b"), T_150)
    node T_152 = mux(T_118, UInt<4>("h0c"), T_151)
    node T_153 = mux(T_116, UInt<4>("h0d"), T_152)
    node T_154 = mux(T_114, UInt<4>("h0e"), T_153)
    node T_155 = mux(T_112, UInt<4>("h0f"), T_154)
    node T_156 = mux(T_110, UInt<5>("h010"), T_155)
    node T_157 = mux(T_108, UInt<5>("h011"), T_156)
    node T_158 = mux(T_106, UInt<5>("h012"), T_157)
    node T_159 = mux(T_104, UInt<5>("h013"), T_158)
    node T_160 = mux(T_102, UInt<5>("h014"), T_159)
    node T_161 = mux(T_100, UInt<5>("h015"), T_160)
    node T_162 = mux(T_98, UInt<5>("h016"), T_161)
    node T_163 = mux(T_96, UInt<5>("h017"), T_162)
    node T_164 = mux(T_94, UInt<5>("h018"), T_163)
    node T_165 = mux(T_92, UInt<5>("h019"), T_164)
    node T_166 = mux(T_90, UInt<5>("h01a"), T_165)
    node T_167 = mux(T_88, UInt<5>("h01b"), T_166)
    node T_168 = mux(T_86, UInt<5>("h01c"), T_167)
    node T_169 = mux(T_84, UInt<5>("h01d"), T_168)
    node T_170 = mux(T_82, UInt<5>("h01e"), T_169)
    node T_171 = mux(T_80, UInt<5>("h01f"), T_170)
    node T_172 = mux(T_78, UInt<6>("h020"), T_171)
    node T_173 = mux(T_76, UInt<6>("h021"), T_172)
    node T_174 = mux(T_74, UInt<6>("h022"), T_173)
    node T_175 = mux(T_72, UInt<6>("h023"), T_174)
    node T_176 = mux(T_70, UInt<6>("h024"), T_175)
    node T_177 = mux(T_68, UInt<6>("h025"), T_176)
    node T_178 = mux(T_66, UInt<6>("h026"), T_177)
    node T_179 = mux(T_64, UInt<6>("h027"), T_178)
    node T_180 = mux(T_62, UInt<6>("h028"), T_179)
    node T_181 = mux(T_60, UInt<6>("h029"), T_180)
    node T_182 = mux(T_58, UInt<6>("h02a"), T_181)
    node T_183 = mux(T_56, UInt<6>("h02b"), T_182)
    node T_184 = mux(T_54, UInt<6>("h02c"), T_183)
    node T_185 = mux(T_52, UInt<6>("h02d"), T_184)
    node T_186 = mux(T_50, UInt<6>("h02e"), T_185)
    node T_187 = mux(T_48, UInt<6>("h02f"), T_186)
    node T_188 = mux(T_46, UInt<6>("h030"), T_187)
    node T_189 = mux(T_44, UInt<6>("h031"), T_188)
    node T_190 = mux(T_42, UInt<6>("h032"), T_189)
    node T_191 = mux(T_40, UInt<6>("h033"), T_190)
    node T_192 = mux(T_38, UInt<6>("h034"), T_191)
    node T_193 = mux(T_36, UInt<6>("h035"), T_192)
    node T_194 = mux(T_34, UInt<6>("h036"), T_193)
    node T_195 = mux(T_32, UInt<6>("h037"), T_194)
    node T_196 = mux(T_30, UInt<6>("h038"), T_195)
    node T_197 = mux(T_28, UInt<6>("h039"), T_196)
    node T_198 = mux(T_26, UInt<6>("h03a"), T_197)
    node T_199 = mux(T_24, UInt<6>("h03b"), T_198)
    node T_200 = mux(T_22, UInt<6>("h03c"), T_199)
    node T_201 = mux(T_20, UInt<6>("h03d"), T_200)
    node T_202 = mux(T_18, UInt<6>("h03e"), T_201)
    node T_203 = mux(T_16, UInt<6>("h03f"), T_202)
    node normCount = not(T_203)
    node T_205 = dshl(absIn, normCount)
    node normAbsIn = bits(T_205, 63, 0)
    node T_208 = bits(normAbsIn, 40, 39)
    node T_209 = bits(normAbsIn, 38, 0)
    node T_211 = neq(T_209, UInt<1>("h00"))
    node roundBits = cat(T_208, T_211)
    node T_213 = bits(roundBits, 1, 0)
    node roundInexact = neq(T_213, UInt<1>("h00"))
    node T_216 = eq(io.roundingMode, UInt<2>("h00"))
    node T_217 = bits(roundBits, 2, 1)
    node T_218 = not(T_217)
    node T_220 = eq(T_218, UInt<1>("h00"))
    node T_221 = bits(roundBits, 1, 0)
    node T_222 = not(T_221)
    node T_224 = eq(T_222, UInt<1>("h00"))
    node T_225 = or(T_220, T_224)
    node T_227 = mux(T_216, T_225, UInt<1>("h00"))
    node T_228 = eq(io.roundingMode, UInt<2>("h02"))
    node T_229 = and(sign, roundInexact)
    node T_231 = mux(T_228, T_229, UInt<1>("h00"))
    node T_232 = or(T_227, T_231)
    node T_233 = eq(io.roundingMode, UInt<2>("h03"))
    node T_235 = eq(sign, UInt<1>("h00"))
    node T_236 = and(T_235, roundInexact)
    node T_238 = mux(T_233, T_236, UInt<1>("h00"))
    node round = or(T_232, T_238)
    node T_241 = bits(normAbsIn, 63, 40)
    node unroundedNorm = cat(UInt<1>("h00"), T_241)
    node T_245 = add(unroundedNorm, UInt<1>("h01"))
    node T_246 = tail(T_245, 1)
    node roundedNorm = mux(round, T_246, unroundedNorm)
    node T_249 = not(normCount)
    node unroundedExp = cat(UInt<1>("h00"), T_249)
    node T_253 = cat(UInt<1>("h00"), unroundedExp)
    node T_254 = bits(roundedNorm, 24, 24)
    node T_255 = add(T_253, T_254)
    node roundedExp = tail(T_255, 1)
    node T_258 = bits(normAbsIn, 63, 63)
    node T_260 = bits(roundedExp, 7, 0)
    node T_261 = mux(UInt<1>("h00"), UInt<8>("h080"), T_260)
    node expOut = cat(T_258, T_261)
    node overflow = or(UInt<1>("h00"), UInt<1>("h00"))
    node inexact = or(roundInexact, overflow)
    node T_265 = bits(roundedNorm, 22, 0)
    node T_266 = cat(expOut, T_265)
    node T_267 = cat(sign, T_266)
    io.out <= T_267
    node T_270 = cat(UInt<2>("h00"), overflow)
    node T_271 = cat(UInt<1>("h00"), inexact)
    node T_272 = cat(T_270, T_271)
    io.exceptionFlags <= T_272
    
  module INToRecFN_119 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>}
    
    io is invalid
    node T_9 = bits(io.in, 63, 63)
    node sign = and(io.signedIn, T_9)
    node T_12 = sub(UInt<1>("h00"), io.in)
    node T_13 = tail(T_12, 1)
    node absIn = mux(sign, T_13, io.in)
    node T_15 = shl(absIn, 0)
    node T_16 = bits(T_15, 63, 63)
    node T_18 = bits(T_15, 62, 62)
    node T_20 = bits(T_15, 61, 61)
    node T_22 = bits(T_15, 60, 60)
    node T_24 = bits(T_15, 59, 59)
    node T_26 = bits(T_15, 58, 58)
    node T_28 = bits(T_15, 57, 57)
    node T_30 = bits(T_15, 56, 56)
    node T_32 = bits(T_15, 55, 55)
    node T_34 = bits(T_15, 54, 54)
    node T_36 = bits(T_15, 53, 53)
    node T_38 = bits(T_15, 52, 52)
    node T_40 = bits(T_15, 51, 51)
    node T_42 = bits(T_15, 50, 50)
    node T_44 = bits(T_15, 49, 49)
    node T_46 = bits(T_15, 48, 48)
    node T_48 = bits(T_15, 47, 47)
    node T_50 = bits(T_15, 46, 46)
    node T_52 = bits(T_15, 45, 45)
    node T_54 = bits(T_15, 44, 44)
    node T_56 = bits(T_15, 43, 43)
    node T_58 = bits(T_15, 42, 42)
    node T_60 = bits(T_15, 41, 41)
    node T_62 = bits(T_15, 40, 40)
    node T_64 = bits(T_15, 39, 39)
    node T_66 = bits(T_15, 38, 38)
    node T_68 = bits(T_15, 37, 37)
    node T_70 = bits(T_15, 36, 36)
    node T_72 = bits(T_15, 35, 35)
    node T_74 = bits(T_15, 34, 34)
    node T_76 = bits(T_15, 33, 33)
    node T_78 = bits(T_15, 32, 32)
    node T_80 = bits(T_15, 31, 31)
    node T_82 = bits(T_15, 30, 30)
    node T_84 = bits(T_15, 29, 29)
    node T_86 = bits(T_15, 28, 28)
    node T_88 = bits(T_15, 27, 27)
    node T_90 = bits(T_15, 26, 26)
    node T_92 = bits(T_15, 25, 25)
    node T_94 = bits(T_15, 24, 24)
    node T_96 = bits(T_15, 23, 23)
    node T_98 = bits(T_15, 22, 22)
    node T_100 = bits(T_15, 21, 21)
    node T_102 = bits(T_15, 20, 20)
    node T_104 = bits(T_15, 19, 19)
    node T_106 = bits(T_15, 18, 18)
    node T_108 = bits(T_15, 17, 17)
    node T_110 = bits(T_15, 16, 16)
    node T_112 = bits(T_15, 15, 15)
    node T_114 = bits(T_15, 14, 14)
    node T_116 = bits(T_15, 13, 13)
    node T_118 = bits(T_15, 12, 12)
    node T_120 = bits(T_15, 11, 11)
    node T_122 = bits(T_15, 10, 10)
    node T_124 = bits(T_15, 9, 9)
    node T_126 = bits(T_15, 8, 8)
    node T_128 = bits(T_15, 7, 7)
    node T_130 = bits(T_15, 6, 6)
    node T_132 = bits(T_15, 5, 5)
    node T_134 = bits(T_15, 4, 4)
    node T_136 = bits(T_15, 3, 3)
    node T_138 = bits(T_15, 2, 2)
    node T_140 = bits(T_15, 1, 1)
    node T_141 = shl(T_140, 0)
    node T_142 = mux(T_138, UInt<2>("h02"), T_141)
    node T_143 = mux(T_136, UInt<2>("h03"), T_142)
    node T_144 = mux(T_134, UInt<3>("h04"), T_143)
    node T_145 = mux(T_132, UInt<3>("h05"), T_144)
    node T_146 = mux(T_130, UInt<3>("h06"), T_145)
    node T_147 = mux(T_128, UInt<3>("h07"), T_146)
    node T_148 = mux(T_126, UInt<4>("h08"), T_147)
    node T_149 = mux(T_124, UInt<4>("h09"), T_148)
    node T_150 = mux(T_122, UInt<4>("h0a"), T_149)
    node T_151 = mux(T_120, UInt<4>("h0b"), T_150)
    node T_152 = mux(T_118, UInt<4>("h0c"), T_151)
    node T_153 = mux(T_116, UInt<4>("h0d"), T_152)
    node T_154 = mux(T_114, UInt<4>("h0e"), T_153)
    node T_155 = mux(T_112, UInt<4>("h0f"), T_154)
    node T_156 = mux(T_110, UInt<5>("h010"), T_155)
    node T_157 = mux(T_108, UInt<5>("h011"), T_156)
    node T_158 = mux(T_106, UInt<5>("h012"), T_157)
    node T_159 = mux(T_104, UInt<5>("h013"), T_158)
    node T_160 = mux(T_102, UInt<5>("h014"), T_159)
    node T_161 = mux(T_100, UInt<5>("h015"), T_160)
    node T_162 = mux(T_98, UInt<5>("h016"), T_161)
    node T_163 = mux(T_96, UInt<5>("h017"), T_162)
    node T_164 = mux(T_94, UInt<5>("h018"), T_163)
    node T_165 = mux(T_92, UInt<5>("h019"), T_164)
    node T_166 = mux(T_90, UInt<5>("h01a"), T_165)
    node T_167 = mux(T_88, UInt<5>("h01b"), T_166)
    node T_168 = mux(T_86, UInt<5>("h01c"), T_167)
    node T_169 = mux(T_84, UInt<5>("h01d"), T_168)
    node T_170 = mux(T_82, UInt<5>("h01e"), T_169)
    node T_171 = mux(T_80, UInt<5>("h01f"), T_170)
    node T_172 = mux(T_78, UInt<6>("h020"), T_171)
    node T_173 = mux(T_76, UInt<6>("h021"), T_172)
    node T_174 = mux(T_74, UInt<6>("h022"), T_173)
    node T_175 = mux(T_72, UInt<6>("h023"), T_174)
    node T_176 = mux(T_70, UInt<6>("h024"), T_175)
    node T_177 = mux(T_68, UInt<6>("h025"), T_176)
    node T_178 = mux(T_66, UInt<6>("h026"), T_177)
    node T_179 = mux(T_64, UInt<6>("h027"), T_178)
    node T_180 = mux(T_62, UInt<6>("h028"), T_179)
    node T_181 = mux(T_60, UInt<6>("h029"), T_180)
    node T_182 = mux(T_58, UInt<6>("h02a"), T_181)
    node T_183 = mux(T_56, UInt<6>("h02b"), T_182)
    node T_184 = mux(T_54, UInt<6>("h02c"), T_183)
    node T_185 = mux(T_52, UInt<6>("h02d"), T_184)
    node T_186 = mux(T_50, UInt<6>("h02e"), T_185)
    node T_187 = mux(T_48, UInt<6>("h02f"), T_186)
    node T_188 = mux(T_46, UInt<6>("h030"), T_187)
    node T_189 = mux(T_44, UInt<6>("h031"), T_188)
    node T_190 = mux(T_42, UInt<6>("h032"), T_189)
    node T_191 = mux(T_40, UInt<6>("h033"), T_190)
    node T_192 = mux(T_38, UInt<6>("h034"), T_191)
    node T_193 = mux(T_36, UInt<6>("h035"), T_192)
    node T_194 = mux(T_34, UInt<6>("h036"), T_193)
    node T_195 = mux(T_32, UInt<6>("h037"), T_194)
    node T_196 = mux(T_30, UInt<6>("h038"), T_195)
    node T_197 = mux(T_28, UInt<6>("h039"), T_196)
    node T_198 = mux(T_26, UInt<6>("h03a"), T_197)
    node T_199 = mux(T_24, UInt<6>("h03b"), T_198)
    node T_200 = mux(T_22, UInt<6>("h03c"), T_199)
    node T_201 = mux(T_20, UInt<6>("h03d"), T_200)
    node T_202 = mux(T_18, UInt<6>("h03e"), T_201)
    node T_203 = mux(T_16, UInt<6>("h03f"), T_202)
    node normCount = not(T_203)
    node T_205 = dshl(absIn, normCount)
    node normAbsIn = bits(T_205, 63, 0)
    node T_208 = bits(normAbsIn, 11, 10)
    node T_209 = bits(normAbsIn, 9, 0)
    node T_211 = neq(T_209, UInt<1>("h00"))
    node roundBits = cat(T_208, T_211)
    node T_213 = bits(roundBits, 1, 0)
    node roundInexact = neq(T_213, UInt<1>("h00"))
    node T_216 = eq(io.roundingMode, UInt<2>("h00"))
    node T_217 = bits(roundBits, 2, 1)
    node T_218 = not(T_217)
    node T_220 = eq(T_218, UInt<1>("h00"))
    node T_221 = bits(roundBits, 1, 0)
    node T_222 = not(T_221)
    node T_224 = eq(T_222, UInt<1>("h00"))
    node T_225 = or(T_220, T_224)
    node T_227 = mux(T_216, T_225, UInt<1>("h00"))
    node T_228 = eq(io.roundingMode, UInt<2>("h02"))
    node T_229 = and(sign, roundInexact)
    node T_231 = mux(T_228, T_229, UInt<1>("h00"))
    node T_232 = or(T_227, T_231)
    node T_233 = eq(io.roundingMode, UInt<2>("h03"))
    node T_235 = eq(sign, UInt<1>("h00"))
    node T_236 = and(T_235, roundInexact)
    node T_238 = mux(T_233, T_236, UInt<1>("h00"))
    node round = or(T_232, T_238)
    node T_241 = bits(normAbsIn, 63, 11)
    node unroundedNorm = cat(UInt<1>("h00"), T_241)
    node T_245 = add(unroundedNorm, UInt<1>("h01"))
    node T_246 = tail(T_245, 1)
    node roundedNorm = mux(round, T_246, unroundedNorm)
    node T_249 = not(normCount)
    node unroundedExp = cat(UInt<4>("h00"), T_249)
    node T_253 = cat(UInt<1>("h00"), unroundedExp)
    node T_254 = bits(roundedNorm, 53, 53)
    node T_255 = add(T_253, T_254)
    node roundedExp = tail(T_255, 1)
    node T_258 = bits(normAbsIn, 63, 63)
    node T_260 = bits(roundedExp, 10, 0)
    node T_261 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_260)
    node expOut = cat(T_258, T_261)
    node overflow = or(UInt<1>("h00"), UInt<1>("h00"))
    node inexact = or(roundInexact, overflow)
    node T_265 = bits(roundedNorm, 51, 0)
    node T_266 = cat(expOut, T_265)
    node T_267 = cat(sign, T_266)
    io.out <= T_267
    node T_270 = cat(UInt<2>("h00"), overflow)
    node T_271 = cat(UInt<1>("h00"), inexact)
    node T_272 = cat(T_270, T_271)
    io.exceptionFlags <= T_272
    
  module IntToFP : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}
    
    io is invalid
    reg T_136 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_136 <= io.in.valid
    reg T_137 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk
    when io.in.valid :
      T_137 <- io.in.bits
      skip
    wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
    in is invalid
    in.valid <= T_136
    in.bits <- T_137
    wire mux : {data : UInt<65>, exc : UInt<5>}
    mux is invalid
    mux.exc <= UInt<1>("h00")
    node T_263 = bits(in.bits.in1, 63, 63)
    node T_264 = bits(in.bits.in1, 62, 52)
    node T_265 = bits(in.bits.in1, 51, 0)
    node T_267 = eq(T_264, UInt<1>("h00"))
    node T_269 = eq(T_265, UInt<1>("h00"))
    node T_270 = and(T_267, T_269)
    node T_271 = shl(T_265, 12)
    node T_272 = bits(T_271, 63, 63)
    node T_274 = bits(T_271, 62, 62)
    node T_276 = bits(T_271, 61, 61)
    node T_278 = bits(T_271, 60, 60)
    node T_280 = bits(T_271, 59, 59)
    node T_282 = bits(T_271, 58, 58)
    node T_284 = bits(T_271, 57, 57)
    node T_286 = bits(T_271, 56, 56)
    node T_288 = bits(T_271, 55, 55)
    node T_290 = bits(T_271, 54, 54)
    node T_292 = bits(T_271, 53, 53)
    node T_294 = bits(T_271, 52, 52)
    node T_296 = bits(T_271, 51, 51)
    node T_298 = bits(T_271, 50, 50)
    node T_300 = bits(T_271, 49, 49)
    node T_302 = bits(T_271, 48, 48)
    node T_304 = bits(T_271, 47, 47)
    node T_306 = bits(T_271, 46, 46)
    node T_308 = bits(T_271, 45, 45)
    node T_310 = bits(T_271, 44, 44)
    node T_312 = bits(T_271, 43, 43)
    node T_314 = bits(T_271, 42, 42)
    node T_316 = bits(T_271, 41, 41)
    node T_318 = bits(T_271, 40, 40)
    node T_320 = bits(T_271, 39, 39)
    node T_322 = bits(T_271, 38, 38)
    node T_324 = bits(T_271, 37, 37)
    node T_326 = bits(T_271, 36, 36)
    node T_328 = bits(T_271, 35, 35)
    node T_330 = bits(T_271, 34, 34)
    node T_332 = bits(T_271, 33, 33)
    node T_334 = bits(T_271, 32, 32)
    node T_336 = bits(T_271, 31, 31)
    node T_338 = bits(T_271, 30, 30)
    node T_340 = bits(T_271, 29, 29)
    node T_342 = bits(T_271, 28, 28)
    node T_344 = bits(T_271, 27, 27)
    node T_346 = bits(T_271, 26, 26)
    node T_348 = bits(T_271, 25, 25)
    node T_350 = bits(T_271, 24, 24)
    node T_352 = bits(T_271, 23, 23)
    node T_354 = bits(T_271, 22, 22)
    node T_356 = bits(T_271, 21, 21)
    node T_358 = bits(T_271, 20, 20)
    node T_360 = bits(T_271, 19, 19)
    node T_362 = bits(T_271, 18, 18)
    node T_364 = bits(T_271, 17, 17)
    node T_366 = bits(T_271, 16, 16)
    node T_368 = bits(T_271, 15, 15)
    node T_370 = bits(T_271, 14, 14)
    node T_372 = bits(T_271, 13, 13)
    node T_374 = bits(T_271, 12, 12)
    node T_376 = bits(T_271, 11, 11)
    node T_378 = bits(T_271, 10, 10)
    node T_380 = bits(T_271, 9, 9)
    node T_382 = bits(T_271, 8, 8)
    node T_384 = bits(T_271, 7, 7)
    node T_386 = bits(T_271, 6, 6)
    node T_388 = bits(T_271, 5, 5)
    node T_390 = bits(T_271, 4, 4)
    node T_392 = bits(T_271, 3, 3)
    node T_394 = bits(T_271, 2, 2)
    node T_396 = bits(T_271, 1, 1)
    node T_397 = shl(T_396, 0)
    node T_398 = mux(T_394, UInt<2>("h02"), T_397)
    node T_399 = mux(T_392, UInt<2>("h03"), T_398)
    node T_400 = mux(T_390, UInt<3>("h04"), T_399)
    node T_401 = mux(T_388, UInt<3>("h05"), T_400)
    node T_402 = mux(T_386, UInt<3>("h06"), T_401)
    node T_403 = mux(T_384, UInt<3>("h07"), T_402)
    node T_404 = mux(T_382, UInt<4>("h08"), T_403)
    node T_405 = mux(T_380, UInt<4>("h09"), T_404)
    node T_406 = mux(T_378, UInt<4>("h0a"), T_405)
    node T_407 = mux(T_376, UInt<4>("h0b"), T_406)
    node T_408 = mux(T_374, UInt<4>("h0c"), T_407)
    node T_409 = mux(T_372, UInt<4>("h0d"), T_408)
    node T_410 = mux(T_370, UInt<4>("h0e"), T_409)
    node T_411 = mux(T_368, UInt<4>("h0f"), T_410)
    node T_412 = mux(T_366, UInt<5>("h010"), T_411)
    node T_413 = mux(T_364, UInt<5>("h011"), T_412)
    node T_414 = mux(T_362, UInt<5>("h012"), T_413)
    node T_415 = mux(T_360, UInt<5>("h013"), T_414)
    node T_416 = mux(T_358, UInt<5>("h014"), T_415)
    node T_417 = mux(T_356, UInt<5>("h015"), T_416)
    node T_418 = mux(T_354, UInt<5>("h016"), T_417)
    node T_419 = mux(T_352, UInt<5>("h017"), T_418)
    node T_420 = mux(T_350, UInt<5>("h018"), T_419)
    node T_421 = mux(T_348, UInt<5>("h019"), T_420)
    node T_422 = mux(T_346, UInt<5>("h01a"), T_421)
    node T_423 = mux(T_344, UInt<5>("h01b"), T_422)
    node T_424 = mux(T_342, UInt<5>("h01c"), T_423)
    node T_425 = mux(T_340, UInt<5>("h01d"), T_424)
    node T_426 = mux(T_338, UInt<5>("h01e"), T_425)
    node T_427 = mux(T_336, UInt<5>("h01f"), T_426)
    node T_428 = mux(T_334, UInt<6>("h020"), T_427)
    node T_429 = mux(T_332, UInt<6>("h021"), T_428)
    node T_430 = mux(T_330, UInt<6>("h022"), T_429)
    node T_431 = mux(T_328, UInt<6>("h023"), T_430)
    node T_432 = mux(T_326, UInt<6>("h024"), T_431)
    node T_433 = mux(T_324, UInt<6>("h025"), T_432)
    node T_434 = mux(T_322, UInt<6>("h026"), T_433)
    node T_435 = mux(T_320, UInt<6>("h027"), T_434)
    node T_436 = mux(T_318, UInt<6>("h028"), T_435)
    node T_437 = mux(T_316, UInt<6>("h029"), T_436)
    node T_438 = mux(T_314, UInt<6>("h02a"), T_437)
    node T_439 = mux(T_312, UInt<6>("h02b"), T_438)
    node T_440 = mux(T_310, UInt<6>("h02c"), T_439)
    node T_441 = mux(T_308, UInt<6>("h02d"), T_440)
    node T_442 = mux(T_306, UInt<6>("h02e"), T_441)
    node T_443 = mux(T_304, UInt<6>("h02f"), T_442)
    node T_444 = mux(T_302, UInt<6>("h030"), T_443)
    node T_445 = mux(T_300, UInt<6>("h031"), T_444)
    node T_446 = mux(T_298, UInt<6>("h032"), T_445)
    node T_447 = mux(T_296, UInt<6>("h033"), T_446)
    node T_448 = mux(T_294, UInt<6>("h034"), T_447)
    node T_449 = mux(T_292, UInt<6>("h035"), T_448)
    node T_450 = mux(T_290, UInt<6>("h036"), T_449)
    node T_451 = mux(T_288, UInt<6>("h037"), T_450)
    node T_452 = mux(T_286, UInt<6>("h038"), T_451)
    node T_453 = mux(T_284, UInt<6>("h039"), T_452)
    node T_454 = mux(T_282, UInt<6>("h03a"), T_453)
    node T_455 = mux(T_280, UInt<6>("h03b"), T_454)
    node T_456 = mux(T_278, UInt<6>("h03c"), T_455)
    node T_457 = mux(T_276, UInt<6>("h03d"), T_456)
    node T_458 = mux(T_274, UInt<6>("h03e"), T_457)
    node T_459 = mux(T_272, UInt<6>("h03f"), T_458)
    node T_460 = not(T_459)
    node T_461 = dshl(T_265, T_460)
    node T_462 = bits(T_461, 50, 0)
    node T_464 = cat(T_462, UInt<1>("h00"))
    node T_467 = sub(UInt<12>("h00"), UInt<1>("h01"))
    node T_468 = tail(T_467, 1)
    node T_469 = xor(T_460, T_468)
    node T_470 = mux(T_267, T_469, T_264)
    node T_474 = mux(T_267, UInt<2>("h02"), UInt<1>("h01"))
    node T_475 = or(UInt<11>("h0400"), T_474)
    node T_476 = add(T_470, T_475)
    node T_477 = tail(T_476, 1)
    node T_478 = bits(T_477, 11, 10)
    node T_480 = eq(T_478, UInt<2>("h03"))
    node T_482 = eq(T_269, UInt<1>("h00"))
    node T_483 = and(T_480, T_482)
    node T_485 = sub(UInt<3>("h00"), T_270)
    node T_486 = tail(T_485, 1)
    node T_487 = shl(T_486, 9)
    node T_488 = not(T_487)
    node T_489 = and(T_477, T_488)
    node T_490 = shl(T_483, 9)
    node T_491 = or(T_489, T_490)
    node T_492 = mux(T_267, T_464, T_265)
    node T_493 = cat(T_491, T_492)
    node T_494 = cat(T_263, T_493)
    mux.data <= T_494
    when in.bits.single :
      node T_496 = bits(in.bits.in1, 31, 31)
      node T_497 = bits(in.bits.in1, 30, 23)
      node T_498 = bits(in.bits.in1, 22, 0)
      node T_500 = eq(T_497, UInt<1>("h00"))
      node T_502 = eq(T_498, UInt<1>("h00"))
      node T_503 = and(T_500, T_502)
      node T_504 = shl(T_498, 9)
      node T_505 = bits(T_504, 31, 31)
      node T_507 = bits(T_504, 30, 30)
      node T_509 = bits(T_504, 29, 29)
      node T_511 = bits(T_504, 28, 28)
      node T_513 = bits(T_504, 27, 27)
      node T_515 = bits(T_504, 26, 26)
      node T_517 = bits(T_504, 25, 25)
      node T_519 = bits(T_504, 24, 24)
      node T_521 = bits(T_504, 23, 23)
      node T_523 = bits(T_504, 22, 22)
      node T_525 = bits(T_504, 21, 21)
      node T_527 = bits(T_504, 20, 20)
      node T_529 = bits(T_504, 19, 19)
      node T_531 = bits(T_504, 18, 18)
      node T_533 = bits(T_504, 17, 17)
      node T_535 = bits(T_504, 16, 16)
      node T_537 = bits(T_504, 15, 15)
      node T_539 = bits(T_504, 14, 14)
      node T_541 = bits(T_504, 13, 13)
      node T_543 = bits(T_504, 12, 12)
      node T_545 = bits(T_504, 11, 11)
      node T_547 = bits(T_504, 10, 10)
      node T_549 = bits(T_504, 9, 9)
      node T_551 = bits(T_504, 8, 8)
      node T_553 = bits(T_504, 7, 7)
      node T_555 = bits(T_504, 6, 6)
      node T_557 = bits(T_504, 5, 5)
      node T_559 = bits(T_504, 4, 4)
      node T_561 = bits(T_504, 3, 3)
      node T_563 = bits(T_504, 2, 2)
      node T_565 = bits(T_504, 1, 1)
      node T_566 = shl(T_565, 0)
      node T_567 = mux(T_563, UInt<2>("h02"), T_566)
      node T_568 = mux(T_561, UInt<2>("h03"), T_567)
      node T_569 = mux(T_559, UInt<3>("h04"), T_568)
      node T_570 = mux(T_557, UInt<3>("h05"), T_569)
      node T_571 = mux(T_555, UInt<3>("h06"), T_570)
      node T_572 = mux(T_553, UInt<3>("h07"), T_571)
      node T_573 = mux(T_551, UInt<4>("h08"), T_572)
      node T_574 = mux(T_549, UInt<4>("h09"), T_573)
      node T_575 = mux(T_547, UInt<4>("h0a"), T_574)
      node T_576 = mux(T_545, UInt<4>("h0b"), T_575)
      node T_577 = mux(T_543, UInt<4>("h0c"), T_576)
      node T_578 = mux(T_541, UInt<4>("h0d"), T_577)
      node T_579 = mux(T_539, UInt<4>("h0e"), T_578)
      node T_580 = mux(T_537, UInt<4>("h0f"), T_579)
      node T_581 = mux(T_535, UInt<5>("h010"), T_580)
      node T_582 = mux(T_533, UInt<5>("h011"), T_581)
      node T_583 = mux(T_531, UInt<5>("h012"), T_582)
      node T_584 = mux(T_529, UInt<5>("h013"), T_583)
      node T_585 = mux(T_527, UInt<5>("h014"), T_584)
      node T_586 = mux(T_525, UInt<5>("h015"), T_585)
      node T_587 = mux(T_523, UInt<5>("h016"), T_586)
      node T_588 = mux(T_521, UInt<5>("h017"), T_587)
      node T_589 = mux(T_519, UInt<5>("h018"), T_588)
      node T_590 = mux(T_517, UInt<5>("h019"), T_589)
      node T_591 = mux(T_515, UInt<5>("h01a"), T_590)
      node T_592 = mux(T_513, UInt<5>("h01b"), T_591)
      node T_593 = mux(T_511, UInt<5>("h01c"), T_592)
      node T_594 = mux(T_509, UInt<5>("h01d"), T_593)
      node T_595 = mux(T_507, UInt<5>("h01e"), T_594)
      node T_596 = mux(T_505, UInt<5>("h01f"), T_595)
      node T_597 = not(T_596)
      node T_598 = dshl(T_498, T_597)
      node T_599 = bits(T_598, 21, 0)
      node T_601 = cat(T_599, UInt<1>("h00"))
      node T_604 = sub(UInt<9>("h00"), UInt<1>("h01"))
      node T_605 = tail(T_604, 1)
      node T_606 = xor(T_597, T_605)
      node T_607 = mux(T_500, T_606, T_497)
      node T_611 = mux(T_500, UInt<2>("h02"), UInt<1>("h01"))
      node T_612 = or(UInt<8>("h080"), T_611)
      node T_613 = add(T_607, T_612)
      node T_614 = tail(T_613, 1)
      node T_615 = bits(T_614, 8, 7)
      node T_617 = eq(T_615, UInt<2>("h03"))
      node T_619 = eq(T_502, UInt<1>("h00"))
      node T_620 = and(T_617, T_619)
      node T_622 = sub(UInt<3>("h00"), T_503)
      node T_623 = tail(T_622, 1)
      node T_624 = shl(T_623, 6)
      node T_625 = not(T_624)
      node T_626 = and(T_614, T_625)
      node T_627 = shl(T_620, 6)
      node T_628 = or(T_626, T_627)
      node T_629 = mux(T_500, T_601, T_498)
      node T_630 = cat(T_628, T_629)
      node T_631 = cat(T_496, T_630)
      node T_632 = asUInt(asSInt(UInt<32>("h0ffffffff")))
      node T_633 = cat(T_632, T_631)
      mux.data <= T_633
      skip
    node T_634 = bits(in.bits.typ, 1, 1)
    node T_635 = asSInt(in.bits.in1)
    node T_636 = bits(in.bits.typ, 0, 0)
    node T_637 = bits(in.bits.in1, 31, 0)
    node T_638 = cvt(T_637)
    node T_639 = bits(in.bits.in1, 31, 0)
    node T_640 = asSInt(T_639)
    node T_641 = mux(T_636, T_638, T_640)
    node longValue = mux(T_634, T_635, T_641)
    inst l2s of INToRecFN
    l2s.io is invalid
    l2s.clk <= clk
    l2s.reset <= reset
    node T_644 = bits(in.bits.typ, 0, 0)
    node T_645 = not(T_644)
    l2s.io.signedIn <= T_645
    node T_646 = asUInt(longValue)
    l2s.io.in <= T_646
    l2s.io.roundingMode <= in.bits.rm
    inst l2d of INToRecFN_119
    l2d.io is invalid
    l2d.clk <= clk
    l2d.reset <= reset
    node T_648 = bits(in.bits.typ, 0, 0)
    node T_649 = not(T_648)
    l2d.io.signedIn <= T_649
    node T_650 = asUInt(longValue)
    l2d.io.in <= T_650
    l2d.io.roundingMode <= in.bits.rm
    node T_653 = and(in.bits.cmd, UInt<3>("h04"))
    node T_654 = eq(UInt<1>("h00"), T_653)
    when T_654 :
      when in.bits.single :
        node T_656 = asUInt(asSInt(UInt<32>("h0ffffffff")))
        node T_657 = cat(T_656, l2s.io.out)
        mux.data <= T_657
        mux.exc <= l2s.io.exceptionFlags
        skip
      node T_659 = eq(in.bits.single, UInt<1>("h00"))
      when T_659 :
        mux.data <= l2d.io.out
        mux.exc <= l2d.io.exceptionFlags
        skip
      skip
    reg T_662 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_662 <= in.valid
    reg T_663 : {data : UInt<65>, exc : UInt<5>}, clk
    when in.valid :
      T_663 <- mux
      skip
    reg T_668 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_668 <= T_662
    reg T_669 : {data : UInt<65>, exc : UInt<5>}, clk
    when T_662 :
      T_669 <- T_663
      skip
    wire T_680 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}
    T_680 is invalid
    T_680.valid <= T_668
    T_680.bits <- T_669
    io.out <- T_680
    
  module RoundRawFNToRecFN : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>}
    
    io is invalid
    node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00"))
    node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01"))
    node roundingMode_min = eq(io.roundingMode, UInt<2>("h02"))
    node roundingMode_max = eq(io.roundingMode, UInt<2>("h03"))
    node T_27 = and(roundingMode_min, io.in.sign)
    node T_28 = not(io.in.sign)
    node T_29 = and(roundingMode_max, T_28)
    node roundMagUp = or(T_27, T_29)
    node doShiftSigDown1 = bits(io.in.sig, 26, 26)
    node T_33 = lt(io.in.sExp, asSInt(UInt<1>("h00")))
    node T_35 = sub(UInt<25>("h00"), T_33)
    node T_36 = tail(T_35, 1)
    node T_37 = bits(io.in.sExp, 8, 0)
    node T_38 = not(T_37)
    node T_40 = dshr(asSInt(UInt<513>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_38)
    node T_41 = bits(T_40, 130, 106)
    node T_42 = bits(T_41, 15, 0)
    node T_45 = shl(UInt<8>("h0ff"), 8)
    node T_46 = xor(UInt<16>("h0ffff"), T_45)
    node T_47 = shr(T_42, 8)
    node T_48 = and(T_47, T_46)
    node T_49 = bits(T_42, 7, 0)
    node T_50 = shl(T_49, 8)
    node T_51 = not(T_46)
    node T_52 = and(T_50, T_51)
    node T_53 = or(T_48, T_52)
    node T_54 = bits(T_46, 11, 0)
    node T_55 = shl(T_54, 4)
    node T_56 = xor(T_46, T_55)
    node T_57 = shr(T_53, 4)
    node T_58 = and(T_57, T_56)
    node T_59 = bits(T_53, 11, 0)
    node T_60 = shl(T_59, 4)
    node T_61 = not(T_56)
    node T_62 = and(T_60, T_61)
    node T_63 = or(T_58, T_62)
    node T_64 = bits(T_56, 13, 0)
    node T_65 = shl(T_64, 2)
    node T_66 = xor(T_56, T_65)
    node T_67 = shr(T_63, 2)
    node T_68 = and(T_67, T_66)
    node T_69 = bits(T_63, 13, 0)
    node T_70 = shl(T_69, 2)
    node T_71 = not(T_66)
    node T_72 = and(T_70, T_71)
    node T_73 = or(T_68, T_72)
    node T_74 = bits(T_66, 14, 0)
    node T_75 = shl(T_74, 1)
    node T_76 = xor(T_66, T_75)
    node T_77 = shr(T_73, 1)
    node T_78 = and(T_77, T_76)
    node T_79 = bits(T_73, 14, 0)
    node T_80 = shl(T_79, 1)
    node T_81 = not(T_76)
    node T_82 = and(T_80, T_81)
    node T_83 = or(T_78, T_82)
    node T_84 = bits(T_41, 24, 16)
    node T_85 = bits(T_84, 7, 0)
    node T_88 = shl(UInt<4>("h0f"), 4)
    node T_89 = xor(UInt<8>("h0ff"), T_88)
    node T_90 = shr(T_85, 4)
    node T_91 = and(T_90, T_89)
    node T_92 = bits(T_85, 3, 0)
    node T_93 = shl(T_92, 4)
    node T_94 = not(T_89)
    node T_95 = and(T_93, T_94)
    node T_96 = or(T_91, T_95)
    node T_97 = bits(T_89, 5, 0)
    node T_98 = shl(T_97, 2)
    node T_99 = xor(T_89, T_98)
    node T_100 = shr(T_96, 2)
    node T_101 = and(T_100, T_99)
    node T_102 = bits(T_96, 5, 0)
    node T_103 = shl(T_102, 2)
    node T_104 = not(T_99)
    node T_105 = and(T_103, T_104)
    node T_106 = or(T_101, T_105)
    node T_107 = bits(T_99, 6, 0)
    node T_108 = shl(T_107, 1)
    node T_109 = xor(T_99, T_108)
    node T_110 = shr(T_106, 1)
    node T_111 = and(T_110, T_109)
    node T_112 = bits(T_106, 6, 0)
    node T_113 = shl(T_112, 1)
    node T_114 = not(T_109)
    node T_115 = and(T_113, T_114)
    node T_116 = or(T_111, T_115)
    node T_117 = bits(T_84, 8, 8)
    node T_118 = cat(T_116, T_117)
    node T_119 = cat(T_83, T_118)
    node T_120 = or(T_36, T_119)
    node T_121 = or(T_120, doShiftSigDown1)
    node roundMask = cat(T_121, UInt<2>("h03"))
    node T_124 = shr(roundMask, 1)
    node T_125 = not(T_124)
    node roundPosMask = and(T_125, roundMask)
    node T_127 = and(io.in.sig, roundPosMask)
    node roundPosBit = neq(T_127, UInt<1>("h00"))
    node T_130 = shr(roundMask, 1)
    node T_131 = and(io.in.sig, T_130)
    node anyRoundExtra = neq(T_131, UInt<1>("h00"))
    node common_inexact = or(roundPosBit, anyRoundExtra)
    node T_135 = and(roundingMode_nearest_even, roundPosBit)
    node T_136 = and(roundMagUp, common_inexact)
    node T_137 = or(T_135, T_136)
    node T_138 = or(io.in.sig, roundMask)
    node T_139 = shr(T_138, 2)
    node T_141 = add(T_139, UInt<1>("h01"))
    node T_142 = tail(T_141, 1)
    node T_143 = and(roundingMode_nearest_even, roundPosBit)
    node T_144 = not(anyRoundExtra)
    node T_145 = and(T_143, T_144)
    node T_146 = shr(roundMask, 1)
    node T_148 = mux(T_145, T_146, UInt<26>("h00"))
    node T_149 = not(T_148)
    node T_150 = and(T_142, T_149)
    node T_151 = not(roundMask)
    node T_152 = and(io.in.sig, T_151)
    node T_153 = shr(T_152, 2)
    node roundedSig = mux(T_137, T_150, T_153)
    node T_155 = shr(roundedSig, 24)
    node T_156 = cvt(T_155)
    node T_157 = add(io.in.sExp, T_156)
    node T_158 = tail(T_157, 1)
    node sRoundedExp = asSInt(T_158)
    node common_expOut = bits(sRoundedExp, 8, 0)
    node T_161 = bits(roundedSig, 23, 1)
    node T_162 = bits(roundedSig, 22, 0)
    node common_fractOut = mux(doShiftSigDown1, T_161, T_162)
    node T_164 = shr(sRoundedExp, 7)
    node common_overflow = geq(T_164, asSInt(UInt<3>("h03")))
    node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b")))
    node T_171 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082")))
    node T_172 = lt(io.in.sExp, T_171)
    node common_underflow = and(common_inexact, T_172)
    node isNaNOut = or(io.invalidExc, io.in.isNaN)
    node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
    node T_176 = not(isNaNOut)
    node T_177 = not(notNaN_isSpecialInfOut)
    node T_178 = and(T_176, T_177)
    node T_179 = not(io.in.isZero)
    node commonCase = and(T_178, T_179)
    node overflow = and(commonCase, common_overflow)
    node underflow = and(commonCase, common_underflow)
    node T_183 = and(commonCase, common_inexact)
    node inexact = or(overflow, T_183)
    node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp)
    node T_186 = and(commonCase, common_totalUnderflow)
    node pegMinNonzeroMagOut = and(T_186, roundMagUp)
    node T_188 = and(commonCase, overflow)
    node T_189 = not(overflow_roundMagUp)
    node pegMaxFiniteMagOut = and(T_188, T_189)
    node T_191 = and(overflow, overflow_roundMagUp)
    node notNaN_isInfOut = or(notNaN_isSpecialInfOut, T_191)
    node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign)
    node T_195 = or(io.in.isZero, common_totalUnderflow)
    node T_198 = mux(T_195, UInt<9>("h01c0"), UInt<1>("h00"))
    node T_199 = not(T_198)
    node T_200 = and(common_expOut, T_199)
    node T_202 = not(UInt<9>("h06b"))
    node T_204 = mux(pegMinNonzeroMagOut, T_202, UInt<1>("h00"))
    node T_205 = not(T_204)
    node T_206 = and(T_200, T_205)
    node T_209 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00"))
    node T_210 = not(T_209)
    node T_211 = and(T_206, T_210)
    node T_214 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00"))
    node T_215 = not(T_214)
    node T_216 = and(T_211, T_215)
    node T_219 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00"))
    node T_220 = or(T_216, T_219)
    node T_223 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00"))
    node T_224 = or(T_220, T_223)
    node T_227 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00"))
    node T_228 = or(T_224, T_227)
    node T_231 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00"))
    node expOut = or(T_228, T_231)
    node T_233 = and(common_totalUnderflow, roundMagUp)
    node T_234 = or(T_233, isNaNOut)
    node T_236 = mux(T_234, UInt<1>("h00"), common_fractOut)
    node T_238 = sub(UInt<23>("h00"), pegMaxFiniteMagOut)
    node T_239 = tail(T_238, 1)
    node T_240 = or(T_236, T_239)
    node T_241 = shl(isNaNOut, 22)
    node fractOut = or(T_240, T_241)
    node T_243 = cat(expOut, fractOut)
    node T_244 = cat(signOut, T_243)
    io.out <= T_244
    node T_245 = cat(io.invalidExc, io.infiniteExc)
    node T_246 = cat(underflow, inexact)
    node T_247 = cat(overflow, T_246)
    node T_248 = cat(T_245, T_247)
    io.exceptionFlags <= T_248
    
  module RecFNToRecFN_121 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>}
    
    io is invalid
    node T_8 = bits(io.in, 63, 52)
    node T_9 = bits(T_8, 11, 10)
    node T_11 = eq(T_9, UInt<2>("h03"))
    wire T_19 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>}
    T_19 is invalid
    node T_26 = bits(io.in, 64, 64)
    T_19.sign <= T_26
    node T_27 = bits(T_8, 9, 9)
    node T_28 = and(T_11, T_27)
    T_19.isNaN <= T_28
    node T_29 = bits(T_8, 9, 9)
    node T_31 = eq(T_29, UInt<1>("h00"))
    node T_32 = and(T_11, T_31)
    T_19.isInf <= T_32
    node T_33 = bits(T_8, 11, 9)
    node T_35 = eq(T_33, UInt<1>("h00"))
    T_19.isZero <= T_35
    node T_36 = cvt(T_8)
    T_19.sExp <= T_36
    node T_38 = bits(io.in, 51, 0)
    node T_40 = cat(T_38, UInt<2>("h00"))
    node T_41 = cat(UInt<2>("h01"), T_40)
    T_19.sig <= T_41
    node T_43 = add(T_19.sExp, asSInt(UInt<12>("h0900")))
    node T_44 = tail(T_43, 1)
    node T_45 = asSInt(T_44)
    wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}
    outRawFloat is invalid
    outRawFloat.sign <= T_19.sign
    outRawFloat.isNaN <= T_19.isNaN
    outRawFloat.isInf <= T_19.isInf
    outRawFloat.isZero <= T_19.isZero
    node T_61 = lt(T_45, asSInt(UInt<1>("h00")))
    node T_62 = bits(T_45, 11, 9)
    node T_64 = neq(T_62, UInt<1>("h00"))
    node T_66 = cat(UInt<1>("h01"), UInt<1>("h01"))
    node T_67 = cat(T_66, T_66)
    node T_68 = cat(T_66, T_67)
    node T_69 = cat(UInt<1>("h01"), T_68)
    node T_71 = cat(T_69, UInt<2>("h00"))
    node T_72 = bits(T_45, 8, 0)
    node T_73 = mux(T_64, T_71, T_72)
    node T_74 = cat(T_61, T_73)
    node T_75 = asSInt(T_74)
    outRawFloat.sExp <= T_75
    node T_76 = bits(T_19.sig, 55, 30)
    node T_77 = bits(T_19.sig, 29, 0)
    node T_79 = neq(T_77, UInt<1>("h00"))
    node T_80 = cat(T_76, T_79)
    outRawFloat.sig <= T_80
    node T_81 = bits(outRawFloat.sig, 24, 24)
    node T_83 = eq(T_81, UInt<1>("h00"))
    node invalidExc = and(outRawFloat.isNaN, T_83)
    inst T_85 of RoundRawFNToRecFN
    T_85.io is invalid
    T_85.clk <= clk
    T_85.reset <= reset
    T_85.io.invalidExc <= invalidExc
    T_85.io.infiniteExc <= UInt<1>("h00")
    T_85.io.in <- outRawFloat
    T_85.io.roundingMode <= io.roundingMode
    io.out <= T_85.io.out
    io.exceptionFlags <= T_85.io.exceptionFlags
    
  module FPToFP : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>}
    
    io is invalid
    reg T_137 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_137 <= io.in.valid
    reg T_138 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk
    when io.in.valid :
      T_138 <- io.in.bits
      skip
    wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
    in is invalid
    in.valid <= T_137
    in.bits <- T_138
    node T_259 = and(in.bits.cmd, UInt<3>("h05"))
    node isSgnj = eq(UInt<3>("h04"), T_259)
    node T_261 = and(in.bits.single, isSgnj)
    node T_262 = bits(in.bits.rm, 1, 1)
    node T_264 = eq(T_261, UInt<1>("h00"))
    node T_265 = or(T_262, T_264)
    node T_266 = bits(in.bits.in1, 32, 32)
    node T_267 = bits(in.bits.rm, 0, 0)
    node T_268 = mux(T_265, T_266, T_267)
    node T_269 = bits(in.bits.in2, 32, 32)
    node T_270 = and(T_261, T_269)
    node sign_s = xor(T_268, T_270)
    node T_273 = eq(in.bits.single, UInt<1>("h00"))
    node T_274 = and(T_273, isSgnj)
    node T_275 = bits(in.bits.rm, 1, 1)
    node T_277 = eq(T_274, UInt<1>("h00"))
    node T_278 = or(T_275, T_277)
    node T_279 = bits(in.bits.in1, 64, 64)
    node T_280 = bits(in.bits.rm, 0, 0)
    node T_281 = mux(T_278, T_279, T_280)
    node T_282 = bits(in.bits.in2, 64, 64)
    node T_283 = and(T_274, T_282)
    node sign_d = xor(T_281, T_283)
    node T_285 = bits(in.bits.in1, 63, 33)
    node T_286 = bits(in.bits.in1, 31, 0)
    node T_287 = cat(sign_d, T_285)
    node T_288 = cat(sign_s, T_286)
    node fsgnj = cat(T_287, T_288)
    inst s2d of RecFNToRecFN
    s2d.io is invalid
    s2d.clk <= clk
    s2d.reset <= reset
    inst d2s of RecFNToRecFN_121
    d2s.io is invalid
    d2s.clk <= clk
    d2s.reset <= reset
    s2d.io.in <= in.bits.in1
    s2d.io.roundingMode <= in.bits.rm
    d2s.io.in <= in.bits.in1
    d2s.io.roundingMode <= in.bits.rm
    node T_292 = bits(in.bits.in1, 31, 29)
    node T_293 = not(T_292)
    node T_295 = eq(T_293, UInt<1>("h00"))
    node T_296 = bits(in.bits.in1, 63, 61)
    node T_297 = not(T_296)
    node T_299 = eq(T_297, UInt<1>("h00"))
    node isnan1 = mux(in.bits.single, T_295, T_299)
    node T_301 = bits(in.bits.in2, 31, 29)
    node T_302 = not(T_301)
    node T_304 = eq(T_302, UInt<1>("h00"))
    node T_305 = bits(in.bits.in2, 63, 61)
    node T_306 = not(T_305)
    node T_308 = eq(T_306, UInt<1>("h00"))
    node isnan2 = mux(in.bits.single, T_304, T_308)
    node T_310 = bits(in.bits.in1, 22, 22)
    node T_311 = bits(in.bits.in1, 51, 51)
    node T_312 = mux(in.bits.single, T_310, T_311)
    node T_313 = not(T_312)
    node issnan1 = and(isnan1, T_313)
    node T_315 = bits(in.bits.in2, 22, 22)
    node T_316 = bits(in.bits.in2, 51, 51)
    node T_317 = mux(in.bits.single, T_315, T_316)
    node T_318 = not(T_317)
    node issnan2 = and(isnan2, T_318)
    node T_320 = or(issnan1, issnan2)
    node minmax_exc = cat(T_320, UInt<4>("h00"))
    node isMax = bits(in.bits.rm, 0, 0)
    node T_324 = neq(isMax, io.lt)
    node T_326 = eq(isnan1, UInt<1>("h00"))
    node T_327 = and(T_324, T_326)
    node isLHS = or(isnan2, T_327)
    wire mux : {data : UInt<65>, exc : UInt<5>}
    mux is invalid
    mux.exc <= minmax_exc
    mux.data <= in.bits.in2
    when isSgnj :
      mux.exc <= UInt<1>("h00")
      skip
    node T_336 = or(isSgnj, isLHS)
    when T_336 :
      mux.data <= fsgnj
      skip
    node T_339 = and(in.bits.cmd, UInt<3>("h04"))
    node T_340 = eq(UInt<1>("h00"), T_339)
    when T_340 :
      when in.bits.single :
        node T_342 = asUInt(asSInt(UInt<32>("h0ffffffff")))
        node T_343 = cat(T_342, d2s.io.out)
        mux.data <= T_343
        mux.exc <= d2s.io.exceptionFlags
        skip
      node T_345 = eq(in.bits.single, UInt<1>("h00"))
      when T_345 :
        mux.data <= s2d.io.out
        mux.exc <= s2d.io.exceptionFlags
        skip
      skip
    reg T_348 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    T_348 <= in.valid
    reg T_349 : {data : UInt<65>, exc : UInt<5>}, clk
    when in.valid :
      T_349 <- mux
      skip
    wire T_360 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}
    T_360 is invalid
    T_360.valid <= T_348
    T_360.bits <- T_349
    io.out <- T_360
    
  module DivSqrtRecF64_mulAddZ31 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>}
    
    io is invalid
    reg valid_PA : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg sqrtOp_PA : UInt<1>, clk
    reg sign_PA : UInt<1>, clk
    reg specialCodeB_PA : UInt<3>, clk
    reg fractB_51_PA : UInt<1>, clk
    reg roundingMode_PA : UInt<2>, clk
    reg specialCodeA_PA : UInt<3>, clk
    reg fractA_51_PA : UInt<1>, clk
    reg exp_PA : UInt<14>, clk
    reg fractB_other_PA : UInt<51>, clk
    reg fractA_other_PA : UInt<51>, clk
    reg valid_PB : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg sqrtOp_PB : UInt<1>, clk
    reg sign_PB : UInt<1>, clk
    reg specialCodeA_PB : UInt<3>, clk
    reg fractA_51_PB : UInt<1>, clk
    reg specialCodeB_PB : UInt<3>, clk
    reg fractB_51_PB : UInt<1>, clk
    reg roundingMode_PB : UInt<2>, clk
    reg exp_PB : UInt<14>, clk
    reg fractA_0_PB : UInt<1>, clk
    reg fractB_other_PB : UInt<51>, clk
    reg valid_PC : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg sqrtOp_PC : UInt<1>, clk
    reg sign_PC : UInt<1>, clk
    reg specialCodeA_PC : UInt<3>, clk
    reg fractA_51_PC : UInt<1>, clk
    reg specialCodeB_PC : UInt<3>, clk
    reg fractB_51_PC : UInt<1>, clk
    reg roundingMode_PC : UInt<2>, clk
    reg exp_PC : UInt<14>, clk
    reg fractA_0_PC : UInt<1>, clk
    reg fractB_other_PC : UInt<51>, clk
    reg cycleNum_A : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg cycleNum_B : UInt<4>, clk with : (reset => (reset, UInt<4>("h00")))
    reg cycleNum_C : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg cycleNum_E : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
    reg fractR0_A : UInt<9>, clk
    reg hiSqrR0_A_sqrt : UInt<10>, clk
    reg partNegSigma0_A : UInt<21>, clk
    reg nextMulAdd9A_A : UInt<9>, clk
    reg nextMulAdd9B_A : UInt<9>, clk
    reg ER1_B_sqrt : UInt<17>, clk
    reg ESqrR1_B_sqrt : UInt<32>, clk
    reg sigX1_B : UInt<58>, clk
    reg sqrSigma1_C : UInt<33>, clk
    reg sigXN_C : UInt<58>, clk
    reg u_C_sqrt : UInt<31>, clk
    reg E_E_div : UInt<1>, clk
    reg sigT_E : UInt<53>, clk
    reg extraT_E : UInt<1>, clk
    reg isNegRemT_E : UInt<1>, clk
    reg trueEqX_E1 : UInt<1>, clk
    wire ready_PA : UInt<1>
    ready_PA is invalid
    wire ready_PB : UInt<1>
    ready_PB is invalid
    wire ready_PC : UInt<1>
    ready_PC is invalid
    wire leaving_PA : UInt<1>
    leaving_PA is invalid
    wire leaving_PB : UInt<1>
    leaving_PB is invalid
    wire leaving_PC : UInt<1>
    leaving_PC is invalid
    wire cyc_B10_sqrt : UInt<1>
    cyc_B10_sqrt is invalid
    wire cyc_B9_sqrt : UInt<1>
    cyc_B9_sqrt is invalid
    wire cyc_B8_sqrt : UInt<1>
    cyc_B8_sqrt is invalid
    wire cyc_B7_sqrt : UInt<1>
    cyc_B7_sqrt is invalid
    wire cyc_B6 : UInt<1>
    cyc_B6 is invalid
    wire cyc_B5 : UInt<1>
    cyc_B5 is invalid
    wire cyc_B4 : UInt<1>
    cyc_B4 is invalid
    wire cyc_B3 : UInt<1>
    cyc_B3 is invalid
    wire cyc_B2 : UInt<1>
    cyc_B2 is invalid
    wire cyc_B1 : UInt<1>
    cyc_B1 is invalid
    wire cyc_B6_div : UInt<1>
    cyc_B6_div is invalid
    wire cyc_B5_div : UInt<1>
    cyc_B5_div is invalid
    wire cyc_B4_div : UInt<1>
    cyc_B4_div is invalid
    wire cyc_B3_div : UInt<1>
    cyc_B3_div is invalid
    wire cyc_B2_div : UInt<1>
    cyc_B2_div is invalid
    wire cyc_B1_div : UInt<1>
    cyc_B1_div is invalid
    wire cyc_B6_sqrt : UInt<1>
    cyc_B6_sqrt is invalid
    wire cyc_B5_sqrt : UInt<1>
    cyc_B5_sqrt is invalid
    wire cyc_B4_sqrt : UInt<1>
    cyc_B4_sqrt is invalid
    wire cyc_B3_sqrt : UInt<1>
    cyc_B3_sqrt is invalid
    wire cyc_B2_sqrt : UInt<1>
    cyc_B2_sqrt is invalid
    wire cyc_B1_sqrt : UInt<1>
    cyc_B1_sqrt is invalid
    wire cyc_C5 : UInt<1>
    cyc_C5 is invalid
    wire cyc_C4 : UInt<1>
    cyc_C4 is invalid
    wire valid_normalCase_leaving_PB : UInt<1>
    valid_normalCase_leaving_PB is invalid
    wire cyc_C2 : UInt<1>
    cyc_C2 is invalid
    wire cyc_C1 : UInt<1>
    cyc_C1 is invalid
    wire cyc_E4 : UInt<1>
    cyc_E4 is invalid
    wire cyc_E3 : UInt<1>
    cyc_E3 is invalid
    wire cyc_E2 : UInt<1>
    cyc_E2 is invalid
    wire cyc_E1 : UInt<1>
    cyc_E1 is invalid
    wire zSigma1_B4 : UInt
    zSigma1_B4 is invalid
    wire sigXNU_B3_CX : UInt
    sigXNU_B3_CX is invalid
    wire zComplSigT_C1_sqrt : UInt
    zComplSigT_C1_sqrt is invalid
    wire zComplSigT_C1 : UInt
    zComplSigT_C1 is invalid
    node T_210 = not(cyc_B7_sqrt)
    node T_211 = and(ready_PA, T_210)
    node T_212 = not(cyc_B6_sqrt)
    node T_213 = and(T_211, T_212)
    node T_214 = not(cyc_B5_sqrt)
    node T_215 = and(T_213, T_214)
    node T_216 = not(cyc_B4_sqrt)
    node T_217 = and(T_215, T_216)
    node T_218 = not(cyc_B3)
    node T_219 = and(T_217, T_218)
    node T_220 = not(cyc_B2)
    node T_221 = and(T_219, T_220)
    node T_222 = not(cyc_B1_sqrt)
    node T_223 = and(T_221, T_222)
    node T_224 = not(cyc_C5)
    node T_225 = and(T_223, T_224)
    node T_226 = not(cyc_C4)
    node T_227 = and(T_225, T_226)
    io.inReady_div <= T_227
    node T_228 = not(cyc_B6_sqrt)
    node T_229 = and(ready_PA, T_228)
    node T_230 = not(cyc_B5_sqrt)
    node T_231 = and(T_229, T_230)
    node T_232 = not(cyc_B4_sqrt)
    node T_233 = and(T_231, T_232)
    node T_234 = not(cyc_B2_div)
    node T_235 = and(T_233, T_234)
    node T_236 = not(cyc_B1_sqrt)
    node T_237 = and(T_235, T_236)
    io.inReady_sqrt <= T_237
    node T_238 = and(io.inReady_div, io.inValid)
    node T_239 = not(io.sqrtOp)
    node cyc_S_div = and(T_238, T_239)
    node T_241 = and(io.inReady_sqrt, io.inValid)
    node cyc_S_sqrt = and(T_241, io.sqrtOp)
    node cyc_S = or(cyc_S_div, cyc_S_sqrt)
    node signA_S = bits(io.a, 64, 64)
    node expA_S = bits(io.a, 63, 52)
    node fractA_S = bits(io.a, 51, 0)
    node specialCodeA_S = bits(expA_S, 11, 9)
    node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00"))
    node T_250 = bits(specialCodeA_S, 2, 1)
    node isSpecialA_S = eq(T_250, UInt<2>("h03"))
    node signB_S = bits(io.b, 64, 64)
    node expB_S = bits(io.b, 63, 52)
    node fractB_S = bits(io.b, 51, 0)
    node specialCodeB_S = bits(expB_S, 11, 9)
    node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00"))
    node T_259 = bits(specialCodeB_S, 2, 1)
    node isSpecialB_S = eq(T_259, UInt<2>("h03"))
    node T_262 = xor(signA_S, signB_S)
    node sign_S = mux(io.sqrtOp, signB_S, T_262)
    node T_264 = not(isSpecialA_S)
    node T_265 = not(isSpecialB_S)
    node T_266 = and(T_264, T_265)
    node T_267 = not(isZeroA_S)
    node T_268 = and(T_266, T_267)
    node T_269 = not(isZeroB_S)
    node normalCase_S_div = and(T_268, T_269)
    node T_271 = not(isSpecialB_S)
    node T_272 = not(isZeroB_S)
    node T_273 = and(T_271, T_272)
    node T_274 = not(signB_S)
    node normalCase_S_sqrt = and(T_273, T_274)
    node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
    node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div)
    node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt)
    node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt)
    node T_280 = not(ready_PB)
    node T_281 = or(valid_PA, T_280)
    node T_282 = and(cyc_S, T_281)
    node entering_PA = or(entering_PA_normalCase, T_282)
    node T_284 = not(normalCase_S)
    node T_285 = and(cyc_S, T_284)
    node T_286 = not(valid_PA)
    node T_287 = and(T_285, T_286)
    node T_288 = not(valid_PB)
    node T_289 = not(ready_PC)
    node T_290 = and(T_288, T_289)
    node T_291 = or(leaving_PB, T_290)
    node entering_PB_S = and(T_287, T_291)
    node T_293 = not(normalCase_S)
    node T_294 = and(cyc_S, T_293)
    node T_295 = not(valid_PA)
    node T_296 = and(T_294, T_295)
    node T_297 = not(valid_PB)
    node T_298 = and(T_296, T_297)
    node entering_PC_S = and(T_298, ready_PC)
    node T_300 = or(entering_PA, leaving_PA)
    when T_300 :
      valid_PA <= entering_PA
      skip
    when entering_PA :
      sqrtOp_PA <= io.sqrtOp
      sign_PA <= sign_S
      specialCodeB_PA <= specialCodeB_S
      node T_301 = bits(fractB_S, 51, 51)
      fractB_51_PA <= T_301
      roundingMode_PA <= io.roundingMode
      skip
    node T_302 = not(io.sqrtOp)
    node T_303 = and(entering_PA, T_302)
    when T_303 :
      specialCodeA_PA <= specialCodeA_S
      node T_304 = bits(fractA_S, 51, 51)
      fractA_51_PA <= T_304
      skip
    when entering_PA_normalCase :
      node T_305 = bits(expB_S, 11, 11)
      node T_307 = sub(UInt<3>("h00"), T_305)
      node T_308 = tail(T_307, 1)
      node T_309 = bits(expB_S, 10, 0)
      node T_310 = not(T_309)
      node T_311 = cat(T_308, T_310)
      node T_312 = add(expA_S, T_311)
      node T_313 = tail(T_312, 1)
      node T_314 = mux(io.sqrtOp, expB_S, T_313)
      exp_PA <= T_314
      node T_315 = bits(fractB_S, 50, 0)
      fractB_other_PA <= T_315
      skip
    when entering_PA_normalCase_div :
      node T_316 = bits(fractA_S, 50, 0)
      fractA_other_PA <= T_316
      skip
    node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00"))
    node T_319 = bits(specialCodeA_PA, 2, 1)
    node isSpecialA_PA = eq(T_319, UInt<2>("h03"))
    node T_323 = cat(fractA_51_PA, fractA_other_PA)
    node sigA_PA = cat(UInt<1>("h01"), T_323)
    node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00"))
    node T_327 = bits(specialCodeB_PA, 2, 1)
    node isSpecialB_PA = eq(T_327, UInt<2>("h03"))
    node T_331 = cat(fractB_51_PA, fractB_other_PA)
    node sigB_PA = cat(UInt<1>("h01"), T_331)
    node T_333 = not(isSpecialB_PA)
    node T_334 = not(isZeroB_PA)
    node T_335 = and(T_333, T_334)
    node T_336 = not(sign_PA)
    node T_337 = and(T_335, T_336)
    node T_338 = not(isSpecialA_PA)
    node T_339 = not(isSpecialB_PA)
    node T_340 = and(T_338, T_339)
    node T_341 = not(isZeroA_PA)
    node T_342 = and(T_340, T_341)
    node T_343 = not(isZeroB_PA)
    node T_344 = and(T_342, T_343)
    node normalCase_PA = mux(sqrtOp_PA, T_337, T_344)
    node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt)
    node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB)
    node T_348 = and(valid_PA, valid_leaving_PA)
    leaving_PA <= T_348
    node T_349 = not(valid_PA)
    node T_350 = or(T_349, valid_leaving_PA)
    ready_PA <= T_350
    node T_351 = and(valid_PA, normalCase_PA)
    node entering_PB_normalCase = and(T_351, valid_normalCase_leaving_PA)
    node entering_PB = or(entering_PB_S, leaving_PA)
    node T_354 = or(entering_PB, leaving_PB)
    when T_354 :
      valid_PB <= entering_PB
      skip
    when entering_PB :
      node T_355 = mux(valid_PA, sqrtOp_PA, io.sqrtOp)
      sqrtOp_PB <= T_355
      node T_356 = mux(valid_PA, sign_PA, sign_S)
      sign_PB <= T_356
      node T_357 = mux(valid_PA, specialCodeA_PA, specialCodeA_S)
      specialCodeA_PB <= T_357
      node T_358 = bits(fractA_S, 51, 51)
      node T_359 = mux(valid_PA, fractA_51_PA, T_358)
      fractA_51_PB <= T_359
      node T_360 = mux(valid_PA, specialCodeB_PA, specialCodeB_S)
      specialCodeB_PB <= T_360
      node T_361 = bits(fractB_S, 51, 51)
      node T_362 = mux(valid_PA, fractB_51_PA, T_361)
      fractB_51_PB <= T_362
      node T_363 = mux(valid_PA, roundingMode_PA, io.roundingMode)
      roundingMode_PB <= T_363
      skip
    when entering_PB_normalCase :
      exp_PB <= exp_PA
      node T_364 = bits(fractA_other_PA, 0, 0)
      fractA_0_PB <= T_364
      fractB_other_PB <= fractB_other_PA
      skip
    node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00"))
    node T_367 = bits(specialCodeA_PB, 2, 1)
    node isSpecialA_PB = eq(T_367, UInt<2>("h03"))
    node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00"))
    node T_372 = bits(specialCodeB_PB, 2, 1)
    node isSpecialB_PB = eq(T_372, UInt<2>("h03"))
    node T_375 = not(isSpecialB_PB)
    node T_376 = not(isZeroB_PB)
    node T_377 = and(T_375, T_376)
    node T_378 = not(sign_PB)
    node T_379 = and(T_377, T_378)
    node T_380 = not(isSpecialA_PB)
    node T_381 = not(isSpecialB_PB)
    node T_382 = and(T_380, T_381)
    node T_383 = not(isZeroA_PB)
    node T_384 = and(T_382, T_383)
    node T_385 = not(isZeroB_PB)
    node T_386 = and(T_384, T_385)
    node normalCase_PB = mux(sqrtOp_PB, T_379, T_386)
    node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC)
    node T_389 = and(valid_PB, valid_leaving_PB)
    leaving_PB <= T_389
    node T_390 = not(valid_PB)
    node T_391 = or(T_390, valid_leaving_PB)
    ready_PB <= T_391
    node T_392 = and(valid_PB, normalCase_PB)
    node entering_PC_normalCase = and(T_392, valid_normalCase_leaving_PB)
    node entering_PC = or(entering_PC_S, leaving_PB)
    node T_395 = or(entering_PC, leaving_PC)
    when T_395 :
      valid_PC <= entering_PC
      skip
    when entering_PC :
      node T_396 = mux(valid_PB, sqrtOp_PB, io.sqrtOp)
      sqrtOp_PC <= T_396
      node T_397 = mux(valid_PB, sign_PB, sign_S)
      sign_PC <= T_397
      node T_398 = mux(valid_PB, specialCodeA_PB, specialCodeA_S)
      specialCodeA_PC <= T_398
      node T_399 = bits(fractA_S, 51, 51)
      node T_400 = mux(valid_PB, fractA_51_PB, T_399)
      fractA_51_PC <= T_400
      node T_401 = mux(valid_PB, specialCodeB_PB, specialCodeB_S)
      specialCodeB_PC <= T_401
      node T_402 = bits(fractB_S, 51, 51)
      node T_403 = mux(valid_PB, fractB_51_PB, T_402)
      fractB_51_PC <= T_403
      node T_404 = mux(valid_PB, roundingMode_PB, io.roundingMode)
      roundingMode_PC <= T_404
      skip
    when entering_PC_normalCase :
      exp_PC <= exp_PB
      fractA_0_PC <= fractA_0_PB
      fractB_other_PC <= fractB_other_PB
      skip
    node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00"))
    node T_407 = bits(specialCodeA_PC, 2, 1)
    node isSpecialA_PC = eq(T_407, UInt<2>("h03"))
    node T_410 = bits(specialCodeA_PC, 0, 0)
    node T_411 = not(T_410)
    node isInfA_PC = and(isSpecialA_PC, T_411)
    node T_413 = bits(specialCodeA_PC, 0, 0)
    node isNaNA_PC = and(isSpecialA_PC, T_413)
    node T_415 = not(fractA_51_PC)
    node isSigNaNA_PC = and(isNaNA_PC, T_415)
    node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00"))
    node T_419 = bits(specialCodeB_PC, 2, 1)
    node isSpecialB_PC = eq(T_419, UInt<2>("h03"))
    node T_422 = bits(specialCodeB_PC, 0, 0)
    node T_423 = not(T_422)
    node isInfB_PC = and(isSpecialB_PC, T_423)
    node T_425 = bits(specialCodeB_PC, 0, 0)
    node isNaNB_PC = and(isSpecialB_PC, T_425)
    node T_427 = not(fractB_51_PC)
    node isSigNaNB_PC = and(isNaNB_PC, T_427)
    node T_430 = cat(fractB_51_PC, fractB_other_PC)
    node sigB_PC = cat(UInt<1>("h01"), T_430)
    node T_432 = not(isSpecialB_PC)
    node T_433 = not(isZeroB_PC)
    node T_434 = and(T_432, T_433)
    node T_435 = not(sign_PC)
    node T_436 = and(T_434, T_435)
    node T_437 = not(isSpecialA_PC)
    node T_438 = not(isSpecialB_PC)
    node T_439 = and(T_437, T_438)
    node T_440 = not(isZeroA_PC)
    node T_441 = and(T_439, T_440)
    node T_442 = not(isZeroB_PC)
    node T_443 = and(T_441, T_442)
    node normalCase_PC = mux(sqrtOp_PC, T_436, T_443)
    node T_446 = add(exp_PC, UInt<2>("h02"))
    node expP2_PC = tail(T_446, 1)
    node T_448 = bits(exp_PC, 0, 0)
    node T_449 = bits(expP2_PC, 13, 1)
    node T_451 = cat(T_449, UInt<1>("h00"))
    node T_452 = bits(exp_PC, 13, 1)
    node T_454 = cat(T_452, UInt<1>("h01"))
    node expP1_PC = mux(T_448, T_451, T_454)
    node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00"))
    node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01"))
    node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02"))
    node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03"))
    node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC)
    node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC)
    node T_462 = not(roundMagUp_PC)
    node T_463 = not(roundingMode_near_even_PC)
    node roundMagDown_PC = and(T_462, T_463)
    node T_465 = not(normalCase_PC)
    node valid_leaving_PC = or(T_465, cyc_E1)
    node T_467 = and(valid_PC, valid_leaving_PC)
    leaving_PC <= T_467
    node T_468 = not(valid_PC)
    node T_469 = or(T_468, valid_leaving_PC)
    ready_PC <= T_469
    node T_470 = not(sqrtOp_PC)
    node T_471 = and(leaving_PC, T_470)
    io.outValid_div <= T_471
    node T_472 = and(leaving_PC, sqrtOp_PC)
    io.outValid_sqrt <= T_472
    node T_474 = neq(cycleNum_A, UInt<1>("h00"))
    node T_475 = or(entering_PA_normalCase, T_474)
    when T_475 :
      node T_478 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00"))
      node T_481 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00"))
      node T_482 = or(T_478, T_481)
      node T_483 = not(entering_PA_normalCase)
      node T_485 = sub(cycleNum_A, UInt<1>("h01"))
      node T_486 = tail(T_485, 1)
      node T_488 = mux(T_483, T_486, UInt<1>("h00"))
      node T_489 = or(T_482, T_488)
      cycleNum_A <= T_489
      skip
    node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06"))
    node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05"))
    node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04"))
    node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div)
    node cyc_A3 = eq(cycleNum_A, UInt<2>("h03"))
    node cyc_A2 = eq(cycleNum_A, UInt<2>("h02"))
    node cyc_A1 = eq(cycleNum_A, UInt<1>("h01"))
    node T_503 = not(sqrtOp_PA)
    node cyc_A3_div = and(cyc_A3, T_503)
    node T_505 = not(sqrtOp_PA)
    node cyc_A2_div = and(cyc_A2, T_505)
    node T_507 = not(sqrtOp_PA)
    node cyc_A1_div = and(cyc_A1, T_507)
    node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA)
    node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA)
    node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA)
    node T_513 = neq(cycleNum_B, UInt<1>("h00"))
    node T_514 = or(cyc_A1, T_513)
    when T_514 :
      node T_517 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06"))
      node T_519 = sub(cycleNum_B, UInt<1>("h01"))
      node T_520 = tail(T_519, 1)
      node T_521 = mux(cyc_A1, T_517, T_520)
      cycleNum_B <= T_521
      skip
    node T_523 = eq(cycleNum_B, UInt<4>("h0a"))
    cyc_B10_sqrt <= T_523
    node T_525 = eq(cycleNum_B, UInt<4>("h09"))
    cyc_B9_sqrt <= T_525
    node T_527 = eq(cycleNum_B, UInt<4>("h08"))
    cyc_B8_sqrt <= T_527
    node T_529 = eq(cycleNum_B, UInt<3>("h07"))
    cyc_B7_sqrt <= T_529
    node T_531 = eq(cycleNum_B, UInt<3>("h06"))
    cyc_B6 <= T_531
    node T_533 = eq(cycleNum_B, UInt<3>("h05"))
    cyc_B5 <= T_533
    node T_535 = eq(cycleNum_B, UInt<3>("h04"))
    cyc_B4 <= T_535
    node T_537 = eq(cycleNum_B, UInt<2>("h03"))
    cyc_B3 <= T_537
    node T_539 = eq(cycleNum_B, UInt<2>("h02"))
    cyc_B2 <= T_539
    node T_541 = eq(cycleNum_B, UInt<1>("h01"))
    cyc_B1 <= T_541
    node T_542 = and(cyc_B6, valid_PA)
    node T_543 = not(sqrtOp_PA)
    node T_544 = and(T_542, T_543)
    cyc_B6_div <= T_544
    node T_545 = and(cyc_B5, valid_PA)
    node T_546 = not(sqrtOp_PA)
    node T_547 = and(T_545, T_546)
    cyc_B5_div <= T_547
    node T_548 = and(cyc_B4, valid_PA)
    node T_549 = not(sqrtOp_PA)
    node T_550 = and(T_548, T_549)
    cyc_B4_div <= T_550
    node T_551 = not(sqrtOp_PB)
    node T_552 = and(cyc_B3, T_551)
    cyc_B3_div <= T_552
    node T_553 = not(sqrtOp_PB)
    node T_554 = and(cyc_B2, T_553)
    cyc_B2_div <= T_554
    node T_555 = not(sqrtOp_PB)
    node T_556 = and(cyc_B1, T_555)
    cyc_B1_div <= T_556
    node T_557 = and(cyc_B6, valid_PB)
    node T_558 = and(T_557, sqrtOp_PB)
    cyc_B6_sqrt <= T_558
    node T_559 = and(cyc_B5, valid_PB)
    node T_560 = and(T_559, sqrtOp_PB)
    cyc_B5_sqrt <= T_560
    node T_561 = and(cyc_B4, valid_PB)
    node T_562 = and(T_561, sqrtOp_PB)
    cyc_B4_sqrt <= T_562
    node T_563 = and(cyc_B3, sqrtOp_PB)
    cyc_B3_sqrt <= T_563
    node T_564 = and(cyc_B2, sqrtOp_PB)
    cyc_B2_sqrt <= T_564
    node T_565 = and(cyc_B1, sqrtOp_PB)
    cyc_B1_sqrt <= T_565
    node T_567 = neq(cycleNum_C, UInt<1>("h00"))
    node T_568 = or(cyc_B1, T_567)
    when T_568 :
      node T_571 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05"))
      node T_573 = sub(cycleNum_C, UInt<1>("h01"))
      node T_574 = tail(T_573, 1)
      node T_575 = mux(cyc_B1, T_571, T_574)
      cycleNum_C <= T_575
      skip
    node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06"))
    node T_579 = eq(cycleNum_C, UInt<3>("h05"))
    cyc_C5 <= T_579
    node T_581 = eq(cycleNum_C, UInt<3>("h04"))
    cyc_C4 <= T_581
    node T_583 = eq(cycleNum_C, UInt<2>("h03"))
    valid_normalCase_leaving_PB <= T_583
    node T_585 = eq(cycleNum_C, UInt<2>("h02"))
    cyc_C2 <= T_585
    node T_587 = eq(cycleNum_C, UInt<1>("h01"))
    cyc_C1 <= T_587
    node T_588 = not(sqrtOp_PB)
    node cyc_C5_div = and(cyc_C5, T_588)
    node T_590 = not(sqrtOp_PB)
    node cyc_C4_div = and(cyc_C4, T_590)
    node T_592 = not(sqrtOp_PB)
    node cyc_C3_div = and(valid_normalCase_leaving_PB, T_592)
    node T_594 = not(sqrtOp_PC)
    node cyc_C2_div = and(cyc_C2, T_594)
    node T_596 = not(sqrtOp_PC)
    node cyc_C1_div = and(cyc_C1, T_596)
    node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB)
    node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB)
    node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB)
    node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC)
    node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC)
    node T_604 = neq(cycleNum_E, UInt<1>("h00"))
    node T_605 = or(cyc_C1, T_604)
    when T_605 :
      node T_608 = sub(cycleNum_E, UInt<1>("h01"))
      node T_609 = tail(T_608, 1)
      node T_610 = mux(cyc_C1, UInt<3>("h04"), T_609)
      cycleNum_E <= T_610
      skip
    node T_612 = eq(cycleNum_E, UInt<3>("h04"))
    cyc_E4 <= T_612
    node T_614 = eq(cycleNum_E, UInt<2>("h03"))
    cyc_E3 <= T_614
    node T_616 = eq(cycleNum_E, UInt<2>("h02"))
    cyc_E2 <= T_616
    node T_618 = eq(cycleNum_E, UInt<1>("h01"))
    cyc_E1 <= T_618
    node T_619 = not(sqrtOp_PC)
    node cyc_E4_div = and(cyc_E4, T_619)
    node T_621 = not(sqrtOp_PC)
    node cyc_E3_div = and(cyc_E3, T_621)
    node T_623 = not(sqrtOp_PC)
    node cyc_E2_div = and(cyc_E2, T_623)
    node T_625 = not(sqrtOp_PC)
    node cyc_E1_div = and(cyc_E1, T_625)
    node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC)
    node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC)
    node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC)
    node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC)
    node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h00"))
    node T_633 = bits(fractB_S, 51, 49)
    node T_635 = eq(T_633, UInt<1>("h00"))
    node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_635)
    node T_637 = bits(fractB_S, 51, 49)
    node T_639 = eq(T_637, UInt<1>("h01"))
    node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_639)
    node T_641 = bits(fractB_S, 51, 49)
    node T_643 = eq(T_641, UInt<2>("h02"))
    node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_643)
    node T_645 = bits(fractB_S, 51, 49)
    node T_647 = eq(T_645, UInt<2>("h03"))
    node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_647)
    node T_649 = bits(fractB_S, 51, 49)
    node T_651 = eq(T_649, UInt<3>("h04"))
    node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_651)
    node T_653 = bits(fractB_S, 51, 49)
    node T_655 = eq(T_653, UInt<3>("h05"))
    node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_655)
    node T_657 = bits(fractB_S, 51, 49)
    node T_659 = eq(T_657, UInt<3>("h06"))
    node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_659)
    node T_661 = bits(fractB_S, 51, 49)
    node T_663 = eq(T_661, UInt<3>("h07"))
    node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_663)
    node T_667 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00"))
    node T_670 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00"))
    node T_671 = or(T_667, T_670)
    node T_674 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00"))
    node T_675 = or(T_671, T_674)
    node T_678 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00"))
    node T_679 = or(T_675, T_678)
    node T_682 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00"))
    node T_683 = or(T_679, T_682)
    node T_686 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00"))
    node T_687 = or(T_683, T_686)
    node T_690 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00"))
    node T_691 = or(T_687, T_690)
    node T_694 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00"))
    node zK1_A4_div = or(T_691, T_694)
    node T_697 = not(UInt<12>("h0fe3"))
    node T_699 = mux(zLinPiece_0_A4_div, T_697, UInt<1>("h00"))
    node T_701 = not(UInt<12>("h0c5d"))
    node T_703 = mux(zLinPiece_1_A4_div, T_701, UInt<1>("h00"))
    node T_704 = or(T_699, T_703)
    node T_706 = not(UInt<12>("h098a"))
    node T_708 = mux(zLinPiece_2_A4_div, T_706, UInt<1>("h00"))
    node T_709 = or(T_704, T_708)
    node T_711 = not(UInt<12>("h0739"))
    node T_713 = mux(zLinPiece_3_A4_div, T_711, UInt<1>("h00"))
    node T_714 = or(T_709, T_713)
    node T_716 = not(UInt<12>("h054b"))
    node T_718 = mux(zLinPiece_4_A4_div, T_716, UInt<1>("h00"))
    node T_719 = or(T_714, T_718)
    node T_721 = not(UInt<12>("h03a9"))
    node T_723 = mux(zLinPiece_5_A4_div, T_721, UInt<1>("h00"))
    node T_724 = or(T_719, T_723)
    node T_726 = not(UInt<12>("h0242"))
    node T_728 = mux(zLinPiece_6_A4_div, T_726, UInt<1>("h00"))
    node T_729 = or(T_724, T_728)
    node T_731 = not(UInt<12>("h010b"))
    node T_733 = mux(zLinPiece_7_A4_div, T_731, UInt<1>("h00"))
    node zComplFractK0_A4_div = or(T_729, T_733)
    node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h00"))
    node T_737 = bits(expB_S, 0, 0)
    node T_738 = not(T_737)
    node T_739 = and(entering_PA_normalCase_sqrt, T_738)
    node T_740 = bits(fractB_S, 51, 51)
    node T_741 = not(T_740)
    node zQuadPiece_0_A7_sqrt = and(T_739, T_741)
    node T_743 = bits(expB_S, 0, 0)
    node T_744 = not(T_743)
    node T_745 = and(entering_PA_normalCase_sqrt, T_744)
    node T_746 = bits(fractB_S, 51, 51)
    node zQuadPiece_1_A7_sqrt = and(T_745, T_746)
    node T_748 = bits(expB_S, 0, 0)
    node T_749 = and(entering_PA_normalCase_sqrt, T_748)
    node T_750 = bits(fractB_S, 51, 51)
    node T_751 = not(T_750)
    node zQuadPiece_2_A7_sqrt = and(T_749, T_751)
    node T_753 = bits(expB_S, 0, 0)
    node T_754 = and(entering_PA_normalCase_sqrt, T_753)
    node T_755 = bits(fractB_S, 51, 51)
    node zQuadPiece_3_A7_sqrt = and(T_754, T_755)
    node T_759 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00"))
    node T_762 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00"))
    node T_763 = or(T_759, T_762)
    node T_766 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00"))
    node T_767 = or(T_763, T_766)
    node T_770 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00"))
    node zK2_A7_sqrt = or(T_767, T_770)
    node T_773 = not(UInt<10>("h03d0"))
    node T_775 = mux(zQuadPiece_0_A7_sqrt, T_773, UInt<1>("h00"))
    node T_777 = not(UInt<10>("h0220"))
    node T_779 = mux(zQuadPiece_1_A7_sqrt, T_777, UInt<1>("h00"))
    node T_780 = or(T_775, T_779)
    node T_782 = not(UInt<10>("h02b2"))
    node T_784 = mux(zQuadPiece_2_A7_sqrt, T_782, UInt<1>("h00"))
    node T_785 = or(T_780, T_784)
    node T_787 = not(UInt<10>("h0181"))
    node T_789 = mux(zQuadPiece_3_A7_sqrt, T_787, UInt<1>("h00"))
    node zComplK1_A7_sqrt = or(T_785, T_789)
    node T_791 = bits(exp_PA, 0, 0)
    node T_792 = not(T_791)
    node T_793 = and(cyc_A6_sqrt, T_792)
    node T_794 = bits(sigB_PA, 51, 51)
    node T_795 = not(T_794)
    node zQuadPiece_0_A6_sqrt = and(T_793, T_795)
    node T_797 = bits(exp_PA, 0, 0)
    node T_798 = not(T_797)
    node T_799 = and(cyc_A6_sqrt, T_798)
    node T_800 = bits(sigB_PA, 51, 51)
    node zQuadPiece_1_A6_sqrt = and(T_799, T_800)
    node T_802 = bits(exp_PA, 0, 0)
    node T_803 = and(cyc_A6_sqrt, T_802)
    node T_804 = bits(sigB_PA, 51, 51)
    node T_805 = not(T_804)
    node zQuadPiece_2_A6_sqrt = and(T_803, T_805)
    node T_807 = bits(exp_PA, 0, 0)
    node T_808 = and(cyc_A6_sqrt, T_807)
    node T_809 = bits(sigB_PA, 51, 51)
    node zQuadPiece_3_A6_sqrt = and(T_808, T_809)
    node T_812 = not(UInt<13>("h01fe5"))
    node T_814 = mux(zQuadPiece_0_A6_sqrt, T_812, UInt<1>("h00"))
    node T_816 = not(UInt<13>("h01435"))
    node T_818 = mux(zQuadPiece_1_A6_sqrt, T_816, UInt<1>("h00"))
    node T_819 = or(T_814, T_818)
    node T_821 = not(UInt<13>("h0d2c"))
    node T_823 = mux(zQuadPiece_2_A6_sqrt, T_821, UInt<1>("h00"))
    node T_824 = or(T_819, T_823)
    node T_826 = not(UInt<13>("h04e8"))
    node T_828 = mux(zQuadPiece_3_A6_sqrt, T_826, UInt<1>("h00"))
    node zComplFractK0_A6_sqrt = or(T_824, T_828)
    node T_830 = bits(zFractB_A4_div, 48, 40)
    node T_831 = or(T_830, zK2_A7_sqrt)
    node T_832 = not(cyc_S)
    node T_834 = mux(T_832, nextMulAdd9A_A, UInt<1>("h00"))
    node mulAdd9A_A = or(T_831, T_834)
    node T_836 = bits(zFractB_A7_sqrt, 50, 42)
    node T_837 = or(zK1_A4_div, T_836)
    node T_838 = not(cyc_S)
    node T_840 = mux(T_838, nextMulAdd9B_A, UInt<1>("h00"))
    node mulAdd9B_A = or(T_837, T_840)
    node T_842 = shl(zComplK1_A7_sqrt, 10)
    node T_844 = sub(UInt<6>("h00"), cyc_A6_sqrt)
    node T_845 = tail(T_844, 1)
    node T_846 = cat(zComplFractK0_A6_sqrt, T_845)
    node T_847 = cat(cyc_A6_sqrt, T_846)
    node T_848 = or(T_842, T_847)
    node T_850 = sub(UInt<8>("h00"), entering_PA_normalCase_div)
    node T_851 = tail(T_850, 1)
    node T_852 = cat(zComplFractK0_A4_div, T_851)
    node T_853 = cat(entering_PA_normalCase_div, T_852)
    node T_854 = or(T_848, T_853)
    node T_856 = shl(fractR0_A, 10)
    node T_857 = add(UInt<20>("h040000"), T_856)
    node T_858 = tail(T_857, 1)
    node T_860 = mux(cyc_A5_sqrt, T_858, UInt<1>("h00"))
    node T_861 = or(T_854, T_860)
    node T_862 = bits(hiSqrR0_A_sqrt, 9, 9)
    node T_863 = not(T_862)
    node T_864 = and(cyc_A4_sqrt, T_863)
    node T_867 = mux(T_864, UInt<11>("h0400"), UInt<1>("h00"))
    node T_868 = or(T_861, T_867)
    node T_869 = bits(hiSqrR0_A_sqrt, 9, 9)
    node T_870 = and(cyc_A4_sqrt, T_869)
    node T_871 = or(T_870, cyc_A3_div)
    node T_872 = bits(sigB_PA, 46, 26)
    node T_874 = add(T_872, UInt<11>("h0400"))
    node T_875 = tail(T_874, 1)
    node T_877 = mux(T_871, T_875, UInt<1>("h00"))
    node T_878 = or(T_868, T_877)
    node T_879 = or(cyc_A3_sqrt, cyc_A2)
    node T_881 = mux(T_879, partNegSigma0_A, UInt<1>("h00"))
    node T_882 = or(T_878, T_881)
    node T_883 = shl(fractR0_A, 16)
    node T_885 = mux(cyc_A1_sqrt, T_883, UInt<1>("h00"))
    node T_886 = or(T_882, T_885)
    node T_887 = shl(fractR0_A, 15)
    node T_889 = mux(cyc_A1_div, T_887, UInt<1>("h00"))
    node mulAdd9C_A = or(T_886, T_889)
    node T_891 = mul(mulAdd9A_A, mulAdd9B_A)
    node T_893 = bits(mulAdd9C_A, 17, 0)
    node T_894 = cat(UInt<1>("h00"), T_893)
    node T_895 = add(T_891, T_894)
    node loMulAdd9Out_A = tail(T_895, 1)
    node T_897 = bits(loMulAdd9Out_A, 18, 18)
    node T_898 = bits(mulAdd9C_A, 24, 18)
    node T_900 = add(T_898, UInt<1>("h01"))
    node T_901 = tail(T_900, 1)
    node T_902 = bits(mulAdd9C_A, 24, 18)
    node T_903 = mux(T_897, T_901, T_902)
    node T_904 = bits(loMulAdd9Out_A, 17, 0)
    node mulAdd9Out_A = cat(T_903, T_904)
    node T_906 = bits(mulAdd9Out_A, 19, 19)
    node T_907 = and(cyc_A6_sqrt, T_906)
    node T_908 = not(mulAdd9Out_A)
    node T_909 = shr(T_908, 10)
    node T_911 = mux(T_907, T_909, UInt<1>("h00"))
    node zFractR0_A6_sqrt = bits(T_911, 8, 0)
    node T_913 = bits(exp_PA, 0, 0)
    node T_914 = shl(mulAdd9Out_A, 1)
    node sqrR0_A5_sqrt = mux(T_913, T_914, mulAdd9Out_A)
    node T_916 = bits(mulAdd9Out_A, 20, 20)
    node T_917 = and(entering_PA_normalCase_div, T_916)
    node T_918 = not(mulAdd9Out_A)
    node T_919 = shr(T_918, 11)
    node T_921 = mux(T_917, T_919, UInt<1>("h00"))
    node zFractR0_A4_div = bits(T_921, 8, 0)
    node T_923 = bits(mulAdd9Out_A, 11, 11)
    node T_924 = and(cyc_A2, T_923)
    node T_925 = not(mulAdd9Out_A)
    node T_926 = shr(T_925, 2)
    node T_928 = mux(T_924, T_926, UInt<1>("h00"))
    node zSigma0_A2 = bits(T_928, 8, 0)
    node T_930 = shr(mulAdd9Out_A, 10)
    node T_931 = shr(mulAdd9Out_A, 9)
    node T_932 = mux(sqrtOp_PA, T_930, T_931)
    node fractR1_A1 = bits(T_932, 14, 0)
    node r1_A1 = cat(UInt<1>("h01"), fractR1_A1)
    node T_936 = bits(exp_PA, 0, 0)
    node T_937 = shl(r1_A1, 1)
    node ER1_A1_sqrt = mux(T_936, T_937, r1_A1)
    node T_939 = or(cyc_A6_sqrt, entering_PA_normalCase_div)
    when T_939 :
      node T_940 = or(zFractR0_A6_sqrt, zFractR0_A4_div)
      fractR0_A <= T_940
      skip
    when cyc_A5_sqrt :
      node T_941 = shr(sqrR0_A5_sqrt, 10)
      hiSqrR0_A_sqrt <= T_941
      skip
    node T_942 = or(cyc_A4_sqrt, cyc_A3)
    when T_942 :
      node T_943 = shr(mulAdd9Out_A, 9)
      node T_944 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_943)
      node T_945 = bits(T_944, 20, 0)
      partNegSigma0_A <= T_945
      skip
    node T_946 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt)
    node T_947 = or(T_946, cyc_A5_sqrt)
    node T_948 = or(T_947, cyc_A4)
    node T_949 = or(T_948, cyc_A3)
    node T_950 = or(T_949, cyc_A2)
    when T_950 :
      node T_951 = not(mulAdd9Out_A)
      node T_952 = shr(T_951, 11)
      node T_954 = mux(entering_PA_normalCase_sqrt, T_952, UInt<1>("h00"))
      node T_955 = or(T_954, zFractR0_A6_sqrt)
      node T_956 = bits(sigB_PA, 43, 35)
      node T_958 = mux(cyc_A4_sqrt, T_956, UInt<1>("h00"))
      node T_959 = or(T_955, T_958)
      node T_960 = bits(zFractB_A4_div, 43, 35)
      node T_961 = or(T_959, T_960)
      node T_962 = or(cyc_A5_sqrt, cyc_A3)
      node T_963 = bits(sigB_PA, 52, 44)
      node T_965 = mux(T_962, T_963, UInt<1>("h00"))
      node T_966 = or(T_961, T_965)
      node T_967 = or(T_966, zSigma0_A2)
      nextMulAdd9A_A <= T_967
      skip
    node T_968 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt)
    node T_969 = or(T_968, cyc_A5_sqrt)
    node T_970 = or(T_969, cyc_A4)
    node T_971 = or(T_970, cyc_A2)
    when T_971 :
      node T_972 = bits(zFractB_A7_sqrt, 50, 42)
      node T_973 = or(T_972, zFractR0_A6_sqrt)
      node T_974 = bits(sqrR0_A5_sqrt, 9, 1)
      node T_976 = mux(cyc_A5_sqrt, T_974, UInt<1>("h00"))
      node T_977 = or(T_973, T_976)
      node T_978 = or(T_977, zFractR0_A4_div)
      node T_979 = bits(hiSqrR0_A_sqrt, 8, 0)
      node T_981 = mux(cyc_A4_sqrt, T_979, UInt<1>("h00"))
      node T_982 = or(T_978, T_981)
      node T_984 = bits(fractR0_A, 8, 1)
      node T_985 = cat(UInt<1>("h01"), T_984)
      node T_987 = mux(cyc_A2, T_985, UInt<1>("h00"))
      node T_988 = or(T_982, T_987)
      nextMulAdd9B_A <= T_988
      skip
    when cyc_A1_sqrt :
      ER1_B_sqrt <= ER1_A1_sqrt
      skip
    node T_989 = or(cyc_A1, cyc_B7_sqrt)
    node T_990 = or(T_989, cyc_B6_div)
    node T_991 = or(T_990, cyc_B4)
    node T_992 = or(T_991, cyc_B3)
    node T_993 = or(T_992, cyc_C6_sqrt)
    node T_994 = or(T_993, cyc_C4)
    node T_995 = or(T_994, cyc_C1)
    io.latchMulAddA_0 <= T_995
    node T_996 = shl(ER1_A1_sqrt, 36)
    node T_998 = mux(cyc_A1_sqrt, T_996, UInt<1>("h00"))
    node T_999 = or(cyc_B7_sqrt, cyc_A1_div)
    node T_1001 = mux(T_999, sigB_PA, UInt<1>("h00"))
    node T_1002 = or(T_998, T_1001)
    node T_1004 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00"))
    node T_1005 = or(T_1002, T_1004)
    node T_1006 = bits(zSigma1_B4, 45, 12)
    node T_1007 = or(T_1005, T_1006)
    node T_1008 = or(cyc_B3, cyc_C6_sqrt)
    node T_1009 = bits(sigXNU_B3_CX, 57, 12)
    node T_1011 = mux(T_1008, T_1009, UInt<1>("h00"))
    node T_1012 = or(T_1007, T_1011)
    node T_1013 = bits(sigXN_C, 57, 25)
    node T_1014 = shl(T_1013, 13)
    node T_1016 = mux(cyc_C4_div, T_1014, UInt<1>("h00"))
    node T_1017 = or(T_1012, T_1016)
    node T_1018 = shl(u_C_sqrt, 15)
    node T_1020 = mux(cyc_C4_sqrt, T_1018, UInt<1>("h00"))
    node T_1021 = or(T_1017, T_1020)
    node T_1023 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00"))
    node T_1024 = or(T_1021, T_1023)
    node T_1025 = or(T_1024, zComplSigT_C1_sqrt)
    io.mulAddA_0 <= T_1025
    node T_1026 = or(cyc_A1, cyc_B7_sqrt)
    node T_1027 = or(T_1026, cyc_B6_sqrt)
    node T_1028 = or(T_1027, cyc_B4)
    node T_1029 = or(T_1028, cyc_C6_sqrt)
    node T_1030 = or(T_1029, cyc_C4)
    node T_1031 = or(T_1030, cyc_C1)
    io.latchMulAddB_0 <= T_1031
    node T_1032 = shl(r1_A1, 36)
    node T_1034 = mux(cyc_A1, T_1032, UInt<1>("h00"))
    node T_1035 = shl(ESqrR1_B_sqrt, 19)
    node T_1037 = mux(cyc_B7_sqrt, T_1035, UInt<1>("h00"))
    node T_1038 = or(T_1034, T_1037)
    node T_1039 = shl(ER1_B_sqrt, 36)
    node T_1041 = mux(cyc_B6_sqrt, T_1039, UInt<1>("h00"))
    node T_1042 = or(T_1038, T_1041)
    node T_1043 = or(T_1042, zSigma1_B4)
    node T_1044 = bits(sqrSigma1_C, 30, 1)
    node T_1046 = mux(cyc_C6_sqrt, T_1044, UInt<1>("h00"))
    node T_1047 = or(T_1043, T_1046)
    node T_1049 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00"))
    node T_1050 = or(T_1047, T_1049)
    node T_1051 = or(T_1050, zComplSigT_C1)
    io.mulAddB_0 <= T_1051
    node T_1052 = or(cyc_A4, cyc_A3_div)
    node T_1053 = or(T_1052, cyc_A1_div)
    node T_1054 = or(T_1053, cyc_B10_sqrt)
    node T_1055 = or(T_1054, cyc_B9_sqrt)
    node T_1056 = or(T_1055, cyc_B7_sqrt)
    node T_1057 = or(T_1056, cyc_B6)
    node T_1058 = or(T_1057, cyc_B5_sqrt)
    node T_1059 = or(T_1058, cyc_B3_sqrt)
    node T_1060 = or(T_1059, cyc_B2_div)
    node T_1061 = or(T_1060, cyc_B1_sqrt)
    node T_1062 = or(T_1061, cyc_C4)
    node T_1063 = or(cyc_A3, cyc_A2_div)
    node T_1064 = or(T_1063, cyc_B9_sqrt)
    node T_1065 = or(T_1064, cyc_B8_sqrt)
    node T_1066 = or(T_1065, cyc_B6)
    node T_1067 = or(T_1066, cyc_B5)
    node T_1068 = or(T_1067, cyc_B4_sqrt)
    node T_1069 = or(T_1068, cyc_B2_sqrt)
    node T_1070 = or(T_1069, cyc_B1_div)
    node T_1071 = or(T_1070, cyc_C6_sqrt)
    node T_1072 = or(T_1071, valid_normalCase_leaving_PB)
    node T_1073 = or(cyc_A2, cyc_A1_div)
    node T_1074 = or(T_1073, cyc_B8_sqrt)
    node T_1075 = or(T_1074, cyc_B7_sqrt)
    node T_1076 = or(T_1075, cyc_B5)
    node T_1077 = or(T_1076, cyc_B4)
    node T_1078 = or(T_1077, cyc_B3_sqrt)
    node T_1079 = or(T_1078, cyc_B1_sqrt)
    node T_1080 = or(T_1079, cyc_C5)
    node T_1081 = or(T_1080, cyc_C2)
    node T_1082 = or(io.latchMulAddA_0, cyc_B6)
    node T_1083 = or(T_1082, cyc_B2_sqrt)
    node T_1084 = cat(T_1062, T_1072)
    node T_1085 = cat(T_1081, T_1083)
    node T_1086 = cat(T_1084, T_1085)
    io.usingMulAdd <= T_1086
    node T_1087 = shl(sigX1_B, 47)
    node T_1089 = mux(cyc_B1, T_1087, UInt<1>("h00"))
    node T_1090 = shl(sigX1_B, 46)
    node T_1092 = mux(cyc_C6_sqrt, T_1090, UInt<1>("h00"))
    node T_1093 = or(T_1089, T_1092)
    node T_1094 = or(cyc_C4_sqrt, cyc_C2)
    node T_1095 = shl(sigXN_C, 47)
    node T_1097 = mux(T_1094, T_1095, UInt<1>("h00"))
    node T_1098 = or(T_1093, T_1097)
    node T_1099 = not(E_E_div)
    node T_1100 = and(cyc_E3_div, T_1099)
    node T_1101 = shl(fractA_0_PC, 53)
    node T_1103 = mux(T_1100, T_1101, UInt<1>("h00"))
    node T_1104 = or(T_1098, T_1103)
    node T_1105 = bits(exp_PC, 0, 0)
    node T_1106 = bits(sigB_PC, 0, 0)
    node T_1108 = cat(T_1106, UInt<1>("h00"))
    node T_1109 = bits(sigB_PC, 1, 1)
    node T_1110 = bits(sigB_PC, 0, 0)
    node T_1111 = xor(T_1109, T_1110)
    node T_1112 = bits(sigB_PC, 0, 0)
    node T_1113 = cat(T_1111, T_1112)
    node T_1114 = mux(T_1105, T_1108, T_1113)
    node T_1115 = not(extraT_E)
    node T_1117 = cat(T_1115, UInt<1>("h00"))
    node T_1118 = xor(T_1114, T_1117)
    node T_1119 = shl(T_1118, 54)
    node T_1121 = mux(cyc_E3_sqrt, T_1119, UInt<1>("h00"))
    node T_1122 = or(T_1104, T_1121)
    io.mulAddC_2 <= T_1122
    node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72)
    node T_1124 = bits(io.mulAddResult_3, 90, 45)
    node T_1125 = not(T_1124)
    node T_1127 = mux(cyc_B4, T_1125, UInt<1>("h00"))
    zSigma1_B4 <= T_1127
    node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47)
    node T_1129 = bits(io.mulAddResult_3, 104, 47)
    sigXNU_B3_CX <= T_1129
    node T_1130 = bits(io.mulAddResult_3, 104, 104)
    node E_C1_div = not(T_1130)
    node T_1132 = not(E_C1_div)
    node T_1133 = and(cyc_C1_div, T_1132)
    node T_1134 = or(T_1133, cyc_C1_sqrt)
    node T_1135 = bits(io.mulAddResult_3, 104, 51)
    node T_1136 = not(T_1135)
    node T_1138 = mux(T_1134, T_1136, UInt<1>("h00"))
    node T_1139 = and(cyc_C1_div, E_C1_div)
    node T_1141 = bits(io.mulAddResult_3, 102, 50)
    node T_1142 = not(T_1141)
    node T_1143 = cat(UInt<1>("h00"), T_1142)
    node T_1145 = mux(T_1139, T_1143, UInt<1>("h00"))
    node T_1146 = or(T_1138, T_1145)
    zComplSigT_C1 <= T_1146
    node T_1147 = bits(io.mulAddResult_3, 104, 51)
    node T_1148 = not(T_1147)
    node T_1150 = mux(cyc_C1_sqrt, T_1148, UInt<1>("h00"))
    zComplSigT_C1_sqrt <= T_1150
    node sigT_C1 = not(zComplSigT_C1)
    node remT_E2 = bits(io.mulAddResult_3, 55, 0)
    when cyc_B8_sqrt :
      ESqrR1_B_sqrt <= ESqrR1_B8_sqrt
      skip
    when cyc_B3 :
      sigX1_B <= sigXNU_B3_CX
      skip
    when cyc_B1 :
      sqrSigma1_C <= sqrSigma1_B1
      skip
    node T_1153 = or(cyc_C6_sqrt, cyc_C5_div)
    node T_1154 = or(T_1153, cyc_C3_sqrt)
    when T_1154 :
      sigXN_C <= sigXNU_B3_CX
      skip
    when cyc_C5_sqrt :
      node T_1155 = bits(sigXNU_B3_CX, 56, 26)
      u_C_sqrt <= T_1155
      skip
    when cyc_C1 :
      E_E_div <= E_C1_div
      node T_1156 = bits(sigT_C1, 53, 1)
      sigT_E <= T_1156
      node T_1157 = bits(sigT_C1, 0, 0)
      extraT_E <= T_1157
      skip
    when cyc_E2 :
      node T_1158 = bits(remT_E2, 55, 55)
      node T_1159 = bits(remT_E2, 53, 53)
      node T_1160 = mux(sqrtOp_PC, T_1158, T_1159)
      isNegRemT_E <= T_1160
      node T_1161 = bits(remT_E2, 53, 0)
      node T_1163 = eq(T_1161, UInt<1>("h00"))
      node T_1164 = not(sqrtOp_PC)
      node T_1165 = bits(remT_E2, 55, 54)
      node T_1167 = eq(T_1165, UInt<1>("h00"))
      node T_1168 = or(T_1164, T_1167)
      node T_1169 = and(T_1163, T_1168)
      trueEqX_E1 <= T_1169
      skip
    node T_1170 = not(sqrtOp_PC)
    node T_1171 = and(T_1170, E_E_div)
    node T_1173 = mux(T_1171, exp_PC, UInt<1>("h00"))
    node T_1174 = not(sqrtOp_PC)
    node T_1175 = not(E_E_div)
    node T_1176 = and(T_1174, T_1175)
    node T_1178 = mux(T_1176, expP1_PC, UInt<1>("h00"))
    node T_1179 = or(T_1173, T_1178)
    node T_1180 = shr(exp_PC, 1)
    node T_1182 = add(T_1180, UInt<12>("h0400"))
    node T_1183 = tail(T_1182, 1)
    node T_1185 = mux(sqrtOp_PC, T_1183, UInt<1>("h00"))
    node sExpX_E = or(T_1179, T_1185)
    node posExpX_E = bits(sExpX_E, 12, 0)
    node T_1188 = not(posExpX_E)
    node T_1190 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_1188)
    node T_1191 = bits(T_1190, 1026, 974)
    node T_1192 = bits(T_1191, 31, 0)
    node T_1195 = shl(UInt<16>("h0ffff"), 16)
    node T_1196 = xor(UInt<32>("h0ffffffff"), T_1195)
    node T_1197 = shr(T_1192, 16)
    node T_1198 = and(T_1197, T_1196)
    node T_1199 = bits(T_1192, 15, 0)
    node T_1200 = shl(T_1199, 16)
    node T_1201 = not(T_1196)
    node T_1202 = and(T_1200, T_1201)
    node T_1203 = or(T_1198, T_1202)
    node T_1204 = bits(T_1196, 23, 0)
    node T_1205 = shl(T_1204, 8)
    node T_1206 = xor(T_1196, T_1205)
    node T_1207 = shr(T_1203, 8)
    node T_1208 = and(T_1207, T_1206)
    node T_1209 = bits(T_1203, 23, 0)
    node T_1210 = shl(T_1209, 8)
    node T_1211 = not(T_1206)
    node T_1212 = and(T_1210, T_1211)
    node T_1213 = or(T_1208, T_1212)
    node T_1214 = bits(T_1206, 27, 0)
    node T_1215 = shl(T_1214, 4)
    node T_1216 = xor(T_1206, T_1215)
    node T_1217 = shr(T_1213, 4)
    node T_1218 = and(T_1217, T_1216)
    node T_1219 = bits(T_1213, 27, 0)
    node T_1220 = shl(T_1219, 4)
    node T_1221 = not(T_1216)
    node T_1222 = and(T_1220, T_1221)
    node T_1223 = or(T_1218, T_1222)
    node T_1224 = bits(T_1216, 29, 0)
    node T_1225 = shl(T_1224, 2)
    node T_1226 = xor(T_1216, T_1225)
    node T_1227 = shr(T_1223, 2)
    node T_1228 = and(T_1227, T_1226)
    node T_1229 = bits(T_1223, 29, 0)
    node T_1230 = shl(T_1229, 2)
    node T_1231 = not(T_1226)
    node T_1232 = and(T_1230, T_1231)
    node T_1233 = or(T_1228, T_1232)
    node T_1234 = bits(T_1226, 30, 0)
    node T_1235 = shl(T_1234, 1)
    node T_1236 = xor(T_1226, T_1235)
    node T_1237 = shr(T_1233, 1)
    node T_1238 = and(T_1237, T_1236)
    node T_1239 = bits(T_1233, 30, 0)
    node T_1240 = shl(T_1239, 1)
    node T_1241 = not(T_1236)
    node T_1242 = and(T_1240, T_1241)
    node T_1243 = or(T_1238, T_1242)
    node T_1244 = bits(T_1191, 52, 32)
    node T_1245 = bits(T_1244, 15, 0)
    node T_1248 = shl(UInt<8>("h0ff"), 8)
    node T_1249 = xor(UInt<16>("h0ffff"), T_1248)
    node T_1250 = shr(T_1245, 8)
    node T_1251 = and(T_1250, T_1249)
    node T_1252 = bits(T_1245, 7, 0)
    node T_1253 = shl(T_1252, 8)
    node T_1254 = not(T_1249)
    node T_1255 = and(T_1253, T_1254)
    node T_1256 = or(T_1251, T_1255)
    node T_1257 = bits(T_1249, 11, 0)
    node T_1258 = shl(T_1257, 4)
    node T_1259 = xor(T_1249, T_1258)
    node T_1260 = shr(T_1256, 4)
    node T_1261 = and(T_1260, T_1259)
    node T_1262 = bits(T_1256, 11, 0)
    node T_1263 = shl(T_1262, 4)
    node T_1264 = not(T_1259)
    node T_1265 = and(T_1263, T_1264)
    node T_1266 = or(T_1261, T_1265)
    node T_1267 = bits(T_1259, 13, 0)
    node T_1268 = shl(T_1267, 2)
    node T_1269 = xor(T_1259, T_1268)
    node T_1270 = shr(T_1266, 2)
    node T_1271 = and(T_1270, T_1269)
    node T_1272 = bits(T_1266, 13, 0)
    node T_1273 = shl(T_1272, 2)
    node T_1274 = not(T_1269)
    node T_1275 = and(T_1273, T_1274)
    node T_1276 = or(T_1271, T_1275)
    node T_1277 = bits(T_1269, 14, 0)
    node T_1278 = shl(T_1277, 1)
    node T_1279 = xor(T_1269, T_1278)
    node T_1280 = shr(T_1276, 1)
    node T_1281 = and(T_1280, T_1279)
    node T_1282 = bits(T_1276, 14, 0)
    node T_1283 = shl(T_1282, 1)
    node T_1284 = not(T_1279)
    node T_1285 = and(T_1283, T_1284)
    node T_1286 = or(T_1281, T_1285)
    node T_1287 = bits(T_1244, 20, 16)
    node T_1288 = bits(T_1287, 3, 0)
    node T_1289 = bits(T_1288, 1, 0)
    node T_1290 = bits(T_1289, 0, 0)
    node T_1291 = bits(T_1289, 1, 1)
    node T_1292 = cat(T_1290, T_1291)
    node T_1293 = bits(T_1288, 3, 2)
    node T_1294 = bits(T_1293, 0, 0)
    node T_1295 = bits(T_1293, 1, 1)
    node T_1296 = cat(T_1294, T_1295)
    node T_1297 = cat(T_1292, T_1296)
    node T_1298 = bits(T_1287, 4, 4)
    node T_1299 = cat(T_1297, T_1298)
    node T_1300 = cat(T_1286, T_1299)
    node roundMask_E = cat(T_1243, T_1300)
    node T_1303 = cat(UInt<1>("h00"), roundMask_E)
    node T_1304 = not(T_1303)
    node T_1306 = cat(roundMask_E, UInt<1>("h01"))
    node incrPosMask_E = and(T_1304, T_1306)
    node T_1308 = shr(incrPosMask_E, 1)
    node T_1309 = and(sigT_E, T_1308)
    node hiRoundPosBitT_E = neq(T_1309, UInt<1>("h00"))
    node T_1312 = shr(roundMask_E, 1)
    node T_1313 = and(sigT_E, T_1312)
    node all0sHiRoundExtraT_E = eq(T_1313, UInt<1>("h00"))
    node T_1316 = not(sigT_E)
    node T_1317 = shr(roundMask_E, 1)
    node T_1318 = and(T_1316, T_1317)
    node all1sHiRoundExtraT_E = eq(T_1318, UInt<1>("h00"))
    node T_1321 = bits(roundMask_E, 0, 0)
    node T_1322 = not(T_1321)
    node T_1323 = or(T_1322, hiRoundPosBitT_E)
    node all1sHiRoundT_E = and(T_1323, all1sHiRoundExtraT_E)
    node T_1326 = add(UInt<54>("h00"), sigT_E)
    node T_1327 = tail(T_1326, 1)
    node T_1328 = add(T_1327, roundMagUp_PC)
    node sigAdjT_E = tail(T_1328, 1)
    node T_1331 = not(roundMask_E)
    node T_1332 = cat(UInt<1>("h01"), T_1331)
    node sigY0_E = and(sigAdjT_E, T_1332)
    node T_1335 = cat(UInt<1>("h00"), roundMask_E)
    node T_1336 = or(sigAdjT_E, T_1335)
    node T_1338 = add(T_1336, UInt<1>("h01"))
    node sigY1_E = tail(T_1338, 1)
    node T_1340 = not(isNegRemT_E)
    node T_1341 = not(trueEqX_E1)
    node T_1342 = and(T_1340, T_1341)
    node trueLtX_E1 = mux(sqrtOp_PC, T_1342, isNegRemT_E)
    node T_1344 = bits(roundMask_E, 0, 0)
    node T_1345 = not(trueLtX_E1)
    node T_1346 = and(T_1344, T_1345)
    node T_1347 = and(T_1346, all1sHiRoundExtraT_E)
    node T_1348 = and(T_1347, extraT_E)
    node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1348)
    node T_1350 = not(trueEqX_E1)
    node T_1351 = not(extraT_E)
    node T_1352 = or(T_1350, T_1351)
    node T_1353 = not(all1sHiRoundExtraT_E)
    node anyRoundExtra_E1 = or(T_1352, T_1353)
    node T_1355 = and(roundingMode_near_even_PC, hiRoundPosBit_E1)
    node T_1356 = not(anyRoundExtra_E1)
    node T_1357 = and(T_1355, T_1356)
    node roundEvenMask_E1 = mux(T_1357, incrPosMask_E, UInt<1>("h00"))
    node T_1360 = and(roundMagDown_PC, extraT_E)
    node T_1361 = not(trueLtX_E1)
    node T_1362 = and(T_1360, T_1361)
    node T_1363 = and(T_1362, all1sHiRoundT_E)
    node T_1364 = not(trueLtX_E1)
    node T_1365 = and(extraT_E, T_1364)
    node T_1366 = not(trueEqX_E1)
    node T_1367 = and(T_1365, T_1366)
    node T_1368 = not(all1sHiRoundT_E)
    node T_1369 = or(T_1367, T_1368)
    node T_1370 = and(roundMagUp_PC, T_1369)
    node T_1371 = or(T_1363, T_1370)
    node T_1372 = not(trueLtX_E1)
    node T_1373 = or(extraT_E, T_1372)
    node T_1374 = bits(roundMask_E, 0, 0)
    node T_1375 = not(T_1374)
    node T_1376 = and(T_1373, T_1375)
    node T_1377 = or(hiRoundPosBitT_E, T_1376)
    node T_1378 = not(trueLtX_E1)
    node T_1379 = and(extraT_E, T_1378)
    node T_1380 = and(T_1379, all1sHiRoundExtraT_E)
    node T_1381 = or(T_1377, T_1380)
    node T_1382 = and(roundingMode_near_even_PC, T_1381)
    node T_1383 = or(T_1371, T_1382)
    node T_1384 = mux(T_1383, sigY1_E, sigY0_E)
    node T_1385 = not(roundEvenMask_E1)
    node sigY_E1 = and(T_1384, T_1385)
    node fractY_E1 = bits(sigY_E1, 51, 0)
    node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1)
    node T_1389 = bits(sigY_E1, 53, 53)
    node T_1390 = not(T_1389)
    node T_1392 = mux(T_1390, sExpX_E, UInt<1>("h00"))
    node T_1393 = bits(sigY_E1, 53, 53)
    node T_1394 = not(sqrtOp_PC)
    node T_1395 = and(T_1393, T_1394)
    node T_1396 = and(T_1395, E_E_div)
    node T_1398 = mux(T_1396, expP1_PC, UInt<1>("h00"))
    node T_1399 = or(T_1392, T_1398)
    node T_1400 = bits(sigY_E1, 53, 53)
    node T_1401 = not(sqrtOp_PC)
    node T_1402 = and(T_1400, T_1401)
    node T_1403 = not(E_E_div)
    node T_1404 = and(T_1402, T_1403)
    node T_1406 = mux(T_1404, expP2_PC, UInt<1>("h00"))
    node T_1407 = or(T_1399, T_1406)
    node T_1408 = bits(sigY_E1, 53, 53)
    node T_1409 = and(T_1408, sqrtOp_PC)
    node T_1410 = shr(expP2_PC, 1)
    node T_1412 = add(T_1410, UInt<12>("h0400"))
    node T_1413 = tail(T_1412, 1)
    node T_1415 = mux(T_1409, T_1413, UInt<1>("h00"))
    node sExpY_E1 = or(T_1407, T_1415)
    node expY_E1 = bits(sExpY_E1, 11, 0)
    node T_1418 = bits(sExpY_E1, 13, 13)
    node T_1419 = not(T_1418)
    node T_1421 = bits(sExpY_E1, 12, 10)
    node T_1422 = leq(UInt<3>("h03"), T_1421)
    node overflowY_E1 = and(T_1419, T_1422)
    node T_1424 = bits(sExpY_E1, 13, 13)
    node T_1425 = bits(sExpY_E1, 12, 0)
    node T_1427 = lt(T_1425, UInt<13>("h03ce"))
    node totalUnderflowY_E1 = or(T_1424, T_1427)
    node T_1430 = leq(posExpX_E, UInt<13>("h0401"))
    node T_1431 = and(T_1430, inexactY_E1)
    node underflowY_E1 = or(totalUnderflowY_E1, T_1431)
    node T_1433 = not(isNaNB_PC)
    node T_1434 = not(isZeroB_PC)
    node T_1435 = and(T_1433, T_1434)
    node T_1436 = and(T_1435, sign_PC)
    node T_1437 = and(isZeroA_PC, isZeroB_PC)
    node T_1438 = and(isInfA_PC, isInfB_PC)
    node T_1439 = or(T_1437, T_1438)
    node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1436, T_1439)
    node T_1441 = not(sqrtOp_PC)
    node T_1442 = and(T_1441, isSigNaNA_PC)
    node T_1443 = or(T_1442, isSigNaNB_PC)
    node invalid_PC = or(T_1443, notSigNaN_invalid_PC)
    node T_1445 = not(sqrtOp_PC)
    node T_1446 = not(isSpecialA_PC)
    node T_1447 = and(T_1445, T_1446)
    node T_1448 = not(isZeroA_PC)
    node T_1449 = and(T_1447, T_1448)
    node infinity_PC = and(T_1449, isZeroB_PC)
    node overflow_E1 = and(normalCase_PC, overflowY_E1)
    node underflow_E1 = and(normalCase_PC, underflowY_E1)
    node T_1453 = or(overflow_E1, underflow_E1)
    node T_1454 = and(normalCase_PC, inexactY_E1)
    node inexact_E1 = or(T_1453, T_1454)
    node T_1456 = or(isZeroA_PC, isInfB_PC)
    node T_1457 = not(roundMagUp_PC)
    node T_1458 = and(totalUnderflowY_E1, T_1457)
    node T_1459 = or(T_1456, T_1458)
    node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1459)
    node T_1461 = and(normalCase_PC, totalUnderflowY_E1)
    node pegMinFiniteMagOut_E1 = and(T_1461, roundMagUp_PC)
    node T_1463 = not(overflowY_roundMagUp_PC)
    node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1463)
    node T_1465 = or(isInfA_PC, isZeroB_PC)
    node T_1466 = and(overflow_E1, overflowY_roundMagUp_PC)
    node T_1467 = or(T_1465, T_1466)
    node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1467)
    node T_1469 = not(sqrtOp_PC)
    node T_1470 = and(T_1469, isNaNA_PC)
    node T_1471 = or(T_1470, isNaNB_PC)
    node isNaNOut_PC = or(T_1471, notSigNaN_invalid_PC)
    node T_1473 = not(isNaNOut_PC)
    node T_1474 = and(isZeroB_PC, sign_PC)
    node T_1475 = mux(sqrtOp_PC, T_1474, sign_PC)
    node signOut_PC = and(T_1473, T_1475)
    node T_1478 = not(UInt<12>("h01ff"))
    node T_1480 = mux(notSpecial_isZeroOut_E1, T_1478, UInt<1>("h00"))
    node T_1481 = not(T_1480)
    node T_1482 = and(expY_E1, T_1481)
    node T_1484 = not(UInt<12>("h03ce"))
    node T_1486 = mux(pegMinFiniteMagOut_E1, T_1484, UInt<1>("h00"))
    node T_1487 = not(T_1486)
    node T_1488 = and(T_1482, T_1487)
    node T_1490 = not(UInt<12>("h0bff"))
    node T_1492 = mux(pegMaxFiniteMagOut_E1, T_1490, UInt<1>("h00"))
    node T_1493 = not(T_1492)
    node T_1494 = and(T_1488, T_1493)
    node T_1496 = not(UInt<12>("h0dff"))
    node T_1498 = mux(notNaN_isInfOut_E1, T_1496, UInt<1>("h00"))
    node T_1499 = not(T_1498)
    node T_1500 = and(T_1494, T_1499)
    node T_1503 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00"))
    node T_1504 = or(T_1500, T_1503)
    node T_1507 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00"))
    node T_1508 = or(T_1504, T_1507)
    node T_1511 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00"))
    node T_1512 = or(T_1508, T_1511)
    node T_1515 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00"))
    node expOut_E1 = or(T_1512, T_1515)
    node T_1517 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1)
    node T_1518 = or(T_1517, isNaNOut_PC)
    node T_1520 = mux(T_1518, UInt<1>("h00"), fractY_E1)
    node T_1522 = sub(UInt<52>("h00"), pegMaxFiniteMagOut_E1)
    node T_1523 = tail(T_1522, 1)
    node T_1524 = or(T_1520, T_1523)
    node T_1525 = shl(isNaNOut_PC, 51)
    node fractOut_E1 = or(T_1524, T_1525)
    node T_1527 = cat(expOut_E1, fractOut_E1)
    node T_1528 = cat(signOut_PC, T_1527)
    io.out <= T_1528
    node T_1529 = cat(invalid_PC, infinity_PC)
    node T_1530 = cat(underflow_E1, inexact_E1)
    node T_1531 = cat(overflow_E1, T_1530)
    node T_1532 = cat(T_1529, T_1531)
    io.exceptionFlags <= T_1532
    
  module Mul54 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>}
    
    io is invalid
    reg val_s1 : UInt<1>, clk
    reg val_s2 : UInt<1>, clk
    reg reg_a_s1 : UInt<54>, clk
    reg reg_b_s1 : UInt<54>, clk
    reg reg_a_s2 : UInt<54>, clk
    reg reg_b_s2 : UInt<54>, clk
    reg reg_result_s3 : UInt<105>, clk
    val_s1 <= io.val_s0
    val_s2 <= val_s1
    when io.val_s0 :
      when io.latch_a_s0 :
        reg_a_s1 <= io.a_s0
        skip
      when io.latch_b_s0 :
        reg_b_s1 <= io.b_s0
        skip
      skip
    when val_s1 :
      reg_a_s2 <= reg_a_s1
      reg_b_s2 <= reg_b_s1
      skip
    when val_s2 :
      node T_25 = mul(reg_a_s2, reg_b_s2)
      node T_26 = bits(T_25, 104, 0)
      node T_27 = add(T_26, io.c_s2)
      node T_28 = tail(T_27, 1)
      reg_result_s3 <= T_28
      skip
    io.result_s3 <= reg_result_s3
    
  module DivSqrtRecF64 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
    
    io is invalid
    inst ds of DivSqrtRecF64_mulAddZ31
    ds.io is invalid
    ds.clk <= clk
    ds.reset <= reset
    io.inReady_div <= ds.io.inReady_div
    io.inReady_sqrt <= ds.io.inReady_sqrt
    ds.io.inValid <= io.inValid
    ds.io.sqrtOp <= io.sqrtOp
    ds.io.a <= io.a
    ds.io.b <= io.b
    ds.io.roundingMode <= io.roundingMode
    io.outValid_div <= ds.io.outValid_div
    io.outValid_sqrt <= ds.io.outValid_sqrt
    io.out <= ds.io.out
    io.exceptionFlags <= ds.io.exceptionFlags
    inst mul of Mul54
    mul.io is invalid
    mul.clk <= clk
    mul.reset <= reset
    node T_17 = bits(ds.io.usingMulAdd, 0, 0)
    mul.io.val_s0 <= T_17
    mul.io.latch_a_s0 <= ds.io.latchMulAddA_0
    mul.io.a_s0 <= ds.io.mulAddA_0
    mul.io.latch_b_s0 <= ds.io.latchMulAddB_0
    mul.io.b_s0 <= ds.io.mulAddB_0
    mul.io.c_s2 <= ds.io.mulAddC_2
    ds.io.mulAddResult_3 <= mul.io.result_s3
    
  module FPU : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}
    
    io is invalid
    reg ex_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    ex_reg_valid <= io.valid
    node req_valid = or(ex_reg_valid, io.cp_req.valid)
    reg ex_reg_inst : UInt<32>, clk
    when io.valid :
      ex_reg_inst <= io.inst
      skip
    node T_202 = eq(ex_reg_valid, UInt<1>("h00"))
    node ex_cp_valid = and(io.cp_req.valid, T_202)
    node T_205 = eq(io.killx, UInt<1>("h00"))
    node T_206 = and(ex_reg_valid, T_205)
    node T_207 = or(T_206, ex_cp_valid)
    reg mem_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    mem_reg_valid <= T_207
    reg mem_reg_inst : UInt<32>, clk
    when ex_reg_valid :
      mem_reg_inst <= ex_reg_inst
      skip
    reg mem_cp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    mem_cp_valid <= ex_cp_valid
    node T_213 = or(io.killm, io.nack_mem)
    node T_215 = eq(mem_cp_valid, UInt<1>("h00"))
    node killm = and(T_213, T_215)
    node T_218 = eq(killm, UInt<1>("h00"))
    node T_219 = or(T_218, mem_cp_valid)
    node T_220 = and(mem_reg_valid, T_219)
    reg wb_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wb_reg_valid <= T_220
    reg wb_cp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    wb_cp_valid <= mem_cp_valid
    inst fp_decoder of FPUDecoder
    fp_decoder.io is invalid
    fp_decoder.clk <= clk
    fp_decoder.reset <= reset
    fp_decoder.io.inst <= io.inst
    wire cp_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}
    cp_ctrl is invalid
    cp_ctrl <- io.cp_req.bits
    io.cp_resp.valid <= UInt<1>("h00")
    io.cp_resp.bits.data <= UInt<1>("h00")
    reg T_264 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk
    when io.valid :
      T_264 <- fp_decoder.io.sigs
      skip
    node ex_ctrl = mux(ex_reg_valid, T_264, cp_ctrl)
    reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk
    when req_valid :
      mem_ctrl <- ex_ctrl
      skip
    reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk
    when mem_reg_valid :
      wb_ctrl <- mem_ctrl
      skip
    reg load_wb : UInt<1>, clk
    load_wb <= io.dmem_resp_val
    node T_337 = eq(io.dmem_resp_type, UInt<3>("h02"))
    node T_338 = eq(io.dmem_resp_type, UInt<3>("h06"))
    node T_339 = or(T_337, T_338)
    reg load_wb_single : UInt<1>, clk
    when io.dmem_resp_val :
      load_wb_single <= T_339
      skip
    reg load_wb_data : UInt<64>, clk
    when io.dmem_resp_val :
      load_wb_data <= io.dmem_resp_data
      skip
    reg load_wb_tag : UInt<5>, clk
    when io.dmem_resp_val :
      load_wb_tag <= io.dmem_resp_tag
      skip
    node T_343 = bits(load_wb_data, 31, 31)
    node T_344 = bits(load_wb_data, 30, 23)
    node T_345 = bits(load_wb_data, 22, 0)
    node T_347 = eq(T_344, UInt<1>("h00"))
    node T_349 = eq(T_345, UInt<1>("h00"))
    node T_350 = and(T_347, T_349)
    node T_351 = shl(T_345, 9)
    node T_352 = bits(T_351, 31, 31)
    node T_354 = bits(T_351, 30, 30)
    node T_356 = bits(T_351, 29, 29)
    node T_358 = bits(T_351, 28, 28)
    node T_360 = bits(T_351, 27, 27)
    node T_362 = bits(T_351, 26, 26)
    node T_364 = bits(T_351, 25, 25)
    node T_366 = bits(T_351, 24, 24)
    node T_368 = bits(T_351, 23, 23)
    node T_370 = bits(T_351, 22, 22)
    node T_372 = bits(T_351, 21, 21)
    node T_374 = bits(T_351, 20, 20)
    node T_376 = bits(T_351, 19, 19)
    node T_378 = bits(T_351, 18, 18)
    node T_380 = bits(T_351, 17, 17)
    node T_382 = bits(T_351, 16, 16)
    node T_384 = bits(T_351, 15, 15)
    node T_386 = bits(T_351, 14, 14)
    node T_388 = bits(T_351, 13, 13)
    node T_390 = bits(T_351, 12, 12)
    node T_392 = bits(T_351, 11, 11)
    node T_394 = bits(T_351, 10, 10)
    node T_396 = bits(T_351, 9, 9)
    node T_398 = bits(T_351, 8, 8)
    node T_400 = bits(T_351, 7, 7)
    node T_402 = bits(T_351, 6, 6)
    node T_404 = bits(T_351, 5, 5)
    node T_406 = bits(T_351, 4, 4)
    node T_408 = bits(T_351, 3, 3)
    node T_410 = bits(T_351, 2, 2)
    node T_412 = bits(T_351, 1, 1)
    node T_413 = shl(T_412, 0)
    node T_414 = mux(T_410, UInt<2>("h02"), T_413)
    node T_415 = mux(T_408, UInt<2>("h03"), T_414)
    node T_416 = mux(T_406, UInt<3>("h04"), T_415)
    node T_417 = mux(T_404, UInt<3>("h05"), T_416)
    node T_418 = mux(T_402, UInt<3>("h06"), T_417)
    node T_419 = mux(T_400, UInt<3>("h07"), T_418)
    node T_420 = mux(T_398, UInt<4>("h08"), T_419)
    node T_421 = mux(T_396, UInt<4>("h09"), T_420)
    node T_422 = mux(T_394, UInt<4>("h0a"), T_421)
    node T_423 = mux(T_392, UInt<4>("h0b"), T_422)
    node T_424 = mux(T_390, UInt<4>("h0c"), T_423)
    node T_425 = mux(T_388, UInt<4>("h0d"), T_424)
    node T_426 = mux(T_386, UInt<4>("h0e"), T_425)
    node T_427 = mux(T_384, UInt<4>("h0f"), T_426)
    node T_428 = mux(T_382, UInt<5>("h010"), T_427)
    node T_429 = mux(T_380, UInt<5>("h011"), T_428)
    node T_430 = mux(T_378, UInt<5>("h012"), T_429)
    node T_431 = mux(T_376, UInt<5>("h013"), T_430)
    node T_432 = mux(T_374, UInt<5>("h014"), T_431)
    node T_433 = mux(T_372, UInt<5>("h015"), T_432)
    node T_434 = mux(T_370, UInt<5>("h016"), T_433)
    node T_435 = mux(T_368, UInt<5>("h017"), T_434)
    node T_436 = mux(T_366, UInt<5>("h018"), T_435)
    node T_437 = mux(T_364, UInt<5>("h019"), T_436)
    node T_438 = mux(T_362, UInt<5>("h01a"), T_437)
    node T_439 = mux(T_360, UInt<5>("h01b"), T_438)
    node T_440 = mux(T_358, UInt<5>("h01c"), T_439)
    node T_441 = mux(T_356, UInt<5>("h01d"), T_440)
    node T_442 = mux(T_354, UInt<5>("h01e"), T_441)
    node T_443 = mux(T_352, UInt<5>("h01f"), T_442)
    node T_444 = not(T_443)
    node T_445 = dshl(T_345, T_444)
    node T_446 = bits(T_445, 21, 0)
    node T_448 = cat(T_446, UInt<1>("h00"))
    node T_451 = sub(UInt<9>("h00"), UInt<1>("h01"))
    node T_452 = tail(T_451, 1)
    node T_453 = xor(T_444, T_452)
    node T_454 = mux(T_347, T_453, T_344)
    node T_458 = mux(T_347, UInt<2>("h02"), UInt<1>("h01"))
    node T_459 = or(UInt<8>("h080"), T_458)
    node T_460 = add(T_454, T_459)
    node T_461 = tail(T_460, 1)
    node T_462 = bits(T_461, 8, 7)
    node T_464 = eq(T_462, UInt<2>("h03"))
    node T_466 = eq(T_349, UInt<1>("h00"))
    node T_467 = and(T_464, T_466)
    node T_469 = sub(UInt<3>("h00"), T_350)
    node T_470 = tail(T_469, 1)
    node T_471 = shl(T_470, 6)
    node T_472 = not(T_471)
    node T_473 = and(T_461, T_472)
    node T_474 = shl(T_467, 6)
    node T_475 = or(T_473, T_474)
    node T_476 = mux(T_347, T_448, T_345)
    node T_477 = cat(T_475, T_476)
    node rec_s = cat(T_343, T_477)
    node T_479 = bits(load_wb_data, 63, 63)
    node T_480 = bits(load_wb_data, 62, 52)
    node T_481 = bits(load_wb_data, 51, 0)
    node T_483 = eq(T_480, UInt<1>("h00"))
    node T_485 = eq(T_481, UInt<1>("h00"))
    node T_486 = and(T_483, T_485)
    node T_487 = shl(T_481, 12)
    node T_488 = bits(T_487, 63, 63)
    node T_490 = bits(T_487, 62, 62)
    node T_492 = bits(T_487, 61, 61)
    node T_494 = bits(T_487, 60, 60)
    node T_496 = bits(T_487, 59, 59)
    node T_498 = bits(T_487, 58, 58)
    node T_500 = bits(T_487, 57, 57)
    node T_502 = bits(T_487, 56, 56)
    node T_504 = bits(T_487, 55, 55)
    node T_506 = bits(T_487, 54, 54)
    node T_508 = bits(T_487, 53, 53)
    node T_510 = bits(T_487, 52, 52)
    node T_512 = bits(T_487, 51, 51)
    node T_514 = bits(T_487, 50, 50)
    node T_516 = bits(T_487, 49, 49)
    node T_518 = bits(T_487, 48, 48)
    node T_520 = bits(T_487, 47, 47)
    node T_522 = bits(T_487, 46, 46)
    node T_524 = bits(T_487, 45, 45)
    node T_526 = bits(T_487, 44, 44)
    node T_528 = bits(T_487, 43, 43)
    node T_530 = bits(T_487, 42, 42)
    node T_532 = bits(T_487, 41, 41)
    node T_534 = bits(T_487, 40, 40)
    node T_536 = bits(T_487, 39, 39)
    node T_538 = bits(T_487, 38, 38)
    node T_540 = bits(T_487, 37, 37)
    node T_542 = bits(T_487, 36, 36)
    node T_544 = bits(T_487, 35, 35)
    node T_546 = bits(T_487, 34, 34)
    node T_548 = bits(T_487, 33, 33)
    node T_550 = bits(T_487, 32, 32)
    node T_552 = bits(T_487, 31, 31)
    node T_554 = bits(T_487, 30, 30)
    node T_556 = bits(T_487, 29, 29)
    node T_558 = bits(T_487, 28, 28)
    node T_560 = bits(T_487, 27, 27)
    node T_562 = bits(T_487, 26, 26)
    node T_564 = bits(T_487, 25, 25)
    node T_566 = bits(T_487, 24, 24)
    node T_568 = bits(T_487, 23, 23)
    node T_570 = bits(T_487, 22, 22)
    node T_572 = bits(T_487, 21, 21)
    node T_574 = bits(T_487, 20, 20)
    node T_576 = bits(T_487, 19, 19)
    node T_578 = bits(T_487, 18, 18)
    node T_580 = bits(T_487, 17, 17)
    node T_582 = bits(T_487, 16, 16)
    node T_584 = bits(T_487, 15, 15)
    node T_586 = bits(T_487, 14, 14)
    node T_588 = bits(T_487, 13, 13)
    node T_590 = bits(T_487, 12, 12)
    node T_592 = bits(T_487, 11, 11)
    node T_594 = bits(T_487, 10, 10)
    node T_596 = bits(T_487, 9, 9)
    node T_598 = bits(T_487, 8, 8)
    node T_600 = bits(T_487, 7, 7)
    node T_602 = bits(T_487, 6, 6)
    node T_604 = bits(T_487, 5, 5)
    node T_606 = bits(T_487, 4, 4)
    node T_608 = bits(T_487, 3, 3)
    node T_610 = bits(T_487, 2, 2)
    node T_612 = bits(T_487, 1, 1)
    node T_613 = shl(T_612, 0)
    node T_614 = mux(T_610, UInt<2>("h02"), T_613)
    node T_615 = mux(T_608, UInt<2>("h03"), T_614)
    node T_616 = mux(T_606, UInt<3>("h04"), T_615)
    node T_617 = mux(T_604, UInt<3>("h05"), T_616)
    node T_618 = mux(T_602, UInt<3>("h06"), T_617)
    node T_619 = mux(T_600, UInt<3>("h07"), T_618)
    node T_620 = mux(T_598, UInt<4>("h08"), T_619)
    node T_621 = mux(T_596, UInt<4>("h09"), T_620)
    node T_622 = mux(T_594, UInt<4>("h0a"), T_621)
    node T_623 = mux(T_592, UInt<4>("h0b"), T_622)
    node T_624 = mux(T_590, UInt<4>("h0c"), T_623)
    node T_625 = mux(T_588, UInt<4>("h0d"), T_624)
    node T_626 = mux(T_586, UInt<4>("h0e"), T_625)
    node T_627 = mux(T_584, UInt<4>("h0f"), T_626)
    node T_628 = mux(T_582, UInt<5>("h010"), T_627)
    node T_629 = mux(T_580, UInt<5>("h011"), T_628)
    node T_630 = mux(T_578, UInt<5>("h012"), T_629)
    node T_631 = mux(T_576, UInt<5>("h013"), T_630)
    node T_632 = mux(T_574, UInt<5>("h014"), T_631)
    node T_633 = mux(T_572, UInt<5>("h015"), T_632)
    node T_634 = mux(T_570, UInt<5>("h016"), T_633)
    node T_635 = mux(T_568, UInt<5>("h017"), T_634)
    node T_636 = mux(T_566, UInt<5>("h018"), T_635)
    node T_637 = mux(T_564, UInt<5>("h019"), T_636)
    node T_638 = mux(T_562, UInt<5>("h01a"), T_637)
    node T_639 = mux(T_560, UInt<5>("h01b"), T_638)
    node T_640 = mux(T_558, UInt<5>("h01c"), T_639)
    node T_641 = mux(T_556, UInt<5>("h01d"), T_640)
    node T_642 = mux(T_554, UInt<5>("h01e"), T_641)
    node T_643 = mux(T_552, UInt<5>("h01f"), T_642)
    node T_644 = mux(T_550, UInt<6>("h020"), T_643)
    node T_645 = mux(T_548, UInt<6>("h021"), T_644)
    node T_646 = mux(T_546, UInt<6>("h022"), T_645)
    node T_647 = mux(T_544, UInt<6>("h023"), T_646)
    node T_648 = mux(T_542, UInt<6>("h024"), T_647)
    node T_649 = mux(T_540, UInt<6>("h025"), T_648)
    node T_650 = mux(T_538, UInt<6>("h026"), T_649)
    node T_651 = mux(T_536, UInt<6>("h027"), T_650)
    node T_652 = mux(T_534, UInt<6>("h028"), T_651)
    node T_653 = mux(T_532, UInt<6>("h029"), T_652)
    node T_654 = mux(T_530, UInt<6>("h02a"), T_653)
    node T_655 = mux(T_528, UInt<6>("h02b"), T_654)
    node T_656 = mux(T_526, UInt<6>("h02c"), T_655)
    node T_657 = mux(T_524, UInt<6>("h02d"), T_656)
    node T_658 = mux(T_522, UInt<6>("h02e"), T_657)
    node T_659 = mux(T_520, UInt<6>("h02f"), T_658)
    node T_660 = mux(T_518, UInt<6>("h030"), T_659)
    node T_661 = mux(T_516, UInt<6>("h031"), T_660)
    node T_662 = mux(T_514, UInt<6>("h032"), T_661)
    node T_663 = mux(T_512, UInt<6>("h033"), T_662)
    node T_664 = mux(T_510, UInt<6>("h034"), T_663)
    node T_665 = mux(T_508, UInt<6>("h035"), T_664)
    node T_666 = mux(T_506, UInt<6>("h036"), T_665)
    node T_667 = mux(T_504, UInt<6>("h037"), T_666)
    node T_668 = mux(T_502, UInt<6>("h038"), T_667)
    node T_669 = mux(T_500, UInt<6>("h039"), T_668)
    node T_670 = mux(T_498, UInt<6>("h03a"), T_669)
    node T_671 = mux(T_496, UInt<6>("h03b"), T_670)
    node T_672 = mux(T_494, UInt<6>("h03c"), T_671)
    node T_673 = mux(T_492, UInt<6>("h03d"), T_672)
    node T_674 = mux(T_490, UInt<6>("h03e"), T_673)
    node T_675 = mux(T_488, UInt<6>("h03f"), T_674)
    node T_676 = not(T_675)
    node T_677 = dshl(T_481, T_676)
    node T_678 = bits(T_677, 50, 0)
    node T_680 = cat(T_678, UInt<1>("h00"))
    node T_683 = sub(UInt<12>("h00"), UInt<1>("h01"))
    node T_684 = tail(T_683, 1)
    node T_685 = xor(T_676, T_684)
    node T_686 = mux(T_483, T_685, T_480)
    node T_690 = mux(T_483, UInt<2>("h02"), UInt<1>("h01"))
    node T_691 = or(UInt<11>("h0400"), T_690)
    node T_692 = add(T_686, T_691)
    node T_693 = tail(T_692, 1)
    node T_694 = bits(T_693, 11, 10)
    node T_696 = eq(T_694, UInt<2>("h03"))
    node T_698 = eq(T_485, UInt<1>("h00"))
    node T_699 = and(T_696, T_698)
    node T_701 = sub(UInt<3>("h00"), T_486)
    node T_702 = tail(T_701, 1)
    node T_703 = shl(T_702, 9)
    node T_704 = not(T_703)
    node T_705 = and(T_693, T_704)
    node T_706 = shl(T_699, 9)
    node T_707 = or(T_705, T_706)
    node T_708 = mux(T_483, T_680, T_481)
    node T_709 = cat(T_707, T_708)
    node rec_d = cat(T_479, T_709)
    node T_712 = asUInt(asSInt(UInt<32>("h0ffffffff")))
    node T_713 = cat(T_712, rec_s)
    node load_wb_data_recoded = mux(load_wb_single, T_713, rec_d)
    cmem regfile : UInt<65>[32]
    when load_wb :
      infer mport T_718 = regfile[load_wb_tag], clk
      T_718 <= load_wb_data_recoded
      skip
    reg ex_ra1 : UInt, clk
    reg ex_ra2 : UInt, clk
    reg ex_ra3 : UInt, clk
    when io.valid :
      when fp_decoder.io.sigs.ren1 :
        node T_726 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00"))
        when T_726 :
          node T_727 = bits(io.inst, 19, 15)
          ex_ra1 <= T_727
          skip
        when fp_decoder.io.sigs.swap12 :
          node T_728 = bits(io.inst, 19, 15)
          ex_ra2 <= T_728
          skip
        skip
      when fp_decoder.io.sigs.ren2 :
        when fp_decoder.io.sigs.swap12 :
          node T_729 = bits(io.inst, 24, 20)
          ex_ra1 <= T_729
          skip
        when fp_decoder.io.sigs.swap23 :
          node T_730 = bits(io.inst, 24, 20)
          ex_ra3 <= T_730
          skip
        node T_732 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00"))
        node T_734 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00"))
        node T_735 = and(T_732, T_734)
        when T_735 :
          node T_736 = bits(io.inst, 24, 20)
          ex_ra2 <= T_736
          skip
        skip
      when fp_decoder.io.sigs.ren3 :
        node T_737 = bits(io.inst, 31, 27)
        ex_ra3 <= T_737
        skip
      skip
    infer mport ex_rs1 = regfile[ex_ra1], clk
    infer mport ex_rs2 = regfile[ex_ra2], clk
    infer mport ex_rs3 = regfile[ex_ra3], clk
    node T_741 = bits(ex_reg_inst, 14, 12)
    node T_743 = eq(T_741, UInt<3>("h07"))
    node T_744 = bits(ex_reg_inst, 14, 12)
    node ex_rm = mux(T_743, io.fcsr_rm, T_744)
    node cp_rs2 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in3, io.cp_req.bits.in2)
    node cp_rs3 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in2, io.cp_req.bits.in3)
    wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}
    req is invalid
    req <- ex_ctrl
    node T_794 = mux(ex_reg_valid, ex_rm, io.cp_req.bits.rm)
    req.rm <= T_794
    node T_795 = mux(ex_reg_valid, ex_rs1, io.cp_req.bits.in1)
    req.in1 <= T_795
    node T_796 = mux(ex_reg_valid, ex_rs2, cp_rs2)
    req.in2 <= T_796
    node T_797 = mux(ex_reg_valid, ex_rs3, cp_rs3)
    req.in3 <= T_797
    node T_798 = bits(ex_reg_inst, 21, 20)
    node T_799 = mux(ex_reg_valid, T_798, io.cp_req.bits.typ)
    req.typ <= T_799
    inst sfma of FPUFMAPipe
    sfma.io is invalid
    sfma.clk <= clk
    sfma.reset <= reset
    node T_801 = and(req_valid, ex_ctrl.fma)
    node T_802 = and(T_801, ex_ctrl.single)
    sfma.io.in.valid <= T_802
    sfma.io.in.bits <- req
    inst dfma of FPUFMAPipe_113
    dfma.io is invalid
    dfma.clk <= clk
    dfma.reset <= reset
    node T_804 = and(req_valid, ex_ctrl.fma)
    node T_806 = eq(ex_ctrl.single, UInt<1>("h00"))
    node T_807 = and(T_804, T_806)
    dfma.io.in.valid <= T_807
    dfma.io.in.bits <- req
    inst fpiu of FPToInt
    fpiu.io is invalid
    fpiu.clk <= clk
    fpiu.reset <= reset
    node T_809 = or(ex_ctrl.toint, ex_ctrl.div)
    node T_810 = or(T_809, ex_ctrl.sqrt)
    node T_813 = and(ex_ctrl.cmd, UInt<4>("h0d"))
    node T_814 = eq(UInt<3>("h05"), T_813)
    node T_815 = or(T_810, T_814)
    node T_816 = and(req_valid, T_815)
    fpiu.io.in.valid <= T_816
    fpiu.io.in.bits <- req
    io.store_data <= fpiu.io.out.bits.store
    io.toint_data <= fpiu.io.out.bits.toint
    node T_817 = and(fpiu.io.out.valid, mem_cp_valid)
    node T_818 = and(T_817, mem_ctrl.toint)
    when T_818 :
      io.cp_resp.bits.data <= fpiu.io.out.bits.toint
      io.cp_resp.valid <= UInt<1>("h01")
      skip
    inst ifpu of IntToFP
    ifpu.io is invalid
    ifpu.clk <= clk
    ifpu.reset <= reset
    node T_821 = and(req_valid, ex_ctrl.fromint)
    ifpu.io.in.valid <= T_821
    ifpu.io.in.bits <- req
    node T_822 = mux(ex_reg_valid, io.fromint_data, io.cp_req.bits.in1)
    ifpu.io.in.bits.in1 <= T_822
    inst fpmu of FPToFP
    fpmu.io is invalid
    fpmu.clk <= clk
    fpmu.reset <= reset
    node T_824 = and(req_valid, ex_ctrl.fastpipe)
    fpmu.io.in.valid <= T_824
    fpmu.io.in.bits <- req
    fpmu.io.lt <= fpiu.io.out.bits.lt
    reg divSqrt_wen : UInt<1>, clk
    divSqrt_wen <= UInt<1>("h00")
    wire divSqrt_inReady : UInt<1>
    divSqrt_inReady <= UInt<1>("h00")
    reg divSqrt_waddr : UInt, clk
    wire divSqrt_wdata : UInt
    divSqrt_wdata is invalid
    wire divSqrt_flags : UInt
    divSqrt_flags is invalid
    reg divSqrt_in_flight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg divSqrt_killed : UInt<1>, clk
    node T_841 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00"))
    node T_844 = mux(mem_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00"))
    node T_845 = and(mem_ctrl.fma, mem_ctrl.single)
    node T_848 = mux(T_845, UInt<1>("h01"), UInt<1>("h00"))
    node T_850 = eq(mem_ctrl.single, UInt<1>("h00"))
    node T_851 = and(mem_ctrl.fma, T_850)
    node T_854 = mux(T_851, UInt<2>("h02"), UInt<1>("h00"))
    node T_855 = or(T_841, T_844)
    node T_856 = or(T_855, T_848)
    node memLatencyMask = or(T_856, T_854)
    reg wen : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
    reg winfo : UInt[2], clk
    node T_872 = or(mem_ctrl.fma, mem_ctrl.fastpipe)
    node T_873 = or(T_872, mem_ctrl.fromint)
    node mem_wen = and(mem_reg_valid, T_873)
    node T_877 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00"))
    node T_880 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00"))
    node T_881 = and(ex_ctrl.fma, ex_ctrl.single)
    node T_884 = mux(T_881, UInt<2>("h02"), UInt<1>("h00"))
    node T_886 = eq(ex_ctrl.single, UInt<1>("h00"))
    node T_887 = and(ex_ctrl.fma, T_886)
    node T_890 = mux(T_887, UInt<3>("h04"), UInt<1>("h00"))
    node T_891 = or(T_877, T_880)
    node T_892 = or(T_891, T_884)
    node T_893 = or(T_892, T_890)
    node T_894 = and(memLatencyMask, T_893)
    node T_896 = neq(T_894, UInt<1>("h00"))
    node T_897 = and(mem_wen, T_896)
    node T_900 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00"))
    node T_903 = mux(ex_ctrl.fromint, UInt<4>("h08"), UInt<1>("h00"))
    node T_904 = and(ex_ctrl.fma, ex_ctrl.single)
    node T_907 = mux(T_904, UInt<3>("h04"), UInt<1>("h00"))
    node T_909 = eq(ex_ctrl.single, UInt<1>("h00"))
    node T_910 = and(ex_ctrl.fma, T_909)
    node T_913 = mux(T_910, UInt<4>("h08"), UInt<1>("h00"))
    node T_914 = or(T_900, T_903)
    node T_915 = or(T_914, T_907)
    node T_916 = or(T_915, T_913)
    node T_917 = and(wen, T_916)
    node T_919 = neq(T_917, UInt<1>("h00"))
    node T_920 = or(T_897, T_919)
    reg write_port_busy : UInt<1>, clk
    when req_valid :
      write_port_busy <= T_920
      skip
    node T_924 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00"))
    node T_927 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00"))
    node T_928 = and(mem_ctrl.fma, mem_ctrl.single)
    node T_931 = mux(T_928, UInt<2>("h02"), UInt<1>("h00"))
    node T_933 = eq(mem_ctrl.single, UInt<1>("h00"))
    node T_934 = and(mem_ctrl.fma, T_933)
    node T_937 = mux(T_934, UInt<2>("h03"), UInt<1>("h00"))
    node T_938 = or(T_924, T_927)
    node T_939 = or(T_938, T_931)
    node T_940 = or(T_939, T_937)
    node T_941 = bits(mem_reg_inst, 11, 7)
    node T_942 = cat(mem_cp_valid, T_940)
    node T_943 = cat(mem_ctrl.single, T_941)
    node mem_winfo = cat(T_942, T_943)
    node T_945 = bits(wen, 1, 1)
    when T_945 :
      winfo[0] <= winfo[1]
      skip
    node T_946 = shr(wen, 1)
    wen <= T_946
    when mem_wen :
      node T_948 = eq(killm, UInt<1>("h00"))
      when T_948 :
        node T_949 = shr(wen, 1)
        node T_950 = or(T_949, memLatencyMask)
        wen <= T_950
        skip
      node T_952 = eq(write_port_busy, UInt<1>("h00"))
      node T_953 = bits(memLatencyMask, 0, 0)
      node T_954 = and(T_952, T_953)
      when T_954 :
        winfo[0] <= mem_winfo
        skip
      node T_956 = eq(write_port_busy, UInt<1>("h00"))
      node T_957 = bits(memLatencyMask, 1, 1)
      node T_958 = and(T_956, T_957)
      when T_958 :
        winfo[1] <= mem_winfo
        skip
      skip
    node T_959 = bits(winfo[0], 4, 0)
    node waddr = mux(divSqrt_wen, divSqrt_waddr, T_959)
    node wsrc = shr(winfo[0], 6)
    node wcp = bits(winfo[0], 8, 8)
    wire T_964 : UInt<65>[4]
    T_964[0] <= fpmu.io.out.bits.data
    T_964[1] <= ifpu.io.out.bits.data
    T_964[2] <= sfma.io.out.bits.data
    T_964[3] <= dfma.io.out.bits.data
    node wdata = mux(divSqrt_wen, divSqrt_wdata, T_964[wsrc])
    wire T_973 : UInt<5>[4]
    T_973[0] <= fpmu.io.out.bits.exc
    T_973[1] <= ifpu.io.out.bits.exc
    T_973[2] <= sfma.io.out.bits.exc
    T_973[3] <= dfma.io.out.bits.exc
    node T_981 = eq(wcp, UInt<1>("h00"))
    node T_982 = bits(wen, 0, 0)
    node T_983 = and(T_981, T_982)
    node T_984 = or(T_983, divSqrt_wen)
    when T_984 :
      infer mport T_985 = regfile[waddr], clk
      T_985 <= wdata
      skip
    node T_986 = bits(wen, 0, 0)
    node T_987 = and(wcp, T_986)
    when T_987 :
      io.cp_resp.bits.data <= wdata
      io.cp_resp.valid <= UInt<1>("h01")
      skip
    node T_990 = eq(ex_reg_valid, UInt<1>("h00"))
    io.cp_req.ready <= T_990
    node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint)
    reg wb_toint_exc : UInt<5>, clk
    when mem_ctrl.toint :
      wb_toint_exc <= fpiu.io.out.bits.exc
      skip
    node T_993 = or(wb_toint_valid, divSqrt_wen)
    node T_994 = bits(wen, 0, 0)
    node T_995 = or(T_993, T_994)
    io.fcsr_flags.valid <= T_995
    node T_997 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00"))
    node T_999 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00"))
    node T_1000 = or(T_997, T_999)
    node T_1001 = bits(wen, 0, 0)
    node T_1003 = mux(T_1001, T_973[wsrc], UInt<1>("h00"))
    node T_1004 = or(T_1000, T_1003)
    io.fcsr_flags.bits <= T_1004
    node T_1005 = or(mem_ctrl.div, mem_ctrl.sqrt)
    node T_1006 = and(mem_reg_valid, T_1005)
    node T_1008 = eq(divSqrt_inReady, UInt<1>("h00"))
    node T_1010 = neq(wen, UInt<1>("h00"))
    node T_1011 = or(T_1008, T_1010)
    node units_busy = and(T_1006, T_1011)
    node T_1013 = and(ex_reg_valid, ex_ctrl.wflags)
    node T_1014 = and(mem_reg_valid, mem_ctrl.wflags)
    node T_1015 = or(T_1013, T_1014)
    node T_1016 = and(wb_reg_valid, wb_ctrl.toint)
    node T_1017 = or(T_1015, T_1016)
    node T_1019 = neq(wen, UInt<1>("h00"))
    node T_1020 = or(T_1017, T_1019)
    node T_1021 = or(T_1020, divSqrt_in_flight)
    node T_1023 = eq(T_1021, UInt<1>("h00"))
    io.fcsr_rdy <= T_1023
    node T_1024 = or(units_busy, write_port_busy)
    node T_1025 = or(T_1024, divSqrt_in_flight)
    io.nack_mem <= T_1025
    io.dec <- fp_decoder.io.sigs
    node T_1027 = eq(wb_cp_valid, UInt<1>("h00"))
    node T_1028 = and(wb_reg_valid, T_1027)
    node T_1030 = or(UInt<1>("h00"), mem_ctrl.div)
    node T_1031 = or(T_1030, mem_ctrl.sqrt)
    reg T_1032 : UInt<1>, clk
    T_1032 <= T_1031
    node T_1033 = and(T_1028, T_1032)
    io.sboard_set <= T_1033
    node T_1035 = eq(wb_cp_valid, UInt<1>("h00"))
    node T_1036 = bits(wen, 0, 0)
    node T_1038 = and(T_1036, UInt<1>("h00"))
    node T_1039 = or(divSqrt_wen, T_1038)
    node T_1040 = and(T_1035, T_1039)
    io.sboard_clr <= T_1040
    io.sboard_clra <= waddr
    node T_1041 = bits(ex_rm, 2, 2)
    node T_1042 = and(T_1041, ex_ctrl.round)
    io.illegal_rm <= T_1042
    divSqrt_wdata <= UInt<1>("h00")
    divSqrt_flags <= UInt<1>("h00")
    reg T_1046 : UInt<1>, clk
    reg T_1048 : UInt, clk
    reg T_1050 : UInt, clk
    reg T_1052 : UInt, clk
    inst T_1053 of DivSqrtRecF64
    T_1053.io is invalid
    T_1053.clk <= clk
    T_1053.reset <= reset
    node T_1054 = mux(T_1053.io.sqrtOp, T_1053.io.inReady_sqrt, T_1053.io.inReady_div)
    divSqrt_inReady <= T_1054
    node T_1055 = or(T_1053.io.outValid_div, T_1053.io.outValid_sqrt)
    node T_1056 = or(mem_ctrl.div, mem_ctrl.sqrt)
    node T_1057 = and(mem_reg_valid, T_1056)
    node T_1059 = eq(divSqrt_in_flight, UInt<1>("h00"))
    node T_1060 = and(T_1057, T_1059)
    T_1053.io.inValid <= T_1060
    T_1053.io.sqrtOp <= mem_ctrl.sqrt
    T_1053.io.a <= fpiu.io.as_double.in1
    T_1053.io.b <= fpiu.io.as_double.in2
    T_1053.io.roundingMode <= fpiu.io.as_double.rm
    node T_1061 = and(T_1053.io.inValid, divSqrt_inReady)
    when T_1061 :
      divSqrt_in_flight <= UInt<1>("h01")
      divSqrt_killed <= killm
      T_1046 <= mem_ctrl.single
      node T_1063 = bits(mem_reg_inst, 11, 7)
      divSqrt_waddr <= T_1063
      T_1048 <= T_1053.io.roundingMode
      skip
    when T_1055 :
      node T_1065 = eq(divSqrt_killed, UInt<1>("h00"))
      divSqrt_wen <= T_1065
      T_1052 <= T_1053.io.out
      divSqrt_in_flight <= UInt<1>("h00")
      T_1050 <= T_1053.io.exceptionFlags
      skip
    inst T_1067 of RecFNToRecFN_121
    T_1067.io is invalid
    T_1067.clk <= clk
    T_1067.reset <= reset
    T_1067.io.in <= T_1052
    T_1067.io.roundingMode <= ex_rm
    node T_1068 = mux(T_1046, T_1067.io.out, T_1052)
    divSqrt_wdata <= T_1068
    node T_1070 = mux(T_1046, T_1067.io.exceptionFlags, UInt<1>("h00"))
    node T_1071 = or(T_1050, T_1070)
    divSqrt_flags <= T_1071
    
  module RocketTile : 
    input clk : Clock
    input reset : UInt<1>
    output io : {cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}
    
    io is invalid
    inst core of Rocket
    core.io is invalid
    core.clk <= clk
    core.reset <= reset
    inst icache of Frontend
    icache.io is invalid
    icache.clk <= clk
    icache.reset <= reset
    inst dcache of HellaCache
    dcache.io is invalid
    dcache.clk <= clk
    dcache.reset <= reset
    inst ptw of PTW
    ptw.io is invalid
    ptw.clk <= clk
    ptw.reset <= reset
    dcache.io.cpu.invalidate_lr <= core.io.dmem.invalidate_lr
    inst dcArb of HellaCacheArbiter
    dcArb.io is invalid
    dcArb.clk <= clk
    dcArb.reset <= reset
    dcArb.io.requestor[0] <- ptw.io.mem
    dcArb.io.requestor[1] <- core.io.dmem
    dcache.io.cpu <- dcArb.io.mem
    ptw.io.requestor[0] <- icache.io.ptw
    ptw.io.requestor[1] <- dcache.io.ptw
    io.host <- core.io.host
    icache.io.cpu <- core.io.imem
    core.io.ptw <- ptw.io.dpath
    inst T_3284 of FPU
    T_3284.io is invalid
    T_3284.clk <= clk
    T_3284.reset <= reset
    core.io.fpu <- T_3284.io
    io.cached[0] <- dcache.io.mem
    io.uncached[0] <- icache.io.mem
    T_3284.io.cp_req.valid <= UInt<1>("h00")
    T_3284.io.cp_resp.ready <= UInt<1>("h00")
    io.dma.req.valid <= UInt<1>("h00")
    io.dma.resp.ready <= UInt<1>("h00")
    
  module Queue_124 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, count : UInt<2>}
    
    io is invalid
    cmem ram : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}[2]
    reg T_53 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_55 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_53, T_55)
    node T_60 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_60)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_66 = and(io.enq.ready, io.enq.valid)
    node T_68 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_66, T_68)
    node T_70 = and(io.deq.ready, io.deq.valid)
    node T_72 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_70, T_72)
    when do_enq :
      infer mport T_74 = ram[T_53], clk
      T_74 <- io.enq.bits
      node T_79 = eq(T_53, UInt<1>("h01"))
      node T_81 = and(UInt<1>("h00"), T_79)
      node T_84 = add(T_53, UInt<1>("h01"))
      node T_85 = tail(T_84, 1)
      node T_86 = mux(T_81, UInt<1>("h00"), T_85)
      T_53 <= T_86
      skip
    when do_deq :
      node T_88 = eq(T_55, UInt<1>("h01"))
      node T_90 = and(UInt<1>("h00"), T_88)
      node T_93 = add(T_55, UInt<1>("h01"))
      node T_94 = tail(T_93, 1)
      node T_95 = mux(T_90, UInt<1>("h00"), T_94)
      T_55 <= T_95
      skip
    node T_96 = neq(do_enq, do_deq)
    when T_96 :
      maybe_full <= do_enq
      skip
    node T_98 = eq(empty, UInt<1>("h00"))
    node T_100 = and(UInt<1>("h00"), io.enq.valid)
    node T_101 = or(T_98, T_100)
    io.deq.valid <= T_101
    node T_103 = eq(full, UInt<1>("h00"))
    node T_105 = and(UInt<1>("h00"), io.deq.ready)
    node T_106 = or(T_103, T_105)
    io.enq.ready <= T_106
    infer mport T_107 = ram[T_55], clk
    node T_111 = mux(maybe_flow, io.enq.bits, T_107)
    io.deq.bits <- T_111
    node T_115 = sub(T_53, T_55)
    node ptr_diff = tail(T_115, 1)
    node T_117 = and(maybe_full, ptr_match)
    node T_118 = cat(T_117, ptr_diff)
    io.count <= T_118
    
  module Queue_125 : 
    input clk : Clock
    input reset : UInt<1>
    output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, count : UInt<2>}
    
    io is invalid
    cmem ram : UInt<64>[2]
    reg T_26 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg T_28 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
    node ptr_match = eq(T_26, T_28)
    node T_33 = eq(maybe_full, UInt<1>("h00"))
    node empty = and(ptr_match, T_33)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>("h00"), empty)
    node do_flow = and(maybe_flow, io.deq.ready)
    node T_39 = and(io.enq.ready, io.enq.valid)
    node T_41 = eq(do_flow, UInt<1>("h00"))
    node do_enq = and(T_39, T_41)
    node T_43 = and(io.deq.ready, io.deq.valid)
    node T_45 = eq(do_flow, UInt<1>("h00"))
    node do_deq = and(T_43, T_45)
    when do_enq :
      infer mport T_47 = ram[T_26], clk
      T_47 <= io.enq.bits
      node T_49 = eq(T_26, UInt<1>("h01"))
      node T_51 = and(UInt<1>("h00"), T_49)
      node T_54 = add(T_26, UInt<1>("h01"))
      node T_55 = tail(T_54, 1)
      node T_56 = mux(T_51, UInt<1>("h00"), T_55)
      T_26 <= T_56
      skip
    when do_deq :
      node T_58 = eq(T_28, UInt<1>("h01"))
      node T_60 = and(UInt<1>("h00"), T_58)
      node T_63 = add(T_28, UInt<1>("h01"))
      node T_64 = tail(T_63, 1)
      node T_65 = mux(T_60, UInt<1>("h00"), T_64)
      T_28 <= T_65
      skip
    node T_66 = neq(do_enq, do_deq)
    when T_66 :
      maybe_full <= do_enq
      skip
    node T_68 = eq(empty, UInt<1>("h00"))
    node T_70 = and(UInt<1>("h00"), io.enq.valid)
    node T_71 = or(T_68, T_70)
    io.deq.valid <= T_71
    node T_73 = eq(full, UInt<1>("h00"))
    node T_75 = and(UInt<1>("h00"), io.deq.ready)
    node T_76 = or(T_73, T_75)
    io.enq.ready <= T_76
    infer mport T_77 = ram[T_28], clk
    node T_78 = mux(maybe_flow, io.enq.bits, T_77)
    io.deq.bits <= T_78
    node T_79 = sub(T_26, T_28)
    node ptr_diff = tail(T_79, 1)
    node T_81 = and(maybe_full, ptr_match)
    node T_82 = cat(T_81, ptr_diff)
    io.count <= T_82
    
  module Top : 
    input clk : Clock
    input reset : UInt<1>
    output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1]}
    
    io is invalid
    inst uncore of Uncore
    uncore.io is invalid
    uncore.clk <= clk
    uncore.reset <= reset
    inst T_669 of RocketTile
    T_669.io is invalid
    T_669.clk <= clk
    T_669.reset <= uncore.io.htif[0].reset
    T_669.io.host.id <= UInt<1>("h00")
    reg T_671 : UInt<1>, clk
    T_671 <= uncore.io.htif[0].reset
    reg T_672 : UInt<1>, clk
    T_672 <= T_671
    T_669.io.host.reset <= T_672
    inst T_677 of Queue_124
    T_677.io is invalid
    T_677.clk <= clk
    T_677.reset <= reset
    T_677.io.enq.valid <= uncore.io.htif[0].csr.req.valid
    T_677.io.enq.bits <- uncore.io.htif[0].csr.req.bits
    uncore.io.htif[0].csr.req.ready <= T_677.io.enq.ready
    T_669.io.host.csr.req <- T_677.io.deq
    inst T_679 of Queue_125
    T_679.io is invalid
    T_679.clk <= clk
    T_679.reset <= reset
    T_679.io.enq.valid <= T_669.io.host.csr.resp.valid
    T_679.io.enq.bits <= T_669.io.host.csr.resp.bits
    T_669.io.host.csr.resp.ready <= T_679.io.enq.ready
    uncore.io.htif[0].csr.resp <- T_679.io.deq
    uncore.io.htif[0].debug_stats_csr <= T_669.io.host.debug_stats_csr
    uncore.io.tiles_cached[0] <- T_669.io.cached[0]
    uncore.io.tiles_uncached[0] <- T_669.io.uncached[0]
    io.host <- uncore.io.host
    io.mem_backup_ctrl <- uncore.io.mem_backup_ctrl
    inst T_692 of Queue_36
    T_692.io is invalid
    T_692.clk <= clk
    T_692.reset <= reset
    T_692.io.enq.valid <= uncore.io.mem[0].ar.valid
    T_692.io.enq.bits <- uncore.io.mem[0].ar.bits
    uncore.io.mem[0].ar.ready <= T_692.io.enq.ready
    io.mem[0].ar <- T_692.io.deq
    inst T_705 of Queue_36
    T_705.io is invalid
    T_705.clk <= clk
    T_705.reset <= reset
    T_705.io.enq.valid <= uncore.io.mem[0].aw.valid
    T_705.io.enq.bits <- uncore.io.mem[0].aw.bits
    uncore.io.mem[0].aw.ready <= T_705.io.enq.ready
    io.mem[0].aw <- T_705.io.deq
    inst T_711 of Queue_74
    T_711.io is invalid
    T_711.clk <= clk
    T_711.reset <= reset
    T_711.io.enq.valid <= uncore.io.mem[0].w.valid
    T_711.io.enq.bits <- uncore.io.mem[0].w.bits
    uncore.io.mem[0].w.ready <= T_711.io.enq.ready
    io.mem[0].w <- T_711.io.deq
    inst T_718 of Queue_75
    T_718.io is invalid
    T_718.clk <= clk
    T_718.reset <= reset
    T_718.io.enq.valid <= io.mem[0].r.valid
    T_718.io.enq.bits <- io.mem[0].r.bits
    io.mem[0].r.ready <= T_718.io.enq.ready
    uncore.io.mem[0].r <- T_718.io.deq
    inst T_723 of Queue_76
    T_723.io is invalid
    T_723.clk <= clk
    T_723.reset <= reset
    T_723.io.enq.valid <= io.mem[0].b.valid
    T_723.io.enq.bits <- io.mem[0].b.bits
    io.mem[0].b.ready <= T_723.io.enq.ready
    uncore.io.mem[0].b <- T_723.io.deq
    io.mem[0].ar.bits.cache <= UInt<4>("h03")
    io.mem[0].aw.bits.cache <= UInt<4>("h03")
    inst errslave of NastiErrorSlave_40
    errslave.io is invalid
    errslave.clk <= clk
    errslave.reset <= reset
    errslave.io <- uncore.io.mmio