path: root/regress/RocketCore.fir

; SPDX-License-Identifier: Apache-2.0
circuit RocketCore :
  module RocketCore : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip interrupts : {debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>}, flip hartid : UInt<64>, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>, speculative : UInt<1>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flush_icache : UInt<1>, flush_tlb : UInt<1>, flip npc : UInt<40>, flip acquire : UInt<1>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>}}
    
    io is invalid
    io is invalid
    reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 115:20]
    reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 116:21]
    reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 117:20]
    reg ex_reg_xcpt_interrupt : UInt<1>, clock @[Rocket.scala 119:35]
    reg ex_reg_valid : UInt<1>, clock @[Rocket.scala 120:35]
    reg ex_reg_rvc : UInt<1>, clock @[Rocket.scala 121:35]
    reg ex_reg_btb_hit : UInt<1>, clock @[Rocket.scala 122:35]
    reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[Rocket.scala 123:35]
    reg ex_reg_xcpt : UInt<1>, clock @[Rocket.scala 124:35]
    reg ex_reg_flush_pipe : UInt<1>, clock @[Rocket.scala 125:35]
    reg ex_reg_load_use : UInt<1>, clock @[Rocket.scala 126:35]
    reg ex_cause : UInt, clock @[Rocket.scala 127:35]
    reg ex_reg_replay : UInt<1>, clock @[Rocket.scala 128:26]
    reg ex_reg_pc : UInt, clock @[Rocket.scala 129:22]
    reg ex_reg_inst : UInt, clock @[Rocket.scala 130:24]
    reg mem_reg_xcpt_interrupt : UInt<1>, clock @[Rocket.scala 132:36]
    reg mem_reg_valid : UInt<1>, clock @[Rocket.scala 133:36]
    reg mem_reg_rvc : UInt<1>, clock @[Rocket.scala 134:36]
    reg mem_reg_btb_hit : UInt<1>, clock @[Rocket.scala 135:36]
    reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[Rocket.scala 136:36]
    reg mem_reg_xcpt : UInt<1>, clock @[Rocket.scala 137:36]
    reg mem_reg_replay : UInt<1>, clock @[Rocket.scala 138:36]
    reg mem_reg_flush_pipe : UInt<1>, clock @[Rocket.scala 139:36]
    reg mem_reg_cause : UInt, clock @[Rocket.scala 140:36]
    reg mem_reg_slow_bypass : UInt<1>, clock @[Rocket.scala 141:36]
    reg mem_reg_load : UInt<1>, clock @[Rocket.scala 142:36]
    reg mem_reg_store : UInt<1>, clock @[Rocket.scala 143:36]
    reg mem_reg_pc : UInt, clock @[Rocket.scala 144:23]
    reg mem_reg_inst : UInt, clock @[Rocket.scala 145:25]
    reg mem_reg_wdata : UInt, clock @[Rocket.scala 146:26]
    reg mem_reg_rs2 : UInt, clock @[Rocket.scala 147:24]
    wire take_pc_mem : UInt<1> @[Rocket.scala 148:25]
    take_pc_mem is invalid @[Rocket.scala 148:25]
    reg wb_reg_valid : UInt<1>, clock @[Rocket.scala 150:35]
    reg wb_reg_xcpt : UInt<1>, clock @[Rocket.scala 151:35]
    reg wb_reg_replay : UInt<1>, clock @[Rocket.scala 152:35]
    reg wb_reg_cause : UInt, clock @[Rocket.scala 153:35]
    reg wb_reg_pc : UInt, clock @[Rocket.scala 154:22]
    reg wb_reg_inst : UInt, clock @[Rocket.scala 155:24]
    reg wb_reg_wdata : UInt, clock @[Rocket.scala 156:25]
    reg wb_reg_rs2 : UInt, clock @[Rocket.scala 157:23]
    wire take_pc_wb : UInt<1> @[Rocket.scala 158:24]
    take_pc_wb is invalid @[Rocket.scala 158:24]
    wire take_pc_id : UInt<1> @[Rocket.scala 160:24]
    take_pc_id is invalid @[Rocket.scala 160:24]
    node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) @[Rocket.scala 161:35]
    node take_pc = or(take_pc_mem_wb, take_pc_id) @[Rocket.scala 162:32]
    inst ibuf of IBuf @[Rocket.scala 165:20]
    ibuf.io is invalid
    ibuf.clock <= clock
    ibuf.reset <= reset
    ibuf.io.imem <- io.imem.resp @[Rocket.scala 168:16]
    ibuf.io.kill <= take_pc @[Rocket.scala 169:16]
    wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>} @[Rocket.scala 172:21]
    id_ctrl is invalid @[Rocket.scala 172:21]
    node _T_2603 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65]
    node _T_2605 = eq(_T_2603, UInt<32>("h03")) @[Decode.scala 13:121]
    node _T_2607 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0106f")) @[Decode.scala 13:65]
    node _T_2609 = eq(_T_2607, UInt<32>("h03")) @[Decode.scala 13:121]
    node _T_2611 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0607f")) @[Decode.scala 13:65]
    node _T_2613 = eq(_T_2611, UInt<32>("h0f")) @[Decode.scala 13:121]
    node _T_2615 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07077")) @[Decode.scala 13:65]
    node _T_2617 = eq(_T_2615, UInt<32>("h013")) @[Decode.scala 13:121]
    node _T_2619 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05f")) @[Decode.scala 13:65]
    node _T_2621 = eq(_T_2619, UInt<32>("h017")) @[Decode.scala 13:121]
    node _T_2623 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc00007f")) @[Decode.scala 13:65]
    node _T_2625 = eq(_T_2623, UInt<32>("h033")) @[Decode.scala 13:121]
    node _T_2627 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be007077")) @[Decode.scala 13:65]
    node _T_2629 = eq(_T_2627, UInt<32>("h033")) @[Decode.scala 13:121]
    node _T_2631 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04000073")) @[Decode.scala 13:65]
    node _T_2633 = eq(_T_2631, UInt<32>("h043")) @[Decode.scala 13:121]
    node _T_2635 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0e400007f")) @[Decode.scala 13:65]
    node _T_2637 = eq(_T_2635, UInt<32>("h053")) @[Decode.scala 13:121]
    node _T_2639 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0707b")) @[Decode.scala 13:65]
    node _T_2641 = eq(_T_2639, UInt<32>("h063")) @[Decode.scala 13:121]
    node _T_2643 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07f")) @[Decode.scala 13:65]
    node _T_2645 = eq(_T_2643, UInt<32>("h06f")) @[Decode.scala 13:121]
    node _T_2647 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0ffefffff")) @[Decode.scala 13:65]
    node _T_2649 = eq(_T_2647, UInt<32>("h073")) @[Decode.scala 13:121]
    node _T_2651 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc00305f")) @[Decode.scala 13:65]
    node _T_2653 = eq(_T_2651, UInt<32>("h01013")) @[Decode.scala 13:121]
    node _T_2655 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe00305f")) @[Decode.scala 13:65]
    node _T_2657 = eq(_T_2655, UInt<32>("h0101b")) @[Decode.scala 13:121]
    node _T_2659 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0605b")) @[Decode.scala 13:65]
    node _T_2661 = eq(_T_2659, UInt<32>("h02003")) @[Decode.scala 13:121]
    node _T_2663 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65]
    node _T_2665 = eq(_T_2663, UInt<32>("h02013")) @[Decode.scala 13:121]
    node _T_2667 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01800607f")) @[Decode.scala 13:65]
    node _T_2669 = eq(_T_2667, UInt<32>("h0202f")) @[Decode.scala 13:121]
    node _T_2671 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65]
    node _T_2673 = eq(_T_2671, UInt<32>("h02073")) @[Decode.scala 13:121]
    node _T_2675 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0bc00707f")) @[Decode.scala 13:65]
    node _T_2677 = eq(_T_2675, UInt<32>("h05013")) @[Decode.scala 13:121]
    node _T_2679 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be00705f")) @[Decode.scala 13:65]
    node _T_2681 = eq(_T_2679, UInt<32>("h0501b")) @[Decode.scala 13:121]
    node _T_2683 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be007077")) @[Decode.scala 13:65]
    node _T_2685 = eq(_T_2683, UInt<32>("h05033")) @[Decode.scala 13:121]
    node _T_2687 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe004077")) @[Decode.scala 13:65]
    node _T_2689 = eq(_T_2687, UInt<32>("h02004033")) @[Decode.scala 13:121]
    node _T_2691 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0e800607f")) @[Decode.scala 13:65]
    node _T_2693 = eq(_T_2691, UInt<32>("h0800202f")) @[Decode.scala 13:121]
    node _T_2695 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0f9f0607f")) @[Decode.scala 13:65]
    node _T_2697 = eq(_T_2695, UInt<32>("h01000202f")) @[Decode.scala 13:121]
    node _T_2699 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0dfffffff")) @[Decode.scala 13:65]
    node _T_2701 = eq(_T_2699, UInt<32>("h010200073")) @[Decode.scala 13:121]
    node _T_2703 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010500073")) @[Decode.scala 13:121]
    node _T_2705 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe007fff")) @[Decode.scala 13:65]
    node _T_2707 = eq(_T_2705, UInt<32>("h012000073")) @[Decode.scala 13:121]
    node _T_2709 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0f400607f")) @[Decode.scala 13:65]
    node _T_2711 = eq(_T_2709, UInt<32>("h020000053")) @[Decode.scala 13:121]
    node _T_2713 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c00607f")) @[Decode.scala 13:65]
    node _T_2715 = eq(_T_2713, UInt<32>("h020000053")) @[Decode.scala 13:121]
    node _T_2717 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c00507f")) @[Decode.scala 13:65]
    node _T_2719 = eq(_T_2717, UInt<32>("h020000053")) @[Decode.scala 13:121]
    node _T_2721 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07ff0007f")) @[Decode.scala 13:65]
    node _T_2723 = eq(_T_2721, UInt<32>("h040100053")) @[Decode.scala 13:121]
    node _T_2725 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07ff0007f")) @[Decode.scala 13:65]
    node _T_2727 = eq(_T_2725, UInt<32>("h042000053")) @[Decode.scala 13:121]
    node _T_2729 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fdf0007f")) @[Decode.scala 13:65]
    node _T_2731 = eq(_T_2729, UInt<32>("h058000053")) @[Decode.scala 13:121]
    node _T_2733 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07b200073")) @[Decode.scala 13:121]
    node _T_2735 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0edc0007f")) @[Decode.scala 13:65]
    node _T_2737 = eq(_T_2735, UInt<32>("h0c0000053")) @[Decode.scala 13:121]
    node _T_2739 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fdf0607f")) @[Decode.scala 13:65]
    node _T_2741 = eq(_T_2739, UInt<32>("h0e0000053")) @[Decode.scala 13:121]
    node _T_2743 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0edf0707f")) @[Decode.scala 13:65]
    node _T_2745 = eq(_T_2743, UInt<32>("h0e0000053")) @[Decode.scala 13:121]
    node _T_2747 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0603f")) @[Decode.scala 13:65]
    node _T_2749 = eq(_T_2747, UInt<32>("h023")) @[Decode.scala 13:121]
    node _T_2751 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0306f")) @[Decode.scala 13:65]
    node _T_2753 = eq(_T_2751, UInt<32>("h01063")) @[Decode.scala 13:121]
    node _T_2755 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0407f")) @[Decode.scala 13:65]
    node _T_2757 = eq(_T_2755, UInt<32>("h04063")) @[Decode.scala 13:121]
    node _T_2759 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc007077")) @[Decode.scala 13:65]
    node _T_2761 = eq(_T_2759, UInt<32>("h033")) @[Decode.scala 13:121]
    node _T_2763 = or(UInt<1>("h00"), _T_2605) @[Decode.scala 14:30]
    node _T_2764 = or(_T_2763, _T_2609) @[Decode.scala 14:30]
    node _T_2765 = or(_T_2764, _T_2613) @[Decode.scala 14:30]
    node _T_2766 = or(_T_2765, _T_2617) @[Decode.scala 14:30]
    node _T_2767 = or(_T_2766, _T_2621) @[Decode.scala 14:30]
    node _T_2768 = or(_T_2767, _T_2625) @[Decode.scala 14:30]
    node _T_2769 = or(_T_2768, _T_2629) @[Decode.scala 14:30]
    node _T_2770 = or(_T_2769, _T_2633) @[Decode.scala 14:30]
    node _T_2771 = or(_T_2770, _T_2637) @[Decode.scala 14:30]
    node _T_2772 = or(_T_2771, _T_2641) @[Decode.scala 14:30]
    node _T_2773 = or(_T_2772, _T_2645) @[Decode.scala 14:30]
    node _T_2774 = or(_T_2773, _T_2649) @[Decode.scala 14:30]
    node _T_2775 = or(_T_2774, _T_2653) @[Decode.scala 14:30]
    node _T_2776 = or(_T_2775, _T_2657) @[Decode.scala 14:30]
    node _T_2777 = or(_T_2776, _T_2661) @[Decode.scala 14:30]
    node _T_2778 = or(_T_2777, _T_2665) @[Decode.scala 14:30]
    node _T_2779 = or(_T_2778, _T_2669) @[Decode.scala 14:30]
    node _T_2780 = or(_T_2779, _T_2673) @[Decode.scala 14:30]
    node _T_2781 = or(_T_2780, _T_2677) @[Decode.scala 14:30]
    node _T_2782 = or(_T_2781, _T_2681) @[Decode.scala 14:30]
    node _T_2783 = or(_T_2782, _T_2685) @[Decode.scala 14:30]
    node _T_2784 = or(_T_2783, _T_2689) @[Decode.scala 14:30]
    node _T_2785 = or(_T_2784, _T_2693) @[Decode.scala 14:30]
    node _T_2786 = or(_T_2785, _T_2697) @[Decode.scala 14:30]
    node _T_2787 = or(_T_2786, _T_2701) @[Decode.scala 14:30]
    node _T_2788 = or(_T_2787, _T_2703) @[Decode.scala 14:30]
    node _T_2789 = or(_T_2788, _T_2707) @[Decode.scala 14:30]
    node _T_2790 = or(_T_2789, _T_2711) @[Decode.scala 14:30]
    node _T_2791 = or(_T_2790, _T_2715) @[Decode.scala 14:30]
    node _T_2792 = or(_T_2791, _T_2719) @[Decode.scala 14:30]
    node _T_2793 = or(_T_2792, _T_2723) @[Decode.scala 14:30]
    node _T_2794 = or(_T_2793, _T_2727) @[Decode.scala 14:30]
    node _T_2795 = or(_T_2794, _T_2731) @[Decode.scala 14:30]
    node _T_2796 = or(_T_2795, _T_2733) @[Decode.scala 14:30]
    node _T_2797 = or(_T_2796, _T_2737) @[Decode.scala 14:30]
    node _T_2798 = or(_T_2797, _T_2741) @[Decode.scala 14:30]
    node _T_2799 = or(_T_2798, _T_2745) @[Decode.scala 14:30]
    node _T_2800 = or(_T_2799, _T_2749) @[Decode.scala 14:30]
    node _T_2801 = or(_T_2800, _T_2753) @[Decode.scala 14:30]
    node _T_2802 = or(_T_2801, _T_2757) @[Decode.scala 14:30]
    node _T_2803 = or(_T_2802, _T_2761) @[Decode.scala 14:30]
    node _T_2805 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05c")) @[Decode.scala 13:65]
    node _T_2807 = eq(_T_2805, UInt<32>("h04")) @[Decode.scala 13:121]
    node _T_2809 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h060")) @[Decode.scala 13:65]
    node _T_2811 = eq(_T_2809, UInt<32>("h040")) @[Decode.scala 13:121]
    node _T_2813 = or(UInt<1>("h00"), _T_2807) @[Decode.scala 14:30]
    node _T_2814 = or(_T_2813, _T_2811) @[Decode.scala 14:30]
    node _T_2817 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h074")) @[Decode.scala 13:65]
    node _T_2819 = eq(_T_2817, UInt<32>("h060")) @[Decode.scala 13:121]
    node _T_2821 = or(UInt<1>("h00"), _T_2819) @[Decode.scala 14:30]
    node _T_2823 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h068")) @[Decode.scala 13:65]
    node _T_2825 = eq(_T_2823, UInt<32>("h068")) @[Decode.scala 13:121]
    node _T_2827 = or(UInt<1>("h00"), _T_2825) @[Decode.scala 14:30]
    node _T_2829 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0203c")) @[Decode.scala 13:65]
    node _T_2831 = eq(_T_2829, UInt<32>("h024")) @[Decode.scala 13:121]
    node _T_2833 = or(UInt<1>("h00"), _T_2831) @[Decode.scala 14:30]
    node _T_2835 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h064")) @[Decode.scala 13:65]
    node _T_2837 = eq(_T_2835, UInt<32>("h020")) @[Decode.scala 13:121]
    node _T_2839 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h034")) @[Decode.scala 13:65]
    node _T_2841 = eq(_T_2839, UInt<32>("h020")) @[Decode.scala 13:121]
    node _T_2843 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02048")) @[Decode.scala 13:65]
    node _T_2845 = eq(_T_2843, UInt<32>("h02008")) @[Decode.scala 13:121]
    node _T_2847 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h042003024")) @[Decode.scala 13:65]
    node _T_2849 = eq(_T_2847, UInt<32>("h02000020")) @[Decode.scala 13:121]
    node _T_2851 = or(UInt<1>("h00"), _T_2837) @[Decode.scala 14:30]
    node _T_2852 = or(_T_2851, _T_2841) @[Decode.scala 14:30]
    node _T_2853 = or(_T_2852, _T_2845) @[Decode.scala 14:30]
    node _T_2854 = or(_T_2853, _T_2849) @[Decode.scala 14:30]
    node _T_2856 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h044")) @[Decode.scala 13:65]
    node _T_2858 = eq(_T_2856, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2860 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04024")) @[Decode.scala 13:65]
    node _T_2862 = eq(_T_2860, UInt<32>("h020")) @[Decode.scala 13:121]
    node _T_2864 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h038")) @[Decode.scala 13:65]
    node _T_2866 = eq(_T_2864, UInt<32>("h020")) @[Decode.scala 13:121]
    node _T_2868 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02050")) @[Decode.scala 13:65]
    node _T_2870 = eq(_T_2868, UInt<32>("h02000")) @[Decode.scala 13:121]
    node _T_2872 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000034")) @[Decode.scala 13:65]
    node _T_2874 = eq(_T_2872, UInt<32>("h090000010")) @[Decode.scala 13:121]
    node _T_2876 = or(UInt<1>("h00"), _T_2858) @[Decode.scala 14:30]
    node _T_2877 = or(_T_2876, _T_2862) @[Decode.scala 14:30]
    node _T_2878 = or(_T_2877, _T_2866) @[Decode.scala 14:30]
    node _T_2879 = or(_T_2878, _T_2870) @[Decode.scala 14:30]
    node _T_2880 = or(_T_2879, _T_2874) @[Decode.scala 14:30]
    node _T_2882 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h058")) @[Decode.scala 13:65]
    node _T_2884 = eq(_T_2882, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2886 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h020")) @[Decode.scala 13:65]
    node _T_2888 = eq(_T_2886, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2890 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0c")) @[Decode.scala 13:65]
    node _T_2892 = eq(_T_2890, UInt<32>("h04")) @[Decode.scala 13:121]
    node _T_2894 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h048")) @[Decode.scala 13:65]
    node _T_2896 = eq(_T_2894, UInt<32>("h048")) @[Decode.scala 13:121]
    node _T_2898 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04050")) @[Decode.scala 13:65]
    node _T_2900 = eq(_T_2898, UInt<32>("h04050")) @[Decode.scala 13:121]
    node _T_2902 = or(UInt<1>("h00"), _T_2884) @[Decode.scala 14:30]
    node _T_2903 = or(_T_2902, _T_2888) @[Decode.scala 14:30]
    node _T_2904 = or(_T_2903, _T_2892) @[Decode.scala 14:30]
    node _T_2905 = or(_T_2904, _T_2896) @[Decode.scala 14:30]
    node _T_2906 = or(_T_2905, _T_2900) @[Decode.scala 14:30]
    node _T_2908 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h048")) @[Decode.scala 13:65]
    node _T_2910 = eq(_T_2908, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2912 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018")) @[Decode.scala 13:65]
    node _T_2914 = eq(_T_2912, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2916 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04008")) @[Decode.scala 13:65]
    node _T_2918 = eq(_T_2916, UInt<32>("h04000")) @[Decode.scala 13:121]
    node _T_2920 = or(UInt<1>("h00"), _T_2910) @[Decode.scala 14:30]
    node _T_2921 = or(_T_2920, _T_2858) @[Decode.scala 14:30]
    node _T_2922 = or(_T_2921, _T_2914) @[Decode.scala 14:30]
    node _T_2923 = or(_T_2922, _T_2918) @[Decode.scala 14:30]
    node _T_2924 = cat(_T_2923, _T_2906) @[Cat.scala 30:58]
    node _T_2926 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04004")) @[Decode.scala 13:65]
    node _T_2928 = eq(_T_2926, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2930 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h050")) @[Decode.scala 13:65]
    node _T_2932 = eq(_T_2930, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2934 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h024")) @[Decode.scala 13:65]
    node _T_2936 = eq(_T_2934, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2938 = or(UInt<1>("h00"), _T_2928) @[Decode.scala 14:30]
    node _T_2939 = or(_T_2938, _T_2932) @[Decode.scala 14:30]
    node _T_2940 = or(_T_2939, _T_2858) @[Decode.scala 14:30]
    node _T_2941 = or(_T_2940, _T_2936) @[Decode.scala 14:30]
    node _T_2942 = or(_T_2941, _T_2914) @[Decode.scala 14:30]
    node _T_2944 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h034")) @[Decode.scala 13:65]
    node _T_2946 = eq(_T_2944, UInt<32>("h014")) @[Decode.scala 13:121]
    node _T_2948 = or(UInt<1>("h00"), _T_2946) @[Decode.scala 14:30]
    node _T_2949 = or(_T_2948, _T_2896) @[Decode.scala 14:30]
    node _T_2950 = cat(_T_2949, _T_2942) @[Cat.scala 30:58]
    node _T_2952 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018")) @[Decode.scala 13:65]
    node _T_2954 = eq(_T_2952, UInt<32>("h08")) @[Decode.scala 13:121]
    node _T_2956 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h044")) @[Decode.scala 13:65]
    node _T_2958 = eq(_T_2956, UInt<32>("h040")) @[Decode.scala 13:121]
    node _T_2960 = or(UInt<1>("h00"), _T_2954) @[Decode.scala 14:30]
    node _T_2961 = or(_T_2960, _T_2958) @[Decode.scala 14:30]
    node _T_2963 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h014")) @[Decode.scala 13:65]
    node _T_2965 = eq(_T_2963, UInt<32>("h014")) @[Decode.scala 13:121]
    node _T_2967 = or(UInt<1>("h00"), _T_2954) @[Decode.scala 14:30]
    node _T_2968 = or(_T_2967, _T_2965) @[Decode.scala 14:30]
    node _T_2970 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h030")) @[Decode.scala 13:65]
    node _T_2972 = eq(_T_2970, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2974 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0201c")) @[Decode.scala 13:65]
    node _T_2976 = eq(_T_2974, UInt<32>("h04")) @[Decode.scala 13:121]
    node _T_2978 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h014")) @[Decode.scala 13:65]
    node _T_2980 = eq(_T_2978, UInt<32>("h010")) @[Decode.scala 13:121]
    node _T_2982 = or(UInt<1>("h00"), _T_2972) @[Decode.scala 14:30]
    node _T_2983 = or(_T_2982, _T_2976) @[Decode.scala 14:30]
    node _T_2984 = or(_T_2983, _T_2980) @[Decode.scala 14:30]
    node _T_2985 = cat(_T_2984, _T_2968) @[Cat.scala 30:58]
    node _T_2986 = cat(_T_2985, _T_2961) @[Cat.scala 30:58]
    node _T_2988 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010")) @[Decode.scala 13:65]
    node _T_2990 = eq(_T_2988, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2992 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h08")) @[Decode.scala 13:65]
    node _T_2994 = eq(_T_2992, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_2996 = or(UInt<1>("h00"), _T_2990) @[Decode.scala 14:30]
    node _T_2997 = or(_T_2996, _T_2994) @[Decode.scala 14:30]
    node _T_2999 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03054")) @[Decode.scala 13:65]
    node _T_3001 = eq(_T_2999, UInt<32>("h01010")) @[Decode.scala 13:121]
    node _T_3003 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01058")) @[Decode.scala 13:65]
    node _T_3005 = eq(_T_3003, UInt<32>("h01040")) @[Decode.scala 13:121]
    node _T_3007 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07044")) @[Decode.scala 13:65]
    node _T_3009 = eq(_T_3007, UInt<32>("h07000")) @[Decode.scala 13:121]
    node _T_3011 = or(UInt<1>("h00"), _T_3001) @[Decode.scala 14:30]
    node _T_3012 = or(_T_3011, _T_3005) @[Decode.scala 14:30]
    node _T_3013 = or(_T_3012, _T_3009) @[Decode.scala 14:30]
    node _T_3015 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04054")) @[Decode.scala 13:65]
    node _T_3017 = eq(_T_3015, UInt<32>("h040")) @[Decode.scala 13:121]
    node _T_3019 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02058")) @[Decode.scala 13:65]
    node _T_3021 = eq(_T_3019, UInt<32>("h02040")) @[Decode.scala 13:121]
    node _T_3023 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03054")) @[Decode.scala 13:65]
    node _T_3025 = eq(_T_3023, UInt<32>("h03010")) @[Decode.scala 13:121]
    node _T_3027 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06054")) @[Decode.scala 13:65]
    node _T_3029 = eq(_T_3027, UInt<32>("h06010")) @[Decode.scala 13:121]
    node _T_3031 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040003034")) @[Decode.scala 13:65]
    node _T_3033 = eq(_T_3031, UInt<32>("h040000030")) @[Decode.scala 13:121]
    node _T_3035 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040001054")) @[Decode.scala 13:65]
    node _T_3037 = eq(_T_3035, UInt<32>("h040001010")) @[Decode.scala 13:121]
    node _T_3039 = or(UInt<1>("h00"), _T_3017) @[Decode.scala 14:30]
    node _T_3040 = or(_T_3039, _T_3021) @[Decode.scala 14:30]
    node _T_3041 = or(_T_3040, _T_3025) @[Decode.scala 14:30]
    node _T_3042 = or(_T_3041, _T_3029) @[Decode.scala 14:30]
    node _T_3043 = or(_T_3042, _T_3033) @[Decode.scala 14:30]
    node _T_3044 = or(_T_3043, _T_3037) @[Decode.scala 14:30]
    node _T_3046 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02054")) @[Decode.scala 13:65]
    node _T_3048 = eq(_T_3046, UInt<32>("h02010")) @[Decode.scala 13:121]
    node _T_3050 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040004054")) @[Decode.scala 13:65]
    node _T_3052 = eq(_T_3050, UInt<32>("h04010")) @[Decode.scala 13:121]
    node _T_3054 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05054")) @[Decode.scala 13:65]
    node _T_3056 = eq(_T_3054, UInt<32>("h04010")) @[Decode.scala 13:121]
    node _T_3058 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04058")) @[Decode.scala 13:65]
    node _T_3060 = eq(_T_3058, UInt<32>("h04040")) @[Decode.scala 13:121]
    node _T_3062 = or(UInt<1>("h00"), _T_3048) @[Decode.scala 14:30]
    node _T_3063 = or(_T_3062, _T_3052) @[Decode.scala 14:30]
    node _T_3064 = or(_T_3063, _T_3056) @[Decode.scala 14:30]
    node _T_3065 = or(_T_3064, _T_3060) @[Decode.scala 14:30]
    node _T_3067 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06054")) @[Decode.scala 13:65]
    node _T_3069 = eq(_T_3067, UInt<32>("h02010")) @[Decode.scala 13:121]
    node _T_3071 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040003054")) @[Decode.scala 13:65]
    node _T_3073 = eq(_T_3071, UInt<32>("h040001010")) @[Decode.scala 13:121]
    node _T_3075 = or(UInt<1>("h00"), _T_3069) @[Decode.scala 14:30]
    node _T_3076 = or(_T_3075, _T_3060) @[Decode.scala 14:30]
    node _T_3077 = or(_T_3076, _T_3033) @[Decode.scala 14:30]
    node _T_3078 = or(_T_3077, _T_3073) @[Decode.scala 14:30]
    node _T_3079 = cat(_T_3044, _T_3013) @[Cat.scala 30:58]
    node _T_3080 = cat(_T_3078, _T_3065) @[Cat.scala 30:58]
    node _T_3081 = cat(_T_3080, _T_3079) @[Cat.scala 30:58]
    node _T_3083 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0405f")) @[Decode.scala 13:65]
    node _T_3085 = eq(_T_3083, UInt<32>("h03")) @[Decode.scala 13:121]
    node _T_3087 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0107f")) @[Decode.scala 13:65]
    node _T_3089 = eq(_T_3087, UInt<32>("h03")) @[Decode.scala 13:121]
    node _T_3091 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0707f")) @[Decode.scala 13:65]
    node _T_3093 = eq(_T_3091, UInt<32>("h0100f")) @[Decode.scala 13:121]
    node _T_3095 = or(UInt<1>("h00"), _T_3085) @[Decode.scala 14:30]
    node _T_3096 = or(_T_3095, _T_2605) @[Decode.scala 14:30]
    node _T_3097 = or(_T_3096, _T_3089) @[Decode.scala 14:30]
    node _T_3098 = or(_T_3097, _T_3093) @[Decode.scala 14:30]
    node _T_3099 = or(_T_3098, _T_2661) @[Decode.scala 14:30]
    node _T_3100 = or(_T_3099, _T_2669) @[Decode.scala 14:30]
    node _T_3101 = or(_T_3100, _T_2693) @[Decode.scala 14:30]
    node _T_3102 = or(_T_3101, _T_2697) @[Decode.scala 14:30]
    node _T_3104 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02008")) @[Decode.scala 13:65]
    node _T_3106 = eq(_T_3104, UInt<32>("h08")) @[Decode.scala 13:121]
    node _T_3108 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h028")) @[Decode.scala 13:65]
    node _T_3110 = eq(_T_3108, UInt<32>("h020")) @[Decode.scala 13:121]
    node _T_3112 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018000020")) @[Decode.scala 13:65]
    node _T_3114 = eq(_T_3112, UInt<32>("h018000020")) @[Decode.scala 13:121]
    node _T_3116 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h020000020")) @[Decode.scala 13:65]
    node _T_3118 = eq(_T_3116, UInt<32>("h020000020")) @[Decode.scala 13:121]
    node _T_3120 = or(UInt<1>("h00"), _T_3106) @[Decode.scala 14:30]
    node _T_3121 = or(_T_3120, _T_3110) @[Decode.scala 14:30]
    node _T_3122 = or(_T_3121, _T_3114) @[Decode.scala 14:30]
    node _T_3123 = or(_T_3122, _T_3118) @[Decode.scala 14:30]
    node _T_3125 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010002008")) @[Decode.scala 13:65]
    node _T_3127 = eq(_T_3125, UInt<32>("h010002008")) @[Decode.scala 13:121]
    node _T_3129 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040002008")) @[Decode.scala 13:65]
    node _T_3131 = eq(_T_3129, UInt<32>("h040002008")) @[Decode.scala 13:121]
    node _T_3133 = or(UInt<1>("h00"), _T_3127) @[Decode.scala 14:30]
    node _T_3134 = or(_T_3133, _T_3131) @[Decode.scala 14:30]
    node _T_3136 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h08000008")) @[Decode.scala 13:65]
    node _T_3138 = eq(_T_3136, UInt<32>("h08000008")) @[Decode.scala 13:121]
    node _T_3140 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000008")) @[Decode.scala 13:65]
    node _T_3142 = eq(_T_3140, UInt<32>("h010000008")) @[Decode.scala 13:121]
    node _T_3144 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h080000008")) @[Decode.scala 13:65]
    node _T_3146 = eq(_T_3144, UInt<32>("h080000008")) @[Decode.scala 13:121]
    node _T_3148 = or(UInt<1>("h00"), _T_3106) @[Decode.scala 14:30]
    node _T_3149 = or(_T_3148, _T_3138) @[Decode.scala 14:30]
    node _T_3150 = or(_T_3149, _T_3142) @[Decode.scala 14:30]
    node _T_3151 = or(_T_3150, _T_3146) @[Decode.scala 14:30]
    node _T_3153 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018002008")) @[Decode.scala 13:65]
    node _T_3155 = eq(_T_3153, UInt<32>("h02008")) @[Decode.scala 13:121]
    node _T_3157 = or(UInt<1>("h00"), _T_3155) @[Decode.scala 14:30]
    node _T_3159 = cat(_T_3134, _T_3123) @[Cat.scala 30:58]
    node _T_3160 = cat(UInt<1>("h00"), _T_3157) @[Cat.scala 30:58]
    node _T_3161 = cat(_T_3160, _T_3151) @[Cat.scala 30:58]
    node _T_3162 = cat(_T_3161, _T_3159) @[Cat.scala 30:58]
    node _T_3164 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01000")) @[Decode.scala 13:65]
    node _T_3166 = eq(_T_3164, UInt<32>("h01000")) @[Decode.scala 13:121]
    node _T_3168 = or(UInt<1>("h00"), _T_3166) @[Decode.scala 14:30]
    node _T_3170 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000")) @[Decode.scala 13:65]
    node _T_3172 = eq(_T_3170, UInt<32>("h02000")) @[Decode.scala 13:121]
    node _T_3174 = or(UInt<1>("h00"), _T_3172) @[Decode.scala 14:30]
    node _T_3176 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04000")) @[Decode.scala 13:65]
    node _T_3178 = eq(_T_3176, UInt<32>("h04000")) @[Decode.scala 13:121]
    node _T_3180 = or(UInt<1>("h00"), _T_3178) @[Decode.scala 14:30]
    node _T_3181 = cat(_T_3180, _T_3174) @[Cat.scala 30:58]
    node _T_3182 = cat(_T_3181, _T_3168) @[Cat.scala 30:58]
    node _T_3184 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h080000060")) @[Decode.scala 13:65]
    node _T_3186 = eq(_T_3184, UInt<32>("h040")) @[Decode.scala 13:121]
    node _T_3188 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000060")) @[Decode.scala 13:65]
    node _T_3190 = eq(_T_3188, UInt<32>("h040")) @[Decode.scala 13:121]
    node _T_3192 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h070")) @[Decode.scala 13:65]
    node _T_3194 = eq(_T_3192, UInt<32>("h040")) @[Decode.scala 13:121]
    node _T_3196 = or(UInt<1>("h00"), _T_3186) @[Decode.scala 14:30]
    node _T_3197 = or(_T_3196, _T_3190) @[Decode.scala 14:30]
    node _T_3198 = or(_T_3197, _T_3194) @[Decode.scala 14:30]
    node _T_3200 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c")) @[Decode.scala 13:65]
    node _T_3202 = eq(_T_3200, UInt<32>("h024")) @[Decode.scala 13:121]
    node _T_3204 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040000060")) @[Decode.scala 13:65]
    node _T_3206 = eq(_T_3204, UInt<32>("h040")) @[Decode.scala 13:121]
    node _T_3208 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000060")) @[Decode.scala 13:65]
    node _T_3210 = eq(_T_3208, UInt<32>("h010000040")) @[Decode.scala 13:121]
    node _T_3212 = or(UInt<1>("h00"), _T_3202) @[Decode.scala 14:30]
    node _T_3213 = or(_T_3212, _T_3206) @[Decode.scala 14:30]
    node _T_3214 = or(_T_3213, _T_3194) @[Decode.scala 14:30]
    node _T_3215 = or(_T_3214, _T_3210) @[Decode.scala 14:30]
    node _T_3217 = or(UInt<1>("h00"), _T_3194) @[Decode.scala 14:30]
    node _T_3219 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03c")) @[Decode.scala 13:65]
    node _T_3221 = eq(_T_3219, UInt<32>("h04")) @[Decode.scala 13:121]
    node _T_3223 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000060")) @[Decode.scala 13:65]
    node _T_3225 = eq(_T_3223, UInt<32>("h010000040")) @[Decode.scala 13:121]
    node _T_3227 = or(UInt<1>("h00"), _T_3221) @[Decode.scala 14:30]
    node _T_3228 = or(_T_3227, _T_3186) @[Decode.scala 14:30]
    node _T_3229 = or(_T_3228, _T_3194) @[Decode.scala 14:30]
    node _T_3230 = or(_T_3229, _T_3225) @[Decode.scala 14:30]
    node _T_3232 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000074")) @[Decode.scala 13:65]
    node _T_3234 = eq(_T_3232, UInt<32>("h02000030")) @[Decode.scala 13:121]
    node _T_3236 = or(UInt<1>("h00"), _T_3234) @[Decode.scala 14:30]
    node _T_3238 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h064")) @[Decode.scala 13:65]
    node _T_3240 = eq(_T_3238, UInt<32>("h00")) @[Decode.scala 13:121]
    node _T_3242 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h050")) @[Decode.scala 13:65]
    node _T_3244 = eq(_T_3242, UInt<32>("h010")) @[Decode.scala 13:121]
    node _T_3246 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02024")) @[Decode.scala 13:65]
    node _T_3248 = eq(_T_3246, UInt<32>("h024")) @[Decode.scala 13:121]
    node _T_3250 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h028")) @[Decode.scala 13:65]
    node _T_3252 = eq(_T_3250, UInt<32>("h028")) @[Decode.scala 13:121]
    node _T_3254 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01030")) @[Decode.scala 13:65]
    node _T_3256 = eq(_T_3254, UInt<32>("h01030")) @[Decode.scala 13:121]
    node _T_3258 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02030")) @[Decode.scala 13:65]
    node _T_3260 = eq(_T_3258, UInt<32>("h02030")) @[Decode.scala 13:121]
    node _T_3262 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000010")) @[Decode.scala 13:65]
    node _T_3264 = eq(_T_3262, UInt<32>("h080000010")) @[Decode.scala 13:121]
    node _T_3266 = or(UInt<1>("h00"), _T_3240) @[Decode.scala 14:30]
    node _T_3267 = or(_T_3266, _T_3244) @[Decode.scala 14:30]
    node _T_3268 = or(_T_3267, _T_3248) @[Decode.scala 14:30]
    node _T_3269 = or(_T_3268, _T_3252) @[Decode.scala 14:30]
    node _T_3270 = or(_T_3269, _T_3256) @[Decode.scala 14:30]
    node _T_3271 = or(_T_3270, _T_3260) @[Decode.scala 14:30]
    node _T_3272 = or(_T_3271, _T_3264) @[Decode.scala 14:30]
    node _T_3274 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01070")) @[Decode.scala 13:65]
    node _T_3276 = eq(_T_3274, UInt<32>("h01070")) @[Decode.scala 13:121]
    node _T_3278 = or(UInt<1>("h00"), _T_3276) @[Decode.scala 14:30]
    node _T_3280 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02070")) @[Decode.scala 13:65]
    node _T_3282 = eq(_T_3280, UInt<32>("h02070")) @[Decode.scala 13:121]
    node _T_3284 = or(UInt<1>("h00"), _T_3282) @[Decode.scala 14:30]
    node _T_3286 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03070")) @[Decode.scala 13:65]
    node _T_3288 = eq(_T_3286, UInt<32>("h070")) @[Decode.scala 13:121]
    node _T_3290 = or(UInt<1>("h00"), _T_3288) @[Decode.scala 14:30]
    node _T_3291 = cat(_T_3290, _T_3284) @[Cat.scala 30:58]
    node _T_3292 = cat(_T_3291, _T_3278) @[Cat.scala 30:58]
    node _T_3294 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03058")) @[Decode.scala 13:65]
    node _T_3296 = eq(_T_3294, UInt<32>("h01008")) @[Decode.scala 13:121]
    node _T_3298 = or(UInt<1>("h00"), _T_3296) @[Decode.scala 14:30]
    node _T_3300 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03058")) @[Decode.scala 13:65]
    node _T_3302 = eq(_T_3300, UInt<32>("h08")) @[Decode.scala 13:121]
    node _T_3304 = or(UInt<1>("h00"), _T_3302) @[Decode.scala 14:30]
    node _T_3306 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06048")) @[Decode.scala 13:65]
    node _T_3308 = eq(_T_3306, UInt<32>("h02008")) @[Decode.scala 13:121]
    node _T_3310 = or(UInt<1>("h00"), _T_3308) @[Decode.scala 14:30]
    node _T_3312 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0105c")) @[Decode.scala 13:65]
    node _T_3314 = eq(_T_3312, UInt<32>("h01004")) @[Decode.scala 13:121]
    node _T_3316 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000060")) @[Decode.scala 13:65]
    node _T_3318 = eq(_T_3316, UInt<32>("h02000040")) @[Decode.scala 13:121]
    node _T_3320 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0d0000070")) @[Decode.scala 13:65]
    node _T_3322 = eq(_T_3320, UInt<32>("h040000050")) @[Decode.scala 13:121]
    node _T_3324 = or(UInt<1>("h00"), _T_3314) @[Decode.scala 14:30]
    node _T_3325 = or(_T_3324, _T_3318) @[Decode.scala 14:30]
    node _T_3326 = or(_T_3325, _T_3322) @[Decode.scala 14:30]
    id_ctrl.legal <= _T_2803 @[IDecode.scala 65:42]
    id_ctrl.fp <= _T_2814 @[IDecode.scala 65:42]
    id_ctrl.rocc <= UInt<1>("h00") @[IDecode.scala 65:42]
    id_ctrl.branch <= _T_2821 @[IDecode.scala 65:42]
    id_ctrl.jal <= _T_2827 @[IDecode.scala 65:42]
    id_ctrl.jalr <= _T_2833 @[IDecode.scala 65:42]
    id_ctrl.rxs2 <= _T_2854 @[IDecode.scala 65:42]
    id_ctrl.rxs1 <= _T_2880 @[IDecode.scala 65:42]
    id_ctrl.sel_alu2 <= _T_2924 @[IDecode.scala 65:42]
    id_ctrl.sel_alu1 <= _T_2950 @[IDecode.scala 65:42]
    id_ctrl.sel_imm <= _T_2986 @[IDecode.scala 65:42]
    id_ctrl.alu_dw <= _T_2997 @[IDecode.scala 65:42]
    id_ctrl.alu_fn <= _T_3081 @[IDecode.scala 65:42]
    id_ctrl.mem <= _T_3102 @[IDecode.scala 65:42]
    id_ctrl.mem_cmd <= _T_3162 @[IDecode.scala 65:42]
    id_ctrl.mem_type <= _T_3182 @[IDecode.scala 65:42]
    id_ctrl.rfs1 <= _T_3198 @[IDecode.scala 65:42]
    id_ctrl.rfs2 <= _T_3215 @[IDecode.scala 65:42]
    id_ctrl.rfs3 <= _T_3217 @[IDecode.scala 65:42]
    id_ctrl.wfd <= _T_3230 @[IDecode.scala 65:42]
    id_ctrl.div <= _T_3236 @[IDecode.scala 65:42]
    id_ctrl.wxd <= _T_3272 @[IDecode.scala 65:42]
    id_ctrl.csr <= _T_3292 @[IDecode.scala 65:42]
    id_ctrl.fence_i <= _T_3298 @[IDecode.scala 65:42]
    id_ctrl.fence <= _T_3304 @[IDecode.scala 65:42]
    id_ctrl.amo <= _T_3310 @[IDecode.scala 65:42]
    id_ctrl.dp <= _T_3326 @[IDecode.scala 65:42]
    wire id_load_use : UInt<1> @[Rocket.scala 177:25]
    id_load_use is invalid @[Rocket.scala 177:25]
    reg id_reg_fence : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Rocket.scala 178:25]
    cmem _T_3331 : UInt<64>[31] @[Rocket.scala 682:23]
    wire id_rs_0 : UInt @[Rocket.scala 688:26]
    id_rs_0 is invalid @[Rocket.scala 688:26]
    node _T_3335 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 689:45]
    node _T_3336 = and(UInt<1>("h00"), _T_3335) @[Rocket.scala 689:37]
    node _T_3338 = bits(ibuf.io.inst[0].bits.inst.rs1, 4, 0) @[Rocket.scala 683:44]
    node _T_3339 = not(_T_3338) @[Rocket.scala 683:39]
    infer mport _T_3340 = _T_3331[_T_3339], clock
    node _T_3341 = mux(_T_3336, UInt<1>("h00"), _T_3340) @[Rocket.scala 689:25]
    id_rs_0 <= _T_3341 @[Rocket.scala 689:19]
    wire id_rs_1 : UInt @[Rocket.scala 688:26]
    id_rs_1 is invalid @[Rocket.scala 688:26]
    node _T_3345 = eq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h00")) @[Rocket.scala 689:45]
    node _T_3346 = and(UInt<1>("h00"), _T_3345) @[Rocket.scala 689:37]
    node _T_3348 = bits(ibuf.io.inst[0].bits.inst.rs2, 4, 0) @[Rocket.scala 683:44]
    node _T_3349 = not(_T_3348) @[Rocket.scala 683:39]
    infer mport _T_3350 = _T_3331[_T_3349], clock
    node _T_3351 = mux(_T_3346, UInt<1>("h00"), _T_3350) @[Rocket.scala 689:25]
    id_rs_1 <= _T_3351 @[Rocket.scala 689:19]
    wire ctrl_killd : UInt<1> @[Rocket.scala 183:24]
    ctrl_killd is invalid @[Rocket.scala 183:24]
    node _T_3353 = asSInt(ibuf.io.pc) @[Rocket.scala 184:28]
    node _T_3356 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 704:24]
    node _T_3358 = bits(ibuf.io.inst[0].bits.inst.bits, 31, 31) @[Rocket.scala 704:48]
    node _T_3359 = asSInt(_T_3358) @[Rocket.scala 704:53]
    node _T_3360 = mux(_T_3356, asSInt(UInt<1>("h00")), _T_3359) @[Rocket.scala 704:19]
    node _T_3362 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 705:26]
    node _T_3363 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 20) @[Rocket.scala 705:41]
    node _T_3364 = asSInt(_T_3363) @[Rocket.scala 705:49]
    node _T_3365 = mux(_T_3362, _T_3364, _T_3360) @[Rocket.scala 705:21]
    node _T_3367 = neq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 706:26]
    node _T_3369 = neq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 706:43]
    node _T_3370 = and(_T_3367, _T_3369) @[Rocket.scala 706:36]
    node _T_3371 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 12) @[Rocket.scala 706:65]
    node _T_3372 = asSInt(_T_3371) @[Rocket.scala 706:73]
    node _T_3373 = mux(_T_3370, _T_3360, _T_3372) @[Rocket.scala 706:21]
    node _T_3375 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 707:23]
    node _T_3377 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 707:40]
    node _T_3378 = or(_T_3375, _T_3377) @[Rocket.scala 707:33]
    node _T_3381 = eq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 708:23]
    node _T_3382 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[Rocket.scala 708:39]
    node _T_3383 = asSInt(_T_3382) @[Rocket.scala 708:44]
    node _T_3385 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 709:23]
    node _T_3386 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[Rocket.scala 709:39]
    node _T_3387 = asSInt(_T_3386) @[Rocket.scala 709:43]
    node _T_3388 = mux(_T_3385, _T_3387, _T_3360) @[Rocket.scala 709:18]
    node _T_3389 = mux(_T_3381, _T_3383, _T_3388) @[Rocket.scala 708:18]
    node _T_3390 = mux(_T_3378, asSInt(UInt<1>("h00")), _T_3389) @[Rocket.scala 707:18]
    node _T_3392 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 710:25]
    node _T_3394 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 710:42]
    node _T_3395 = or(_T_3392, _T_3394) @[Rocket.scala 710:35]
    node _T_3397 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 25) @[Rocket.scala 710:66]
    node _T_3398 = mux(_T_3395, UInt<1>("h00"), _T_3397) @[Rocket.scala 710:20]
    node _T_3400 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 711:24]
    node _T_3403 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 712:24]
    node _T_3405 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 712:41]
    node _T_3406 = or(_T_3403, _T_3405) @[Rocket.scala 712:34]
    node _T_3407 = bits(ibuf.io.inst[0].bits.inst.bits, 11, 8) @[Rocket.scala 712:57]
    node _T_3409 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 713:24]
    node _T_3410 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 16) @[Rocket.scala 713:39]
    node _T_3411 = bits(ibuf.io.inst[0].bits.inst.bits, 24, 21) @[Rocket.scala 713:52]
    node _T_3412 = mux(_T_3409, _T_3410, _T_3411) @[Rocket.scala 713:19]
    node _T_3413 = mux(_T_3406, _T_3407, _T_3412) @[Rocket.scala 712:19]
    node _T_3414 = mux(_T_3400, UInt<1>("h00"), _T_3413) @[Rocket.scala 711:19]
    node _T_3416 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 714:22]
    node _T_3417 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[Rocket.scala 714:37]
    node _T_3419 = eq(UInt<3>("h03"), UInt<3>("h04")) @[Rocket.scala 715:22]
    node _T_3420 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[Rocket.scala 715:37]
    node _T_3422 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 716:22]
    node _T_3423 = bits(ibuf.io.inst[0].bits.inst.bits, 15, 15) @[Rocket.scala 716:37]
    node _T_3425 = mux(_T_3422, _T_3423, UInt<1>("h00")) @[Rocket.scala 716:17]
    node _T_3426 = mux(_T_3419, _T_3420, _T_3425) @[Rocket.scala 715:17]
    node _T_3427 = mux(_T_3416, _T_3417, _T_3426) @[Rocket.scala 714:17]
    node _T_3428 = cat(_T_3398, _T_3414) @[Cat.scala 30:58]
    node _T_3429 = cat(_T_3428, _T_3427) @[Cat.scala 30:58]
    node _T_3430 = asUInt(_T_3390) @[Cat.scala 30:58]
    node _T_3431 = asUInt(_T_3373) @[Cat.scala 30:58]
    node _T_3432 = cat(_T_3431, _T_3430) @[Cat.scala 30:58]
    node _T_3433 = asUInt(_T_3365) @[Cat.scala 30:58]
    node _T_3434 = asUInt(_T_3360) @[Cat.scala 30:58]
    node _T_3435 = cat(_T_3434, _T_3433) @[Cat.scala 30:58]
    node _T_3436 = cat(_T_3435, _T_3432) @[Cat.scala 30:58]
    node _T_3437 = cat(_T_3436, _T_3429) @[Cat.scala 30:58]
    node _T_3438 = asSInt(_T_3437) @[Rocket.scala 718:53]
    node _T_3439 = add(_T_3353, _T_3438) @[Rocket.scala 184:35]
    node _T_3440 = tail(_T_3439, 1) @[Rocket.scala 184:35]
    node _T_3441 = asSInt(_T_3440) @[Rocket.scala 184:35]
    node id_npc = asUInt(_T_3441) @[Rocket.scala 184:65]
    node _T_3444 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 185:34]
    node _T_3445 = and(UInt<1>("h00"), _T_3444) @[Rocket.scala 185:31]
    node _T_3446 = and(_T_3445, id_ctrl.jal) @[Rocket.scala 185:46]
    take_pc_id <= _T_3446 @[Rocket.scala 185:14]
    inst csr of CSRFile @[Rocket.scala 187:19]
    csr.io is invalid
    csr.clock <= clock
    csr.reset <= reset
    node _T_3450 = eq(id_ctrl.csr, UInt<3>("h02")) @[Package.scala 7:47]
    node _T_3451 = eq(id_ctrl.csr, UInt<3>("h03")) @[Package.scala 7:47]
    node _T_3452 = eq(id_ctrl.csr, UInt<3>("h01")) @[Package.scala 7:47]
    node _T_3453 = or(_T_3450, _T_3451) @[Package.scala 7:62]
    node id_csr_en = or(_T_3453, _T_3452) @[Package.scala 7:62]
    node id_system_insn = geq(id_ctrl.csr, UInt<3>("h04")) @[Rocket.scala 189:36]
    node _T_3457 = eq(id_ctrl.csr, UInt<3>("h02")) @[Package.scala 7:47]
    node _T_3458 = eq(id_ctrl.csr, UInt<3>("h03")) @[Package.scala 7:47]
    node _T_3459 = or(_T_3457, _T_3458) @[Package.scala 7:62]
    node _T_3461 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 190:67]
    node id_csr_ren = and(_T_3459, _T_3461) @[Rocket.scala 190:54]
    node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) @[Rocket.scala 191:19]
    node _T_3464 = eq(id_csr_ren, UInt<1>("h00")) @[Rocket.scala 192:54]
    node _T_3465 = and(id_csr_en, _T_3464) @[Rocket.scala 192:51]
    node _T_3466 = and(_T_3465, csr.io.decode.write_flush) @[Rocket.scala 192:66]
    node id_csr_flush = or(id_system_insn, _T_3466) @[Rocket.scala 192:37]
    node _T_3468 = eq(id_ctrl.legal, UInt<1>("h00")) @[Rocket.scala 194:25]
    node _T_3469 = bits(csr.io.status.isa, 12, 12) @[Rocket.scala 195:38]
    node _T_3471 = eq(_T_3469, UInt<1>("h00")) @[Rocket.scala 195:20]
    node _T_3472 = and(id_ctrl.div, _T_3471) @[Rocket.scala 195:17]
    node _T_3473 = or(_T_3468, _T_3472) @[Rocket.scala 194:40]
    node _T_3474 = bits(csr.io.status.isa, 0, 0) @[Rocket.scala 196:38]
    node _T_3476 = eq(_T_3474, UInt<1>("h00")) @[Rocket.scala 196:20]
    node _T_3477 = and(id_ctrl.amo, _T_3476) @[Rocket.scala 196:17]
    node _T_3478 = or(_T_3473, _T_3477) @[Rocket.scala 195:48]
    node _T_3479 = or(csr.io.decode.fp_illegal, io.fpu.illegal_rm) @[Rocket.scala 197:45]
    node _T_3480 = and(id_ctrl.fp, _T_3479) @[Rocket.scala 197:16]
    node _T_3481 = or(_T_3478, _T_3480) @[Rocket.scala 196:48]
    node _T_3482 = bits(csr.io.status.isa, 3, 3) @[Rocket.scala 198:37]
    node _T_3484 = eq(_T_3482, UInt<1>("h00")) @[Rocket.scala 198:19]
    node _T_3485 = and(id_ctrl.dp, _T_3484) @[Rocket.scala 198:16]
    node _T_3486 = or(_T_3481, _T_3485) @[Rocket.scala 197:67]
    node _T_3487 = bits(csr.io.status.isa, 2, 2) @[Rocket.scala 199:51]
    node _T_3489 = eq(_T_3487, UInt<1>("h00")) @[Rocket.scala 199:33]
    node _T_3490 = and(ibuf.io.inst[0].bits.rvc, _T_3489) @[Rocket.scala 199:30]
    node _T_3491 = or(_T_3486, _T_3490) @[Rocket.scala 198:47]
    node _T_3492 = and(id_ctrl.rocc, csr.io.decode.rocc_illegal) @[Rocket.scala 200:18]
    node _T_3493 = or(_T_3491, _T_3492) @[Rocket.scala 199:61]
    node _T_3495 = eq(id_csr_ren, UInt<1>("h00")) @[Rocket.scala 201:49]
    node _T_3496 = and(_T_3495, csr.io.decode.write_illegal) @[Rocket.scala 201:61]
    node _T_3497 = or(csr.io.decode.read_illegal, _T_3496) @[Rocket.scala 201:46]
    node _T_3498 = and(id_csr_en, _T_3497) @[Rocket.scala 201:15]
    node _T_3499 = or(_T_3493, _T_3498) @[Rocket.scala 200:48]
    node _T_3500 = and(id_system_insn, csr.io.decode.system_illegal) @[Rocket.scala 202:20]
    node id_illegal_insn = or(_T_3499, _T_3500) @[Rocket.scala 201:93]
    node id_amo_aq = bits(ibuf.io.inst[0].bits.inst.bits, 26, 26) @[Rocket.scala 204:29]
    node id_amo_rl = bits(ibuf.io.inst[0].bits.inst.bits, 25, 25) @[Rocket.scala 205:29]
    node _T_3501 = and(id_ctrl.amo, id_amo_rl) @[Rocket.scala 206:52]
    node id_fence_next = or(id_ctrl.fence, _T_3501) @[Rocket.scala 206:37]
    node _T_3503 = eq(io.dmem.ordered, UInt<1>("h00")) @[Rocket.scala 207:21]
    node id_mem_busy = or(_T_3503, io.dmem.req.valid) @[Rocket.scala 207:38]
    node _T_3505 = and(ex_reg_valid, ex_ctrl.rocc) @[Rocket.scala 209:35]
    node _T_3506 = or(io.rocc.busy, _T_3505) @[Rocket.scala 209:19]
    node _T_3507 = and(mem_reg_valid, mem_ctrl.rocc) @[Rocket.scala 210:20]
    node _T_3508 = or(_T_3506, _T_3507) @[Rocket.scala 209:51]
    node _T_3509 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 210:53]
    node _T_3510 = or(_T_3508, _T_3509) @[Rocket.scala 210:37]
    node id_rocc_busy = and(UInt<1>("h00"), _T_3510) @[Rocket.scala 208:38]
    node _T_3511 = and(id_reg_fence, id_mem_busy) @[Rocket.scala 211:49]
    node _T_3512 = or(id_fence_next, _T_3511) @[Rocket.scala 211:33]
    id_reg_fence <= _T_3512 @[Rocket.scala 211:16]
    node _T_3513 = and(id_rocc_busy, id_ctrl.fence) @[Rocket.scala 212:34]
    node _T_3514 = and(id_ctrl.amo, id_amo_aq) @[Rocket.scala 213:33]
    node _T_3515 = or(_T_3514, id_ctrl.fence_i) @[Rocket.scala 213:46]
    node _T_3516 = or(id_ctrl.mem, id_ctrl.rocc) @[Rocket.scala 213:97]
    node _T_3517 = and(id_reg_fence, _T_3516) @[Rocket.scala 213:81]
    node _T_3518 = or(_T_3515, _T_3517) @[Rocket.scala 213:65]
    node _T_3519 = and(id_mem_busy, _T_3518) @[Rocket.scala 213:17]
    node id_do_fence = or(_T_3513, _T_3519) @[Rocket.scala 212:51]
    inst bpu of BreakpointUnit @[Rocket.scala 215:19]
    bpu.io is invalid
    bpu.clock <= clock
    bpu.reset <= reset
    bpu.io.status <- csr.io.status @[Rocket.scala 216:17]
    bpu.io.bp <- csr.io.bp @[Rocket.scala 217:13]
    bpu.io.pc <= ibuf.io.pc @[Rocket.scala 218:13]
    bpu.io.ea <= mem_reg_wdata @[Rocket.scala 219:13]
    node id_xcpt_if = or(ibuf.io.inst[0].bits.pf0, ibuf.io.inst[0].bits.pf1) @[Rocket.scala 221:45]
    node _T_3552 = or(csr.io.interrupt, bpu.io.debug_if) @[Rocket.scala 645:26]
    node _T_3553 = or(_T_3552, bpu.io.xcpt_if) @[Rocket.scala 645:26]
    node _T_3554 = or(_T_3553, id_xcpt_if) @[Rocket.scala 645:26]
    node id_xcpt = or(_T_3554, id_illegal_insn) @[Rocket.scala 645:26]
    node _T_3555 = mux(id_xcpt_if, UInt<1>("h01"), UInt<2>("h02")) @[Mux.scala 31:69]
    node _T_3556 = mux(bpu.io.xcpt_if, UInt<2>("h03"), _T_3555) @[Mux.scala 31:69]
    node _T_3557 = mux(bpu.io.debug_if, UInt<4>("h0d"), _T_3556) @[Mux.scala 31:69]
    node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, _T_3557) @[Mux.scala 31:69]
    node ex_waddr = bits(ex_reg_inst, 11, 7) @[Rocket.scala 235:29]
    node mem_waddr = bits(mem_reg_inst, 11, 7) @[Rocket.scala 236:31]
    node wb_waddr = bits(wb_reg_inst, 11, 7) @[Rocket.scala 237:29]
    node _T_3561 = and(ex_reg_valid, ex_ctrl.wxd) @[Rocket.scala 240:19]
    node _T_3562 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 241:20]
    node _T_3564 = eq(mem_ctrl.mem, UInt<1>("h00")) @[Rocket.scala 241:39]
    node _T_3565 = and(_T_3562, _T_3564) @[Rocket.scala 241:36]
    node _T_3566 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 242:20]
    node _T_3567 = eq(UInt<1>("h00"), ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82]
    node id_bypass_src_0_0 = and(UInt<1>("h01"), _T_3567) @[Rocket.scala 243:74]
    node _T_3568 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82]
    node id_bypass_src_0_1 = and(_T_3561, _T_3568) @[Rocket.scala 243:74]
    node _T_3569 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82]
    node id_bypass_src_0_2 = and(_T_3565, _T_3569) @[Rocket.scala 243:74]
    node _T_3570 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82]
    node id_bypass_src_0_3 = and(_T_3566, _T_3570) @[Rocket.scala 243:74]
    node _T_3571 = eq(UInt<1>("h00"), ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82]
    node id_bypass_src_1_0 = and(UInt<1>("h01"), _T_3571) @[Rocket.scala 243:74]
    node _T_3572 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82]
    node id_bypass_src_1_1 = and(_T_3561, _T_3572) @[Rocket.scala 243:74]
    node _T_3573 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82]
    node id_bypass_src_1_2 = and(_T_3565, _T_3573) @[Rocket.scala 243:74]
    node _T_3574 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82]
    node id_bypass_src_1_3 = and(_T_3566, _T_3574) @[Rocket.scala 243:74]
    wire bypass_mux : UInt[4] @[Rocket.scala 246:23]
    bypass_mux is invalid @[Rocket.scala 246:23]
    bypass_mux[0] <= UInt<1>("h00") @[Rocket.scala 246:23]
    bypass_mux[1] <= mem_reg_wdata @[Rocket.scala 246:23]
    bypass_mux[2] <= wb_reg_wdata @[Rocket.scala 246:23]
    bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass @[Rocket.scala 246:23]
    reg ex_reg_rs_bypass : UInt<1>[2], clock @[Rocket.scala 247:29]
    reg ex_reg_rs_lsb : UInt<2>[2], clock @[Rocket.scala 248:26]
    reg ex_reg_rs_msb : UInt[2], clock @[Rocket.scala 249:26]
    node _T_3605 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) @[Cat.scala 30:58]
    node ex_rs_0 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], _T_3605) @[Rocket.scala 251:14]
    node _T_3607 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) @[Cat.scala 30:58]
    node ex_rs_1 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], _T_3607) @[Rocket.scala 251:14]
    node _T_3609 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 704:24]
    node _T_3611 = bits(ex_reg_inst, 31, 31) @[Rocket.scala 704:48]
    node _T_3612 = asSInt(_T_3611) @[Rocket.scala 704:53]
    node _T_3613 = mux(_T_3609, asSInt(UInt<1>("h00")), _T_3612) @[Rocket.scala 704:19]
    node _T_3615 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 705:26]
    node _T_3616 = bits(ex_reg_inst, 30, 20) @[Rocket.scala 705:41]
    node _T_3617 = asSInt(_T_3616) @[Rocket.scala 705:49]
    node _T_3618 = mux(_T_3615, _T_3617, _T_3613) @[Rocket.scala 705:21]
    node _T_3620 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 706:26]
    node _T_3622 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) @[Rocket.scala 706:43]
    node _T_3623 = and(_T_3620, _T_3622) @[Rocket.scala 706:36]
    node _T_3624 = bits(ex_reg_inst, 19, 12) @[Rocket.scala 706:65]
    node _T_3625 = asSInt(_T_3624) @[Rocket.scala 706:73]
    node _T_3626 = mux(_T_3623, _T_3613, _T_3625) @[Rocket.scala 706:21]
    node _T_3628 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 707:23]
    node _T_3630 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 707:40]
    node _T_3631 = or(_T_3628, _T_3630) @[Rocket.scala 707:33]
    node _T_3634 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) @[Rocket.scala 708:23]
    node _T_3635 = bits(ex_reg_inst, 20, 20) @[Rocket.scala 708:39]
    node _T_3636 = asSInt(_T_3635) @[Rocket.scala 708:44]
    node _T_3638 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) @[Rocket.scala 709:23]
    node _T_3639 = bits(ex_reg_inst, 7, 7) @[Rocket.scala 709:39]
    node _T_3640 = asSInt(_T_3639) @[Rocket.scala 709:43]
    node _T_3641 = mux(_T_3638, _T_3640, _T_3613) @[Rocket.scala 709:18]
    node _T_3642 = mux(_T_3634, _T_3636, _T_3641) @[Rocket.scala 708:18]
    node _T_3643 = mux(_T_3631, asSInt(UInt<1>("h00")), _T_3642) @[Rocket.scala 707:18]
    node _T_3645 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 710:25]
    node _T_3647 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 710:42]
    node _T_3648 = or(_T_3645, _T_3647) @[Rocket.scala 710:35]
    node _T_3650 = bits(ex_reg_inst, 30, 25) @[Rocket.scala 710:66]
    node _T_3651 = mux(_T_3648, UInt<1>("h00"), _T_3650) @[Rocket.scala 710:20]
    node _T_3653 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 711:24]
    node _T_3656 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) @[Rocket.scala 712:24]
    node _T_3658 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) @[Rocket.scala 712:41]
    node _T_3659 = or(_T_3656, _T_3658) @[Rocket.scala 712:34]
    node _T_3660 = bits(ex_reg_inst, 11, 8) @[Rocket.scala 712:57]
    node _T_3662 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 713:24]
    node _T_3663 = bits(ex_reg_inst, 19, 16) @[Rocket.scala 713:39]
    node _T_3664 = bits(ex_reg_inst, 24, 21) @[Rocket.scala 713:52]
    node _T_3665 = mux(_T_3662, _T_3663, _T_3664) @[Rocket.scala 713:19]
    node _T_3666 = mux(_T_3659, _T_3660, _T_3665) @[Rocket.scala 712:19]
    node _T_3667 = mux(_T_3653, UInt<1>("h00"), _T_3666) @[Rocket.scala 711:19]
    node _T_3669 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) @[Rocket.scala 714:22]
    node _T_3670 = bits(ex_reg_inst, 7, 7) @[Rocket.scala 714:37]
    node _T_3672 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) @[Rocket.scala 715:22]
    node _T_3673 = bits(ex_reg_inst, 20, 20) @[Rocket.scala 715:37]
    node _T_3675 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 716:22]
    node _T_3676 = bits(ex_reg_inst, 15, 15) @[Rocket.scala 716:37]
    node _T_3678 = mux(_T_3675, _T_3676, UInt<1>("h00")) @[Rocket.scala 716:17]
    node _T_3679 = mux(_T_3672, _T_3673, _T_3678) @[Rocket.scala 715:17]
    node _T_3680 = mux(_T_3669, _T_3670, _T_3679) @[Rocket.scala 714:17]
    node _T_3681 = cat(_T_3651, _T_3667) @[Cat.scala 30:58]
    node _T_3682 = cat(_T_3681, _T_3680) @[Cat.scala 30:58]
    node _T_3683 = asUInt(_T_3643) @[Cat.scala 30:58]
    node _T_3684 = asUInt(_T_3626) @[Cat.scala 30:58]
    node _T_3685 = cat(_T_3684, _T_3683) @[Cat.scala 30:58]
    node _T_3686 = asUInt(_T_3618) @[Cat.scala 30:58]
    node _T_3687 = asUInt(_T_3613) @[Cat.scala 30:58]
    node _T_3688 = cat(_T_3687, _T_3686) @[Cat.scala 30:58]
    node _T_3689 = cat(_T_3688, _T_3685) @[Cat.scala 30:58]
    node _T_3690 = cat(_T_3689, _T_3682) @[Cat.scala 30:58]
    node ex_imm = asSInt(_T_3690) @[Rocket.scala 718:53]
    node _T_3693 = asSInt(ex_rs_0) @[Rocket.scala 254:24]
    node _T_3695 = asSInt(ex_reg_pc) @[Rocket.scala 255:24]
    node _T_3696 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) @[Mux.scala 46:19]
    node _T_3697 = mux(_T_3696, _T_3695, asSInt(UInt<1>("h00"))) @[Mux.scala 46:16]
    node _T_3698 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) @[Mux.scala 46:19]
    node ex_op1 = mux(_T_3698, _T_3693, _T_3697) @[Mux.scala 46:16]
    node _T_3701 = asSInt(ex_rs_1) @[Rocket.scala 257:24]
    node _T_3706 = mux(ex_reg_rvc, asSInt(UInt<3>("h02")), asSInt(UInt<4>("h04"))) @[Rocket.scala 259:19]
    node _T_3707 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) @[Mux.scala 46:19]
    node _T_3708 = mux(_T_3707, _T_3706, asSInt(UInt<1>("h00"))) @[Mux.scala 46:16]
    node _T_3709 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) @[Mux.scala 46:19]
    node _T_3710 = mux(_T_3709, ex_imm, _T_3708) @[Mux.scala 46:16]
    node _T_3711 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) @[Mux.scala 46:19]
    node ex_op2 = mux(_T_3711, _T_3701, _T_3710) @[Mux.scala 46:16]
    inst alu of ALU @[Rocket.scala 261:19]
    alu.io is invalid
    alu.clock <= clock
    alu.reset <= reset
    alu.io.dw <= ex_ctrl.alu_dw @[Rocket.scala 262:13]
    alu.io.fn <= ex_ctrl.alu_fn @[Rocket.scala 263:13]
    node _T_3712 = asUInt(ex_op2) @[Rocket.scala 264:24]
    alu.io.in2 <= _T_3712 @[Rocket.scala 264:14]
    node _T_3713 = asUInt(ex_op1) @[Rocket.scala 265:24]
    alu.io.in1 <= _T_3713 @[Rocket.scala 265:14]
    inst div of MulDiv @[Rocket.scala 268:19]
    div.io is invalid
    div.clock <= clock
    div.reset <= reset
    node _T_3714 = and(ex_reg_valid, ex_ctrl.div) @[Rocket.scala 269:36]
    div.io.req.valid <= _T_3714 @[Rocket.scala 269:20]
    div.io.req.bits.dw <= ex_ctrl.alu_dw @[Rocket.scala 270:22]
    div.io.req.bits.fn <= ex_ctrl.alu_fn @[Rocket.scala 271:22]
    div.io.req.bits.in1 <= ex_rs_0 @[Rocket.scala 272:23]
    div.io.req.bits.in2 <= ex_rs_1 @[Rocket.scala 273:23]
    div.io.req.bits.tag <= ex_waddr @[Rocket.scala 274:23]
    node _T_3716 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 276:19]
    ex_reg_valid <= _T_3716 @[Rocket.scala 276:16]
    node _T_3718 = eq(take_pc, UInt<1>("h00")) @[Rocket.scala 277:20]
    node _T_3719 = and(_T_3718, ibuf.io.inst[0].valid) @[Rocket.scala 277:29]
    node _T_3720 = and(_T_3719, ibuf.io.inst[0].bits.replay) @[Rocket.scala 277:54]
    ex_reg_replay <= _T_3720 @[Rocket.scala 277:17]
    node _T_3722 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 278:18]
    node _T_3723 = and(_T_3722, id_xcpt) @[Rocket.scala 278:30]
    ex_reg_xcpt <= _T_3723 @[Rocket.scala 278:15]
    node _T_3725 = eq(take_pc, UInt<1>("h00")) @[Rocket.scala 279:28]
    node _T_3726 = and(_T_3725, ibuf.io.inst[0].valid) @[Rocket.scala 279:37]
    node _T_3727 = and(_T_3726, csr.io.interrupt) @[Rocket.scala 279:62]
    ex_reg_xcpt_interrupt <= _T_3727 @[Rocket.scala 279:25]
    when id_xcpt : @[Rocket.scala 280:18]
      ex_cause <= id_cause @[Rocket.scala 280:33]
      skip @[Rocket.scala 280:18]
    ex_reg_btb_hit <= ibuf.io.inst[0].bits.btb_hit @[Rocket.scala 281:18]
    when ibuf.io.inst[0].bits.btb_hit : @[Rocket.scala 282:39]
      ex_reg_btb_resp <- ibuf.io.btb_resp @[Rocket.scala 282:57]
      skip @[Rocket.scala 282:39]
    node _T_3729 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 284:9]
    when _T_3729 : @[Rocket.scala 284:22]
      ex_ctrl <- id_ctrl @[Rocket.scala 285:13]
      ex_reg_rvc <= ibuf.io.inst[0].bits.rvc @[Rocket.scala 286:16]
      ex_ctrl.csr <= id_csr @[Rocket.scala 287:17]
      when id_xcpt : @[Rocket.scala 288:20]
        ex_ctrl.alu_fn <= UInt<1>("h00") @[Rocket.scala 289:22]
        ex_ctrl.alu_dw <= UInt<1>("h01") @[Rocket.scala 290:22]
        ex_ctrl.sel_alu1 <= UInt<2>("h02") @[Rocket.scala 291:24]
        ex_ctrl.sel_alu2 <= UInt<2>("h00") @[Rocket.scala 292:24]
        node _T_3735 = eq(bpu.io.xcpt_if, UInt<1>("h00")) @[Rocket.scala 293:13]
        node _T_3737 = eq(ibuf.io.inst[0].bits.pf0, UInt<1>("h00")) @[Rocket.scala 293:32]
        node _T_3738 = and(_T_3735, _T_3737) @[Rocket.scala 293:29]
        node _T_3739 = and(_T_3738, ibuf.io.inst[0].bits.pf1) @[Rocket.scala 293:58]
        when _T_3739 : @[Rocket.scala 293:87]
          ex_ctrl.sel_alu2 <= UInt<2>("h01") @[Rocket.scala 294:26]
          ex_reg_rvc <= UInt<1>("h01") @[Rocket.scala 295:20]
          skip @[Rocket.scala 293:87]
        skip @[Rocket.scala 288:20]
      node _T_3742 = or(id_ctrl.fence_i, id_csr_flush) @[Rocket.scala 298:42]
      node _T_3743 = or(_T_3742, csr.io.singleStep) @[Rocket.scala 298:58]
      ex_reg_flush_pipe <= _T_3743 @[Rocket.scala 298:23]
      ex_reg_load_use <= id_load_use @[Rocket.scala 299:21]
      node _T_3744 = and(id_ctrl.jalr, csr.io.status.debug) @[Rocket.scala 301:24]
      when _T_3744 : @[Rocket.scala 301:48]
        ex_reg_flush_pipe <= UInt<1>("h01") @[Rocket.scala 302:25]
        ex_ctrl.fence_i <= UInt<1>("h01") @[Rocket.scala 303:23]
        skip @[Rocket.scala 301:48]
      node _T_3747 = or(id_bypass_src_0_0, id_bypass_src_0_1) @[Rocket.scala 307:48]
      node _T_3748 = or(_T_3747, id_bypass_src_0_2) @[Rocket.scala 307:48]
      node _T_3749 = or(_T_3748, id_bypass_src_0_3) @[Rocket.scala 307:48]
      node _T_3754 = mux(id_bypass_src_0_2, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 31:69]
      node _T_3755 = mux(id_bypass_src_0_1, UInt<1>("h01"), _T_3754) @[Mux.scala 31:69]
      node _T_3756 = mux(id_bypass_src_0_0, UInt<1>("h00"), _T_3755) @[Mux.scala 31:69]
      ex_reg_rs_bypass[0] <= _T_3749 @[Rocket.scala 309:27]
      ex_reg_rs_lsb[0] <= _T_3756 @[Rocket.scala 310:24]
      node _T_3758 = eq(_T_3749, UInt<1>("h00")) @[Rocket.scala 311:26]
      node _T_3759 = and(id_ctrl.rxs1, _T_3758) @[Rocket.scala 311:23]
      when _T_3759 : @[Rocket.scala 311:38]
        node _T_3760 = bits(id_rs_0, 1, 0) @[Rocket.scala 312:37]
        ex_reg_rs_lsb[0] <= _T_3760 @[Rocket.scala 312:26]
        node _T_3761 = shr(id_rs_0, 2) @[Rocket.scala 313:38]
        ex_reg_rs_msb[0] <= _T_3761 @[Rocket.scala 313:26]
        skip @[Rocket.scala 311:38]
      node _T_3762 = or(id_bypass_src_1_0, id_bypass_src_1_1) @[Rocket.scala 307:48]
      node _T_3763 = or(_T_3762, id_bypass_src_1_2) @[Rocket.scala 307:48]
      node _T_3764 = or(_T_3763, id_bypass_src_1_3) @[Rocket.scala 307:48]
      node _T_3769 = mux(id_bypass_src_1_2, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 31:69]
      node _T_3770 = mux(id_bypass_src_1_1, UInt<1>("h01"), _T_3769) @[Mux.scala 31:69]
      node _T_3771 = mux(id_bypass_src_1_0, UInt<1>("h00"), _T_3770) @[Mux.scala 31:69]
      ex_reg_rs_bypass[1] <= _T_3764 @[Rocket.scala 309:27]
      ex_reg_rs_lsb[1] <= _T_3771 @[Rocket.scala 310:24]
      node _T_3773 = eq(_T_3764, UInt<1>("h00")) @[Rocket.scala 311:26]
      node _T_3774 = and(id_ctrl.rxs2, _T_3773) @[Rocket.scala 311:23]
      when _T_3774 : @[Rocket.scala 311:38]
        node _T_3775 = bits(id_rs_1, 1, 0) @[Rocket.scala 312:37]
        ex_reg_rs_lsb[1] <= _T_3775 @[Rocket.scala 312:26]
        node _T_3776 = shr(id_rs_1, 2) @[Rocket.scala 313:38]
        ex_reg_rs_msb[1] <= _T_3776 @[Rocket.scala 313:26]
        skip @[Rocket.scala 311:38]
      skip @[Rocket.scala 284:22]
    node _T_3778 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 317:9]
    node _T_3779 = or(_T_3778, csr.io.interrupt) @[Rocket.scala 317:21]
    node _T_3780 = or(_T_3779, ibuf.io.inst[0].bits.replay) @[Rocket.scala 317:41]
    when _T_3780 : @[Rocket.scala 317:73]
      ex_reg_inst <= ibuf.io.inst[0].bits.inst.bits @[Rocket.scala 318:17]
      ex_reg_pc <= ibuf.io.pc @[Rocket.scala 319:15]
      skip @[Rocket.scala 317:73]
    node _T_3781 = or(ex_reg_valid, ex_reg_replay) @[Rocket.scala 323:34]
    node ex_pc_valid = or(_T_3781, ex_reg_xcpt_interrupt) @[Rocket.scala 323:51]
    node _T_3783 = eq(io.dmem.resp.valid, UInt<1>("h00")) @[Rocket.scala 324:39]
    node wb_dcache_miss = and(wb_ctrl.mem, _T_3783) @[Rocket.scala 324:36]
    node _T_3785 = eq(io.dmem.req.ready, UInt<1>("h00")) @[Rocket.scala 325:45]
    node _T_3786 = and(ex_ctrl.mem, _T_3785) @[Rocket.scala 325:42]
    node _T_3788 = eq(div.io.req.ready, UInt<1>("h00")) @[Rocket.scala 326:45]
    node _T_3789 = and(ex_ctrl.div, _T_3788) @[Rocket.scala 326:42]
    node replay_ex_structural = or(_T_3786, _T_3789) @[Rocket.scala 325:64]
    node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) @[Rocket.scala 327:43]
    node _T_3790 = or(replay_ex_structural, replay_ex_load_use) @[Rocket.scala 328:75]
    node _T_3791 = and(ex_reg_valid, _T_3790) @[Rocket.scala 328:50]
    node replay_ex = or(ex_reg_replay, _T_3791) @[Rocket.scala 328:33]
    node _T_3792 = or(take_pc_mem_wb, replay_ex) @[Rocket.scala 329:35]
    node _T_3794 = eq(ex_reg_valid, UInt<1>("h00")) @[Rocket.scala 329:51]
    node ctrl_killx = or(_T_3792, _T_3794) @[Rocket.scala 329:48]
    node _T_3796 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Rocket.scala 331:40]
    wire _T_3803 : UInt<3>[4] @[Rocket.scala 331:56]
    _T_3803 is invalid @[Rocket.scala 331:56]
    _T_3803[0] <= UInt<1>("h00") @[Rocket.scala 331:56]
    _T_3803[1] <= UInt<3>("h04") @[Rocket.scala 331:56]
    _T_3803[2] <= UInt<1>("h01") @[Rocket.scala 331:56]
    _T_3803[3] <= UInt<3>("h05") @[Rocket.scala 331:56]
    node _T_3810 = eq(_T_3803[0], ex_ctrl.mem_type) @[Rocket.scala 331:91]
    node _T_3811 = eq(_T_3803[1], ex_ctrl.mem_type) @[Rocket.scala 331:91]
    node _T_3812 = eq(_T_3803[2], ex_ctrl.mem_type) @[Rocket.scala 331:91]
    node _T_3813 = eq(_T_3803[3], ex_ctrl.mem_type) @[Rocket.scala 331:91]
    node _T_3815 = or(UInt<1>("h00"), _T_3810) @[Rocket.scala 331:91]
    node _T_3816 = or(_T_3815, _T_3811) @[Rocket.scala 331:91]
    node _T_3817 = or(_T_3816, _T_3812) @[Rocket.scala 331:91]
    node _T_3818 = or(_T_3817, _T_3813) @[Rocket.scala 331:91]
    node ex_slow_bypass = or(_T_3796, _T_3818) @[Rocket.scala 331:50]
    node ex_xcpt = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) @[Rocket.scala 334:28]
    node _T_3819 = or(mem_reg_valid, mem_reg_replay) @[Rocket.scala 337:36]
    node mem_pc_valid = or(_T_3819, mem_reg_xcpt_interrupt) @[Rocket.scala 337:54]
    node mem_br_taken = bits(mem_reg_wdata, 0, 0) @[Rocket.scala 338:35]
    node _T_3820 = asSInt(mem_reg_pc) @[Rocket.scala 339:34]
    node _T_3821 = and(mem_ctrl.branch, mem_br_taken) @[Rocket.scala 340:25]
    node _T_3824 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 704:24]
    node _T_3826 = bits(mem_reg_inst, 31, 31) @[Rocket.scala 704:48]
    node _T_3827 = asSInt(_T_3826) @[Rocket.scala 704:53]
    node _T_3828 = mux(_T_3824, asSInt(UInt<1>("h00")), _T_3827) @[Rocket.scala 704:19]
    node _T_3830 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 705:26]
    node _T_3831 = bits(mem_reg_inst, 30, 20) @[Rocket.scala 705:41]
    node _T_3832 = asSInt(_T_3831) @[Rocket.scala 705:49]
    node _T_3833 = mux(_T_3830, _T_3832, _T_3828) @[Rocket.scala 705:21]
    node _T_3835 = neq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 706:26]
    node _T_3837 = neq(UInt<3>("h01"), UInt<3>("h03")) @[Rocket.scala 706:43]
    node _T_3838 = and(_T_3835, _T_3837) @[Rocket.scala 706:36]
    node _T_3839 = bits(mem_reg_inst, 19, 12) @[Rocket.scala 706:65]
    node _T_3840 = asSInt(_T_3839) @[Rocket.scala 706:73]
    node _T_3841 = mux(_T_3838, _T_3828, _T_3840) @[Rocket.scala 706:21]
    node _T_3843 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 707:23]
    node _T_3845 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 707:40]
    node _T_3846 = or(_T_3843, _T_3845) @[Rocket.scala 707:33]
    node _T_3849 = eq(UInt<3>("h01"), UInt<3>("h03")) @[Rocket.scala 708:23]
    node _T_3850 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 708:39]
    node _T_3851 = asSInt(_T_3850) @[Rocket.scala 708:44]
    node _T_3853 = eq(UInt<3>("h01"), UInt<3>("h01")) @[Rocket.scala 709:23]
    node _T_3854 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 709:39]
    node _T_3855 = asSInt(_T_3854) @[Rocket.scala 709:43]
    node _T_3856 = mux(_T_3853, _T_3855, _T_3828) @[Rocket.scala 709:18]
    node _T_3857 = mux(_T_3849, _T_3851, _T_3856) @[Rocket.scala 708:18]
    node _T_3858 = mux(_T_3846, asSInt(UInt<1>("h00")), _T_3857) @[Rocket.scala 707:18]
    node _T_3860 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 710:25]
    node _T_3862 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 710:42]
    node _T_3863 = or(_T_3860, _T_3862) @[Rocket.scala 710:35]
    node _T_3865 = bits(mem_reg_inst, 30, 25) @[Rocket.scala 710:66]
    node _T_3866 = mux(_T_3863, UInt<1>("h00"), _T_3865) @[Rocket.scala 710:20]
    node _T_3868 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 711:24]
    node _T_3871 = eq(UInt<3>("h01"), UInt<3>("h00")) @[Rocket.scala 712:24]
    node _T_3873 = eq(UInt<3>("h01"), UInt<3>("h01")) @[Rocket.scala 712:41]
    node _T_3874 = or(_T_3871, _T_3873) @[Rocket.scala 712:34]
    node _T_3875 = bits(mem_reg_inst, 11, 8) @[Rocket.scala 712:57]
    node _T_3877 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 713:24]
    node _T_3878 = bits(mem_reg_inst, 19, 16) @[Rocket.scala 713:39]
    node _T_3879 = bits(mem_reg_inst, 24, 21) @[Rocket.scala 713:52]
    node _T_3880 = mux(_T_3877, _T_3878, _T_3879) @[Rocket.scala 713:19]
    node _T_3881 = mux(_T_3874, _T_3875, _T_3880) @[Rocket.scala 712:19]
    node _T_3882 = mux(_T_3868, UInt<1>("h00"), _T_3881) @[Rocket.scala 711:19]
    node _T_3884 = eq(UInt<3>("h01"), UInt<3>("h00")) @[Rocket.scala 714:22]
    node _T_3885 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 714:37]
    node _T_3887 = eq(UInt<3>("h01"), UInt<3>("h04")) @[Rocket.scala 715:22]
    node _T_3888 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 715:37]
    node _T_3890 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 716:22]
    node _T_3891 = bits(mem_reg_inst, 15, 15) @[Rocket.scala 716:37]
    node _T_3893 = mux(_T_3890, _T_3891, UInt<1>("h00")) @[Rocket.scala 716:17]
    node _T_3894 = mux(_T_3887, _T_3888, _T_3893) @[Rocket.scala 715:17]
    node _T_3895 = mux(_T_3884, _T_3885, _T_3894) @[Rocket.scala 714:17]
    node _T_3896 = cat(_T_3866, _T_3882) @[Cat.scala 30:58]
    node _T_3897 = cat(_T_3896, _T_3895) @[Cat.scala 30:58]
    node _T_3898 = asUInt(_T_3858) @[Cat.scala 30:58]
    node _T_3899 = asUInt(_T_3841) @[Cat.scala 30:58]
    node _T_3900 = cat(_T_3899, _T_3898) @[Cat.scala 30:58]
    node _T_3901 = asUInt(_T_3833) @[Cat.scala 30:58]
    node _T_3902 = asUInt(_T_3828) @[Cat.scala 30:58]
    node _T_3903 = cat(_T_3902, _T_3901) @[Cat.scala 30:58]
    node _T_3904 = cat(_T_3903, _T_3900) @[Cat.scala 30:58]
    node _T_3905 = cat(_T_3904, _T_3897) @[Cat.scala 30:58]
    node _T_3906 = asSInt(_T_3905) @[Rocket.scala 718:53]
    node _T_3908 = and(UInt<1>("h01"), mem_ctrl.jal) @[Rocket.scala 341:24]
    node _T_3911 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 704:24]
    node _T_3913 = bits(mem_reg_inst, 31, 31) @[Rocket.scala 704:48]
    node _T_3914 = asSInt(_T_3913) @[Rocket.scala 704:53]
    node _T_3915 = mux(_T_3911, asSInt(UInt<1>("h00")), _T_3914) @[Rocket.scala 704:19]
    node _T_3917 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 705:26]
    node _T_3918 = bits(mem_reg_inst, 30, 20) @[Rocket.scala 705:41]
    node _T_3919 = asSInt(_T_3918) @[Rocket.scala 705:49]
    node _T_3920 = mux(_T_3917, _T_3919, _T_3915) @[Rocket.scala 705:21]
    node _T_3922 = neq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 706:26]
    node _T_3924 = neq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 706:43]
    node _T_3925 = and(_T_3922, _T_3924) @[Rocket.scala 706:36]
    node _T_3926 = bits(mem_reg_inst, 19, 12) @[Rocket.scala 706:65]
    node _T_3927 = asSInt(_T_3926) @[Rocket.scala 706:73]
    node _T_3928 = mux(_T_3925, _T_3915, _T_3927) @[Rocket.scala 706:21]
    node _T_3930 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 707:23]
    node _T_3932 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 707:40]
    node _T_3933 = or(_T_3930, _T_3932) @[Rocket.scala 707:33]
    node _T_3936 = eq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 708:23]
    node _T_3937 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 708:39]
    node _T_3938 = asSInt(_T_3937) @[Rocket.scala 708:44]
    node _T_3940 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 709:23]
    node _T_3941 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 709:39]
    node _T_3942 = asSInt(_T_3941) @[Rocket.scala 709:43]
    node _T_3943 = mux(_T_3940, _T_3942, _T_3915) @[Rocket.scala 709:18]
    node _T_3944 = mux(_T_3936, _T_3938, _T_3943) @[Rocket.scala 708:18]
    node _T_3945 = mux(_T_3933, asSInt(UInt<1>("h00")), _T_3944) @[Rocket.scala 707:18]
    node _T_3947 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 710:25]
    node _T_3949 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 710:42]
    node _T_3950 = or(_T_3947, _T_3949) @[Rocket.scala 710:35]
    node _T_3952 = bits(mem_reg_inst, 30, 25) @[Rocket.scala 710:66]
    node _T_3953 = mux(_T_3950, UInt<1>("h00"), _T_3952) @[Rocket.scala 710:20]
    node _T_3955 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 711:24]
    node _T_3958 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 712:24]
    node _T_3960 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 712:41]
    node _T_3961 = or(_T_3958, _T_3960) @[Rocket.scala 712:34]
    node _T_3962 = bits(mem_reg_inst, 11, 8) @[Rocket.scala 712:57]
    node _T_3964 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 713:24]
    node _T_3965 = bits(mem_reg_inst, 19, 16) @[Rocket.scala 713:39]
    node _T_3966 = bits(mem_reg_inst, 24, 21) @[Rocket.scala 713:52]
    node _T_3967 = mux(_T_3964, _T_3965, _T_3966) @[Rocket.scala 713:19]
    node _T_3968 = mux(_T_3961, _T_3962, _T_3967) @[Rocket.scala 712:19]
    node _T_3969 = mux(_T_3955, UInt<1>("h00"), _T_3968) @[Rocket.scala 711:19]
    node _T_3971 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 714:22]
    node _T_3972 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 714:37]
    node _T_3974 = eq(UInt<3>("h03"), UInt<3>("h04")) @[Rocket.scala 715:22]
    node _T_3975 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 715:37]
    node _T_3977 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 716:22]
    node _T_3978 = bits(mem_reg_inst, 15, 15) @[Rocket.scala 716:37]
    node _T_3980 = mux(_T_3977, _T_3978, UInt<1>("h00")) @[Rocket.scala 716:17]
    node _T_3981 = mux(_T_3974, _T_3975, _T_3980) @[Rocket.scala 715:17]
    node _T_3982 = mux(_T_3971, _T_3972, _T_3981) @[Rocket.scala 714:17]
    node _T_3983 = cat(_T_3953, _T_3969) @[Cat.scala 30:58]
    node _T_3984 = cat(_T_3983, _T_3982) @[Cat.scala 30:58]
    node _T_3985 = asUInt(_T_3945) @[Cat.scala 30:58]
    node _T_3986 = asUInt(_T_3928) @[Cat.scala 30:58]
    node _T_3987 = cat(_T_3986, _T_3985) @[Cat.scala 30:58]
    node _T_3988 = asUInt(_T_3920) @[Cat.scala 30:58]
    node _T_3989 = asUInt(_T_3915) @[Cat.scala 30:58]
    node _T_3990 = cat(_T_3989, _T_3988) @[Cat.scala 30:58]
    node _T_3991 = cat(_T_3990, _T_3987) @[Cat.scala 30:58]
    node _T_3992 = cat(_T_3991, _T_3984) @[Cat.scala 30:58]
    node _T_3993 = asSInt(_T_3992) @[Rocket.scala 718:53]
    node _T_3996 = mux(mem_reg_rvc, asSInt(UInt<3>("h02")), asSInt(UInt<4>("h04"))) @[Rocket.scala 342:8]
    node _T_3997 = mux(_T_3908, _T_3993, _T_3996) @[Rocket.scala 341:8]
    node _T_3998 = mux(_T_3821, _T_3906, _T_3997) @[Rocket.scala 340:8]
    node _T_3999 = add(_T_3820, _T_3998) @[Rocket.scala 339:41]
    node _T_4000 = tail(_T_3999, 1) @[Rocket.scala 339:41]
    node mem_br_target = asSInt(_T_4000) @[Rocket.scala 339:41]
    node _T_4001 = shr(mem_reg_wdata, 38) @[Rocket.scala 653:16]
    node _T_4002 = bits(mem_reg_wdata, 39, 38) @[Rocket.scala 654:15]
    node _T_4003 = asSInt(_T_4002) @[Rocket.scala 654:39]
    node _T_4005 = eq(_T_4001, UInt<1>("h00")) @[Rocket.scala 656:13]
    node _T_4007 = eq(_T_4001, UInt<1>("h01")) @[Rocket.scala 656:30]
    node _T_4008 = or(_T_4005, _T_4007) @[Rocket.scala 656:25]
    node _T_4010 = neq(_T_4003, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45]
    node _T_4011 = asSInt(_T_4001) @[Rocket.scala 657:13]
    node _T_4013 = eq(_T_4011, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20]
    node _T_4014 = asSInt(_T_4001) @[Rocket.scala 657:38]
    node _T_4016 = eq(_T_4014, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45]
    node _T_4017 = or(_T_4013, _T_4016) @[Rocket.scala 657:33]
    node _T_4019 = eq(_T_4003, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61]
    node _T_4020 = bits(_T_4003, 0, 0) @[Rocket.scala 657:76]
    node _T_4021 = mux(_T_4017, _T_4019, _T_4020) @[Rocket.scala 657:10]
    node _T_4022 = mux(_T_4008, _T_4010, _T_4021) @[Rocket.scala 656:10]
    node _T_4023 = bits(mem_reg_wdata, 38, 0) @[Rocket.scala 658:16]
    node _T_4024 = cat(_T_4022, _T_4023) @[Cat.scala 30:58]
    node _T_4025 = asSInt(_T_4024) @[Rocket.scala 343:88]
    node _T_4026 = mux(mem_ctrl.jalr, _T_4025, mem_br_target) @[Rocket.scala 343:21]
    node _T_4028 = and(_T_4026, asSInt(UInt<2>("h02"))) @[Rocket.scala 343:111]
    node _T_4029 = asSInt(_T_4028) @[Rocket.scala 343:111]
    node mem_npc = asUInt(_T_4029) @[Rocket.scala 343:123]
    node _T_4030 = neq(mem_npc, ex_reg_pc) @[Rocket.scala 344:48]
    node _T_4031 = neq(mem_npc, ibuf.io.pc) @[Rocket.scala 344:98]
    node _T_4033 = mux(ibuf.io.inst[0].valid, _T_4031, UInt<1>("h01")) @[Rocket.scala 344:66]
    node mem_misprediction = mux(ex_pc_valid, _T_4030, _T_4033) @[Rocket.scala 344:26]
    node _T_4034 = bits(csr.io.status.isa, 2, 2) @[Rocket.scala 345:46]
    node _T_4036 = eq(_T_4034, UInt<1>("h00")) @[Rocket.scala 345:28]
    node _T_4037 = bits(mem_npc, 1, 1) @[Rocket.scala 345:66]
    node mem_npc_misaligned = and(_T_4036, _T_4037) @[Rocket.scala 345:56]
    node _T_4039 = eq(mem_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 346:27]
    node _T_4040 = xor(mem_ctrl.jalr, mem_npc_misaligned) @[Rocket.scala 346:59]
    node _T_4041 = and(_T_4039, _T_4040) @[Rocket.scala 346:41]
    node _T_4042 = asSInt(mem_reg_wdata) @[Rocket.scala 346:111]
    node _T_4043 = mux(_T_4041, mem_br_target, _T_4042) @[Rocket.scala 346:26]
    node mem_int_wdata = asUInt(_T_4043) @[Rocket.scala 346:119]
    node _T_4044 = or(mem_ctrl.branch, mem_ctrl.jalr) @[Rocket.scala 347:33]
    node mem_cfi = or(_T_4044, mem_ctrl.jal) @[Rocket.scala 347:50]
    node _T_4045 = and(mem_ctrl.branch, mem_br_taken) @[Rocket.scala 348:40]
    node _T_4046 = or(_T_4045, mem_ctrl.jalr) @[Rocket.scala 348:57]
    node _T_4048 = and(UInt<1>("h01"), mem_ctrl.jal) @[Rocket.scala 348:93]
    node mem_cfi_taken = or(_T_4046, _T_4048) @[Rocket.scala 348:74]
    node _T_4049 = and(mem_reg_btb_hit, mem_ctrl.branch) @[Rocket.scala 349:53]
    node _T_4050 = neq(mem_br_taken, mem_reg_btb_resp.taken) @[Rocket.scala 349:88]
    node mem_direction_misprediction = and(_T_4049, _T_4050) @[Rocket.scala 349:72]
    node _T_4051 = or(mem_misprediction, mem_reg_flush_pipe) @[Rocket.scala 351:54]
    node _T_4052 = and(mem_reg_valid, _T_4051) @[Rocket.scala 351:32]
    take_pc_mem <= _T_4052 @[Rocket.scala 351:15]
    node _T_4054 = eq(ctrl_killx, UInt<1>("h00")) @[Rocket.scala 353:20]
    mem_reg_valid <= _T_4054 @[Rocket.scala 353:17]
    node _T_4056 = eq(take_pc_mem_wb, UInt<1>("h00")) @[Rocket.scala 354:21]
    node _T_4057 = and(_T_4056, replay_ex) @[Rocket.scala 354:37]
    mem_reg_replay <= _T_4057 @[Rocket.scala 354:18]
    node _T_4059 = eq(ctrl_killx, UInt<1>("h00")) @[Rocket.scala 355:19]
    node _T_4060 = and(_T_4059, ex_xcpt) @[Rocket.scala 355:31]
    mem_reg_xcpt <= _T_4060 @[Rocket.scala 355:16]
    node _T_4062 = eq(take_pc_mem_wb, UInt<1>("h00")) @[Rocket.scala 356:29]
    node _T_4063 = and(_T_4062, ex_reg_xcpt_interrupt) @[Rocket.scala 356:45]
    mem_reg_xcpt_interrupt <= _T_4063 @[Rocket.scala 356:26]
    when ex_xcpt : @[Rocket.scala 357:18]
      mem_reg_cause <= ex_cause @[Rocket.scala 357:34]
      skip @[Rocket.scala 357:18]
    when ex_pc_valid : @[Rocket.scala 359:22]
      mem_ctrl <- ex_ctrl @[Rocket.scala 360:14]
      mem_reg_rvc <= ex_reg_rvc @[Rocket.scala 361:17]
      node _T_4065 = eq(ex_ctrl.mem_cmd, UInt<1>("h00")) @[Consts.scala 35:31]
      node _T_4067 = eq(ex_ctrl.mem_cmd, UInt<3>("h06")) @[Consts.scala 35:48]
      node _T_4068 = or(_T_4065, _T_4067) @[Consts.scala 35:41]
      node _T_4070 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Consts.scala 35:65]
      node _T_4071 = or(_T_4068, _T_4070) @[Consts.scala 35:58]
      node _T_4072 = bits(ex_ctrl.mem_cmd, 3, 3) @[Consts.scala 33:29]
      node _T_4074 = eq(ex_ctrl.mem_cmd, UInt<3>("h04")) @[Consts.scala 33:40]
      node _T_4075 = or(_T_4072, _T_4074) @[Consts.scala 33:33]
      node _T_4076 = or(_T_4071, _T_4075) @[Consts.scala 35:75]
      node _T_4077 = and(ex_ctrl.mem, _T_4076) @[Rocket.scala 362:33]
      mem_reg_load <= _T_4077 @[Rocket.scala 362:18]
      node _T_4079 = eq(ex_ctrl.mem_cmd, UInt<1>("h01")) @[Consts.scala 36:32]
      node _T_4081 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Consts.scala 36:49]
      node _T_4082 = or(_T_4079, _T_4081) @[Consts.scala 36:42]
      node _T_4083 = bits(ex_ctrl.mem_cmd, 3, 3) @[Consts.scala 33:29]
      node _T_4085 = eq(ex_ctrl.mem_cmd, UInt<3>("h04")) @[Consts.scala 33:40]
      node _T_4086 = or(_T_4083, _T_4085) @[Consts.scala 33:33]
      node _T_4087 = or(_T_4082, _T_4086) @[Consts.scala 36:59]
      node _T_4088 = and(ex_ctrl.mem, _T_4087) @[Rocket.scala 363:34]
      mem_reg_store <= _T_4088 @[Rocket.scala 363:19]
      mem_reg_btb_hit <= ex_reg_btb_hit @[Rocket.scala 364:21]
      when ex_reg_btb_hit : @[Rocket.scala 365:27]
        mem_reg_btb_resp <- ex_reg_btb_resp @[Rocket.scala 365:46]
        skip @[Rocket.scala 365:27]
      mem_reg_flush_pipe <= ex_reg_flush_pipe @[Rocket.scala 366:24]
      mem_reg_slow_bypass <= ex_slow_bypass @[Rocket.scala 367:25]
      mem_reg_inst <= ex_reg_inst @[Rocket.scala 369:18]
      mem_reg_pc <= ex_reg_pc @[Rocket.scala 370:16]
      mem_reg_wdata <= alu.io.out @[Rocket.scala 371:19]
      node _T_4089 = or(ex_ctrl.mem, ex_ctrl.rocc) @[Rocket.scala 372:40]
      node _T_4090 = and(ex_ctrl.rxs2, _T_4089) @[Rocket.scala 372:24]
      when _T_4090 : @[Rocket.scala 372:58]
        mem_reg_rs2 <= ex_rs_1 @[Rocket.scala 373:19]
        skip @[Rocket.scala 372:58]
      skip @[Rocket.scala 359:22]
    node _T_4091 = and(mem_reg_load, bpu.io.xcpt_ld) @[Rocket.scala 377:38]
    node _T_4092 = and(mem_reg_store, bpu.io.xcpt_st) @[Rocket.scala 377:75]
    node mem_breakpoint = or(_T_4091, _T_4092) @[Rocket.scala 377:57]
    node _T_4093 = and(mem_reg_load, bpu.io.debug_ld) @[Rocket.scala 378:44]
    node _T_4094 = and(mem_reg_store, bpu.io.debug_st) @[Rocket.scala 378:82]
    node mem_debug_breakpoint = or(_T_4093, _T_4094) @[Rocket.scala 378:64]
    node _T_4126 = and(mem_ctrl.mem, io.dmem.xcpt.ma.st) @[Rocket.scala 383:19]
    node _T_4128 = and(mem_ctrl.mem, io.dmem.xcpt.ma.ld) @[Rocket.scala 384:19]
    node _T_4130 = and(mem_ctrl.mem, io.dmem.xcpt.pf.st) @[Rocket.scala 385:19]
    node _T_4132 = and(mem_ctrl.mem, io.dmem.xcpt.pf.ld) @[Rocket.scala 386:19]
    node _T_4134 = or(mem_debug_breakpoint, mem_breakpoint) @[Rocket.scala 645:26]
    node _T_4135 = or(_T_4134, mem_npc_misaligned) @[Rocket.scala 645:26]
    node _T_4136 = or(_T_4135, _T_4126) @[Rocket.scala 645:26]
    node _T_4137 = or(_T_4136, _T_4128) @[Rocket.scala 645:26]
    node _T_4138 = or(_T_4137, _T_4130) @[Rocket.scala 645:26]
    node mem_new_xcpt = or(_T_4138, _T_4132) @[Rocket.scala 645:26]
    node _T_4139 = mux(_T_4130, UInt<3>("h07"), UInt<3>("h05")) @[Mux.scala 31:69]
    node _T_4140 = mux(_T_4128, UInt<3>("h04"), _T_4139) @[Mux.scala 31:69]
    node _T_4141 = mux(_T_4126, UInt<3>("h06"), _T_4140) @[Mux.scala 31:69]
    node _T_4142 = mux(mem_npc_misaligned, UInt<1>("h00"), _T_4141) @[Mux.scala 31:69]
    node _T_4143 = mux(mem_breakpoint, UInt<2>("h03"), _T_4142) @[Mux.scala 31:69]
    node mem_new_cause = mux(mem_debug_breakpoint, UInt<4>("h0d"), _T_4143) @[Mux.scala 31:69]
    node _T_4144 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) @[Rocket.scala 389:29]
    node _T_4145 = and(mem_reg_valid, mem_new_xcpt) @[Rocket.scala 390:20]
    node mem_xcpt = or(_T_4144, _T_4145) @[Rocket.scala 645:26]
    node mem_cause = mux(_T_4144, mem_reg_cause, mem_new_cause) @[Mux.scala 31:69]
    node _T_4146 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 392:39]
    node dcache_kill_mem = and(_T_4146, io.dmem.replay_next) @[Rocket.scala 392:55]
    node _T_4147 = and(mem_reg_valid, mem_ctrl.fp) @[Rocket.scala 393:36]
    node fpu_kill_mem = and(_T_4147, io.fpu.nack_mem) @[Rocket.scala 393:51]
    node _T_4148 = or(dcache_kill_mem, mem_reg_replay) @[Rocket.scala 394:37]
    node replay_mem = or(_T_4148, fpu_kill_mem) @[Rocket.scala 394:55]
    node _T_4149 = or(dcache_kill_mem, take_pc_wb) @[Rocket.scala 395:38]
    node _T_4150 = or(_T_4149, mem_reg_xcpt) @[Rocket.scala 395:52]
    node _T_4152 = eq(mem_reg_valid, UInt<1>("h00")) @[Rocket.scala 395:71]
    node killm_common = or(_T_4150, _T_4152) @[Rocket.scala 395:68]
    node _T_4153 = and(div.io.req.ready, div.io.req.valid) @[Decoupled.scala 30:37]
    reg _T_4154 : UInt<1>, clock @[Rocket.scala 396:37]
    _T_4154 <= _T_4153 @[Rocket.scala 396:37]
    node _T_4155 = and(killm_common, _T_4154) @[Rocket.scala 396:31]
    div.io.kill <= _T_4155 @[Rocket.scala 396:15]
    node _T_4156 = or(killm_common, mem_xcpt) @[Rocket.scala 397:33]
    node ctrl_killm = or(_T_4156, fpu_kill_mem) @[Rocket.scala 397:45]
    node _T_4158 = eq(ctrl_killm, UInt<1>("h00")) @[Rocket.scala 400:19]
    wb_reg_valid <= _T_4158 @[Rocket.scala 400:16]
    node _T_4160 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 401:34]
    node _T_4161 = and(replay_mem, _T_4160) @[Rocket.scala 401:31]
    wb_reg_replay <= _T_4161 @[Rocket.scala 401:17]
    node _T_4163 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 402:30]
    node _T_4164 = and(mem_xcpt, _T_4163) @[Rocket.scala 402:27]
    wb_reg_xcpt <= _T_4164 @[Rocket.scala 402:15]
    when mem_xcpt : @[Rocket.scala 403:19]
      wb_reg_cause <= mem_cause @[Rocket.scala 403:34]
      skip @[Rocket.scala 403:19]
    when mem_pc_valid : @[Rocket.scala 404:23]
      wb_ctrl <- mem_ctrl @[Rocket.scala 405:13]
      node _T_4166 = eq(mem_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 406:25]
      node _T_4167 = and(_T_4166, mem_ctrl.fp) @[Rocket.scala 406:39]
      node _T_4168 = and(_T_4167, mem_ctrl.wxd) @[Rocket.scala 406:54]
      node _T_4169 = mux(_T_4168, io.fpu.toint_data, mem_int_wdata) @[Rocket.scala 406:24]
      wb_reg_wdata <= _T_4169 @[Rocket.scala 406:18]
      when mem_ctrl.rocc : @[Rocket.scala 407:26]
        wb_reg_rs2 <= mem_reg_rs2 @[Rocket.scala 408:18]
        skip @[Rocket.scala 407:26]
      wb_reg_inst <= mem_reg_inst @[Rocket.scala 410:17]
      wb_reg_pc <= mem_reg_pc @[Rocket.scala 411:15]
      skip @[Rocket.scala 404:23]
    node wb_wxd = and(wb_reg_valid, wb_ctrl.wxd) @[Rocket.scala 414:29]
    node _T_4170 = or(wb_ctrl.div, wb_dcache_miss) @[Rocket.scala 415:35]
    node wb_set_sboard = or(_T_4170, wb_ctrl.rocc) @[Rocket.scala 415:53]
    node replay_wb_common = or(io.dmem.s2_nack, wb_reg_replay) @[Rocket.scala 416:42]
    node _T_4171 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 417:37]
    node _T_4173 = eq(io.rocc.cmd.ready, UInt<1>("h00")) @[Rocket.scala 417:56]
    node replay_wb_rocc = and(_T_4171, _T_4173) @[Rocket.scala 417:53]
    node replay_wb = or(replay_wb_common, replay_wb_rocc) @[Rocket.scala 418:36]
    node _T_4174 = or(replay_wb, wb_reg_xcpt) @[Rocket.scala 420:27]
    node _T_4175 = or(_T_4174, csr.io.eret) @[Rocket.scala 420:38]
    take_pc_wb <= _T_4175 @[Rocket.scala 420:14]
    node _T_4176 = bits(io.dmem.resp.bits.tag, 0, 0) @[Rocket.scala 423:45]
    node _T_4177 = bits(_T_4176, 0, 0) @[Rocket.scala 423:49]
    node dmem_resp_xpu = eq(_T_4177, UInt<1>("h00")) @[Rocket.scala 423:23]
    node _T_4179 = bits(io.dmem.resp.bits.tag, 0, 0) @[Rocket.scala 424:45]
    node dmem_resp_fpu = bits(_T_4179, 0, 0) @[Rocket.scala 424:49]
    node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) @[Rocket.scala 425:46]
    node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) @[Rocket.scala 426:44]
    node dmem_resp_replay = and(dmem_resp_valid, io.dmem.resp.bits.replay) @[Rocket.scala 427:42]
    node _T_4181 = eq(wb_wxd, UInt<1>("h00")) @[Rocket.scala 429:24]
    div.io.resp.ready <= _T_4181 @[Rocket.scala 429:21]
    wire ll_wdata : UInt
    ll_wdata is invalid
    ll_wdata <= div.io.resp.bits.data
    wire ll_waddr : UInt
    ll_waddr is invalid
    ll_waddr <= div.io.resp.bits.tag
    node _T_4182 = and(div.io.resp.ready, div.io.resp.valid) @[Decoupled.scala 30:37]
    wire ll_wen : UInt<1>
    ll_wen is invalid
    ll_wen <= _T_4182
    node _T_4183 = and(dmem_resp_replay, dmem_resp_xpu) @[Rocket.scala 442:26]
    when _T_4183 : @[Rocket.scala 442:44]
      div.io.resp.ready <= UInt<1>("h00") @[Rocket.scala 443:23]
      ll_waddr <= dmem_resp_waddr @[Rocket.scala 446:14]
      ll_wen <= UInt<1>("h01") @[Rocket.scala 447:12]
      skip @[Rocket.scala 442:44]
    node _T_4187 = eq(replay_wb, UInt<1>("h00")) @[Rocket.scala 450:34]
    node _T_4188 = and(wb_reg_valid, _T_4187) @[Rocket.scala 450:31]
    node _T_4190 = eq(wb_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 450:48]
    node wb_valid = and(_T_4188, _T_4190) @[Rocket.scala 450:45]
    node wb_wen = and(wb_valid, wb_ctrl.wxd) @[Rocket.scala 451:25]
    node rf_wen = or(wb_wen, ll_wen) @[Rocket.scala 452:23]
    node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) @[Rocket.scala 453:21]
    node _T_4191 = and(dmem_resp_valid, dmem_resp_xpu) @[Rocket.scala 454:38]
    node _T_4193 = neq(wb_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 456:34]
    node _T_4194 = mux(_T_4193, csr.io.rw.rdata, wb_reg_wdata) @[Rocket.scala 456:21]
    node _T_4195 = mux(ll_wen, ll_wdata, _T_4194) @[Rocket.scala 455:21]
    node rf_wdata = mux(_T_4191, io.dmem.resp.bits.data, _T_4195) @[Rocket.scala 454:21]
    when rf_wen : @[Rocket.scala 458:17]
      node _T_4197 = neq(rf_waddr, UInt<1>("h00")) @[Rocket.scala 694:16]
      when _T_4197 : @[Rocket.scala 694:29]
        node _T_4198 = bits(rf_waddr, 4, 0) @[Rocket.scala 683:44]
        node _T_4199 = not(_T_4198) @[Rocket.scala 683:39]
        infer mport _T_4200 = _T_3331[_T_4199], clock
        _T_4200 <= rf_wdata @[Rocket.scala 695:20]
        node _T_4201 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 697:20]
        when _T_4201 : @[Rocket.scala 697:31]
          id_rs_0 <= rf_wdata @[Rocket.scala 697:39]
          skip @[Rocket.scala 697:31]
        node _T_4202 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 697:20]
        when _T_4202 : @[Rocket.scala 697:31]
          id_rs_1 <= rf_wdata @[Rocket.scala 697:39]
          skip @[Rocket.scala 697:31]
        skip @[Rocket.scala 694:29]
      skip @[Rocket.scala 458:17]
    node _T_4203 = bits(ibuf.io.inst[0].bits.raw, 31, 20) @[Rocket.scala 461:48]
    csr.io.decode.csr <= _T_4203 @[Rocket.scala 461:21]
    csr.io.exception <= wb_reg_xcpt @[Rocket.scala 462:20]
    csr.io.cause <= wb_reg_cause @[Rocket.scala 463:16]
    csr.io.retire <= wb_valid @[Rocket.scala 464:17]
    csr.io.interrupts <- io.interrupts @[Rocket.scala 465:21]
    csr.io.hartid <= io.hartid @[Rocket.scala 466:17]
    io.fpu.fcsr_rm <= csr.io.fcsr_rm @[Rocket.scala 467:18]
    csr.io.fcsr_flags <- io.fpu.fcsr_flags @[Rocket.scala 468:21]
    csr.io.rocc_interrupt <= io.rocc.interrupt @[Rocket.scala 469:25]
    csr.io.pc <= wb_reg_pc @[Rocket.scala 470:13]
    node _T_4204 = shr(wb_reg_wdata, 38) @[Rocket.scala 653:16]
    node _T_4205 = bits(wb_reg_wdata, 39, 38) @[Rocket.scala 654:15]
    node _T_4206 = asSInt(_T_4205) @[Rocket.scala 654:39]
    node _T_4208 = eq(_T_4204, UInt<1>("h00")) @[Rocket.scala 656:13]
    node _T_4210 = eq(_T_4204, UInt<1>("h01")) @[Rocket.scala 656:30]
    node _T_4211 = or(_T_4208, _T_4210) @[Rocket.scala 656:25]
    node _T_4213 = neq(_T_4206, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45]
    node _T_4214 = asSInt(_T_4204) @[Rocket.scala 657:13]
    node _T_4216 = eq(_T_4214, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20]
    node _T_4217 = asSInt(_T_4204) @[Rocket.scala 657:38]
    node _T_4219 = eq(_T_4217, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45]
    node _T_4220 = or(_T_4216, _T_4219) @[Rocket.scala 657:33]
    node _T_4222 = eq(_T_4206, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61]
    node _T_4223 = bits(_T_4206, 0, 0) @[Rocket.scala 657:76]
    node _T_4224 = mux(_T_4220, _T_4222, _T_4223) @[Rocket.scala 657:10]
    node _T_4225 = mux(_T_4211, _T_4213, _T_4224) @[Rocket.scala 656:10]
    node _T_4226 = bits(wb_reg_wdata, 38, 0) @[Rocket.scala 658:16]
    node _T_4227 = cat(_T_4225, _T_4226) @[Cat.scala 30:58]
    csr.io.badaddr <= _T_4227 @[Rocket.scala 471:18]
    io.ptw.ptbr <- csr.io.ptbr @[Rocket.scala 472:15]
    io.ptw.invalidate <= csr.io.fatc @[Rocket.scala 473:21]
    io.ptw.status <- csr.io.status @[Rocket.scala 474:17]
    node _T_4228 = bits(wb_reg_inst, 31, 20) @[Rocket.scala 475:32]
    csr.io.rw.addr <= _T_4228 @[Rocket.scala 475:18]
    node _T_4230 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 476:23]
    csr.io.rw.cmd <= _T_4230 @[Rocket.scala 476:17]
    csr.io.rw.wdata <= wb_reg_wdata @[Rocket.scala 477:19]
    node _T_4232 = neq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 479:55]
    node _T_4233 = and(id_ctrl.rxs1, _T_4232) @[Rocket.scala 479:42]
    node _T_4235 = neq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h00")) @[Rocket.scala 480:55]
    node _T_4236 = and(id_ctrl.rxs2, _T_4235) @[Rocket.scala 480:42]
    node _T_4238 = neq(ibuf.io.inst[0].bits.inst.rd, UInt<1>("h00")) @[Rocket.scala 481:55]
    node _T_4239 = and(id_ctrl.wxd, _T_4238) @[Rocket.scala 481:42]
    reg _T_4241 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Rocket.scala 668:25]
    node _T_4242 = shr(_T_4241, 1) @[Rocket.scala 669:35]
    node _T_4243 = shl(_T_4242, 1) @[Rocket.scala 669:40]
    node _T_4246 = dshl(UInt<1>("h01"), ll_waddr) @[Rocket.scala 672:62]
    node _T_4248 = mux(ll_wen, _T_4246, UInt<1>("h00")) @[Rocket.scala 672:49]
    node _T_4249 = not(_T_4248) @[Rocket.scala 664:64]
    node _T_4250 = and(_T_4243, _T_4249) @[Rocket.scala 664:62]
    node _T_4251 = or(UInt<1>("h00"), ll_wen) @[Rocket.scala 675:17]
    when _T_4251 : @[Rocket.scala 676:18]
      _T_4241 <= _T_4250 @[Rocket.scala 676:23]
      skip @[Rocket.scala 676:18]
    node _T_4252 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 665:35]
    node _T_4253 = bits(_T_4252, 0, 0) @[Rocket.scala 665:35]
    node _T_4254 = and(_T_4233, _T_4253) @[Rocket.scala 648:27]
    node _T_4255 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 665:35]
    node _T_4256 = bits(_T_4255, 0, 0) @[Rocket.scala 665:35]
    node _T_4257 = and(_T_4236, _T_4256) @[Rocket.scala 648:27]
    node _T_4258 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rd) @[Rocket.scala 665:35]
    node _T_4259 = bits(_T_4258, 0, 0) @[Rocket.scala 665:35]
    node _T_4260 = and(_T_4239, _T_4259) @[Rocket.scala 648:27]
    node _T_4261 = or(_T_4254, _T_4257) @[Rocket.scala 648:50]
    node id_sboard_hazard = or(_T_4261, _T_4260) @[Rocket.scala 648:50]
    node _T_4262 = and(wb_set_sboard, wb_wen) @[Rocket.scala 490:28]
    node _T_4264 = dshl(UInt<1>("h01"), wb_waddr) @[Rocket.scala 672:62]
    node _T_4266 = mux(_T_4262, _T_4264, UInt<1>("h00")) @[Rocket.scala 672:49]
    node _T_4267 = or(_T_4250, _T_4266) @[Rocket.scala 663:60]
    node _T_4268 = or(_T_4251, _T_4262) @[Rocket.scala 675:17]
    when _T_4268 : @[Rocket.scala 676:18]
      _T_4241 <= _T_4267 @[Rocket.scala 676:23]
      skip @[Rocket.scala 676:18]
    node _T_4270 = neq(ex_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 493:38]
    node _T_4271 = or(_T_4270, ex_ctrl.jalr) @[Rocket.scala 493:48]
    node _T_4272 = or(_T_4271, ex_ctrl.mem) @[Rocket.scala 493:64]
    node _T_4273 = or(_T_4272, ex_ctrl.div) @[Rocket.scala 493:79]
    node _T_4274 = or(_T_4273, ex_ctrl.fp) @[Rocket.scala 493:94]
    node ex_cannot_bypass = or(_T_4274, ex_ctrl.rocc) @[Rocket.scala 493:108]
    node _T_4275 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) @[Rocket.scala 494:70]
    node _T_4276 = and(_T_4233, _T_4275) @[Rocket.scala 648:27]
    node _T_4277 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) @[Rocket.scala 494:70]
    node _T_4278 = and(_T_4236, _T_4277) @[Rocket.scala 648:27]
    node _T_4279 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) @[Rocket.scala 494:70]
    node _T_4280 = and(_T_4239, _T_4279) @[Rocket.scala 648:27]
    node _T_4281 = or(_T_4276, _T_4278) @[Rocket.scala 648:50]
    node _T_4282 = or(_T_4281, _T_4280) @[Rocket.scala 648:50]
    node data_hazard_ex = and(ex_ctrl.wxd, _T_4282) @[Rocket.scala 494:36]
    node _T_4283 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) @[Rocket.scala 495:76]
    node _T_4284 = and(io.fpu.dec.ren1, _T_4283) @[Rocket.scala 648:27]
    node _T_4285 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) @[Rocket.scala 495:76]
    node _T_4286 = and(io.fpu.dec.ren2, _T_4285) @[Rocket.scala 648:27]
    node _T_4287 = eq(ibuf.io.inst[0].bits.inst.rs3, ex_waddr) @[Rocket.scala 495:76]
    node _T_4288 = and(io.fpu.dec.ren3, _T_4287) @[Rocket.scala 648:27]
    node _T_4289 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) @[Rocket.scala 495:76]
    node _T_4290 = and(io.fpu.dec.wen, _T_4289) @[Rocket.scala 648:27]
    node _T_4291 = or(_T_4284, _T_4286) @[Rocket.scala 648:50]
    node _T_4292 = or(_T_4291, _T_4288) @[Rocket.scala 648:50]
    node _T_4293 = or(_T_4292, _T_4290) @[Rocket.scala 648:50]
    node fp_data_hazard_ex = and(ex_ctrl.wfd, _T_4293) @[Rocket.scala 495:39]
    node _T_4294 = and(data_hazard_ex, ex_cannot_bypass) @[Rocket.scala 496:54]
    node _T_4295 = or(_T_4294, fp_data_hazard_ex) @[Rocket.scala 496:74]
    node id_ex_hazard = and(ex_reg_valid, _T_4295) @[Rocket.scala 496:35]
    node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) @[Rocket.scala 500:43]
    node _T_4298 = neq(mem_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 502:40]
    node _T_4299 = and(mem_ctrl.mem, mem_mem_cmd_bh) @[Rocket.scala 502:66]
    node _T_4300 = or(_T_4298, _T_4299) @[Rocket.scala 502:50]
    node _T_4301 = or(_T_4300, mem_ctrl.div) @[Rocket.scala 502:84]
    node _T_4302 = or(_T_4301, mem_ctrl.fp) @[Rocket.scala 502:100]
    node mem_cannot_bypass = or(_T_4302, mem_ctrl.rocc) @[Rocket.scala 502:115]
    node _T_4303 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) @[Rocket.scala 503:72]
    node _T_4304 = and(_T_4233, _T_4303) @[Rocket.scala 648:27]
    node _T_4305 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) @[Rocket.scala 503:72]
    node _T_4306 = and(_T_4236, _T_4305) @[Rocket.scala 648:27]
    node _T_4307 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) @[Rocket.scala 503:72]
    node _T_4308 = and(_T_4239, _T_4307) @[Rocket.scala 648:27]
    node _T_4309 = or(_T_4304, _T_4306) @[Rocket.scala 648:50]
    node _T_4310 = or(_T_4309, _T_4308) @[Rocket.scala 648:50]
    node data_hazard_mem = and(mem_ctrl.wxd, _T_4310) @[Rocket.scala 503:38]
    node _T_4311 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) @[Rocket.scala 504:78]
    node _T_4312 = and(io.fpu.dec.ren1, _T_4311) @[Rocket.scala 648:27]
    node _T_4313 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) @[Rocket.scala 504:78]
    node _T_4314 = and(io.fpu.dec.ren2, _T_4313) @[Rocket.scala 648:27]
    node _T_4315 = eq(ibuf.io.inst[0].bits.inst.rs3, mem_waddr) @[Rocket.scala 504:78]
    node _T_4316 = and(io.fpu.dec.ren3, _T_4315) @[Rocket.scala 648:27]
    node _T_4317 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) @[Rocket.scala 504:78]
    node _T_4318 = and(io.fpu.dec.wen, _T_4317) @[Rocket.scala 648:27]
    node _T_4319 = or(_T_4312, _T_4314) @[Rocket.scala 648:50]
    node _T_4320 = or(_T_4319, _T_4316) @[Rocket.scala 648:50]
    node _T_4321 = or(_T_4320, _T_4318) @[Rocket.scala 648:50]
    node fp_data_hazard_mem = and(mem_ctrl.wfd, _T_4321) @[Rocket.scala 504:41]
    node _T_4322 = and(data_hazard_mem, mem_cannot_bypass) @[Rocket.scala 505:57]
    node _T_4323 = or(_T_4322, fp_data_hazard_mem) @[Rocket.scala 505:78]
    node id_mem_hazard = and(mem_reg_valid, _T_4323) @[Rocket.scala 505:37]
    node _T_4324 = and(mem_reg_valid, data_hazard_mem) @[Rocket.scala 506:32]
    node _T_4325 = and(_T_4324, mem_ctrl.mem) @[Rocket.scala 506:51]
    id_load_use <= _T_4325 @[Rocket.scala 506:15]
    node _T_4326 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) @[Rocket.scala 509:70]
    node _T_4327 = and(_T_4233, _T_4326) @[Rocket.scala 648:27]
    node _T_4328 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) @[Rocket.scala 509:70]
    node _T_4329 = and(_T_4236, _T_4328) @[Rocket.scala 648:27]
    node _T_4330 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) @[Rocket.scala 509:70]
    node _T_4331 = and(_T_4239, _T_4330) @[Rocket.scala 648:27]
    node _T_4332 = or(_T_4327, _T_4329) @[Rocket.scala 648:50]
    node _T_4333 = or(_T_4332, _T_4331) @[Rocket.scala 648:50]
    node data_hazard_wb = and(wb_ctrl.wxd, _T_4333) @[Rocket.scala 509:36]
    node _T_4334 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) @[Rocket.scala 510:76]
    node _T_4335 = and(io.fpu.dec.ren1, _T_4334) @[Rocket.scala 648:27]
    node _T_4336 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) @[Rocket.scala 510:76]
    node _T_4337 = and(io.fpu.dec.ren2, _T_4336) @[Rocket.scala 648:27]
    node _T_4338 = eq(ibuf.io.inst[0].bits.inst.rs3, wb_waddr) @[Rocket.scala 510:76]
    node _T_4339 = and(io.fpu.dec.ren3, _T_4338) @[Rocket.scala 648:27]
    node _T_4340 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) @[Rocket.scala 510:76]
    node _T_4341 = and(io.fpu.dec.wen, _T_4340) @[Rocket.scala 648:27]
    node _T_4342 = or(_T_4335, _T_4337) @[Rocket.scala 648:50]
    node _T_4343 = or(_T_4342, _T_4339) @[Rocket.scala 648:50]
    node _T_4344 = or(_T_4343, _T_4341) @[Rocket.scala 648:50]
    node fp_data_hazard_wb = and(wb_ctrl.wfd, _T_4344) @[Rocket.scala 510:39]
    node _T_4345 = and(data_hazard_wb, wb_set_sboard) @[Rocket.scala 511:54]
    node _T_4346 = or(_T_4345, fp_data_hazard_wb) @[Rocket.scala 511:71]
    node id_wb_hazard = and(wb_reg_valid, _T_4346) @[Rocket.scala 511:35]
    reg _T_4348 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Rocket.scala 668:25]
    node _T_4350 = and(wb_dcache_miss, wb_ctrl.wfd) @[Rocket.scala 515:35]
    node _T_4351 = or(_T_4350, io.fpu.sboard_set) @[Rocket.scala 515:50]
    node _T_4352 = and(_T_4351, wb_valid) @[Rocket.scala 515:72]
    node _T_4354 = dshl(UInt<1>("h01"), wb_waddr) @[Rocket.scala 672:62]
    node _T_4356 = mux(_T_4352, _T_4354, UInt<1>("h00")) @[Rocket.scala 672:49]
    node _T_4357 = or(_T_4348, _T_4356) @[Rocket.scala 663:60]
    node _T_4358 = or(UInt<1>("h00"), _T_4352) @[Rocket.scala 675:17]
    when _T_4358 : @[Rocket.scala 676:18]
      _T_4348 <= _T_4357 @[Rocket.scala 676:23]
      skip @[Rocket.scala 676:18]
    node _T_4359 = and(dmem_resp_replay, dmem_resp_fpu) @[Rocket.scala 516:38]
    node _T_4361 = dshl(UInt<1>("h01"), dmem_resp_waddr) @[Rocket.scala 672:62]
    node _T_4363 = mux(_T_4359, _T_4361, UInt<1>("h00")) @[Rocket.scala 672:49]
    node _T_4364 = not(_T_4363) @[Rocket.scala 664:64]
    node _T_4365 = and(_T_4357, _T_4364) @[Rocket.scala 664:62]
    node _T_4366 = or(_T_4358, _T_4359) @[Rocket.scala 675:17]
    when _T_4366 : @[Rocket.scala 676:18]
      _T_4348 <= _T_4365 @[Rocket.scala 676:23]
      skip @[Rocket.scala 676:18]
    node _T_4368 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) @[Rocket.scala 672:62]
    node _T_4370 = mux(io.fpu.sboard_clr, _T_4368, UInt<1>("h00")) @[Rocket.scala 672:49]
    node _T_4371 = not(_T_4370) @[Rocket.scala 664:64]
    node _T_4372 = and(_T_4365, _T_4371) @[Rocket.scala 664:62]
    node _T_4373 = or(_T_4366, io.fpu.sboard_clr) @[Rocket.scala 675:17]
    when _T_4373 : @[Rocket.scala 676:18]
      _T_4348 <= _T_4372 @[Rocket.scala 676:23]
      skip @[Rocket.scala 676:18]
    node _T_4375 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) @[Rocket.scala 519:18]
    node _T_4376 = and(id_csr_en, _T_4375) @[Rocket.scala 519:15]
    node _T_4377 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 665:35]
    node _T_4378 = bits(_T_4377, 0, 0) @[Rocket.scala 665:35]
    node _T_4379 = and(io.fpu.dec.ren1, _T_4378) @[Rocket.scala 648:27]
    node _T_4380 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 665:35]
    node _T_4381 = bits(_T_4380, 0, 0) @[Rocket.scala 665:35]
    node _T_4382 = and(io.fpu.dec.ren2, _T_4381) @[Rocket.scala 648:27]
    node _T_4383 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs3) @[Rocket.scala 665:35]
    node _T_4384 = bits(_T_4383, 0, 0) @[Rocket.scala 665:35]
    node _T_4385 = and(io.fpu.dec.ren3, _T_4384) @[Rocket.scala 648:27]
    node _T_4386 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rd) @[Rocket.scala 665:35]
    node _T_4387 = bits(_T_4386, 0, 0) @[Rocket.scala 665:35]
    node _T_4388 = and(io.fpu.dec.wen, _T_4387) @[Rocket.scala 648:27]
    node _T_4389 = or(_T_4379, _T_4382) @[Rocket.scala 648:50]
    node _T_4390 = or(_T_4389, _T_4385) @[Rocket.scala 648:50]
    node _T_4391 = or(_T_4390, _T_4388) @[Rocket.scala 648:50]
    node id_stall_fpu = or(_T_4376, _T_4391) @[Rocket.scala 519:35]
    reg dcache_blocked : UInt<1>, clock @[Rocket.scala 522:27]
    node _T_4394 = eq(io.dmem.req.ready, UInt<1>("h00")) @[Rocket.scala 523:21]
    node _T_4395 = or(io.dmem.req.valid, dcache_blocked) @[Rocket.scala 523:62]
    node _T_4396 = and(_T_4394, _T_4395) @[Rocket.scala 523:40]
    dcache_blocked <= _T_4396 @[Rocket.scala 523:18]
    reg rocc_blocked : UInt<1>, clock @[Rocket.scala 524:25]
    node _T_4399 = eq(wb_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 525:19]
    node _T_4401 = eq(io.rocc.cmd.ready, UInt<1>("h00")) @[Rocket.scala 525:35]
    node _T_4402 = and(_T_4399, _T_4401) @[Rocket.scala 525:32]
    node _T_4403 = or(io.rocc.cmd.valid, rocc_blocked) @[Rocket.scala 525:76]
    node _T_4404 = and(_T_4402, _T_4403) @[Rocket.scala 525:54]
    rocc_blocked <= _T_4404 @[Rocket.scala 525:16]
    node _T_4405 = or(id_ex_hazard, id_mem_hazard) @[Rocket.scala 528:18]
    node _T_4406 = or(_T_4405, id_wb_hazard) @[Rocket.scala 528:35]
    node _T_4407 = or(_T_4406, id_sboard_hazard) @[Rocket.scala 528:51]
    node _T_4408 = and(id_ctrl.fp, id_stall_fpu) @[Rocket.scala 529:16]
    node _T_4409 = or(_T_4407, _T_4408) @[Rocket.scala 528:71]
    node _T_4410 = and(id_ctrl.mem, dcache_blocked) @[Rocket.scala 530:17]
    node _T_4411 = or(_T_4409, _T_4410) @[Rocket.scala 529:32]
    node _T_4412 = and(id_ctrl.rocc, rocc_blocked) @[Rocket.scala 531:18]
    node _T_4413 = or(_T_4411, _T_4412) @[Rocket.scala 530:35]
    node _T_4415 = eq(wb_wxd, UInt<1>("h00")) @[Rocket.scala 532:65]
    node _T_4416 = and(div.io.resp.valid, _T_4415) @[Rocket.scala 532:62]
    node _T_4417 = or(div.io.req.ready, _T_4416) @[Rocket.scala 532:40]
    node _T_4419 = eq(_T_4417, UInt<1>("h00")) @[Rocket.scala 532:21]
    node _T_4420 = or(_T_4419, div.io.req.valid) @[Rocket.scala 532:75]
    node _T_4421 = and(id_ctrl.div, _T_4420) @[Rocket.scala 532:17]
    node _T_4422 = or(_T_4413, _T_4421) @[Rocket.scala 531:34]
    node _T_4423 = or(_T_4422, id_do_fence) @[Rocket.scala 532:96]
    node ctrl_stalld = or(_T_4423, csr.io.csr_stall) @[Rocket.scala 533:17]
    node _T_4425 = eq(ibuf.io.inst[0].valid, UInt<1>("h00")) @[Rocket.scala 535:17]
    node _T_4426 = or(_T_4425, ibuf.io.inst[0].bits.replay) @[Rocket.scala 535:40]
    node _T_4427 = or(_T_4426, take_pc_mem_wb) @[Rocket.scala 535:71]
    node _T_4428 = or(_T_4427, ctrl_stalld) @[Rocket.scala 535:89]
    node _T_4429 = or(_T_4428, csr.io.interrupt) @[Rocket.scala 535:104]
    ctrl_killd <= _T_4429 @[Rocket.scala 535:14]
    io.imem.req.valid <= take_pc @[Rocket.scala 537:21]
    node _T_4431 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 538:35]
    io.imem.req.bits.speculative <= _T_4431 @[Rocket.scala 538:32]
    node _T_4432 = or(wb_reg_xcpt, csr.io.eret) @[Rocket.scala 540:17]
    node _T_4434 = or(take_pc_mem, UInt<1>("h01")) @[Rocket.scala 542:21]
    node _T_4435 = mux(_T_4434, mem_npc, id_npc) @[Rocket.scala 542:8]
    node _T_4436 = mux(replay_wb, wb_reg_pc, _T_4435) @[Rocket.scala 541:8]
    node _T_4437 = mux(_T_4432, csr.io.evec, _T_4436) @[Rocket.scala 540:8]
    io.imem.req.bits.pc <= _T_4437 @[Rocket.scala 539:23]
    node _T_4438 = and(wb_reg_valid, wb_ctrl.fence_i) @[Rocket.scala 544:40]
    node _T_4440 = eq(io.dmem.s2_nack, UInt<1>("h00")) @[Rocket.scala 544:62]
    node _T_4441 = and(_T_4438, _T_4440) @[Rocket.scala 544:59]
    io.imem.flush_icache <= _T_4441 @[Rocket.scala 544:24]
    io.imem.flush_tlb <= csr.io.fatc @[Rocket.scala 545:21]
    node _T_4443 = eq(ctrl_stalld, UInt<1>("h00")) @[Rocket.scala 547:28]
    node _T_4444 = or(_T_4443, csr.io.interrupt) @[Rocket.scala 547:41]
    ibuf.io.inst[0].ready <= _T_4444 @[Rocket.scala 547:25]
    node _T_4445 = and(mem_reg_replay, mem_reg_btb_hit) @[Rocket.scala 549:47]
    node _T_4447 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 549:88]
    node _T_4448 = and(mem_reg_valid, _T_4447) @[Rocket.scala 549:85]
    node _T_4450 = eq(mem_cfi, UInt<1>("h00")) @[Rocket.scala 549:123]
    node _T_4451 = or(mem_cfi_taken, _T_4450) @[Rocket.scala 549:120]
    node _T_4452 = and(_T_4451, mem_misprediction) @[Rocket.scala 549:133]
    node _T_4454 = and(UInt<1>("h00"), mem_ctrl.jal) @[Rocket.scala 549:169]
    node _T_4456 = eq(mem_reg_btb_hit, UInt<1>("h00")) @[Rocket.scala 549:188]
    node _T_4457 = and(_T_4454, _T_4456) @[Rocket.scala 549:185]
    node _T_4458 = or(_T_4452, _T_4457) @[Rocket.scala 549:151]
    node _T_4459 = and(_T_4448, _T_4458) @[Rocket.scala 549:100]
    node _T_4460 = or(_T_4445, _T_4459) @[Rocket.scala 549:67]
    io.imem.btb_update.valid <= _T_4460 @[Rocket.scala 549:28]
    node _T_4462 = eq(mem_reg_replay, UInt<1>("h00")) @[Rocket.scala 550:38]
    node _T_4463 = and(_T_4462, mem_cfi) @[Rocket.scala 550:54]
    io.imem.btb_update.bits.isValid <= _T_4463 @[Rocket.scala 550:35]
    node _T_4464 = or(mem_ctrl.jal, mem_ctrl.jalr) @[Rocket.scala 551:50]
    io.imem.btb_update.bits.isJump <= _T_4464 @[Rocket.scala 551:34]
    node _T_4465 = bits(mem_reg_inst, 19, 15) @[Rocket.scala 552:68]
    node _T_4468 = and(_T_4465, UInt<5>("h01b")) @[Rocket.scala 552:76]
    node _T_4469 = eq(UInt<1>("h01"), _T_4468) @[Rocket.scala 552:76]
    node _T_4470 = and(mem_ctrl.jalr, _T_4469) @[Rocket.scala 552:53]
    io.imem.btb_update.bits.isReturn <= _T_4470 @[Rocket.scala 552:36]
    io.imem.btb_update.bits.target <= io.imem.req.bits.pc @[Rocket.scala 553:34]
    node _T_4473 = mux(mem_reg_rvc, UInt<1>("h00"), UInt<2>("h02")) @[Rocket.scala 554:74]
    node _T_4474 = add(mem_reg_pc, _T_4473) @[Rocket.scala 554:69]
    node _T_4475 = tail(_T_4474, 1) @[Rocket.scala 554:69]
    io.imem.btb_update.bits.br_pc <= _T_4475 @[Rocket.scala 554:33]
    node _T_4476 = not(io.imem.btb_update.bits.br_pc) @[Rocket.scala 555:35]
    node _T_4478 = or(_T_4476, UInt<2>("h03")) @[Rocket.scala 555:66]
    node _T_4479 = not(_T_4478) @[Rocket.scala 555:33]
    io.imem.btb_update.bits.pc <= _T_4479 @[Rocket.scala 555:30]
    io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit @[Rocket.scala 556:44]
    io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp @[Rocket.scala 557:43]
    node _T_4481 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 559:48]
    node _T_4482 = and(mem_reg_valid, _T_4481) @[Rocket.scala 559:45]
    node _T_4483 = and(_T_4482, mem_ctrl.branch) @[Rocket.scala 559:60]
    io.imem.bht_update.valid <= _T_4483 @[Rocket.scala 559:28]
    io.imem.bht_update.bits.pc <= io.imem.btb_update.bits.pc @[Rocket.scala 560:30]
    io.imem.bht_update.bits.taken <= mem_br_taken @[Rocket.scala 561:33]
    io.imem.bht_update.bits.mispredict <= mem_misprediction @[Rocket.scala 562:38]
    io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction @[Rocket.scala 563:38]
    node _T_4485 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 565:48]
    node _T_4486 = and(mem_reg_valid, _T_4485) @[Rocket.scala 565:45]
    io.imem.ras_update.valid <= _T_4486 @[Rocket.scala 565:28]
    io.imem.ras_update.bits.returnAddr <= mem_int_wdata @[Rocket.scala 566:38]
    node _T_4487 = bits(mem_waddr, 0, 0) @[Rocket.scala 567:80]
    node _T_4488 = and(io.imem.btb_update.bits.isJump, _T_4487) @[Rocket.scala 567:68]
    io.imem.ras_update.bits.isCall <= _T_4488 @[Rocket.scala 567:34]
    io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn @[Rocket.scala 568:36]
    io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction @[Rocket.scala 569:38]
    node _T_4490 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 571:19]
    node _T_4491 = and(_T_4490, id_ctrl.fp) @[Rocket.scala 571:31]
    io.fpu.valid <= _T_4491 @[Rocket.scala 571:16]
    io.fpu.killx <= ctrl_killx @[Rocket.scala 572:16]
    io.fpu.killm <= killm_common @[Rocket.scala 573:16]
    io.fpu.inst <= ibuf.io.inst[0].bits.inst.bits @[Rocket.scala 574:15]
    io.fpu.fromint_data <= ex_rs_0 @[Rocket.scala 575:23]
    node _T_4492 = and(dmem_resp_valid, dmem_resp_fpu) @[Rocket.scala 576:43]
    io.fpu.dmem_resp_val <= _T_4492 @[Rocket.scala 576:24]
    io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass @[Rocket.scala 577:25]
    io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ @[Rocket.scala 578:25]
    io.fpu.dmem_resp_tag <= dmem_resp_waddr @[Rocket.scala 579:24]
    node _T_4493 = and(ex_reg_valid, ex_ctrl.mem) @[Rocket.scala 581:41]
    io.dmem.req.valid <= _T_4493 @[Rocket.scala 581:25]
    node ex_dcache_tag = cat(ex_waddr, ex_ctrl.fp) @[Cat.scala 30:58]
    io.dmem.req.bits.tag <= ex_dcache_tag @[Rocket.scala 584:25]
    io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd @[Rocket.scala 585:25]
    io.dmem.req.bits.typ <= ex_ctrl.mem_type @[Rocket.scala 586:25]
    io.dmem.req.bits.phys <= UInt<1>("h00") @[Rocket.scala 587:25]
    node _T_4495 = shr(ex_rs_0, 38) @[Rocket.scala 653:16]
    node _T_4496 = bits(alu.io.adder_out, 39, 38) @[Rocket.scala 654:15]
    node _T_4497 = asSInt(_T_4496) @[Rocket.scala 654:39]
    node _T_4499 = eq(_T_4495, UInt<1>("h00")) @[Rocket.scala 656:13]
    node _T_4501 = eq(_T_4495, UInt<1>("h01")) @[Rocket.scala 656:30]
    node _T_4502 = or(_T_4499, _T_4501) @[Rocket.scala 656:25]
    node _T_4504 = neq(_T_4497, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45]
    node _T_4505 = asSInt(_T_4495) @[Rocket.scala 657:13]
    node _T_4507 = eq(_T_4505, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20]
    node _T_4508 = asSInt(_T_4495) @[Rocket.scala 657:38]
    node _T_4510 = eq(_T_4508, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45]
    node _T_4511 = or(_T_4507, _T_4510) @[Rocket.scala 657:33]
    node _T_4513 = eq(_T_4497, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61]
    node _T_4514 = bits(_T_4497, 0, 0) @[Rocket.scala 657:76]
    node _T_4515 = mux(_T_4511, _T_4513, _T_4514) @[Rocket.scala 657:10]
    node _T_4516 = mux(_T_4502, _T_4504, _T_4515) @[Rocket.scala 656:10]
    node _T_4517 = bits(alu.io.adder_out, 38, 0) @[Rocket.scala 658:16]
    node _T_4518 = cat(_T_4516, _T_4517) @[Cat.scala 30:58]
    io.dmem.req.bits.addr <= _T_4518 @[Rocket.scala 588:25]
    io.dmem.invalidate_lr <= wb_reg_xcpt @[Rocket.scala 589:25]
    node _T_4519 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) @[Rocket.scala 590:25]
    io.dmem.s1_data <= _T_4519 @[Rocket.scala 590:19]
    node _T_4520 = or(killm_common, mem_breakpoint) @[Rocket.scala 591:35]
    io.dmem.s1_kill <= _T_4520 @[Rocket.scala 591:19]
    node _T_4521 = and(mem_ctrl.mem, mem_xcpt) @[Rocket.scala 592:22]
    node _T_4523 = eq(io.dmem.s1_kill, UInt<1>("h00")) @[Rocket.scala 592:37]
    node _T_4524 = and(_T_4521, _T_4523) @[Rocket.scala 592:34]
    when _T_4524 : @[Rocket.scala 592:55]
      node _T_4525 = cat(io.dmem.xcpt.pf.ld, io.dmem.xcpt.pf.st) @[Rocket.scala 593:25]
      node _T_4526 = cat(io.dmem.xcpt.ma.ld, io.dmem.xcpt.ma.st) @[Rocket.scala 593:25]
      node _T_4527 = cat(_T_4526, _T_4525) @[Rocket.scala 593:25]
      node _T_4529 = neq(_T_4527, UInt<1>("h00")) @[Rocket.scala 593:32]
      node _T_4530 = or(_T_4529, reset) @[Rocket.scala 593:11]
      node _T_4532 = eq(_T_4530, UInt<1>("h00")) @[Rocket.scala 593:11]
      when _T_4532 : @[Rocket.scala 593:11]
        printf(clock, UInt<1>(1), "Assertion failed\n    at Rocket.scala:593 assert(io.dmem.xcpt.asUInt.orR) // make sure s1_kill is exhaustive\n") @[Rocket.scala 593:11]
        stop(clock, UInt<1>(1), 1) @[Rocket.scala 593:11]
        skip @[Rocket.scala 593:11]
      skip @[Rocket.scala 592:55]
    node _T_4533 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 596:37]
    node _T_4535 = eq(replay_wb_common, UInt<1>("h00")) @[Rocket.scala 596:56]
    node _T_4536 = and(_T_4533, _T_4535) @[Rocket.scala 596:53]
    io.rocc.cmd.valid <= _T_4536 @[Rocket.scala 596:21]
    node _T_4538 = neq(csr.io.status.xs, UInt<1>("h00")) @[Rocket.scala 597:52]
    node _T_4539 = and(wb_reg_xcpt, _T_4538) @[Rocket.scala 597:32]
    io.rocc.exception <= _T_4539 @[Rocket.scala 597:21]
    io.rocc.cmd.bits.status <- csr.io.status @[Rocket.scala 598:27]
    wire _T_4558 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} @[Rocket.scala 599:58]
    _T_4558 is invalid @[Rocket.scala 599:58]
    wire _T_4568 : UInt<32>
    _T_4568 is invalid
    _T_4568 <= wb_reg_inst
    node _T_4569 = bits(_T_4568, 6, 0) @[Rocket.scala 599:58]
    _T_4558.opcode <= _T_4569 @[Rocket.scala 599:58]
    node _T_4570 = bits(_T_4568, 11, 7) @[Rocket.scala 599:58]
    _T_4558.rd <= _T_4570 @[Rocket.scala 599:58]
    node _T_4571 = bits(_T_4568, 12, 12) @[Rocket.scala 599:58]
    _T_4558.xs2 <= _T_4571 @[Rocket.scala 599:58]
    node _T_4572 = bits(_T_4568, 13, 13) @[Rocket.scala 599:58]
    _T_4558.xs1 <= _T_4572 @[Rocket.scala 599:58]
    node _T_4573 = bits(_T_4568, 14, 14) @[Rocket.scala 599:58]
    _T_4558.xd <= _T_4573 @[Rocket.scala 599:58]
    node _T_4574 = bits(_T_4568, 19, 15) @[Rocket.scala 599:58]
    _T_4558.rs1 <= _T_4574 @[Rocket.scala 599:58]
    node _T_4575 = bits(_T_4568, 24, 20) @[Rocket.scala 599:58]
    _T_4558.rs2 <= _T_4575 @[Rocket.scala 599:58]
    node _T_4576 = bits(_T_4568, 31, 25) @[Rocket.scala 599:58]
    _T_4558.funct <= _T_4576 @[Rocket.scala 599:58]
    io.rocc.cmd.bits.inst <- _T_4558 @[Rocket.scala 599:25]
    io.rocc.cmd.bits.rs1 <= wb_reg_wdata @[Rocket.scala 600:24]
    io.rocc.cmd.bits.rs2 <= wb_reg_rs2 @[Rocket.scala 601:24]
    node _T_4577 = bits(csr.io.time, 31, 0) @[Rocket.scala 637:32]
    node _T_4579 = mux(rf_wen, rf_waddr, UInt<1>("h00")) @[Rocket.scala 638:13]
    node _T_4580 = bits(wb_reg_inst, 19, 15) @[Rocket.scala 639:21]
    reg _T_4581 : UInt, clock @[Rocket.scala 639:42]
    _T_4581 <= ex_rs_0 @[Rocket.scala 639:42]
    reg _T_4582 : UInt, clock @[Rocket.scala 639:33]
    _T_4582 <= _T_4581 @[Rocket.scala 639:33]
    node _T_4583 = bits(wb_reg_inst, 24, 20) @[Rocket.scala 640:21]
    reg _T_4584 : UInt, clock @[Rocket.scala 640:42]
    _T_4584 <= ex_rs_1 @[Rocket.scala 640:42]
    reg _T_4585 : UInt, clock @[Rocket.scala 640:33]
    _T_4585 <= _T_4584 @[Rocket.scala 640:33]
    node _T_4587 = eq(reset, UInt<1>("h00")) @[Rocket.scala 636:11]
    when _T_4587 : @[Rocket.scala 636:11]
      printf(clock, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, _T_4577, wb_valid, wb_reg_pc, _T_4579, rf_wdata, rf_wen, _T_4580, _T_4582, _T_4583, _T_4585, wb_reg_inst, wb_reg_inst) @[Rocket.scala 636:11]
      skip @[Rocket.scala 636:11]
    
  module IBuf : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip imem : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<40>, btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, inst : {flip ready : UInt<1>, valid : UInt<1>, bits : {pf0 : UInt<1>, pf1 : UInt<1>, replay : UInt<1>, btb_hit : UInt<1>, rvc : UInt<1>, inst : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, raw : UInt<32>}}[1]}
    
    io is invalid
    io is invalid
    reg nBufValid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[IBuf.scala 35:47]
    reg buf : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}, clock @[IBuf.scala 36:16]
    reg ibufBTBHit : UInt<1>, clock @[IBuf.scala 37:23]
    reg ibufBTBResp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[IBuf.scala 38:24]
    node pcWordBits = bits(io.imem.bits.pc, 1, 1) @[Package.scala 44:13]
    wire nReady : UInt<2>
    nReady is invalid
    nReady <= UInt<2>("h00")
    node _T_375 = and(io.imem.bits.btb.valid, io.imem.bits.btb.bits.taken) @[IBuf.scala 43:40]
    node _T_377 = add(io.imem.bits.btb.bits.bridx, UInt<1>("h01")) @[IBuf.scala 43:100]
    node _T_379 = mux(_T_375, _T_377, UInt<2>("h02")) @[IBuf.scala 43:16]
    node _T_380 = sub(_T_379, pcWordBits) @[IBuf.scala 43:124]
    node _T_381 = asUInt(_T_380) @[IBuf.scala 43:124]
    node nIC = tail(_T_381, 1) @[IBuf.scala 43:124]
    node _T_382 = sub(nReady, nBufValid) @[IBuf.scala 44:25]
    node _T_383 = asUInt(_T_382) @[IBuf.scala 44:25]
    node nICReady = tail(_T_383, 1) @[IBuf.scala 44:25]
    node _T_385 = mux(io.imem.valid, nIC, UInt<1>("h00")) @[IBuf.scala 45:19]
    node _T_386 = add(_T_385, nBufValid) @[IBuf.scala 45:49]
    node nValid = tail(_T_386, 1) @[IBuf.scala 45:49]
    node _T_387 = geq(nReady, nBufValid) @[IBuf.scala 46:27]
    node _T_388 = geq(nICReady, nIC) @[IBuf.scala 46:53]
    node _T_390 = sub(nIC, nICReady) @[IBuf.scala 46:72]
    node _T_391 = asUInt(_T_390) @[IBuf.scala 46:72]
    node _T_392 = tail(_T_391, 1) @[IBuf.scala 46:72]
    node _T_393 = geq(UInt<1>("h01"), _T_392) @[IBuf.scala 46:65]
    node _T_394 = or(_T_388, _T_393) @[IBuf.scala 46:60]
    node _T_395 = and(_T_387, _T_394) @[IBuf.scala 46:40]
    io.imem.ready <= _T_395 @[IBuf.scala 46:17]
    node _T_396 = geq(nReady, nBufValid) @[IBuf.scala 49:29]
    node _T_398 = sub(nBufValid, nReady) @[IBuf.scala 49:62]
    node _T_399 = asUInt(_T_398) @[IBuf.scala 49:62]
    node _T_400 = tail(_T_399, 1) @[IBuf.scala 49:62]
    node _T_401 = mux(_T_396, UInt<1>("h00"), _T_400) @[IBuf.scala 49:21]
    nBufValid <= _T_401 @[IBuf.scala 49:15]
    node _T_402 = geq(nReady, nBufValid) @[IBuf.scala 56:35]
    node _T_403 = and(io.imem.valid, _T_402) @[IBuf.scala 56:25]
    node _T_404 = lt(nICReady, nIC) @[IBuf.scala 56:60]
    node _T_405 = and(_T_403, _T_404) @[IBuf.scala 56:48]
    node _T_407 = sub(nIC, nICReady) @[IBuf.scala 56:78]
    node _T_408 = asUInt(_T_407) @[IBuf.scala 56:78]
    node _T_409 = tail(_T_408, 1) @[IBuf.scala 56:78]
    node _T_410 = geq(UInt<1>("h01"), _T_409) @[IBuf.scala 56:71]
    node _T_411 = and(_T_405, _T_410) @[IBuf.scala 56:66]
    when _T_411 : @[IBuf.scala 56:90]
      node _T_412 = add(pcWordBits, nICReady) @[IBuf.scala 57:30]
      node _T_413 = tail(_T_412, 1) @[IBuf.scala 57:30]
      node _T_414 = sub(nIC, nICReady) @[IBuf.scala 58:24]
      node _T_415 = asUInt(_T_414) @[IBuf.scala 58:24]
      node _T_416 = tail(_T_415, 1) @[IBuf.scala 58:24]
      nBufValid <= _T_416 @[IBuf.scala 58:17]
      buf <- io.imem.bits @[IBuf.scala 59:11]
      node _T_417 = shr(io.imem.bits.data, 16) @[IBuf.scala 133:58]
      node _T_418 = cat(_T_417, _T_417) @[Cat.scala 30:58]
      node _T_419 = cat(_T_418, io.imem.bits.data) @[Cat.scala 30:58]
      node _T_420 = shl(_T_413, 4) @[IBuf.scala 134:19]
      node _T_421 = dshr(_T_419, _T_420) @[IBuf.scala 134:10]
      node _T_422 = bits(_T_421, 15, 0) @[IBuf.scala 60:59]
      buf.data <= _T_422 @[IBuf.scala 60:16]
      node _T_423 = not(UInt<40>("h03")) @[IBuf.scala 61:35]
      node _T_424 = and(io.imem.bits.pc, _T_423) @[IBuf.scala 61:33]
      node _T_425 = shl(nICReady, 1) @[IBuf.scala 61:78]
      node _T_426 = add(io.imem.bits.pc, _T_425) @[IBuf.scala 61:66]
      node _T_427 = tail(_T_426, 1) @[IBuf.scala 61:66]
      node _T_428 = and(_T_427, UInt<40>("h03")) @[IBuf.scala 61:107]
      node _T_429 = or(_T_424, _T_428) @[IBuf.scala 61:47]
      buf.pc <= _T_429 @[IBuf.scala 61:14]
      ibufBTBHit <= io.imem.bits.btb.valid @[IBuf.scala 62:18]
      when io.imem.bits.btb.valid : @[IBuf.scala 63:37]
        ibufBTBResp <- io.imem.bits.btb.bits @[IBuf.scala 64:21]
        node _T_430 = add(io.imem.bits.btb.bits.bridx, nICReady) @[IBuf.scala 65:58]
        node _T_431 = tail(_T_430, 1) @[IBuf.scala 65:58]
        ibufBTBResp.bridx <= _T_431 @[IBuf.scala 65:27]
        skip @[IBuf.scala 63:37]
      skip @[IBuf.scala 56:90]
    when io.kill : @[IBuf.scala 68:20]
      nBufValid <= UInt<1>("h00") @[IBuf.scala 69:17]
      skip @[IBuf.scala 68:20]
    node _T_434 = add(UInt<2>("h02"), nBufValid) @[IBuf.scala 73:32]
    node _T_435 = tail(_T_434, 1) @[IBuf.scala 73:32]
    node _T_436 = sub(_T_435, pcWordBits) @[IBuf.scala 73:44]
    node _T_437 = asUInt(_T_436) @[IBuf.scala 73:44]
    node _T_438 = tail(_T_437, 1) @[IBuf.scala 73:44]
    node icShiftAmt = bits(_T_438, 1, 0) @[IBuf.scala 73:57]
    node _T_439 = bits(io.imem.bits.data, 15, 0) @[IBuf.scala 74:87]
    node _T_440 = cat(_T_439, _T_439) @[Cat.scala 30:58]
    node _T_441 = cat(io.imem.bits.data, _T_440) @[Cat.scala 30:58]
    node _T_442 = shr(_T_441, 48) @[IBuf.scala 126:58]
    node _T_443 = cat(_T_442, _T_442) @[Cat.scala 30:58]
    node _T_444 = cat(_T_443, _T_443) @[Cat.scala 30:58]
    node _T_445 = cat(_T_444, _T_441) @[Cat.scala 30:58]
    node _T_446 = shl(icShiftAmt, 4) @[IBuf.scala 127:19]
    node _T_447 = dshl(_T_445, _T_446) @[IBuf.scala 127:10]
    node icData = bits(_T_447, 95, 64) @[Package.scala 44:13]
    node _T_449 = not(UInt<32>("h00")) @[IBuf.scala 76:17]
    node _T_450 = shl(nBufValid, 4) @[IBuf.scala 76:65]
    node _T_451 = dshl(_T_449, _T_450) @[IBuf.scala 76:51]
    node icMask = bits(_T_451, 31, 0) @[IBuf.scala 76:92]
    node _T_452 = and(icData, icMask) @[IBuf.scala 77:21]
    node _T_453 = not(icMask) @[IBuf.scala 77:43]
    node _T_454 = and(buf.data, _T_453) @[IBuf.scala 77:41]
    node inst = or(_T_452, _T_454) @[IBuf.scala 77:30]
    node _T_456 = dshl(UInt<1>("h01"), nValid) @[OneHot.scala 47:11]
    node _T_458 = sub(_T_456, UInt<1>("h01")) @[IBuf.scala 79:33]
    node _T_459 = asUInt(_T_458) @[IBuf.scala 79:33]
    node _T_460 = tail(_T_459, 1) @[IBuf.scala 79:33]
    node valid = bits(_T_460, 1, 0) @[IBuf.scala 79:37]
    node _T_462 = dshl(UInt<1>("h01"), nBufValid) @[OneHot.scala 47:11]
    node _T_464 = sub(_T_462, UInt<1>("h01")) @[IBuf.scala 80:37]
    node _T_465 = asUInt(_T_464) @[IBuf.scala 80:37]
    node bufMask = tail(_T_465, 1) @[IBuf.scala 80:37]
    node _T_467 = mux(buf.xcpt_if, bufMask, UInt<1>("h00")) @[IBuf.scala 81:29]
    node _T_468 = not(bufMask) @[IBuf.scala 81:89]
    node _T_470 = mux(io.imem.bits.xcpt_if, _T_468, UInt<1>("h00")) @[IBuf.scala 81:66]
    node _T_471 = or(_T_467, _T_470) @[IBuf.scala 81:61]
    node xcpt_if = and(valid, _T_471) @[IBuf.scala 81:23]
    node _T_473 = mux(buf.replay, bufMask, UInt<1>("h00")) @[IBuf.scala 82:31]
    node _T_474 = not(bufMask) @[IBuf.scala 82:89]
    node _T_476 = mux(io.imem.bits.replay, _T_474, UInt<1>("h00")) @[IBuf.scala 82:67]
    node _T_477 = or(_T_473, _T_476) @[IBuf.scala 82:62]
    node ic_replay = and(valid, _T_477) @[IBuf.scala 82:25]
    node _T_479 = dshl(UInt<1>("h01"), ibufBTBResp.bridx) @[OneHot.scala 47:11]
    node ibufBTBHitMask = mux(ibufBTBHit, _T_479, UInt<1>("h00")) @[IBuf.scala 83:27]
    node _T_482 = eq(io.imem.bits.btb.valid, UInt<1>("h00")) @[IBuf.scala 84:10]
    node _T_483 = geq(io.imem.bits.btb.bits.bridx, pcWordBits) @[IBuf.scala 84:65]
    node _T_484 = or(_T_482, _T_483) @[IBuf.scala 84:34]
    node _T_485 = or(_T_484, reset) @[IBuf.scala 84:9]
    node _T_487 = eq(_T_485, UInt<1>("h00")) @[IBuf.scala 84:9]
    when _T_487 : @[IBuf.scala 84:9]
      printf(clock, UInt<1>(1), "Assertion failed\n    at IBuf.scala:84 assert(!io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)\n") @[IBuf.scala 84:9]
      stop(clock, UInt<1>(1), 1) @[IBuf.scala 84:9]
      skip @[IBuf.scala 84:9]
    node _T_488 = add(io.imem.bits.btb.bits.bridx, nBufValid) @[IBuf.scala 85:87]
    node _T_489 = sub(_T_488, pcWordBits) @[IBuf.scala 85:100]
    node _T_490 = asUInt(_T_489) @[IBuf.scala 85:100]
    node _T_491 = tail(_T_490, 1) @[IBuf.scala 85:100]
    node _T_493 = dshl(UInt<1>("h01"), _T_491) @[OneHot.scala 47:11]
    node icBTBHitMask = mux(io.imem.bits.btb.valid, _T_493, UInt<1>("h00")) @[IBuf.scala 85:25]
    node _T_495 = and(ibufBTBHitMask, bufMask) @[IBuf.scala 86:35]
    node _T_496 = not(bufMask) @[IBuf.scala 86:62]
    node _T_497 = and(icBTBHitMask, _T_496) @[IBuf.scala 86:60]
    node btbHitMask = or(_T_495, _T_497) @[IBuf.scala 86:45]
    node _T_498 = and(ibufBTBHitMask, bufMask) @[IBuf.scala 88:38]
    node _T_500 = neq(_T_498, UInt<1>("h00")) @[IBuf.scala 88:49]
    node _T_501 = mux(_T_500, ibufBTBResp, io.imem.bits.btb.bits) @[IBuf.scala 88:21]
    io.btb_resp <- _T_501 @[IBuf.scala 88:15]
    node _T_511 = gt(nBufValid, UInt<1>("h00")) @[IBuf.scala 89:26]
    node _T_512 = mux(_T_511, buf.pc, io.imem.bits.pc) @[IBuf.scala 89:15]
    io.pc <= _T_512 @[IBuf.scala 89:9]
    inst RVCExpander of RVCExpander @[IBuf.scala 93:21]
    RVCExpander.io is invalid
    RVCExpander.clock <= clock
    RVCExpander.reset <= reset
    RVCExpander.io.in <= inst @[IBuf.scala 94:15]
    io.inst[0].bits.inst <- RVCExpander.io.out @[IBuf.scala 95:26]
    io.inst[0].bits.raw <= inst @[IBuf.scala 96:25]
    node _T_514 = dshr(ic_replay, UInt<1>("h00")) @[IBuf.scala 99:29]
    node _T_515 = bits(_T_514, 0, 0) @[IBuf.scala 99:29]
    node _T_517 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 99:37]
    node _T_518 = dshr(btbHitMask, UInt<1>("h00")) @[IBuf.scala 99:63]
    node _T_519 = bits(_T_518, 0, 0) @[IBuf.scala 99:63]
    node _T_521 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 99:81]
    node _T_522 = tail(_T_521, 1) @[IBuf.scala 99:81]
    node _T_523 = dshr(ic_replay, _T_522) @[IBuf.scala 99:79]
    node _T_524 = bits(_T_523, 0, 0) @[IBuf.scala 99:79]
    node _T_525 = or(_T_519, _T_524) @[IBuf.scala 99:67]
    node _T_526 = and(_T_517, _T_525) @[IBuf.scala 99:49]
    node _T_527 = or(_T_515, _T_526) @[IBuf.scala 99:33]
    node _T_528 = dshr(valid, UInt<1>("h00")) @[IBuf.scala 100:32]
    node _T_529 = bits(_T_528, 0, 0) @[IBuf.scala 100:32]
    node _T_531 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 100:61]
    node _T_532 = tail(_T_531, 1) @[IBuf.scala 100:61]
    node _T_533 = dshr(valid, _T_532) @[IBuf.scala 100:59]
    node _T_534 = bits(_T_533, 0, 0) @[IBuf.scala 100:59]
    node _T_535 = or(RVCExpander.io.rvc, _T_534) @[IBuf.scala 100:51]
    node _T_537 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 100:77]
    node _T_538 = tail(_T_537, 1) @[IBuf.scala 100:77]
    node _T_539 = dshr(xcpt_if, _T_538) @[IBuf.scala 100:75]
    node _T_540 = bits(_T_539, 0, 0) @[IBuf.scala 100:75]
    node _T_541 = or(_T_535, _T_540) @[IBuf.scala 100:65]
    node _T_542 = or(_T_541, _T_527) @[IBuf.scala 100:81]
    node _T_543 = and(_T_529, _T_542) @[IBuf.scala 100:36]
    io.inst[0].valid <= _T_543 @[IBuf.scala 100:24]
    node _T_544 = dshr(xcpt_if, UInt<1>("h00")) @[IBuf.scala 101:37]
    node _T_545 = bits(_T_544, 0, 0) @[IBuf.scala 101:37]
    io.inst[0].bits.pf0 <= _T_545 @[IBuf.scala 101:27]
    node _T_547 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 102:30]
    node _T_549 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 102:54]
    node _T_550 = tail(_T_549, 1) @[IBuf.scala 102:54]
    node _T_551 = dshr(xcpt_if, _T_550) @[IBuf.scala 102:52]
    node _T_552 = bits(_T_551, 0, 0) @[IBuf.scala 102:52]
    node _T_553 = and(_T_547, _T_552) @[IBuf.scala 102:42]
    io.inst[0].bits.pf1 <= _T_553 @[IBuf.scala 102:27]
    io.inst[0].bits.replay <= _T_527 @[IBuf.scala 103:30]
    node _T_554 = dshr(btbHitMask, UInt<1>("h00")) @[IBuf.scala 104:44]
    node _T_555 = bits(_T_554, 0, 0) @[IBuf.scala 104:44]
    node _T_557 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 104:52]
    node _T_559 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 104:79]
    node _T_560 = tail(_T_559, 1) @[IBuf.scala 104:79]
    node _T_561 = dshr(btbHitMask, _T_560) @[IBuf.scala 104:77]
    node _T_562 = bits(_T_561, 0, 0) @[IBuf.scala 104:77]
    node _T_563 = and(_T_557, _T_562) @[IBuf.scala 104:64]
    node _T_564 = or(_T_555, _T_563) @[IBuf.scala 104:48]
    io.inst[0].bits.btb_hit <= _T_564 @[IBuf.scala 104:31]
    io.inst[0].bits.rvc <= RVCExpander.io.rvc @[IBuf.scala 105:27]
    node _T_565 = and(io.inst[0].ready, io.inst[0].valid) @[Decoupled.scala 30:37]
    when _T_565 : @[IBuf.scala 107:32]
      node _T_567 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 107:61]
      node _T_568 = tail(_T_567, 1) @[IBuf.scala 107:61]
      node _T_570 = add(UInt<1>("h00"), UInt<2>("h02")) @[IBuf.scala 107:66]
      node _T_571 = tail(_T_570, 1) @[IBuf.scala 107:66]
      node _T_572 = mux(RVCExpander.io.rvc, _T_568, _T_571) @[IBuf.scala 107:47]
      nReady <= _T_572 @[IBuf.scala 107:41]
      skip @[IBuf.scala 107:32]
    node _T_574 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 109:36]
    node _T_575 = tail(_T_574, 1) @[IBuf.scala 109:36]
    node _T_577 = add(UInt<1>("h00"), UInt<2>("h02")) @[IBuf.scala 109:41]
    node _T_578 = tail(_T_577, 1) @[IBuf.scala 109:41]
    node _T_579 = mux(RVCExpander.io.rvc, _T_575, _T_578) @[IBuf.scala 109:22]
    node _T_580 = shr(inst, 16) @[IBuf.scala 109:70]
    node _T_581 = shr(inst, 32) @[IBuf.scala 109:85]
    node _T_582 = mux(RVCExpander.io.rvc, _T_580, _T_581) @[IBuf.scala 109:49]
    
  module CSRFile : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip interrupts : {debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>}, flip hartid : UInt<64>, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : {flip csr : UInt<12>, fp_illegal : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>}, csr_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, flip badaddr : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], counters : {eventSel : UInt<64>, flip inc : UInt<1>}[0]}
    
    io is invalid
    io is invalid
    wire _T_347 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 194:55]
    _T_347 is invalid @[CSR.scala 194:55]
    wire _T_377 : UInt<99>
    _T_377 is invalid
    _T_377 <= UInt<1>("h00")
    node _T_378 = bits(_T_377, 0, 0) @[CSR.scala 194:55]
    _T_347.uie <= _T_378 @[CSR.scala 194:55]
    node _T_379 = bits(_T_377, 1, 1) @[CSR.scala 194:55]
    _T_347.sie <= _T_379 @[CSR.scala 194:55]
    node _T_380 = bits(_T_377, 2, 2) @[CSR.scala 194:55]
    _T_347.hie <= _T_380 @[CSR.scala 194:55]
    node _T_381 = bits(_T_377, 3, 3) @[CSR.scala 194:55]
    _T_347.mie <= _T_381 @[CSR.scala 194:55]
    node _T_382 = bits(_T_377, 4, 4) @[CSR.scala 194:55]
    _T_347.upie <= _T_382 @[CSR.scala 194:55]
    node _T_383 = bits(_T_377, 5, 5) @[CSR.scala 194:55]
    _T_347.spie <= _T_383 @[CSR.scala 194:55]
    node _T_384 = bits(_T_377, 6, 6) @[CSR.scala 194:55]
    _T_347.hpie <= _T_384 @[CSR.scala 194:55]
    node _T_385 = bits(_T_377, 7, 7) @[CSR.scala 194:55]
    _T_347.mpie <= _T_385 @[CSR.scala 194:55]
    node _T_386 = bits(_T_377, 8, 8) @[CSR.scala 194:55]
    _T_347.spp <= _T_386 @[CSR.scala 194:55]
    node _T_387 = bits(_T_377, 10, 9) @[CSR.scala 194:55]
    _T_347.hpp <= _T_387 @[CSR.scala 194:55]
    node _T_388 = bits(_T_377, 12, 11) @[CSR.scala 194:55]
    _T_347.mpp <= _T_388 @[CSR.scala 194:55]
    node _T_389 = bits(_T_377, 14, 13) @[CSR.scala 194:55]
    _T_347.fs <= _T_389 @[CSR.scala 194:55]
    node _T_390 = bits(_T_377, 16, 15) @[CSR.scala 194:55]
    _T_347.xs <= _T_390 @[CSR.scala 194:55]
    node _T_391 = bits(_T_377, 17, 17) @[CSR.scala 194:55]
    _T_347.mprv <= _T_391 @[CSR.scala 194:55]
    node _T_392 = bits(_T_377, 18, 18) @[CSR.scala 194:55]
    _T_347.pum <= _T_392 @[CSR.scala 194:55]
    node _T_393 = bits(_T_377, 19, 19) @[CSR.scala 194:55]
    _T_347.mxr <= _T_393 @[CSR.scala 194:55]
    node _T_394 = bits(_T_377, 20, 20) @[CSR.scala 194:55]
    _T_347.tvm <= _T_394 @[CSR.scala 194:55]
    node _T_395 = bits(_T_377, 21, 21) @[CSR.scala 194:55]
    _T_347.tw <= _T_395 @[CSR.scala 194:55]
    node _T_396 = bits(_T_377, 22, 22) @[CSR.scala 194:55]
    _T_347.tsr <= _T_396 @[CSR.scala 194:55]
    node _T_397 = bits(_T_377, 30, 23) @[CSR.scala 194:55]
    _T_347.zero1 <= _T_397 @[CSR.scala 194:55]
    node _T_398 = bits(_T_377, 31, 31) @[CSR.scala 194:55]
    _T_347.sd_rv32 <= _T_398 @[CSR.scala 194:55]
    node _T_399 = bits(_T_377, 33, 32) @[CSR.scala 194:55]
    _T_347.uxl <= _T_399 @[CSR.scala 194:55]
    node _T_400 = bits(_T_377, 35, 34) @[CSR.scala 194:55]
    _T_347.sxl <= _T_400 @[CSR.scala 194:55]
    node _T_401 = bits(_T_377, 62, 36) @[CSR.scala 194:55]
    _T_347.zero2 <= _T_401 @[CSR.scala 194:55]
    node _T_402 = bits(_T_377, 63, 63) @[CSR.scala 194:55]
    _T_347.sd <= _T_402 @[CSR.scala 194:55]
    node _T_403 = bits(_T_377, 65, 64) @[CSR.scala 194:55]
    _T_347.prv <= _T_403 @[CSR.scala 194:55]
    node _T_404 = bits(_T_377, 97, 66) @[CSR.scala 194:55]
    _T_347.isa <= _T_404 @[CSR.scala 194:55]
    node _T_405 = bits(_T_377, 98, 98) @[CSR.scala 194:55]
    _T_347.debug <= _T_405 @[CSR.scala 194:55]
    wire reset_mstatus : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
    reset_mstatus is invalid
    reset_mstatus <- _T_347
    reset_mstatus.mpp <= UInt<2>("h03") @[CSR.scala 195:21]
    reset_mstatus.prv <= UInt<2>("h03") @[CSR.scala 196:21]
    reg reg_mstatus : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock with : (reset => (reset, reset_mstatus)) @[CSR.scala 197:24]
    wire new_prv : UInt
    new_prv is invalid
    new_prv <= reg_mstatus.prv
    node _T_465 = eq(new_prv, UInt<2>("h02")) @[CSR.scala 697:27]
    node _T_467 = mux(_T_465, UInt<1>("h00"), new_prv) @[CSR.scala 697:21]
    reg_mstatus.prv <= _T_467 @[CSR.scala 200:19]
    wire _T_505 : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} @[CSR.scala 202:49]
    _T_505 is invalid @[CSR.scala 202:49]
    wire _T_524 : UInt<32>
    _T_524 is invalid
    _T_524 <= UInt<1>("h00")
    node _T_525 = bits(_T_524, 1, 0) @[CSR.scala 202:49]
    _T_505.prv <= _T_525 @[CSR.scala 202:49]
    node _T_526 = bits(_T_524, 2, 2) @[CSR.scala 202:49]
    _T_505.step <= _T_526 @[CSR.scala 202:49]
    node _T_527 = bits(_T_524, 3, 3) @[CSR.scala 202:49]
    _T_505.halt <= _T_527 @[CSR.scala 202:49]
    node _T_528 = bits(_T_524, 4, 4) @[CSR.scala 202:49]
    _T_505.zero1 <= _T_528 @[CSR.scala 202:49]
    node _T_529 = bits(_T_524, 5, 5) @[CSR.scala 202:49]
    _T_505.debugint <= _T_529 @[CSR.scala 202:49]
    node _T_530 = bits(_T_524, 8, 6) @[CSR.scala 202:49]
    _T_505.cause <= _T_530 @[CSR.scala 202:49]
    node _T_531 = bits(_T_524, 9, 9) @[CSR.scala 202:49]
    _T_505.stoptime <= _T_531 @[CSR.scala 202:49]
    node _T_532 = bits(_T_524, 10, 10) @[CSR.scala 202:49]
    _T_505.stopcycle <= _T_532 @[CSR.scala 202:49]
    node _T_533 = bits(_T_524, 11, 11) @[CSR.scala 202:49]
    _T_505.zero2 <= _T_533 @[CSR.scala 202:49]
    node _T_534 = bits(_T_524, 12, 12) @[CSR.scala 202:49]
    _T_505.ebreaku <= _T_534 @[CSR.scala 202:49]
    node _T_535 = bits(_T_524, 13, 13) @[CSR.scala 202:49]
    _T_505.ebreaks <= _T_535 @[CSR.scala 202:49]
    node _T_536 = bits(_T_524, 14, 14) @[CSR.scala 202:49]
    _T_505.ebreakh <= _T_536 @[CSR.scala 202:49]
    node _T_537 = bits(_T_524, 15, 15) @[CSR.scala 202:49]
    _T_505.ebreakm <= _T_537 @[CSR.scala 202:49]
    node _T_538 = bits(_T_524, 27, 16) @[CSR.scala 202:49]
    _T_505.zero3 <= _T_538 @[CSR.scala 202:49]
    node _T_539 = bits(_T_524, 28, 28) @[CSR.scala 202:49]
    _T_505.fullreset <= _T_539 @[CSR.scala 202:49]
    node _T_540 = bits(_T_524, 29, 29) @[CSR.scala 202:49]
    _T_505.ndreset <= _T_540 @[CSR.scala 202:49]
    node _T_541 = bits(_T_524, 31, 30) @[CSR.scala 202:49]
    _T_505.xdebugver <= _T_541 @[CSR.scala 202:49]
    wire reset_dcsr : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>}
    reset_dcsr is invalid
    reset_dcsr <- _T_505
    reset_dcsr.xdebugver <= UInt<1>("h01") @[CSR.scala 203:24]
    reset_dcsr.prv <= UInt<2>("h03") @[CSR.scala 204:18]
    reg reg_dcsr : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>}, clock with : (reset => (reset, reset_dcsr)) @[CSR.scala 205:21]
    wire _T_607 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 208:43]
    _T_607 is invalid @[CSR.scala 208:43]
    wire _T_622 : UInt<13>
    _T_622 is invalid
    _T_622 <= UInt<1>("h00")
    node _T_623 = bits(_T_622, 0, 0) @[CSR.scala 208:43]
    _T_607.usip <= _T_623 @[CSR.scala 208:43]
    node _T_624 = bits(_T_622, 1, 1) @[CSR.scala 208:43]
    _T_607.ssip <= _T_624 @[CSR.scala 208:43]
    node _T_625 = bits(_T_622, 2, 2) @[CSR.scala 208:43]
    _T_607.hsip <= _T_625 @[CSR.scala 208:43]
    node _T_626 = bits(_T_622, 3, 3) @[CSR.scala 208:43]
    _T_607.msip <= _T_626 @[CSR.scala 208:43]
    node _T_627 = bits(_T_622, 4, 4) @[CSR.scala 208:43]
    _T_607.utip <= _T_627 @[CSR.scala 208:43]
    node _T_628 = bits(_T_622, 5, 5) @[CSR.scala 208:43]
    _T_607.stip <= _T_628 @[CSR.scala 208:43]
    node _T_629 = bits(_T_622, 6, 6) @[CSR.scala 208:43]
    _T_607.htip <= _T_629 @[CSR.scala 208:43]
    node _T_630 = bits(_T_622, 7, 7) @[CSR.scala 208:43]
    _T_607.mtip <= _T_630 @[CSR.scala 208:43]
    node _T_631 = bits(_T_622, 8, 8) @[CSR.scala 208:43]
    _T_607.ueip <= _T_631 @[CSR.scala 208:43]
    node _T_632 = bits(_T_622, 9, 9) @[CSR.scala 208:43]
    _T_607.seip <= _T_632 @[CSR.scala 208:43]
    node _T_633 = bits(_T_622, 10, 10) @[CSR.scala 208:43]
    _T_607.heip <= _T_633 @[CSR.scala 208:43]
    node _T_634 = bits(_T_622, 11, 11) @[CSR.scala 208:43]
    _T_607.meip <= _T_634 @[CSR.scala 208:43]
    node _T_635 = bits(_T_622, 12, 12) @[CSR.scala 208:43]
    _T_607.rocc <= _T_635 @[CSR.scala 208:43]
    wire _T_636 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    _T_636 is invalid
    _T_636 <- _T_607
    _T_636.ssip <= UInt<1>("h01") @[CSR.scala 209:14]
    _T_636.msip <= UInt<1>("h01") @[CSR.scala 210:14]
    _T_636.stip <= UInt<1>("h01") @[CSR.scala 211:14]
    _T_636.mtip <= UInt<1>("h01") @[CSR.scala 212:14]
    _T_636.meip <= UInt<1>("h01") @[CSR.scala 213:14]
    _T_636.seip <= UInt<1>("h01") @[CSR.scala 214:14]
    _T_636.rocc <= UInt<1>("h00") @[CSR.scala 215:14]
    wire _T_657 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    _T_657 is invalid
    _T_657 <- _T_636
    _T_657.msip <= UInt<1>("h00") @[CSR.scala 218:14]
    _T_657.mtip <= UInt<1>("h00") @[CSR.scala 219:14]
    _T_657.meip <= UInt<1>("h00") @[CSR.scala 220:14]
    node _T_674 = cat(_T_636.hsip, _T_636.ssip) @[CSR.scala 222:10]
    node _T_675 = cat(_T_674, _T_636.usip) @[CSR.scala 222:10]
    node _T_676 = cat(_T_636.stip, _T_636.utip) @[CSR.scala 222:10]
    node _T_677 = cat(_T_676, _T_636.msip) @[CSR.scala 222:10]
    node _T_678 = cat(_T_677, _T_675) @[CSR.scala 222:10]
    node _T_679 = cat(_T_636.ueip, _T_636.mtip) @[CSR.scala 222:10]
    node _T_680 = cat(_T_679, _T_636.htip) @[CSR.scala 222:10]
    node _T_681 = cat(_T_636.heip, _T_636.seip) @[CSR.scala 222:10]
    node _T_682 = cat(_T_636.rocc, _T_636.meip) @[CSR.scala 222:10]
    node _T_683 = cat(_T_682, _T_681) @[CSR.scala 222:10]
    node _T_684 = cat(_T_683, _T_680) @[CSR.scala 222:10]
    node supported_interrupts = cat(_T_684, _T_678) @[CSR.scala 222:10]
    node _T_685 = cat(_T_657.hsip, _T_657.ssip) @[CSR.scala 222:22]
    node _T_686 = cat(_T_685, _T_657.usip) @[CSR.scala 222:22]
    node _T_687 = cat(_T_657.stip, _T_657.utip) @[CSR.scala 222:22]
    node _T_688 = cat(_T_687, _T_657.msip) @[CSR.scala 222:22]
    node _T_689 = cat(_T_688, _T_686) @[CSR.scala 222:22]
    node _T_690 = cat(_T_657.ueip, _T_657.mtip) @[CSR.scala 222:22]
    node _T_691 = cat(_T_690, _T_657.htip) @[CSR.scala 222:22]
    node _T_692 = cat(_T_657.heip, _T_657.seip) @[CSR.scala 222:22]
    node _T_693 = cat(_T_657.rocc, _T_657.meip) @[CSR.scala 222:22]
    node _T_694 = cat(_T_693, _T_692) @[CSR.scala 222:22]
    node _T_695 = cat(_T_694, _T_691) @[CSR.scala 222:22]
    node delegable_interrupts = cat(_T_695, _T_689) @[CSR.scala 222:22]
    reg reg_debug : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[CSR.scala 232:22]
    node effective_prv = cat(reg_debug, reg_mstatus.prv) @[Cat.scala 30:58]
    reg reg_dpc : UInt<40>, clock @[CSR.scala 234:20]
    reg reg_dscratch : UInt<64>, clock @[CSR.scala 235:25]
    reg reg_singleStepped : UInt<1>, clock @[CSR.scala 236:30]
    reg reg_tselect : UInt<1>, clock @[CSR.scala 238:24]
    reg reg_bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[2], clock @[CSR.scala 239:19]
    reg reg_mie : UInt<64>, clock @[CSR.scala 241:20]
    reg reg_mideleg : UInt<64>, clock @[CSR.scala 242:24]
    reg reg_medeleg : UInt<64>, clock @[CSR.scala 243:24]
    reg reg_mip : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock @[CSR.scala 244:20]
    reg reg_mepc : UInt<40>, clock @[CSR.scala 245:21]
    reg reg_mcause : UInt<64>, clock @[CSR.scala 246:23]
    reg reg_mbadaddr : UInt<40>, clock @[CSR.scala 247:25]
    reg reg_mscratch : UInt<64>, clock @[CSR.scala 248:25]
    reg reg_mtvec : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[CSR.scala 251:27]
    reg reg_mcounteren : UInt<32>, clock @[CSR.scala 254:27]
    reg reg_scounteren : UInt<32>, clock @[CSR.scala 255:27]
    reg reg_sepc : UInt<40>, clock @[CSR.scala 258:21]
    reg reg_scause : UInt<64>, clock @[CSR.scala 259:23]
    reg reg_sbadaddr : UInt<40>, clock @[CSR.scala 260:25]
    reg reg_sscratch : UInt<64>, clock @[CSR.scala 261:25]
    reg reg_stvec : UInt<39>, clock @[CSR.scala 262:22]
    reg reg_sptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock @[CSR.scala 263:22]
    reg reg_wfi : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[CSR.scala 264:20]
    reg reg_fflags : UInt<5>, clock @[CSR.scala 266:23]
    reg reg_frm : UInt<3>, clock @[CSR.scala 267:20]
    reg _T_931 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Counters.scala 47:37]
    node _T_932 = add(_T_931, io.retire) @[Counters.scala 48:33]
    _T_931 <= _T_932 @[Counters.scala 49:9]
    reg _T_934 : UInt<58>, clock with : (reset => (reset, UInt<58>("h00"))) @[Counters.scala 52:27]
    node _T_935 = bits(_T_932, 6, 6) @[Counters.scala 53:20]
    when _T_935 : @[Counters.scala 53:34]
      node _T_937 = add(_T_934, UInt<1>("h01")) @[Counters.scala 53:43]
      node _T_938 = tail(_T_937, 1) @[Counters.scala 53:43]
      _T_934 <= _T_938 @[Counters.scala 53:38]
      skip @[Counters.scala 53:34]
    node _T_939 = cat(_T_934, _T_931) @[Cat.scala 30:58]
    reg _T_942 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Counters.scala 47:37]
    node _T_943 = add(_T_942, UInt<1>("h01")) @[Counters.scala 48:33]
    _T_942 <= _T_943 @[Counters.scala 49:9]
    reg _T_945 : UInt<58>, clock with : (reset => (reset, UInt<58>("h00"))) @[Counters.scala 52:27]
    node _T_946 = bits(_T_943, 6, 6) @[Counters.scala 53:20]
    when _T_946 : @[Counters.scala 53:34]
      node _T_948 = add(_T_945, UInt<1>("h01")) @[Counters.scala 53:43]
      node _T_949 = tail(_T_948, 1) @[Counters.scala 53:43]
      _T_945 <= _T_949 @[Counters.scala 53:38]
      skip @[Counters.scala 53:34]
    node _T_950 = cat(_T_945, _T_942) @[Cat.scala 30:58]
    node _T_953 = eq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 274:71]
    node _T_954 = or(UInt<1>("h00"), _T_953) @[CSR.scala 274:52]
    node _T_956 = mux(_T_954, UInt<3>("h07"), reg_scounteren) @[CSR.scala 274:38]
    node hpm_mask = and(reg_mcounteren, _T_956) @[CSR.scala 274:33]
    wire mip : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    mip is invalid
    mip <- reg_mip
    mip.rocc <= io.rocc_interrupt @[CSR.scala 277:12]
    node _T_970 = cat(mip.hsip, mip.ssip) @[CSR.scala 278:22]
    node _T_971 = cat(_T_970, mip.usip) @[CSR.scala 278:22]
    node _T_972 = cat(mip.stip, mip.utip) @[CSR.scala 278:22]
    node _T_973 = cat(_T_972, mip.msip) @[CSR.scala 278:22]
    node _T_974 = cat(_T_973, _T_971) @[CSR.scala 278:22]
    node _T_975 = cat(mip.ueip, mip.mtip) @[CSR.scala 278:22]
    node _T_976 = cat(_T_975, mip.htip) @[CSR.scala 278:22]
    node _T_977 = cat(mip.heip, mip.seip) @[CSR.scala 278:22]
    node _T_978 = cat(mip.rocc, mip.meip) @[CSR.scala 278:22]
    node _T_979 = cat(_T_978, _T_977) @[CSR.scala 278:22]
    node _T_980 = cat(_T_979, _T_976) @[CSR.scala 278:22]
    node _T_981 = cat(_T_980, _T_974) @[CSR.scala 278:22]
    node read_mip = and(_T_981, supported_interrupts) @[CSR.scala 278:29]
    node pending_interrupts = and(read_mip, reg_mie) @[CSR.scala 280:37]
    node _T_983 = leq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 281:42]
    node _T_985 = eq(reg_mstatus.prv, UInt<2>("h03")) @[CSR.scala 281:71]
    node _T_986 = and(_T_985, reg_mstatus.mie) @[CSR.scala 281:81]
    node _T_987 = or(_T_983, _T_986) @[CSR.scala 281:51]
    node _T_988 = not(reg_mideleg) @[CSR.scala 281:123]
    node _T_989 = and(pending_interrupts, _T_988) @[CSR.scala 281:121]
    node m_interrupts = mux(_T_987, _T_989, UInt<1>("h00")) @[CSR.scala 281:25]
    node _T_992 = eq(m_interrupts, UInt<1>("h00")) @[CSR.scala 282:39]
    node _T_994 = lt(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 282:65]
    node _T_996 = eq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 282:93]
    node _T_997 = and(_T_996, reg_mstatus.sie) @[CSR.scala 282:103]
    node _T_998 = or(_T_994, _T_997) @[CSR.scala 282:73]
    node _T_999 = and(_T_992, _T_998) @[CSR.scala 282:45]
    node _T_1000 = and(pending_interrupts, reg_mideleg) @[CSR.scala 282:144]
    node s_interrupts = mux(_T_999, _T_1000, UInt<1>("h00")) @[CSR.scala 282:25]
    node all_interrupts = or(m_interrupts, s_interrupts) @[CSR.scala 283:37]
    node _T_1003 = bits(all_interrupts, 0, 0) @[OneHot.scala 39:40]
    node _T_1004 = bits(all_interrupts, 1, 1) @[OneHot.scala 39:40]
    node _T_1005 = bits(all_interrupts, 2, 2) @[OneHot.scala 39:40]
    node _T_1006 = bits(all_interrupts, 3, 3) @[OneHot.scala 39:40]
    node _T_1007 = bits(all_interrupts, 4, 4) @[OneHot.scala 39:40]
    node _T_1008 = bits(all_interrupts, 5, 5) @[OneHot.scala 39:40]
    node _T_1009 = bits(all_interrupts, 6, 6) @[OneHot.scala 39:40]
    node _T_1010 = bits(all_interrupts, 7, 7) @[OneHot.scala 39:40]
    node _T_1011 = bits(all_interrupts, 8, 8) @[OneHot.scala 39:40]
    node _T_1012 = bits(all_interrupts, 9, 9) @[OneHot.scala 39:40]
    node _T_1013 = bits(all_interrupts, 10, 10) @[OneHot.scala 39:40]
    node _T_1014 = bits(all_interrupts, 11, 11) @[OneHot.scala 39:40]
    node _T_1015 = bits(all_interrupts, 12, 12) @[OneHot.scala 39:40]
    node _T_1016 = bits(all_interrupts, 13, 13) @[OneHot.scala 39:40]
    node _T_1017 = bits(all_interrupts, 14, 14) @[OneHot.scala 39:40]
    node _T_1018 = bits(all_interrupts, 15, 15) @[OneHot.scala 39:40]
    node _T_1019 = bits(all_interrupts, 16, 16) @[OneHot.scala 39:40]
    node _T_1020 = bits(all_interrupts, 17, 17) @[OneHot.scala 39:40]
    node _T_1021 = bits(all_interrupts, 18, 18) @[OneHot.scala 39:40]
    node _T_1022 = bits(all_interrupts, 19, 19) @[OneHot.scala 39:40]
    node _T_1023 = bits(all_interrupts, 20, 20) @[OneHot.scala 39:40]
    node _T_1024 = bits(all_interrupts, 21, 21) @[OneHot.scala 39:40]
    node _T_1025 = bits(all_interrupts, 22, 22) @[OneHot.scala 39:40]
    node _T_1026 = bits(all_interrupts, 23, 23) @[OneHot.scala 39:40]
    node _T_1027 = bits(all_interrupts, 24, 24) @[OneHot.scala 39:40]
    node _T_1028 = bits(all_interrupts, 25, 25) @[OneHot.scala 39:40]
    node _T_1029 = bits(all_interrupts, 26, 26) @[OneHot.scala 39:40]
    node _T_1030 = bits(all_interrupts, 27, 27) @[OneHot.scala 39:40]
    node _T_1031 = bits(all_interrupts, 28, 28) @[OneHot.scala 39:40]
    node _T_1032 = bits(all_interrupts, 29, 29) @[OneHot.scala 39:40]
    node _T_1033 = bits(all_interrupts, 30, 30) @[OneHot.scala 39:40]
    node _T_1034 = bits(all_interrupts, 31, 31) @[OneHot.scala 39:40]
    node _T_1035 = bits(all_interrupts, 32, 32) @[OneHot.scala 39:40]
    node _T_1036 = bits(all_interrupts, 33, 33) @[OneHot.scala 39:40]
    node _T_1037 = bits(all_interrupts, 34, 34) @[OneHot.scala 39:40]
    node _T_1038 = bits(all_interrupts, 35, 35) @[OneHot.scala 39:40]
    node _T_1039 = bits(all_interrupts, 36, 36) @[OneHot.scala 39:40]
    node _T_1040 = bits(all_interrupts, 37, 37) @[OneHot.scala 39:40]
    node _T_1041 = bits(all_interrupts, 38, 38) @[OneHot.scala 39:40]
    node _T_1042 = bits(all_interrupts, 39, 39) @[OneHot.scala 39:40]
    node _T_1043 = bits(all_interrupts, 40, 40) @[OneHot.scala 39:40]
    node _T_1044 = bits(all_interrupts, 41, 41) @[OneHot.scala 39:40]
    node _T_1045 = bits(all_interrupts, 42, 42) @[OneHot.scala 39:40]
    node _T_1046 = bits(all_interrupts, 43, 43) @[OneHot.scala 39:40]
    node _T_1047 = bits(all_interrupts, 44, 44) @[OneHot.scala 39:40]
    node _T_1048 = bits(all_interrupts, 45, 45) @[OneHot.scala 39:40]
    node _T_1049 = bits(all_interrupts, 46, 46) @[OneHot.scala 39:40]
    node _T_1050 = bits(all_interrupts, 47, 47) @[OneHot.scala 39:40]
    node _T_1051 = bits(all_interrupts, 48, 48) @[OneHot.scala 39:40]
    node _T_1052 = bits(all_interrupts, 49, 49) @[OneHot.scala 39:40]
    node _T_1053 = bits(all_interrupts, 50, 50) @[OneHot.scala 39:40]
    node _T_1054 = bits(all_interrupts, 51, 51) @[OneHot.scala 39:40]
    node _T_1055 = bits(all_interrupts, 52, 52) @[OneHot.scala 39:40]
    node _T_1056 = bits(all_interrupts, 53, 53) @[OneHot.scala 39:40]
    node _T_1057 = bits(all_interrupts, 54, 54) @[OneHot.scala 39:40]
    node _T_1058 = bits(all_interrupts, 55, 55) @[OneHot.scala 39:40]
    node _T_1059 = bits(all_interrupts, 56, 56) @[OneHot.scala 39:40]
    node _T_1060 = bits(all_interrupts, 57, 57) @[OneHot.scala 39:40]
    node _T_1061 = bits(all_interrupts, 58, 58) @[OneHot.scala 39:40]
    node _T_1062 = bits(all_interrupts, 59, 59) @[OneHot.scala 39:40]
    node _T_1063 = bits(all_interrupts, 60, 60) @[OneHot.scala 39:40]
    node _T_1064 = bits(all_interrupts, 61, 61) @[OneHot.scala 39:40]
    node _T_1065 = bits(all_interrupts, 62, 62) @[OneHot.scala 39:40]
    node _T_1066 = bits(all_interrupts, 63, 63) @[OneHot.scala 39:40]
    node _T_1131 = mux(_T_1065, UInt<6>("h03e"), UInt<6>("h03f")) @[Mux.scala 31:69]
    node _T_1132 = mux(_T_1064, UInt<6>("h03d"), _T_1131) @[Mux.scala 31:69]
    node _T_1133 = mux(_T_1063, UInt<6>("h03c"), _T_1132) @[Mux.scala 31:69]
    node _T_1134 = mux(_T_1062, UInt<6>("h03b"), _T_1133) @[Mux.scala 31:69]
    node _T_1135 = mux(_T_1061, UInt<6>("h03a"), _T_1134) @[Mux.scala 31:69]
    node _T_1136 = mux(_T_1060, UInt<6>("h039"), _T_1135) @[Mux.scala 31:69]
    node _T_1137 = mux(_T_1059, UInt<6>("h038"), _T_1136) @[Mux.scala 31:69]
    node _T_1138 = mux(_T_1058, UInt<6>("h037"), _T_1137) @[Mux.scala 31:69]
    node _T_1139 = mux(_T_1057, UInt<6>("h036"), _T_1138) @[Mux.scala 31:69]
    node _T_1140 = mux(_T_1056, UInt<6>("h035"), _T_1139) @[Mux.scala 31:69]
    node _T_1141 = mux(_T_1055, UInt<6>("h034"), _T_1140) @[Mux.scala 31:69]
    node _T_1142 = mux(_T_1054, UInt<6>("h033"), _T_1141) @[Mux.scala 31:69]
    node _T_1143 = mux(_T_1053, UInt<6>("h032"), _T_1142) @[Mux.scala 31:69]
    node _T_1144 = mux(_T_1052, UInt<6>("h031"), _T_1143) @[Mux.scala 31:69]
    node _T_1145 = mux(_T_1051, UInt<6>("h030"), _T_1144) @[Mux.scala 31:69]
    node _T_1146 = mux(_T_1050, UInt<6>("h02f"), _T_1145) @[Mux.scala 31:69]
    node _T_1147 = mux(_T_1049, UInt<6>("h02e"), _T_1146) @[Mux.scala 31:69]
    node _T_1148 = mux(_T_1048, UInt<6>("h02d"), _T_1147) @[Mux.scala 31:69]
    node _T_1149 = mux(_T_1047, UInt<6>("h02c"), _T_1148) @[Mux.scala 31:69]
    node _T_1150 = mux(_T_1046, UInt<6>("h02b"), _T_1149) @[Mux.scala 31:69]
    node _T_1151 = mux(_T_1045, UInt<6>("h02a"), _T_1150) @[Mux.scala 31:69]
    node _T_1152 = mux(_T_1044, UInt<6>("h029"), _T_1151) @[Mux.scala 31:69]
    node _T_1153 = mux(_T_1043, UInt<6>("h028"), _T_1152) @[Mux.scala 31:69]
    node _T_1154 = mux(_T_1042, UInt<6>("h027"), _T_1153) @[Mux.scala 31:69]
    node _T_1155 = mux(_T_1041, UInt<6>("h026"), _T_1154) @[Mux.scala 31:69]
    node _T_1156 = mux(_T_1040, UInt<6>("h025"), _T_1155) @[Mux.scala 31:69]
    node _T_1157 = mux(_T_1039, UInt<6>("h024"), _T_1156) @[Mux.scala 31:69]
    node _T_1158 = mux(_T_1038, UInt<6>("h023"), _T_1157) @[Mux.scala 31:69]
    node _T_1159 = mux(_T_1037, UInt<6>("h022"), _T_1158) @[Mux.scala 31:69]
    node _T_1160 = mux(_T_1036, UInt<6>("h021"), _T_1159) @[Mux.scala 31:69]
    node _T_1161 = mux(_T_1035, UInt<6>("h020"), _T_1160) @[Mux.scala 31:69]
    node _T_1162 = mux(_T_1034, UInt<5>("h01f"), _T_1161) @[Mux.scala 31:69]
    node _T_1163 = mux(_T_1033, UInt<5>("h01e"), _T_1162) @[Mux.scala 31:69]
    node _T_1164 = mux(_T_1032, UInt<5>("h01d"), _T_1163) @[Mux.scala 31:69]
    node _T_1165 = mux(_T_1031, UInt<5>("h01c"), _T_1164) @[Mux.scala 31:69]
    node _T_1166 = mux(_T_1030, UInt<5>("h01b"), _T_1165) @[Mux.scala 31:69]
    node _T_1167 = mux(_T_1029, UInt<5>("h01a"), _T_1166) @[Mux.scala 31:69]
    node _T_1168 = mux(_T_1028, UInt<5>("h019"), _T_1167) @[Mux.scala 31:69]
    node _T_1169 = mux(_T_1027, UInt<5>("h018"), _T_1168) @[Mux.scala 31:69]
    node _T_1170 = mux(_T_1026, UInt<5>("h017"), _T_1169) @[Mux.scala 31:69]
    node _T_1171 = mux(_T_1025, UInt<5>("h016"), _T_1170) @[Mux.scala 31:69]
    node _T_1172 = mux(_T_1024, UInt<5>("h015"), _T_1171) @[Mux.scala 31:69]
    node _T_1173 = mux(_T_1023, UInt<5>("h014"), _T_1172) @[Mux.scala 31:69]
    node _T_1174 = mux(_T_1022, UInt<5>("h013"), _T_1173) @[Mux.scala 31:69]
    node _T_1175 = mux(_T_1021, UInt<5>("h012"), _T_1174) @[Mux.scala 31:69]
    node _T_1176 = mux(_T_1020, UInt<5>("h011"), _T_1175) @[Mux.scala 31:69]
    node _T_1177 = mux(_T_1019, UInt<5>("h010"), _T_1176) @[Mux.scala 31:69]
    node _T_1178 = mux(_T_1018, UInt<4>("h0f"), _T_1177) @[Mux.scala 31:69]
    node _T_1179 = mux(_T_1017, UInt<4>("h0e"), _T_1178) @[Mux.scala 31:69]
    node _T_1180 = mux(_T_1016, UInt<4>("h0d"), _T_1179) @[Mux.scala 31:69]
    node _T_1181 = mux(_T_1015, UInt<4>("h0c"), _T_1180) @[Mux.scala 31:69]
    node _T_1182 = mux(_T_1014, UInt<4>("h0b"), _T_1181) @[Mux.scala 31:69]
    node _T_1183 = mux(_T_1013, UInt<4>("h0a"), _T_1182) @[Mux.scala 31:69]
    node _T_1184 = mux(_T_1012, UInt<4>("h09"), _T_1183) @[Mux.scala 31:69]
    node _T_1185 = mux(_T_1011, UInt<4>("h08"), _T_1184) @[Mux.scala 31:69]
    node _T_1186 = mux(_T_1010, UInt<3>("h07"), _T_1185) @[Mux.scala 31:69]
    node _T_1187 = mux(_T_1009, UInt<3>("h06"), _T_1186) @[Mux.scala 31:69]
    node _T_1188 = mux(_T_1008, UInt<3>("h05"), _T_1187) @[Mux.scala 31:69]
    node _T_1189 = mux(_T_1007, UInt<3>("h04"), _T_1188) @[Mux.scala 31:69]
    node _T_1190 = mux(_T_1006, UInt<2>("h03"), _T_1189) @[Mux.scala 31:69]
    node _T_1191 = mux(_T_1005, UInt<2>("h02"), _T_1190) @[Mux.scala 31:69]
    node _T_1192 = mux(_T_1004, UInt<1>("h01"), _T_1191) @[Mux.scala 31:69]
    node _T_1193 = mux(_T_1003, UInt<1>("h00"), _T_1192) @[Mux.scala 31:69]
    node _T_1194 = add(UInt<64>("h08000000000000000"), _T_1193) @[CSR.scala 285:43]
    node interruptCause = tail(_T_1194, 1) @[CSR.scala 285:43]
    node _T_1196 = neq(all_interrupts, UInt<1>("h00")) @[CSR.scala 286:34]
    node _T_1198 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 286:41]
    node _T_1199 = and(_T_1196, _T_1198) @[CSR.scala 286:38]
    node _T_1201 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 286:55]
    node _T_1202 = and(_T_1199, _T_1201) @[CSR.scala 286:52]
    node _T_1203 = or(_T_1202, reg_singleStepped) @[CSR.scala 286:70]
    io.interrupt <= _T_1203 @[CSR.scala 286:16]
    io.interrupt_cause <= interruptCause @[CSR.scala 287:22]
    io.bp[0] <- reg_bp[0] @[CSR.scala 288:9]
    node _T_1205 = and(UInt<1>("h01"), reg_dcsr.debugint) @[CSR.scala 291:26]
    node _T_1207 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 291:50]
    node _T_1208 = and(_T_1205, _T_1207) @[CSR.scala 291:47]
    when _T_1208 : @[CSR.scala 291:62]
      io.interrupt <= UInt<1>("h01") @[CSR.scala 292:18]
      node _T_1226 = add(UInt<64>("h08000000000000000"), UInt<4>("h0d")) @[CSR.scala 293:46]
      node _T_1227 = tail(_T_1226, 1) @[CSR.scala 293:46]
      io.interrupt_cause <= _T_1227 @[CSR.scala 293:24]
      skip @[CSR.scala 291:62]
    reg reg_misa : UInt, clock with : (reset => (reset, UInt<64>("h0800000000014112d"))) @[CSR.scala 307:21]
    node _T_1229 = cat(io.status.hie, io.status.sie) @[CSR.scala 308:38]
    node _T_1230 = cat(_T_1229, io.status.uie) @[CSR.scala 308:38]
    node _T_1231 = cat(io.status.upie, io.status.mie) @[CSR.scala 308:38]
    node _T_1232 = cat(io.status.hpie, io.status.spie) @[CSR.scala 308:38]
    node _T_1233 = cat(_T_1232, _T_1231) @[CSR.scala 308:38]
    node _T_1234 = cat(_T_1233, _T_1230) @[CSR.scala 308:38]
    node _T_1235 = cat(io.status.hpp, io.status.spp) @[CSR.scala 308:38]
    node _T_1236 = cat(_T_1235, io.status.mpie) @[CSR.scala 308:38]
    node _T_1237 = cat(io.status.fs, io.status.mpp) @[CSR.scala 308:38]
    node _T_1238 = cat(io.status.mprv, io.status.xs) @[CSR.scala 308:38]
    node _T_1239 = cat(_T_1238, _T_1237) @[CSR.scala 308:38]
    node _T_1240 = cat(_T_1239, _T_1236) @[CSR.scala 308:38]
    node _T_1241 = cat(_T_1240, _T_1234) @[CSR.scala 308:38]
    node _T_1242 = cat(io.status.tvm, io.status.mxr) @[CSR.scala 308:38]
    node _T_1243 = cat(_T_1242, io.status.pum) @[CSR.scala 308:38]
    node _T_1244 = cat(io.status.tsr, io.status.tw) @[CSR.scala 308:38]
    node _T_1245 = cat(io.status.sd_rv32, io.status.zero1) @[CSR.scala 308:38]
    node _T_1246 = cat(_T_1245, _T_1244) @[CSR.scala 308:38]
    node _T_1247 = cat(_T_1246, _T_1243) @[CSR.scala 308:38]
    node _T_1248 = cat(io.status.zero2, io.status.sxl) @[CSR.scala 308:38]
    node _T_1249 = cat(_T_1248, io.status.uxl) @[CSR.scala 308:38]
    node _T_1250 = cat(io.status.prv, io.status.sd) @[CSR.scala 308:38]
    node _T_1251 = cat(io.status.debug, io.status.isa) @[CSR.scala 308:38]
    node _T_1252 = cat(_T_1251, _T_1250) @[CSR.scala 308:38]
    node _T_1253 = cat(_T_1252, _T_1249) @[CSR.scala 308:38]
    node _T_1254 = cat(_T_1253, _T_1247) @[CSR.scala 308:38]
    node _T_1255 = cat(_T_1254, _T_1241) @[CSR.scala 308:38]
    node read_mstatus = bits(_T_1255, 63, 0) @[CSR.scala 308:40]
    node _T_1291 = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) @[CSR.scala 312:48]
    node _T_1292 = cat(_T_1291, reg_bp[reg_tselect].control.r) @[CSR.scala 312:48]
    node _T_1293 = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) @[CSR.scala 312:48]
    node _T_1294 = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) @[CSR.scala 312:48]
    node _T_1295 = cat(_T_1294, _T_1293) @[CSR.scala 312:48]
    node _T_1296 = cat(_T_1295, _T_1292) @[CSR.scala 312:48]
    node _T_1297 = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) @[CSR.scala 312:48]
    node _T_1298 = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) @[CSR.scala 312:48]
    node _T_1299 = cat(_T_1298, _T_1297) @[CSR.scala 312:48]
    node _T_1300 = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) @[CSR.scala 312:48]
    node _T_1301 = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) @[CSR.scala 312:48]
    node _T_1302 = cat(_T_1301, _T_1300) @[CSR.scala 312:48]
    node _T_1303 = cat(_T_1302, _T_1299) @[CSR.scala 312:48]
    node _T_1304 = cat(_T_1303, _T_1296) @[CSR.scala 312:48]
    node _T_1340 = bits(reg_bp[reg_tselect].address, 38, 38) @[Package.scala 40:38]
    node _T_1341 = bits(_T_1340, 0, 0) @[Bitwise.scala 71:15]
    node _T_1344 = mux(_T_1341, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12]
    node _T_1345 = cat(_T_1344, reg_bp[reg_tselect].address) @[Cat.scala 30:58]
    node _T_1349 = bits(reg_mepc, 39, 39) @[Package.scala 40:38]
    node _T_1350 = bits(_T_1349, 0, 0) @[Bitwise.scala 71:15]
    node _T_1353 = mux(_T_1350, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12]
    node _T_1354 = cat(_T_1353, reg_mepc) @[Cat.scala 30:58]
    node _T_1355 = bits(reg_mbadaddr, 39, 39) @[Package.scala 40:38]
    node _T_1356 = bits(_T_1355, 0, 0) @[Bitwise.scala 71:15]
    node _T_1359 = mux(_T_1356, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12]
    node _T_1360 = cat(_T_1359, reg_mbadaddr) @[Cat.scala 30:58]
    node _T_1361 = cat(reg_dcsr.step, reg_dcsr.prv) @[CSR.scala 333:27]
    node _T_1362 = cat(reg_dcsr.zero1, reg_dcsr.halt) @[CSR.scala 333:27]
    node _T_1363 = cat(_T_1362, _T_1361) @[CSR.scala 333:27]
    node _T_1364 = cat(reg_dcsr.cause, reg_dcsr.debugint) @[CSR.scala 333:27]
    node _T_1365 = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) @[CSR.scala 333:27]
    node _T_1366 = cat(_T_1365, _T_1364) @[CSR.scala 333:27]
    node _T_1367 = cat(_T_1366, _T_1363) @[CSR.scala 333:27]
    node _T_1368 = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) @[CSR.scala 333:27]
    node _T_1369 = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) @[CSR.scala 333:27]
    node _T_1370 = cat(_T_1369, _T_1368) @[CSR.scala 333:27]
    node _T_1371 = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) @[CSR.scala 333:27]
    node _T_1372 = cat(reg_dcsr.xdebugver, reg_dcsr.ndreset) @[CSR.scala 333:27]
    node _T_1373 = cat(_T_1372, reg_dcsr.fullreset) @[CSR.scala 333:27]
    node _T_1374 = cat(_T_1373, _T_1371) @[CSR.scala 333:27]
    node _T_1375 = cat(_T_1374, _T_1370) @[CSR.scala 333:27]
    node _T_1376 = cat(_T_1375, _T_1367) @[CSR.scala 333:27]
    node _T_1377 = cat(reg_frm, reg_fflags) @[Cat.scala 30:58]
    node _T_1380 = and(reg_mie, reg_mideleg) @[CSR.scala 360:28]
    node _T_1381 = and(read_mip, reg_mideleg) @[CSR.scala 361:29]
    wire _T_1382 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
    _T_1382 is invalid
    _T_1382 <- io.status
    _T_1382.mprv <= UInt<1>("h00") @[CSR.scala 363:23]
    _T_1382.mpp <= UInt<1>("h00") @[CSR.scala 364:22]
    _T_1382.hpp <= UInt<1>("h00") @[CSR.scala 365:22]
    _T_1382.mpie <= UInt<1>("h00") @[CSR.scala 366:23]
    _T_1382.hpie <= UInt<1>("h00") @[CSR.scala 367:23]
    _T_1382.mie <= UInt<1>("h00") @[CSR.scala 368:22]
    _T_1382.hie <= UInt<1>("h00") @[CSR.scala 369:22]
    node _T_1418 = cat(_T_1382.hie, _T_1382.sie) @[CSR.scala 371:57]
    node _T_1419 = cat(_T_1418, _T_1382.uie) @[CSR.scala 371:57]
    node _T_1420 = cat(_T_1382.upie, _T_1382.mie) @[CSR.scala 371:57]
    node _T_1421 = cat(_T_1382.hpie, _T_1382.spie) @[CSR.scala 371:57]
    node _T_1422 = cat(_T_1421, _T_1420) @[CSR.scala 371:57]
    node _T_1423 = cat(_T_1422, _T_1419) @[CSR.scala 371:57]
    node _T_1424 = cat(_T_1382.hpp, _T_1382.spp) @[CSR.scala 371:57]
    node _T_1425 = cat(_T_1424, _T_1382.mpie) @[CSR.scala 371:57]
    node _T_1426 = cat(_T_1382.fs, _T_1382.mpp) @[CSR.scala 371:57]
    node _T_1427 = cat(_T_1382.mprv, _T_1382.xs) @[CSR.scala 371:57]
    node _T_1428 = cat(_T_1427, _T_1426) @[CSR.scala 371:57]
    node _T_1429 = cat(_T_1428, _T_1425) @[CSR.scala 371:57]
    node _T_1430 = cat(_T_1429, _T_1423) @[CSR.scala 371:57]
    node _T_1431 = cat(_T_1382.tvm, _T_1382.mxr) @[CSR.scala 371:57]
    node _T_1432 = cat(_T_1431, _T_1382.pum) @[CSR.scala 371:57]
    node _T_1433 = cat(_T_1382.tsr, _T_1382.tw) @[CSR.scala 371:57]
    node _T_1434 = cat(_T_1382.sd_rv32, _T_1382.zero1) @[CSR.scala 371:57]
    node _T_1435 = cat(_T_1434, _T_1433) @[CSR.scala 371:57]
    node _T_1436 = cat(_T_1435, _T_1432) @[CSR.scala 371:57]
    node _T_1437 = cat(_T_1382.zero2, _T_1382.sxl) @[CSR.scala 371:57]
    node _T_1438 = cat(_T_1437, _T_1382.uxl) @[CSR.scala 371:57]
    node _T_1439 = cat(_T_1382.prv, _T_1382.sd) @[CSR.scala 371:57]
    node _T_1440 = cat(_T_1382.debug, _T_1382.isa) @[CSR.scala 371:57]
    node _T_1441 = cat(_T_1440, _T_1439) @[CSR.scala 371:57]
    node _T_1442 = cat(_T_1441, _T_1438) @[CSR.scala 371:57]
    node _T_1443 = cat(_T_1442, _T_1436) @[CSR.scala 371:57]
    node _T_1444 = cat(_T_1443, _T_1430) @[CSR.scala 371:57]
    node _T_1445 = bits(_T_1444, 63, 0) @[CSR.scala 371:60]
    node _T_1446 = bits(reg_sbadaddr, 39, 39) @[Package.scala 40:38]
    node _T_1447 = bits(_T_1446, 0, 0) @[Bitwise.scala 71:15]
    node _T_1450 = mux(_T_1447, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12]
    node _T_1451 = cat(_T_1450, reg_sbadaddr) @[Cat.scala 30:58]
    node _T_1452 = cat(reg_sptbr.mode, reg_sptbr.asid) @[CSR.scala 377:45]
    node _T_1453 = cat(_T_1452, reg_sptbr.ppn) @[CSR.scala 377:45]
    node _T_1454 = bits(reg_sepc, 39, 39) @[Package.scala 40:38]
    node _T_1455 = bits(_T_1454, 0, 0) @[Bitwise.scala 71:15]
    node _T_1458 = mux(_T_1455, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12]
    node _T_1459 = cat(_T_1458, reg_sepc) @[Cat.scala 30:58]
    node _T_1460 = bits(reg_stvec, 38, 38) @[Package.scala 40:38]
    node _T_1461 = bits(_T_1460, 0, 0) @[Bitwise.scala 71:15]
    node _T_1464 = mux(_T_1461, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12]
    node _T_1465 = cat(_T_1464, reg_stvec) @[Cat.scala 30:58]
    node _T_1467 = eq(io.rw.addr, UInt<11>("h07a0")) @[CSR.scala 405:73]
    node _T_1469 = eq(io.rw.addr, UInt<11>("h07a1")) @[CSR.scala 405:73]
    node _T_1471 = eq(io.rw.addr, UInt<11>("h07a2")) @[CSR.scala 405:73]
    node _T_1473 = eq(io.rw.addr, UInt<12>("h0f13")) @[CSR.scala 405:73]
    node _T_1475 = eq(io.rw.addr, UInt<12>("h0f12")) @[CSR.scala 405:73]
    node _T_1477 = eq(io.rw.addr, UInt<12>("h0f11")) @[CSR.scala 405:73]
    node _T_1479 = eq(io.rw.addr, UInt<12>("h0b00")) @[CSR.scala 405:73]
    node _T_1481 = eq(io.rw.addr, UInt<12>("h0b02")) @[CSR.scala 405:73]
    node _T_1483 = eq(io.rw.addr, UInt<10>("h0301")) @[CSR.scala 405:73]
    node _T_1485 = eq(io.rw.addr, UInt<10>("h0300")) @[CSR.scala 405:73]
    node _T_1487 = eq(io.rw.addr, UInt<10>("h0305")) @[CSR.scala 405:73]
    node _T_1489 = eq(io.rw.addr, UInt<10>("h0344")) @[CSR.scala 405:73]
    node _T_1491 = eq(io.rw.addr, UInt<10>("h0304")) @[CSR.scala 405:73]
    node _T_1493 = eq(io.rw.addr, UInt<10>("h0303")) @[CSR.scala 405:73]
    node _T_1495 = eq(io.rw.addr, UInt<10>("h0302")) @[CSR.scala 405:73]
    node _T_1497 = eq(io.rw.addr, UInt<10>("h0340")) @[CSR.scala 405:73]
    node _T_1499 = eq(io.rw.addr, UInt<10>("h0341")) @[CSR.scala 405:73]
    node _T_1501 = eq(io.rw.addr, UInt<10>("h0343")) @[CSR.scala 405:73]
    node _T_1503 = eq(io.rw.addr, UInt<10>("h0342")) @[CSR.scala 405:73]
    node _T_1505 = eq(io.rw.addr, UInt<12>("h0f14")) @[CSR.scala 405:73]
    node _T_1507 = eq(io.rw.addr, UInt<11>("h07b0")) @[CSR.scala 405:73]
    node _T_1509 = eq(io.rw.addr, UInt<11>("h07b1")) @[CSR.scala 405:73]
    node _T_1511 = eq(io.rw.addr, UInt<11>("h07b2")) @[CSR.scala 405:73]
    node _T_1513 = eq(io.rw.addr, UInt<1>("h01")) @[CSR.scala 405:73]
    node _T_1515 = eq(io.rw.addr, UInt<2>("h02")) @[CSR.scala 405:73]
    node _T_1517 = eq(io.rw.addr, UInt<2>("h03")) @[CSR.scala 405:73]
    node _T_1519 = eq(io.rw.addr, UInt<10>("h0323")) @[CSR.scala 405:73]
    node _T_1521 = eq(io.rw.addr, UInt<12>("h0b03")) @[CSR.scala 405:73]
    node _T_1523 = eq(io.rw.addr, UInt<12>("h0c03")) @[CSR.scala 405:73]
    node _T_1525 = eq(io.rw.addr, UInt<10>("h0324")) @[CSR.scala 405:73]
    node _T_1527 = eq(io.rw.addr, UInt<12>("h0b04")) @[CSR.scala 405:73]
    node _T_1529 = eq(io.rw.addr, UInt<12>("h0c04")) @[CSR.scala 405:73]
    node _T_1531 = eq(io.rw.addr, UInt<10>("h0325")) @[CSR.scala 405:73]
    node _T_1533 = eq(io.rw.addr, UInt<12>("h0b05")) @[CSR.scala 405:73]
    node _T_1535 = eq(io.rw.addr, UInt<12>("h0c05")) @[CSR.scala 405:73]
    node _T_1537 = eq(io.rw.addr, UInt<10>("h0326")) @[CSR.scala 405:73]
    node _T_1539 = eq(io.rw.addr, UInt<12>("h0b06")) @[CSR.scala 405:73]
    node _T_1541 = eq(io.rw.addr, UInt<12>("h0c06")) @[CSR.scala 405:73]
    node _T_1543 = eq(io.rw.addr, UInt<10>("h0327")) @[CSR.scala 405:73]
    node _T_1545 = eq(io.rw.addr, UInt<12>("h0b07")) @[CSR.scala 405:73]
    node _T_1547 = eq(io.rw.addr, UInt<12>("h0c07")) @[CSR.scala 405:73]
    node _T_1549 = eq(io.rw.addr, UInt<10>("h0328")) @[CSR.scala 405:73]
    node _T_1551 = eq(io.rw.addr, UInt<12>("h0b08")) @[CSR.scala 405:73]
    node _T_1553 = eq(io.rw.addr, UInt<12>("h0c08")) @[CSR.scala 405:73]
    node _T_1555 = eq(io.rw.addr, UInt<10>("h0329")) @[CSR.scala 405:73]
    node _T_1557 = eq(io.rw.addr, UInt<12>("h0b09")) @[CSR.scala 405:73]
    node _T_1559 = eq(io.rw.addr, UInt<12>("h0c09")) @[CSR.scala 405:73]
    node _T_1561 = eq(io.rw.addr, UInt<10>("h032a")) @[CSR.scala 405:73]
    node _T_1563 = eq(io.rw.addr, UInt<12>("h0b0a")) @[CSR.scala 405:73]
    node _T_1565 = eq(io.rw.addr, UInt<12>("h0c0a")) @[CSR.scala 405:73]
    node _T_1567 = eq(io.rw.addr, UInt<10>("h032b")) @[CSR.scala 405:73]
    node _T_1569 = eq(io.rw.addr, UInt<12>("h0b0b")) @[CSR.scala 405:73]
    node _T_1571 = eq(io.rw.addr, UInt<12>("h0c0b")) @[CSR.scala 405:73]
    node _T_1573 = eq(io.rw.addr, UInt<10>("h032c")) @[CSR.scala 405:73]
    node _T_1575 = eq(io.rw.addr, UInt<12>("h0b0c")) @[CSR.scala 405:73]
    node _T_1577 = eq(io.rw.addr, UInt<12>("h0c0c")) @[CSR.scala 405:73]
    node _T_1579 = eq(io.rw.addr, UInt<10>("h032d")) @[CSR.scala 405:73]
    node _T_1581 = eq(io.rw.addr, UInt<12>("h0b0d")) @[CSR.scala 405:73]
    node _T_1583 = eq(io.rw.addr, UInt<12>("h0c0d")) @[CSR.scala 405:73]
    node _T_1585 = eq(io.rw.addr, UInt<10>("h032e")) @[CSR.scala 405:73]
    node _T_1587 = eq(io.rw.addr, UInt<12>("h0b0e")) @[CSR.scala 405:73]
    node _T_1589 = eq(io.rw.addr, UInt<12>("h0c0e")) @[CSR.scala 405:73]
    node _T_1591 = eq(io.rw.addr, UInt<10>("h032f")) @[CSR.scala 405:73]
    node _T_1593 = eq(io.rw.addr, UInt<12>("h0b0f")) @[CSR.scala 405:73]
    node _T_1595 = eq(io.rw.addr, UInt<12>("h0c0f")) @[CSR.scala 405:73]
    node _T_1597 = eq(io.rw.addr, UInt<10>("h0330")) @[CSR.scala 405:73]
    node _T_1599 = eq(io.rw.addr, UInt<12>("h0b10")) @[CSR.scala 405:73]
    node _T_1601 = eq(io.rw.addr, UInt<12>("h0c10")) @[CSR.scala 405:73]
    node _T_1603 = eq(io.rw.addr, UInt<10>("h0331")) @[CSR.scala 405:73]
    node _T_1605 = eq(io.rw.addr, UInt<12>("h0b11")) @[CSR.scala 405:73]
    node _T_1607 = eq(io.rw.addr, UInt<12>("h0c11")) @[CSR.scala 405:73]
    node _T_1609 = eq(io.rw.addr, UInt<10>("h0332")) @[CSR.scala 405:73]
    node _T_1611 = eq(io.rw.addr, UInt<12>("h0b12")) @[CSR.scala 405:73]
    node _T_1613 = eq(io.rw.addr, UInt<12>("h0c12")) @[CSR.scala 405:73]
    node _T_1615 = eq(io.rw.addr, UInt<10>("h0333")) @[CSR.scala 405:73]
    node _T_1617 = eq(io.rw.addr, UInt<12>("h0b13")) @[CSR.scala 405:73]
    node _T_1619 = eq(io.rw.addr, UInt<12>("h0c13")) @[CSR.scala 405:73]
    node _T_1621 = eq(io.rw.addr, UInt<10>("h0334")) @[CSR.scala 405:73]
    node _T_1623 = eq(io.rw.addr, UInt<12>("h0b14")) @[CSR.scala 405:73]
    node _T_1625 = eq(io.rw.addr, UInt<12>("h0c14")) @[CSR.scala 405:73]
    node _T_1627 = eq(io.rw.addr, UInt<10>("h0335")) @[CSR.scala 405:73]
    node _T_1629 = eq(io.rw.addr, UInt<12>("h0b15")) @[CSR.scala 405:73]
    node _T_1631 = eq(io.rw.addr, UInt<12>("h0c15")) @[CSR.scala 405:73]
    node _T_1633 = eq(io.rw.addr, UInt<10>("h0336")) @[CSR.scala 405:73]
    node _T_1635 = eq(io.rw.addr, UInt<12>("h0b16")) @[CSR.scala 405:73]
    node _T_1637 = eq(io.rw.addr, UInt<12>("h0c16")) @[CSR.scala 405:73]
    node _T_1639 = eq(io.rw.addr, UInt<10>("h0337")) @[CSR.scala 405:73]
    node _T_1641 = eq(io.rw.addr, UInt<12>("h0b17")) @[CSR.scala 405:73]
    node _T_1643 = eq(io.rw.addr, UInt<12>("h0c17")) @[CSR.scala 405:73]
    node _T_1645 = eq(io.rw.addr, UInt<10>("h0338")) @[CSR.scala 405:73]
    node _T_1647 = eq(io.rw.addr, UInt<12>("h0b18")) @[CSR.scala 405:73]
    node _T_1649 = eq(io.rw.addr, UInt<12>("h0c18")) @[CSR.scala 405:73]
    node _T_1651 = eq(io.rw.addr, UInt<10>("h0339")) @[CSR.scala 405:73]
    node _T_1653 = eq(io.rw.addr, UInt<12>("h0b19")) @[CSR.scala 405:73]
    node _T_1655 = eq(io.rw.addr, UInt<12>("h0c19")) @[CSR.scala 405:73]
    node _T_1657 = eq(io.rw.addr, UInt<10>("h033a")) @[CSR.scala 405:73]
    node _T_1659 = eq(io.rw.addr, UInt<12>("h0b1a")) @[CSR.scala 405:73]
    node _T_1661 = eq(io.rw.addr, UInt<12>("h0c1a")) @[CSR.scala 405:73]
    node _T_1663 = eq(io.rw.addr, UInt<10>("h033b")) @[CSR.scala 405:73]
    node _T_1665 = eq(io.rw.addr, UInt<12>("h0b1b")) @[CSR.scala 405:73]
    node _T_1667 = eq(io.rw.addr, UInt<12>("h0c1b")) @[CSR.scala 405:73]
    node _T_1669 = eq(io.rw.addr, UInt<10>("h033c")) @[CSR.scala 405:73]
    node _T_1671 = eq(io.rw.addr, UInt<12>("h0b1c")) @[CSR.scala 405:73]
    node _T_1673 = eq(io.rw.addr, UInt<12>("h0c1c")) @[CSR.scala 405:73]
    node _T_1675 = eq(io.rw.addr, UInt<10>("h033d")) @[CSR.scala 405:73]
    node _T_1677 = eq(io.rw.addr, UInt<12>("h0b1d")) @[CSR.scala 405:73]
    node _T_1679 = eq(io.rw.addr, UInt<12>("h0c1d")) @[CSR.scala 405:73]
    node _T_1681 = eq(io.rw.addr, UInt<10>("h033e")) @[CSR.scala 405:73]
    node _T_1683 = eq(io.rw.addr, UInt<12>("h0b1e")) @[CSR.scala 405:73]
    node _T_1685 = eq(io.rw.addr, UInt<12>("h0c1e")) @[CSR.scala 405:73]
    node _T_1687 = eq(io.rw.addr, UInt<10>("h033f")) @[CSR.scala 405:73]
    node _T_1689 = eq(io.rw.addr, UInt<12>("h0b1f")) @[CSR.scala 405:73]
    node _T_1691 = eq(io.rw.addr, UInt<12>("h0c1f")) @[CSR.scala 405:73]
    node _T_1693 = eq(io.rw.addr, UInt<9>("h0100")) @[CSR.scala 405:73]
    node _T_1695 = eq(io.rw.addr, UInt<9>("h0144")) @[CSR.scala 405:73]
    node _T_1697 = eq(io.rw.addr, UInt<9>("h0104")) @[CSR.scala 405:73]
    node _T_1699 = eq(io.rw.addr, UInt<9>("h0140")) @[CSR.scala 405:73]
    node _T_1701 = eq(io.rw.addr, UInt<9>("h0142")) @[CSR.scala 405:73]
    node _T_1703 = eq(io.rw.addr, UInt<9>("h0143")) @[CSR.scala 405:73]
    node _T_1705 = eq(io.rw.addr, UInt<9>("h0180")) @[CSR.scala 405:73]
    node _T_1707 = eq(io.rw.addr, UInt<9>("h0141")) @[CSR.scala 405:73]
    node _T_1709 = eq(io.rw.addr, UInt<9>("h0105")) @[CSR.scala 405:73]
    node _T_1711 = eq(io.rw.addr, UInt<9>("h0106")) @[CSR.scala 405:73]
    node _T_1713 = eq(io.rw.addr, UInt<10>("h0306")) @[CSR.scala 405:73]
    node _T_1715 = eq(io.rw.addr, UInt<12>("h0c00")) @[CSR.scala 405:73]
    node _T_1717 = eq(io.rw.addr, UInt<12>("h0c02")) @[CSR.scala 405:73]
    node _T_1720 = eq(io.rw.cmd, UInt<3>("h02")) @[Package.scala 7:47]
    node _T_1721 = eq(io.rw.cmd, UInt<3>("h03")) @[Package.scala 7:47]
    node _T_1722 = or(_T_1720, _T_1721) @[Package.scala 7:62]
    node _T_1724 = mux(_T_1722, io.rw.rdata, UInt<1>("h00")) @[CSR.scala 406:19]
    node _T_1725 = or(_T_1724, io.rw.wdata) @[CSR.scala 406:75]
    node _T_1727 = eq(io.rw.cmd, UInt<3>("h03")) @[CSR.scala 407:30]
    node _T_1729 = mux(_T_1727, io.rw.wdata, UInt<1>("h00")) @[CSR.scala 407:19]
    node _T_1730 = not(_T_1729) @[CSR.scala 407:15]
    node wdata = and(_T_1725, _T_1730) @[CSR.scala 406:90]
    node system_insn = eq(io.rw.cmd, UInt<3>("h04")) @[CSR.scala 409:31]
    node _T_1733 = bits(io.rw.addr, 2, 0) @[CSR.scala 410:37]
    node opcode = dshl(UInt<1>("h01"), _T_1733) @[CSR.scala 410:24]
    node insn_rs2 = bits(io.rw.addr, 5, 5) @[CSR.scala 411:28]
    node _T_1735 = eq(insn_rs2, UInt<1>("h00")) @[CSR.scala 412:34]
    node _T_1736 = and(system_insn, _T_1735) @[CSR.scala 412:31]
    node _T_1737 = bits(opcode, 0, 0) @[CSR.scala 412:53]
    node insn_call = and(_T_1736, _T_1737) @[CSR.scala 412:44]
    node _T_1738 = bits(opcode, 1, 1) @[CSR.scala 413:41]
    node insn_break = and(system_insn, _T_1738) @[CSR.scala 413:32]
    node _T_1739 = bits(opcode, 2, 2) @[CSR.scala 414:39]
    node insn_ret = and(system_insn, _T_1739) @[CSR.scala 414:30]
    node _T_1740 = bits(opcode, 5, 5) @[CSR.scala 415:39]
    node insn_wfi = and(system_insn, _T_1740) @[CSR.scala 415:30]
    node insn_sfence_vma = and(system_insn, insn_rs2) @[CSR.scala 416:37]
    node _T_1743 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 418:51]
    node _T_1744 = or(UInt<1>("h00"), _T_1743) @[CSR.scala 418:34]
    node _T_1746 = eq(reg_mstatus.tw, UInt<1>("h00")) @[CSR.scala 418:62]
    node allow_wfi = or(_T_1744, _T_1746) @[CSR.scala 418:59]
    node _T_1749 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 419:58]
    node _T_1750 = or(UInt<1>("h00"), _T_1749) @[CSR.scala 419:41]
    node _T_1752 = eq(reg_mstatus.tvm, UInt<1>("h00")) @[CSR.scala 419:69]
    node allow_sfence_vma = or(_T_1750, _T_1752) @[CSR.scala 419:66]
    node _T_1755 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 420:52]
    node _T_1756 = or(UInt<1>("h00"), _T_1755) @[CSR.scala 420:35]
    node _T_1758 = eq(reg_mstatus.tsr, UInt<1>("h00")) @[CSR.scala 420:63]
    node allow_sret = or(_T_1756, _T_1758) @[CSR.scala 420:60]
    node _T_1760 = eq(io.status.fs, UInt<1>("h00")) @[CSR.scala 421:40]
    node _T_1761 = bits(reg_misa, 5, 5) @[CSR.scala 421:58]
    node _T_1763 = eq(_T_1761, UInt<1>("h00")) @[CSR.scala 421:49]
    node _T_1764 = or(_T_1760, _T_1763) @[CSR.scala 421:46]
    io.decode.fp_illegal <= _T_1764 @[CSR.scala 421:24]
    node _T_1766 = eq(io.status.xs, UInt<1>("h00")) @[CSR.scala 422:42]
    node _T_1767 = bits(reg_misa, 23, 23) @[CSR.scala 422:60]
    node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[CSR.scala 422:51]
    node _T_1770 = or(_T_1766, _T_1769) @[CSR.scala 422:48]
    io.decode.rocc_illegal <= _T_1770 @[CSR.scala 422:26]
    node _T_1771 = bits(io.decode.csr, 9, 8) @[CSR.scala 423:58]
    node _T_1772 = lt(effective_prv, _T_1771) @[CSR.scala 423:43]
    node _T_1774 = eq(io.decode.csr, UInt<11>("h07a0")) @[CSR.scala 424:42]
    node _T_1776 = eq(io.decode.csr, UInt<11>("h07a1")) @[CSR.scala 424:42]
    node _T_1778 = eq(io.decode.csr, UInt<11>("h07a2")) @[CSR.scala 424:42]
    node _T_1780 = eq(io.decode.csr, UInt<12>("h0f13")) @[CSR.scala 424:42]
    node _T_1782 = eq(io.decode.csr, UInt<12>("h0f12")) @[CSR.scala 424:42]
    node _T_1784 = eq(io.decode.csr, UInt<12>("h0f11")) @[CSR.scala 424:42]
    node _T_1786 = eq(io.decode.csr, UInt<12>("h0b00")) @[CSR.scala 424:42]
    node _T_1788 = eq(io.decode.csr, UInt<12>("h0b02")) @[CSR.scala 424:42]
    node _T_1790 = eq(io.decode.csr, UInt<10>("h0301")) @[CSR.scala 424:42]
    node _T_1792 = eq(io.decode.csr, UInt<10>("h0300")) @[CSR.scala 424:42]
    node _T_1794 = eq(io.decode.csr, UInt<10>("h0305")) @[CSR.scala 424:42]
    node _T_1796 = eq(io.decode.csr, UInt<10>("h0344")) @[CSR.scala 424:42]
    node _T_1798 = eq(io.decode.csr, UInt<10>("h0304")) @[CSR.scala 424:42]
    node _T_1800 = eq(io.decode.csr, UInt<10>("h0303")) @[CSR.scala 424:42]
    node _T_1802 = eq(io.decode.csr, UInt<10>("h0302")) @[CSR.scala 424:42]
    node _T_1804 = eq(io.decode.csr, UInt<10>("h0340")) @[CSR.scala 424:42]
    node _T_1806 = eq(io.decode.csr, UInt<10>("h0341")) @[CSR.scala 424:42]
    node _T_1808 = eq(io.decode.csr, UInt<10>("h0343")) @[CSR.scala 424:42]
    node _T_1810 = eq(io.decode.csr, UInt<10>("h0342")) @[CSR.scala 424:42]
    node _T_1812 = eq(io.decode.csr, UInt<12>("h0f14")) @[CSR.scala 424:42]
    node _T_1814 = eq(io.decode.csr, UInt<11>("h07b0")) @[CSR.scala 424:42]
    node _T_1816 = eq(io.decode.csr, UInt<11>("h07b1")) @[CSR.scala 424:42]
    node _T_1818 = eq(io.decode.csr, UInt<11>("h07b2")) @[CSR.scala 424:42]
    node _T_1820 = eq(io.decode.csr, UInt<1>("h01")) @[CSR.scala 424:42]
    node _T_1822 = eq(io.decode.csr, UInt<2>("h02")) @[CSR.scala 424:42]
    node _T_1824 = eq(io.decode.csr, UInt<2>("h03")) @[CSR.scala 424:42]
    node _T_1826 = eq(io.decode.csr, UInt<10>("h0323")) @[CSR.scala 424:42]
    node _T_1828 = eq(io.decode.csr, UInt<12>("h0b03")) @[CSR.scala 424:42]
    node _T_1830 = eq(io.decode.csr, UInt<12>("h0c03")) @[CSR.scala 424:42]
    node _T_1832 = eq(io.decode.csr, UInt<10>("h0324")) @[CSR.scala 424:42]
    node _T_1834 = eq(io.decode.csr, UInt<12>("h0b04")) @[CSR.scala 424:42]
    node _T_1836 = eq(io.decode.csr, UInt<12>("h0c04")) @[CSR.scala 424:42]
    node _T_1838 = eq(io.decode.csr, UInt<10>("h0325")) @[CSR.scala 424:42]
    node _T_1840 = eq(io.decode.csr, UInt<12>("h0b05")) @[CSR.scala 424:42]
    node _T_1842 = eq(io.decode.csr, UInt<12>("h0c05")) @[CSR.scala 424:42]
    node _T_1844 = eq(io.decode.csr, UInt<10>("h0326")) @[CSR.scala 424:42]
    node _T_1846 = eq(io.decode.csr, UInt<12>("h0b06")) @[CSR.scala 424:42]
    node _T_1848 = eq(io.decode.csr, UInt<12>("h0c06")) @[CSR.scala 424:42]
    node _T_1850 = eq(io.decode.csr, UInt<10>("h0327")) @[CSR.scala 424:42]
    node _T_1852 = eq(io.decode.csr, UInt<12>("h0b07")) @[CSR.scala 424:42]
    node _T_1854 = eq(io.decode.csr, UInt<12>("h0c07")) @[CSR.scala 424:42]
    node _T_1856 = eq(io.decode.csr, UInt<10>("h0328")) @[CSR.scala 424:42]
    node _T_1858 = eq(io.decode.csr, UInt<12>("h0b08")) @[CSR.scala 424:42]
    node _T_1860 = eq(io.decode.csr, UInt<12>("h0c08")) @[CSR.scala 424:42]
    node _T_1862 = eq(io.decode.csr, UInt<10>("h0329")) @[CSR.scala 424:42]
    node _T_1864 = eq(io.decode.csr, UInt<12>("h0b09")) @[CSR.scala 424:42]
    node _T_1866 = eq(io.decode.csr, UInt<12>("h0c09")) @[CSR.scala 424:42]
    node _T_1868 = eq(io.decode.csr, UInt<10>("h032a")) @[CSR.scala 424:42]
    node _T_1870 = eq(io.decode.csr, UInt<12>("h0b0a")) @[CSR.scala 424:42]
    node _T_1872 = eq(io.decode.csr, UInt<12>("h0c0a")) @[CSR.scala 424:42]
    node _T_1874 = eq(io.decode.csr, UInt<10>("h032b")) @[CSR.scala 424:42]
    node _T_1876 = eq(io.decode.csr, UInt<12>("h0b0b")) @[CSR.scala 424:42]
    node _T_1878 = eq(io.decode.csr, UInt<12>("h0c0b")) @[CSR.scala 424:42]
    node _T_1880 = eq(io.decode.csr, UInt<10>("h032c")) @[CSR.scala 424:42]
    node _T_1882 = eq(io.decode.csr, UInt<12>("h0b0c")) @[CSR.scala 424:42]
    node _T_1884 = eq(io.decode.csr, UInt<12>("h0c0c")) @[CSR.scala 424:42]
    node _T_1886 = eq(io.decode.csr, UInt<10>("h032d")) @[CSR.scala 424:42]
    node _T_1888 = eq(io.decode.csr, UInt<12>("h0b0d")) @[CSR.scala 424:42]
    node _T_1890 = eq(io.decode.csr, UInt<12>("h0c0d")) @[CSR.scala 424:42]
    node _T_1892 = eq(io.decode.csr, UInt<10>("h032e")) @[CSR.scala 424:42]
    node _T_1894 = eq(io.decode.csr, UInt<12>("h0b0e")) @[CSR.scala 424:42]
    node _T_1896 = eq(io.decode.csr, UInt<12>("h0c0e")) @[CSR.scala 424:42]
    node _T_1898 = eq(io.decode.csr, UInt<10>("h032f")) @[CSR.scala 424:42]
    node _T_1900 = eq(io.decode.csr, UInt<12>("h0b0f")) @[CSR.scala 424:42]
    node _T_1902 = eq(io.decode.csr, UInt<12>("h0c0f")) @[CSR.scala 424:42]
    node _T_1904 = eq(io.decode.csr, UInt<10>("h0330")) @[CSR.scala 424:42]
    node _T_1906 = eq(io.decode.csr, UInt<12>("h0b10")) @[CSR.scala 424:42]
    node _T_1908 = eq(io.decode.csr, UInt<12>("h0c10")) @[CSR.scala 424:42]
    node _T_1910 = eq(io.decode.csr, UInt<10>("h0331")) @[CSR.scala 424:42]
    node _T_1912 = eq(io.decode.csr, UInt<12>("h0b11")) @[CSR.scala 424:42]
    node _T_1914 = eq(io.decode.csr, UInt<12>("h0c11")) @[CSR.scala 424:42]
    node _T_1916 = eq(io.decode.csr, UInt<10>("h0332")) @[CSR.scala 424:42]
    node _T_1918 = eq(io.decode.csr, UInt<12>("h0b12")) @[CSR.scala 424:42]
    node _T_1920 = eq(io.decode.csr, UInt<12>("h0c12")) @[CSR.scala 424:42]
    node _T_1922 = eq(io.decode.csr, UInt<10>("h0333")) @[CSR.scala 424:42]
    node _T_1924 = eq(io.decode.csr, UInt<12>("h0b13")) @[CSR.scala 424:42]
    node _T_1926 = eq(io.decode.csr, UInt<12>("h0c13")) @[CSR.scala 424:42]
    node _T_1928 = eq(io.decode.csr, UInt<10>("h0334")) @[CSR.scala 424:42]
    node _T_1930 = eq(io.decode.csr, UInt<12>("h0b14")) @[CSR.scala 424:42]
    node _T_1932 = eq(io.decode.csr, UInt<12>("h0c14")) @[CSR.scala 424:42]
    node _T_1934 = eq(io.decode.csr, UInt<10>("h0335")) @[CSR.scala 424:42]
    node _T_1936 = eq(io.decode.csr, UInt<12>("h0b15")) @[CSR.scala 424:42]
    node _T_1938 = eq(io.decode.csr, UInt<12>("h0c15")) @[CSR.scala 424:42]
    node _T_1940 = eq(io.decode.csr, UInt<10>("h0336")) @[CSR.scala 424:42]
    node _T_1942 = eq(io.decode.csr, UInt<12>("h0b16")) @[CSR.scala 424:42]
    node _T_1944 = eq(io.decode.csr, UInt<12>("h0c16")) @[CSR.scala 424:42]
    node _T_1946 = eq(io.decode.csr, UInt<10>("h0337")) @[CSR.scala 424:42]
    node _T_1948 = eq(io.decode.csr, UInt<12>("h0b17")) @[CSR.scala 424:42]
    node _T_1950 = eq(io.decode.csr, UInt<12>("h0c17")) @[CSR.scala 424:42]
    node _T_1952 = eq(io.decode.csr, UInt<10>("h0338")) @[CSR.scala 424:42]
    node _T_1954 = eq(io.decode.csr, UInt<12>("h0b18")) @[CSR.scala 424:42]
    node _T_1956 = eq(io.decode.csr, UInt<12>("h0c18")) @[CSR.scala 424:42]
    node _T_1958 = eq(io.decode.csr, UInt<10>("h0339")) @[CSR.scala 424:42]
    node _T_1960 = eq(io.decode.csr, UInt<12>("h0b19")) @[CSR.scala 424:42]
    node _T_1962 = eq(io.decode.csr, UInt<12>("h0c19")) @[CSR.scala 424:42]
    node _T_1964 = eq(io.decode.csr, UInt<10>("h033a")) @[CSR.scala 424:42]
    node _T_1966 = eq(io.decode.csr, UInt<12>("h0b1a")) @[CSR.scala 424:42]
    node _T_1968 = eq(io.decode.csr, UInt<12>("h0c1a")) @[CSR.scala 424:42]
    node _T_1970 = eq(io.decode.csr, UInt<10>("h033b")) @[CSR.scala 424:42]
    node _T_1972 = eq(io.decode.csr, UInt<12>("h0b1b")) @[CSR.scala 424:42]
    node _T_1974 = eq(io.decode.csr, UInt<12>("h0c1b")) @[CSR.scala 424:42]
    node _T_1976 = eq(io.decode.csr, UInt<10>("h033c")) @[CSR.scala 424:42]
    node _T_1978 = eq(io.decode.csr, UInt<12>("h0b1c")) @[CSR.scala 424:42]
    node _T_1980 = eq(io.decode.csr, UInt<12>("h0c1c")) @[CSR.scala 424:42]
    node _T_1982 = eq(io.decode.csr, UInt<10>("h033d")) @[CSR.scala 424:42]
    node _T_1984 = eq(io.decode.csr, UInt<12>("h0b1d")) @[CSR.scala 424:42]
    node _T_1986 = eq(io.decode.csr, UInt<12>("h0c1d")) @[CSR.scala 424:42]
    node _T_1988 = eq(io.decode.csr, UInt<10>("h033e")) @[CSR.scala 424:42]
    node _T_1990 = eq(io.decode.csr, UInt<12>("h0b1e")) @[CSR.scala 424:42]
    node _T_1992 = eq(io.decode.csr, UInt<12>("h0c1e")) @[CSR.scala 424:42]
    node _T_1994 = eq(io.decode.csr, UInt<10>("h033f")) @[CSR.scala 424:42]
    node _T_1996 = eq(io.decode.csr, UInt<12>("h0b1f")) @[CSR.scala 424:42]
    node _T_1998 = eq(io.decode.csr, UInt<12>("h0c1f")) @[CSR.scala 424:42]
    node _T_2000 = eq(io.decode.csr, UInt<9>("h0100")) @[CSR.scala 424:42]
    node _T_2002 = eq(io.decode.csr, UInt<9>("h0144")) @[CSR.scala 424:42]
    node _T_2004 = eq(io.decode.csr, UInt<9>("h0104")) @[CSR.scala 424:42]
    node _T_2006 = eq(io.decode.csr, UInt<9>("h0140")) @[CSR.scala 424:42]
    node _T_2008 = eq(io.decode.csr, UInt<9>("h0142")) @[CSR.scala 424:42]
    node _T_2010 = eq(io.decode.csr, UInt<9>("h0143")) @[CSR.scala 424:42]
    node _T_2012 = eq(io.decode.csr, UInt<9>("h0180")) @[CSR.scala 424:42]
    node _T_2014 = eq(io.decode.csr, UInt<9>("h0141")) @[CSR.scala 424:42]
    node _T_2016 = eq(io.decode.csr, UInt<9>("h0105")) @[CSR.scala 424:42]
    node _T_2018 = eq(io.decode.csr, UInt<9>("h0106")) @[CSR.scala 424:42]
    node _T_2020 = eq(io.decode.csr, UInt<10>("h0306")) @[CSR.scala 424:42]
    node _T_2022 = eq(io.decode.csr, UInt<12>("h0c00")) @[CSR.scala 424:42]
    node _T_2024 = eq(io.decode.csr, UInt<12>("h0c02")) @[CSR.scala 424:42]
    node _T_2025 = or(_T_1952, _T_1820) @[CSR.scala 424:57]
    node _T_2026 = or(_T_2025, _T_1864) @[CSR.scala 424:57]
    node _T_2027 = or(_T_2026, _T_2006) @[CSR.scala 424:57]
    node _T_2028 = or(_T_2027, _T_1978) @[CSR.scala 424:57]
    node _T_2029 = or(_T_2028, _T_1946) @[CSR.scala 424:57]
    node _T_2030 = or(_T_2029, _T_1832) @[CSR.scala 424:57]
    node _T_2031 = or(_T_2030, _T_1800) @[CSR.scala 424:57]
    node _T_2032 = or(_T_2031, _T_2020) @[CSR.scala 424:57]
    node _T_2033 = or(_T_2032, _T_1914) @[CSR.scala 424:57]
    node _T_2034 = or(_T_2033, _T_1876) @[CSR.scala 424:57]
    node _T_2035 = or(_T_2034, _T_1920) @[CSR.scala 424:57]
    node _T_2036 = or(_T_2035, _T_1788) @[CSR.scala 424:57]
    node _T_2037 = or(_T_2036, _T_1844) @[CSR.scala 424:57]
    node _T_2038 = or(_T_2037, _T_1888) @[CSR.scala 424:57]
    node _T_2039 = or(_T_2038, _T_1872) @[CSR.scala 424:57]
    node _T_2040 = or(_T_2039, _T_1988) @[CSR.scala 424:57]
    node _T_2041 = or(_T_2040, _T_1910) @[CSR.scala 424:57]
    node _T_2042 = or(_T_2041, _T_1924) @[CSR.scala 424:57]
    node _T_2043 = or(_T_2042, _T_1776) @[CSR.scala 424:57]
    node _T_2044 = or(_T_2043, _T_1808) @[CSR.scala 424:57]
    node _T_2045 = or(_T_2044, _T_1892) @[CSR.scala 424:57]
    node _T_2046 = or(_T_2045, _T_1840) @[CSR.scala 424:57]
    node _T_2047 = or(_T_2046, _T_1956) @[CSR.scala 424:57]
    node _T_2048 = or(_T_2047, _T_2010) @[CSR.scala 424:57]
    node _T_2049 = or(_T_2048, _T_1868) @[CSR.scala 424:57]
    node _T_2050 = or(_T_2049, _T_2000) @[CSR.scala 424:57]
    node _T_2051 = or(_T_2050, _T_1878) @[CSR.scala 424:57]
    node _T_2052 = or(_T_2051, _T_1942) @[CSR.scala 424:57]
    node _T_2053 = or(_T_2052, _T_1812) @[CSR.scala 424:57]
    node _T_2054 = or(_T_2053, _T_1974) @[CSR.scala 424:57]
    node _T_2055 = or(_T_2054, _T_1968) @[CSR.scala 424:57]
    node _T_2056 = or(_T_2055, _T_1780) @[CSR.scala 424:57]
    node _T_2057 = or(_T_2056, _T_1836) @[CSR.scala 424:57]
    node _T_2058 = or(_T_2057, _T_1996) @[CSR.scala 424:57]
    node _T_2059 = or(_T_2058, _T_1814) @[CSR.scala 424:57]
    node _T_2060 = or(_T_2059, _T_1900) @[CSR.scala 424:57]
    node _T_2061 = or(_T_2060, _T_1846) @[CSR.scala 424:57]
    node _T_2062 = or(_T_2061, _T_1932) @[CSR.scala 424:57]
    node _T_2063 = or(_T_2062, _T_1964) @[CSR.scala 424:57]
    node _T_2064 = or(_T_2063, _T_1782) @[CSR.scala 424:57]
    node _T_2065 = or(_T_2064, _T_1904) @[CSR.scala 424:57]
    node _T_2066 = or(_T_2065, _T_1992) @[CSR.scala 424:57]
    node _T_2067 = or(_T_2066, _T_1860) @[CSR.scala 424:57]
    node _T_2068 = or(_T_2067, _T_1804) @[CSR.scala 424:57]
    node _T_2069 = or(_T_2068, _T_1936) @[CSR.scala 424:57]
    node _T_2070 = or(_T_2069, _T_1960) @[CSR.scala 424:57]
    node _T_2071 = or(_T_2070, _T_1828) @[CSR.scala 424:57]
    node _T_2072 = or(_T_2071, _T_1908) @[CSR.scala 424:57]
    node _T_2073 = or(_T_2072, _T_2024) @[CSR.scala 424:57]
    node _T_2074 = or(_T_2073, _T_2004) @[CSR.scala 424:57]
    node _T_2075 = or(_T_2074, _T_1856) @[CSR.scala 424:57]
    node _T_2076 = or(_T_2075, _T_1940) @[CSR.scala 424:57]
    node _T_2077 = or(_T_2076, _T_1792) @[CSR.scala 424:57]
    node _T_2078 = or(_T_2077, _T_1972) @[CSR.scala 424:57]
    node _T_2079 = or(_T_2078, _T_1824) @[CSR.scala 424:57]
    node _T_2080 = or(_T_2079, _T_1896) @[CSR.scala 424:57]
    node _T_2081 = or(_T_2080, _T_1928) @[CSR.scala 424:57]
    node _T_2082 = or(_T_2081, _T_1796) @[CSR.scala 424:57]
    node _T_2083 = or(_T_2082, _T_1918) @[CSR.scala 424:57]
    node _T_2084 = or(_T_2083, _T_1786) @[CSR.scala 424:57]
    node _T_2085 = or(_T_2084, _T_1980) @[CSR.scala 424:57]
    node _T_2086 = or(_T_2085, _T_1774) @[CSR.scala 424:57]
    node _T_2087 = or(_T_2086, _T_1830) @[CSR.scala 424:57]
    node _T_2088 = or(_T_2087, _T_1890) @[CSR.scala 424:57]
    node _T_2089 = or(_T_2088, _T_2018) @[CSR.scala 424:57]
    node _T_2090 = or(_T_2089, _T_1916) @[CSR.scala 424:57]
    node _T_2091 = or(_T_2090, _T_1884) @[CSR.scala 424:57]
    node _T_2092 = or(_T_2091, _T_1862) @[CSR.scala 424:57]
    node _T_2093 = or(_T_2092, _T_1948) @[CSR.scala 424:57]
    node _T_2094 = or(_T_2093, _T_1798) @[CSR.scala 424:57]
    node _T_2095 = or(_T_2094, _T_1976) @[CSR.scala 424:57]
    node _T_2096 = or(_T_2095, _T_1886) @[CSR.scala 424:57]
    node _T_2097 = or(_T_2096, _T_1950) @[CSR.scala 424:57]
    node _T_2098 = or(_T_2097, _T_1818) @[CSR.scala 424:57]
    node _T_2099 = or(_T_2098, _T_1982) @[CSR.scala 424:57]
    node _T_2100 = or(_T_2099, _T_1850) @[CSR.scala 424:57]
    node _T_2101 = or(_T_2100, _T_1810) @[CSR.scala 424:57]
    node _T_2102 = or(_T_2101, _T_1944) @[CSR.scala 424:57]
    node _T_2103 = or(_T_2102, _T_2014) @[CSR.scala 424:57]
    node _T_2104 = or(_T_2103, _T_1838) @[CSR.scala 424:57]
    node _T_2105 = or(_T_2104, _T_1954) @[CSR.scala 424:57]
    node _T_2106 = or(_T_2105, _T_1870) @[CSR.scala 424:57]
    node _T_2107 = or(_T_2106, _T_1986) @[CSR.scala 424:57]
    node _T_2108 = or(_T_2107, _T_2008) @[CSR.scala 424:57]
    node _T_2109 = or(_T_2108, _T_1922) @[CSR.scala 424:57]
    node _T_2110 = or(_T_2109, _T_1778) @[CSR.scala 424:57]
    node _T_2111 = or(_T_2110, _T_1806) @[CSR.scala 424:57]
    node _T_2112 = or(_T_2111, _T_1842) @[CSR.scala 424:57]
    node _T_2113 = or(_T_2112, _T_1874) @[CSR.scala 424:57]
    node _T_2114 = or(_T_2113, _T_1880) @[CSR.scala 424:57]
    node _T_2115 = or(_T_2114, _T_2012) @[CSR.scala 424:57]
    node _T_2116 = or(_T_2115, _T_1912) @[CSR.scala 424:57]
    node _T_2117 = or(_T_2116, _T_1802) @[CSR.scala 424:57]
    node _T_2118 = or(_T_2117, _T_1934) @[CSR.scala 424:57]
    node _T_2119 = or(_T_2118, _T_1848) @[CSR.scala 424:57]
    node _T_2120 = or(_T_2119, _T_1962) @[CSR.scala 424:57]
    node _T_2121 = or(_T_2120, _T_1784) @[CSR.scala 424:57]
    node _T_2122 = or(_T_2121, _T_1902) @[CSR.scala 424:57]
    node _T_2123 = or(_T_2122, _T_1994) @[CSR.scala 424:57]
    node _T_2124 = or(_T_2123, _T_2016) @[CSR.scala 424:57]
    node _T_2125 = or(_T_2124, _T_1930) @[CSR.scala 424:57]
    node _T_2126 = or(_T_2125, _T_1816) @[CSR.scala 424:57]
    node _T_2127 = or(_T_2126, _T_1834) @[CSR.scala 424:57]
    node _T_2128 = or(_T_2127, _T_1966) @[CSR.scala 424:57]
    node _T_2129 = or(_T_2128, _T_1898) @[CSR.scala 424:57]
    node _T_2130 = or(_T_2129, _T_1866) @[CSR.scala 424:57]
    node _T_2131 = or(_T_2130, _T_1998) @[CSR.scala 424:57]
    node _T_2132 = or(_T_2131, _T_1926) @[CSR.scala 424:57]
    node _T_2133 = or(_T_2132, _T_1794) @[CSR.scala 424:57]
    node _T_2134 = or(_T_2133, _T_1882) @[CSR.scala 424:57]
    node _T_2135 = or(_T_2134, _T_1970) @[CSR.scala 424:57]
    node _T_2136 = or(_T_2135, _T_1822) @[CSR.scala 424:57]
    node _T_2137 = or(_T_2136, _T_1894) @[CSR.scala 424:57]
    node _T_2138 = or(_T_2137, _T_2002) @[CSR.scala 424:57]
    node _T_2139 = or(_T_2138, _T_1854) @[CSR.scala 424:57]
    node _T_2140 = or(_T_2139, _T_1938) @[CSR.scala 424:57]
    node _T_2141 = or(_T_2140, _T_1984) @[CSR.scala 424:57]
    node _T_2142 = or(_T_2141, _T_1790) @[CSR.scala 424:57]
    node _T_2143 = or(_T_2142, _T_1852) @[CSR.scala 424:57]
    node _T_2144 = or(_T_2143, _T_1958) @[CSR.scala 424:57]
    node _T_2145 = or(_T_2144, _T_1826) @[CSR.scala 424:57]
    node _T_2146 = or(_T_2145, _T_2022) @[CSR.scala 424:57]
    node _T_2147 = or(_T_2146, _T_1906) @[CSR.scala 424:57]
    node _T_2148 = or(_T_2147, _T_1990) @[CSR.scala 424:57]
    node _T_2149 = or(_T_2148, _T_1858) @[CSR.scala 424:57]
    node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[CSR.scala 424:5]
    node _T_2152 = or(_T_1772, _T_2151) @[CSR.scala 423:64]
    node _T_2154 = eq(io.decode.csr, UInt<9>("h0180")) @[CSR.scala 425:19]
    node _T_2156 = eq(allow_sfence_vma, UInt<1>("h00")) @[CSR.scala 425:37]
    node _T_2157 = and(_T_2154, _T_2156) @[CSR.scala 425:34]
    node _T_2158 = or(_T_2152, _T_2157) @[CSR.scala 424:62]
    node _T_2161 = geq(io.decode.csr, UInt<12>("h0c00")) @[Package.scala 47:47]
    node _T_2162 = lt(io.decode.csr, UInt<12>("h0c20")) @[Package.scala 47:60]
    node _T_2163 = and(_T_2161, _T_2162) @[Package.scala 47:55]
    node _T_2166 = geq(io.decode.csr, UInt<12>("h0c80")) @[Package.scala 47:47]
    node _T_2167 = lt(io.decode.csr, UInt<12>("h0ca0")) @[Package.scala 47:60]
    node _T_2168 = and(_T_2166, _T_2167) @[Package.scala 47:55]
    node _T_2169 = or(_T_2163, _T_2168) @[CSR.scala 426:67]
    node _T_2171 = leq(effective_prv, UInt<1>("h01")) @[CSR.scala 426:151]
    node _T_2172 = and(_T_2169, _T_2171) @[CSR.scala 426:134]
    node _T_2173 = bits(io.decode.csr, 11, 0) @[CSR.scala 426:185]
    node _T_2174 = dshr(hpm_mask, _T_2173) @[CSR.scala 426:171]
    node _T_2175 = bits(_T_2174, 0, 0) @[CSR.scala 426:171]
    node _T_2176 = and(_T_2172, _T_2175) @[CSR.scala 426:160]
    node _T_2177 = or(_T_2158, _T_2176) @[CSR.scala 425:55]
    node _T_2180 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 427:25]
    node _T_2181 = and(UInt<1>("h01"), _T_2180) @[CSR.scala 427:22]
    node _T_2183 = eq(io.decode.csr, UInt<11>("h07b0")) @[CSR.scala 427:73]
    node _T_2185 = eq(io.decode.csr, UInt<11>("h07b1")) @[CSR.scala 427:73]
    node _T_2187 = eq(io.decode.csr, UInt<11>("h07b2")) @[CSR.scala 427:73]
    node _T_2188 = or(_T_2183, _T_2185) @[CSR.scala 427:88]
    node _T_2189 = or(_T_2188, _T_2187) @[CSR.scala 427:88]
    node _T_2190 = and(_T_2181, _T_2189) @[CSR.scala 427:36]
    node _T_2191 = or(_T_2177, _T_2190) @[CSR.scala 426:215]
    node _T_2194 = eq(io.decode.csr, UInt<1>("h01")) @[CSR.scala 428:54]
    node _T_2196 = eq(io.decode.csr, UInt<2>("h02")) @[CSR.scala 428:54]
    node _T_2198 = eq(io.decode.csr, UInt<2>("h03")) @[CSR.scala 428:54]
    node _T_2199 = or(_T_2194, _T_2196) @[CSR.scala 428:69]
    node _T_2200 = or(_T_2199, _T_2198) @[CSR.scala 428:69]
    node _T_2201 = and(UInt<1>("h01"), _T_2200) @[CSR.scala 428:20]
    node _T_2202 = and(_T_2201, io.decode.fp_illegal) @[CSR.scala 428:74]
    node _T_2203 = or(_T_2191, _T_2202) @[CSR.scala 427:93]
    io.decode.read_illegal <= _T_2203 @[CSR.scala 423:26]
    node _T_2204 = bits(io.decode.csr, 11, 10) @[CSR.scala 429:43]
    node _T_2205 = not(_T_2204) @[CSR.scala 429:51]
    node _T_2207 = eq(_T_2205, UInt<1>("h00")) @[CSR.scala 429:51]
    io.decode.write_illegal <= _T_2207 @[CSR.scala 429:27]
    node _T_2209 = geq(io.decode.csr, UInt<10>("h0340")) @[CSR.scala 430:44]
    node _T_2211 = leq(io.decode.csr, UInt<10>("h0343")) @[CSR.scala 430:78]
    node _T_2212 = and(_T_2209, _T_2211) @[CSR.scala 430:61]
    node _T_2214 = geq(io.decode.csr, UInt<9>("h0140")) @[CSR.scala 430:112]
    node _T_2216 = leq(io.decode.csr, UInt<9>("h0143")) @[CSR.scala 430:146]
    node _T_2217 = and(_T_2214, _T_2216) @[CSR.scala 430:129]
    node _T_2218 = or(_T_2212, _T_2217) @[CSR.scala 430:95]
    node _T_2220 = eq(_T_2218, UInt<1>("h00")) @[CSR.scala 430:28]
    io.decode.write_flush <= _T_2220 @[CSR.scala 430:25]
    node _T_2221 = bits(io.decode.csr, 9, 8) @[CSR.scala 431:60]
    node _T_2222 = lt(effective_prv, _T_2221) @[CSR.scala 431:45]
    node _T_2223 = bits(io.decode.csr, 5, 5) @[CSR.scala 432:19]
    node _T_2225 = eq(_T_2223, UInt<1>("h00")) @[CSR.scala 432:5]
    node _T_2226 = bits(io.decode.csr, 2, 2) @[CSR.scala 432:39]
    node _T_2227 = and(_T_2225, _T_2226) @[CSR.scala 432:23]
    node _T_2229 = eq(allow_wfi, UInt<1>("h00")) @[CSR.scala 432:46]
    node _T_2230 = and(_T_2227, _T_2229) @[CSR.scala 432:43]
    node _T_2231 = or(_T_2222, _T_2230) @[CSR.scala 431:66]
    node _T_2232 = bits(io.decode.csr, 5, 5) @[CSR.scala 433:19]
    node _T_2234 = eq(_T_2232, UInt<1>("h00")) @[CSR.scala 433:5]
    node _T_2235 = bits(io.decode.csr, 1, 1) @[CSR.scala 433:39]
    node _T_2236 = and(_T_2234, _T_2235) @[CSR.scala 433:23]
    node _T_2238 = eq(allow_sret, UInt<1>("h00")) @[CSR.scala 433:46]
    node _T_2239 = and(_T_2236, _T_2238) @[CSR.scala 433:43]
    node _T_2240 = or(_T_2231, _T_2239) @[CSR.scala 432:57]
    node _T_2241 = bits(io.decode.csr, 5, 5) @[CSR.scala 434:18]
    node _T_2243 = eq(allow_sfence_vma, UInt<1>("h00")) @[CSR.scala 434:25]
    node _T_2244 = and(_T_2241, _T_2243) @[CSR.scala 434:22]
    node _T_2245 = or(_T_2240, _T_2244) @[CSR.scala 433:58]
    io.decode.system_illegal <= _T_2245 @[CSR.scala 431:28]
    node _T_2247 = add(reg_mstatus.prv, UInt<4>("h08")) @[CSR.scala 437:36]
    node _T_2248 = tail(_T_2247, 1) @[CSR.scala 437:36]
    node _T_2250 = mux(insn_break, UInt<2>("h03"), io.cause) @[CSR.scala 438:14]
    node cause = mux(insn_call, _T_2248, _T_2250) @[CSR.scala 437:8]
    node cause_lsbs = bits(cause, 5, 0) @[CSR.scala 439:25]
    node _T_2251 = bits(cause, 63, 63) @[CSR.scala 440:30]
    node _T_2267 = eq(cause_lsbs, UInt<4>("h0d")) @[CSR.scala 440:53]
    node causeIsDebugInt = and(_T_2251, _T_2267) @[CSR.scala 440:39]
    node _T_2268 = bits(cause, 63, 63) @[CSR.scala 441:35]
    node _T_2270 = eq(_T_2268, UInt<1>("h00")) @[CSR.scala 441:29]
    node _T_2300 = eq(cause_lsbs, UInt<4>("h0d")) @[CSR.scala 441:58]
    node causeIsDebugTrigger = and(_T_2270, _T_2300) @[CSR.scala 441:44]
    node _T_2301 = bits(cause, 63, 63) @[CSR.scala 442:33]
    node _T_2303 = eq(_T_2301, UInt<1>("h00")) @[CSR.scala 442:27]
    node _T_2304 = and(_T_2303, insn_break) @[CSR.scala 442:42]
    node _T_2305 = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) @[Cat.scala 30:58]
    node _T_2306 = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) @[Cat.scala 30:58]
    node _T_2307 = cat(_T_2306, _T_2305) @[Cat.scala 30:58]
    node _T_2308 = dshr(_T_2307, reg_mstatus.prv) @[CSR.scala 442:134]
    node _T_2309 = bits(_T_2308, 0, 0) @[CSR.scala 442:134]
    node causeIsDebugBreak = and(_T_2304, _T_2309) @[CSR.scala 442:56]
    node _T_2311 = or(reg_singleStepped, causeIsDebugInt) @[CSR.scala 443:60]
    node _T_2312 = or(_T_2311, causeIsDebugTrigger) @[CSR.scala 443:79]
    node _T_2313 = or(_T_2312, causeIsDebugBreak) @[CSR.scala 443:102]
    node _T_2314 = or(_T_2313, reg_debug) @[CSR.scala 443:123]
    node trapToDebug = and(UInt<1>("h01"), _T_2314) @[CSR.scala 443:38]
    node _T_2317 = leq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 444:51]
    node _T_2318 = and(UInt<1>("h01"), _T_2317) @[CSR.scala 444:32]
    node _T_2319 = bits(cause, 63, 63) @[CSR.scala 444:72]
    node _T_2320 = dshr(reg_mideleg, cause_lsbs) @[CSR.scala 444:93]
    node _T_2321 = bits(_T_2320, 0, 0) @[CSR.scala 444:93]
    node _T_2322 = dshr(reg_medeleg, cause_lsbs) @[CSR.scala 444:118]
    node _T_2323 = bits(_T_2322, 0, 0) @[CSR.scala 444:118]
    node _T_2324 = mux(_T_2319, _T_2321, _T_2323) @[CSR.scala 444:66]
    node delegate = and(_T_2318, _T_2324) @[CSR.scala 444:60]
    node debugTVec = mux(reg_debug, UInt<12>("h0808"), UInt<12>("h0800")) @[CSR.scala 445:22]
    node _T_2327 = bits(reg_stvec, 38, 38) @[Package.scala 40:38]
    node _T_2328 = cat(_T_2327, reg_stvec) @[Cat.scala 30:58]
    node _T_2329 = mux(delegate, _T_2328, reg_mtvec) @[CSR.scala 446:45]
    node tvec = mux(trapToDebug, debugTVec, _T_2329) @[CSR.scala 446:17]
    io.fatc <= insn_sfence_vma @[CSR.scala 447:11]
    io.evec <= tvec @[CSR.scala 448:11]
    io.ptbr <- reg_sptbr @[CSR.scala 449:11]
    node _T_2330 = or(insn_call, insn_break) @[CSR.scala 450:24]
    node _T_2331 = or(_T_2330, insn_ret) @[CSR.scala 450:38]
    io.eret <= _T_2331 @[CSR.scala 450:11]
    node _T_2333 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 451:37]
    node _T_2334 = and(reg_dcsr.step, _T_2333) @[CSR.scala 451:34]
    io.singleStep <= _T_2334 @[CSR.scala 451:17]
    io.status <- reg_mstatus @[CSR.scala 452:13]
    node _T_2335 = not(io.status.fs) @[CSR.scala 453:32]
    node _T_2337 = eq(_T_2335, UInt<1>("h00")) @[CSR.scala 453:32]
    node _T_2338 = not(io.status.xs) @[CSR.scala 453:53]
    node _T_2340 = eq(_T_2338, UInt<1>("h00")) @[CSR.scala 453:53]
    node _T_2341 = or(_T_2337, _T_2340) @[CSR.scala 453:37]
    io.status.sd <= _T_2341 @[CSR.scala 453:16]
    io.status.debug <= reg_debug @[CSR.scala 454:19]
    io.status.isa <= reg_misa @[CSR.scala 455:17]
    io.status.uxl <= UInt<2>("h02") @[CSR.scala 456:17]
    io.status.sxl <= UInt<2>("h02") @[CSR.scala 457:17]
    node _T_2344 = or(insn_call, insn_break) @[CSR.scala 461:29]
    node exception = or(_T_2344, io.exception) @[CSR.scala 461:43]
    node _T_2345 = add(insn_ret, insn_call) @[Bitwise.scala 48:55]
    node _T_2346 = add(insn_break, io.exception) @[Bitwise.scala 48:55]
    node _T_2347 = add(_T_2345, _T_2346) @[Bitwise.scala 48:55]
    node _T_2349 = leq(_T_2347, UInt<1>("h01")) @[CSR.scala 462:79]
    node _T_2350 = or(_T_2349, reset) @[CSR.scala 462:9]
    node _T_2352 = eq(_T_2350, UInt<1>("h00")) @[CSR.scala 462:9]
    when _T_2352 : @[CSR.scala 462:9]
      printf(clock, UInt<1>(1), "Assertion failed: these conditions must be mutually exclusive\n    at CSR.scala:462 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, \"these conditions must be mutually exclusive\")\n") @[CSR.scala 462:9]
      stop(clock, UInt<1>(1), 1) @[CSR.scala 462:9]
      skip @[CSR.scala 462:9]
    when insn_wfi : @[CSR.scala 464:19]
      reg_wfi <= UInt<1>("h01") @[CSR.scala 464:29]
      skip @[CSR.scala 464:19]
    node _T_2355 = neq(pending_interrupts, UInt<1>("h00")) @[CSR.scala 465:28]
    node _T_2356 = or(_T_2355, exception) @[CSR.scala 465:32]
    when _T_2356 : @[CSR.scala 465:46]
      reg_wfi <= UInt<1>("h00") @[CSR.scala 465:56]
      skip @[CSR.scala 465:46]
    node _T_2359 = eq(reg_wfi, UInt<1>("h00")) @[CSR.scala 466:10]
    node _T_2361 = eq(io.retire, UInt<1>("h00")) @[CSR.scala 466:32]
    node _T_2362 = or(_T_2359, _T_2361) @[CSR.scala 466:19]
    node _T_2363 = or(_T_2362, reset) @[CSR.scala 466:9]
    node _T_2365 = eq(_T_2363, UInt<1>("h00")) @[CSR.scala 466:9]
    when _T_2365 : @[CSR.scala 466:9]
      printf(clock, UInt<1>(1), "Assertion failed\n    at CSR.scala:466 assert(!reg_wfi || io.retire === UInt(0))\n") @[CSR.scala 466:9]
      stop(clock, UInt<1>(1), 1) @[CSR.scala 466:9]
      skip @[CSR.scala 466:9]
    node _T_2366 = bits(io.retire, 0, 0) @[CSR.scala 468:18]
    when _T_2366 : @[CSR.scala 468:23]
      reg_singleStepped <= UInt<1>("h01") @[CSR.scala 468:43]
      skip @[CSR.scala 468:23]
    node _T_2369 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 469:9]
    when _T_2369 : @[CSR.scala 469:25]
      reg_singleStepped <= UInt<1>("h00") @[CSR.scala 469:45]
      skip @[CSR.scala 469:25]
    node _T_2372 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 470:10]
    node _T_2374 = leq(io.retire, UInt<1>("h01")) @[CSR.scala 470:38]
    node _T_2375 = or(_T_2372, _T_2374) @[CSR.scala 470:25]
    node _T_2376 = or(_T_2375, reset) @[CSR.scala 470:9]
    node _T_2378 = eq(_T_2376, UInt<1>("h00")) @[CSR.scala 470:9]
    when _T_2378 : @[CSR.scala 470:9]
      printf(clock, UInt<1>(1), "Assertion failed\n    at CSR.scala:470 assert(!io.singleStep || io.retire <= UInt(1))\n") @[CSR.scala 470:9]
      stop(clock, UInt<1>(1), 1) @[CSR.scala 470:9]
      skip @[CSR.scala 470:9]
    node _T_2380 = eq(reg_singleStepped, UInt<1>("h00")) @[CSR.scala 471:10]
    node _T_2382 = eq(io.retire, UInt<1>("h00")) @[CSR.scala 471:42]
    node _T_2383 = or(_T_2380, _T_2382) @[CSR.scala 471:29]
    node _T_2384 = or(_T_2383, reset) @[CSR.scala 471:9]
    node _T_2386 = eq(_T_2384, UInt<1>("h00")) @[CSR.scala 471:9]
    when _T_2386 : @[CSR.scala 471:9]
      printf(clock, UInt<1>(1), "Assertion failed\n    at CSR.scala:471 assert(!reg_singleStepped || io.retire === UInt(0))\n") @[CSR.scala 471:9]
      stop(clock, UInt<1>(1), 1) @[CSR.scala 471:9]
      skip @[CSR.scala 471:9]
    when exception : @[CSR.scala 473:20]
      node _T_2387 = not(io.pc) @[CSR.scala 474:17]
      node _T_2389 = or(_T_2387, UInt<1>("h01")) @[CSR.scala 474:24]
      node _T_2390 = not(_T_2389) @[CSR.scala 474:15]
      node _T_2391 = dshr(read_mstatus, reg_mstatus.prv) @[CSR.scala 475:27]
      node _T_2392 = bits(_T_2391, 0, 0) @[CSR.scala 475:27]
      node _T_2400 = eq(cause, UInt<2>("h03")) @[Package.scala 7:47]
      node _T_2401 = eq(cause, UInt<3>("h04")) @[Package.scala 7:47]
      node _T_2402 = eq(cause, UInt<3>("h06")) @[Package.scala 7:47]
      node _T_2403 = eq(cause, UInt<1>("h00")) @[Package.scala 7:47]
      node _T_2404 = eq(cause, UInt<3>("h05")) @[Package.scala 7:47]
      node _T_2405 = eq(cause, UInt<3>("h07")) @[Package.scala 7:47]
      node _T_2406 = eq(cause, UInt<1>("h01")) @[Package.scala 7:47]
      node _T_2407 = or(_T_2400, _T_2401) @[Package.scala 7:62]
      node _T_2408 = or(_T_2407, _T_2402) @[Package.scala 7:62]
      node _T_2409 = or(_T_2408, _T_2403) @[Package.scala 7:62]
      node _T_2410 = or(_T_2409, _T_2404) @[Package.scala 7:62]
      node _T_2411 = or(_T_2410, _T_2405) @[Package.scala 7:62]
      node _T_2412 = or(_T_2411, _T_2406) @[Package.scala 7:62]
      when trapToDebug : @[CSR.scala 481:24]
        reg_debug <= UInt<1>("h01") @[CSR.scala 482:17]
        reg_dpc <= _T_2390 @[CSR.scala 483:15]
        node _T_2418 = mux(causeIsDebugTrigger, UInt<2>("h02"), UInt<1>("h01")) @[CSR.scala 484:84]
        node _T_2419 = mux(causeIsDebugInt, UInt<2>("h03"), _T_2418) @[CSR.scala 484:54]
        node _T_2420 = mux(reg_singleStepped, UInt<3>("h04"), _T_2419) @[CSR.scala 484:28]
        reg_dcsr.cause <= _T_2420 @[CSR.scala 484:22]
        reg_dcsr.prv <= reg_mstatus.prv @[CSR.scala 485:20]
        skip @[CSR.scala 481:24]
      node _T_2422 = eq(trapToDebug, UInt<1>("h00")) @[CSR.scala 481:24]
      node _T_2423 = and(_T_2422, delegate) @[CSR.scala 486:27]
      when _T_2423 : @[CSR.scala 486:27]
        node _T_2424 = not(_T_2390) @[CSR.scala 714:28]
        node _T_2425 = bits(reg_misa, 2, 2) @[CSR.scala 714:46]
        node _T_2427 = eq(_T_2425, UInt<1>("h00")) @[CSR.scala 714:37]
        node _T_2429 = cat(_T_2427, UInt<1>("h01")) @[Cat.scala 30:58]
        node _T_2430 = or(_T_2424, _T_2429) @[CSR.scala 714:31]
        node _T_2431 = not(_T_2430) @[CSR.scala 714:26]
        reg_sepc <= _T_2431 @[CSR.scala 487:16]
        reg_scause <= cause @[CSR.scala 488:18]
        when _T_2412 : @[CSR.scala 489:28]
          reg_sbadaddr <= io.badaddr @[CSR.scala 489:43]
          skip @[CSR.scala 489:28]
        reg_mstatus.spie <= _T_2392 @[CSR.scala 490:24]
        reg_mstatus.spp <= reg_mstatus.prv @[CSR.scala 491:23]
        reg_mstatus.sie <= UInt<1>("h00") @[CSR.scala 492:23]
        new_prv <= UInt<1>("h01") @[CSR.scala 493:15]
        skip @[CSR.scala 486:27]
      node _T_2435 = eq(trapToDebug, UInt<1>("h00")) @[CSR.scala 481:24]
      node _T_2437 = eq(delegate, UInt<1>("h00")) @[CSR.scala 486:27]
      node _T_2438 = and(_T_2435, _T_2437) @[CSR.scala 486:27]
      when _T_2438 : @[CSR.scala 494:17]
        node _T_2439 = not(_T_2390) @[CSR.scala 714:28]
        node _T_2440 = bits(reg_misa, 2, 2) @[CSR.scala 714:46]
        node _T_2442 = eq(_T_2440, UInt<1>("h00")) @[CSR.scala 714:37]
        node _T_2444 = cat(_T_2442, UInt<1>("h01")) @[Cat.scala 30:58]
        node _T_2445 = or(_T_2439, _T_2444) @[CSR.scala 714:31]
        node _T_2446 = not(_T_2445) @[CSR.scala 714:26]
        reg_mepc <= _T_2446 @[CSR.scala 495:16]
        reg_mcause <= cause @[CSR.scala 496:18]
        when _T_2412 : @[CSR.scala 497:28]
          reg_mbadaddr <= io.badaddr @[CSR.scala 497:43]
          skip @[CSR.scala 497:28]
        reg_mstatus.mpie <= _T_2392 @[CSR.scala 498:24]
        reg_mstatus.mpp <= reg_mstatus.prv @[CSR.scala 499:23]
        reg_mstatus.mie <= UInt<1>("h00") @[CSR.scala 500:23]
        new_prv <= UInt<2>("h03") @[CSR.scala 501:15]
        skip @[CSR.scala 494:17]
      skip @[CSR.scala 473:20]
    when insn_ret : @[CSR.scala 505:19]
      node _T_2450 = bits(io.rw.addr, 9, 9) @[CSR.scala 506:39]
      node _T_2452 = eq(_T_2450, UInt<1>("h00")) @[CSR.scala 506:28]
      node _T_2453 = and(UInt<1>("h01"), _T_2452) @[CSR.scala 506:25]
      when _T_2453 : @[CSR.scala 506:44]
        node _T_2454 = bits(reg_mstatus.spp, 0, 0) @[CSR.scala 507:29]
        when _T_2454 : @[CSR.scala 507:37]
          reg_mstatus.sie <= reg_mstatus.spie @[CSR.scala 507:55]
          skip @[CSR.scala 507:37]
        reg_mstatus.spie <= UInt<1>("h01") @[CSR.scala 508:24]
        reg_mstatus.spp <= UInt<1>("h00") @[CSR.scala 509:23]
        new_prv <= reg_mstatus.spp @[CSR.scala 510:15]
        io.evec <= reg_sepc @[CSR.scala 511:15]
        skip @[CSR.scala 506:44]
      node _T_2458 = bits(io.rw.addr, 10, 10) @[CSR.scala 512:47]
      node _T_2459 = and(UInt<1>("h01"), _T_2458) @[CSR.scala 512:34]
      node _T_2461 = eq(_T_2453, UInt<1>("h00")) @[CSR.scala 506:44]
      node _T_2462 = and(_T_2461, _T_2459) @[CSR.scala 512:53]
      when _T_2462 : @[CSR.scala 512:53]
        new_prv <= reg_dcsr.prv @[CSR.scala 513:15]
        reg_debug <= UInt<1>("h00") @[CSR.scala 514:17]
        io.evec <= reg_dpc @[CSR.scala 515:15]
        skip @[CSR.scala 512:53]
      node _T_2465 = eq(_T_2453, UInt<1>("h00")) @[CSR.scala 506:44]
      node _T_2467 = eq(_T_2459, UInt<1>("h00")) @[CSR.scala 512:53]
      node _T_2468 = and(_T_2465, _T_2467) @[CSR.scala 512:53]
      when _T_2468 : @[CSR.scala 516:17]
        node _T_2469 = bits(reg_mstatus.mpp, 1, 1) @[CSR.scala 517:28]
        when _T_2469 : @[CSR.scala 517:33]
          reg_mstatus.mie <= reg_mstatus.mpie @[CSR.scala 517:51]
          skip @[CSR.scala 517:33]
        node _T_2471 = bits(reg_mstatus.mpp, 0, 0) @[CSR.scala 518:50]
        node _T_2472 = and(UInt<1>("h01"), _T_2471) @[CSR.scala 518:32]
        node _T_2474 = eq(_T_2469, UInt<1>("h00")) @[CSR.scala 517:33]
        node _T_2475 = and(_T_2474, _T_2472) @[CSR.scala 518:55]
        when _T_2475 : @[CSR.scala 518:55]
          reg_mstatus.sie <= reg_mstatus.mpie @[CSR.scala 518:73]
          skip @[CSR.scala 518:55]
        reg_mstatus.mpie <= UInt<1>("h01") @[CSR.scala 519:24]
        node _T_2479 = eq(UInt<1>("h00"), UInt<2>("h02")) @[CSR.scala 697:27]
        node _T_2481 = mux(_T_2479, UInt<1>("h00"), UInt<1>("h00")) @[CSR.scala 697:21]
        reg_mstatus.mpp <= _T_2481 @[CSR.scala 520:23]
        new_prv <= reg_mstatus.mpp @[CSR.scala 521:15]
        io.evec <= reg_mepc @[CSR.scala 522:15]
        skip @[CSR.scala 516:17]
      skip @[CSR.scala 505:19]
    io.time <= _T_950 @[CSR.scala 526:11]
    io.csr_stall <= reg_wfi @[CSR.scala 527:16]
    node _T_2483 = mux(_T_1467, reg_tselect, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2485 = mux(_T_1469, _T_1304, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2487 = mux(_T_1471, _T_1345, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2489 = mux(_T_1473, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2491 = mux(_T_1475, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2493 = mux(_T_1477, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2495 = mux(_T_1479, _T_950, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2497 = mux(_T_1481, _T_939, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2499 = mux(_T_1483, reg_misa, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2501 = mux(_T_1485, read_mstatus, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2503 = mux(_T_1487, reg_mtvec, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2505 = mux(_T_1489, read_mip, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2507 = mux(_T_1491, reg_mie, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2509 = mux(_T_1493, reg_mideleg, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2511 = mux(_T_1495, reg_medeleg, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2513 = mux(_T_1497, reg_mscratch, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2515 = mux(_T_1499, _T_1354, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2517 = mux(_T_1501, _T_1360, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2519 = mux(_T_1503, reg_mcause, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2521 = mux(_T_1505, io.hartid, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2523 = mux(_T_1507, _T_1376, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2525 = mux(_T_1509, reg_dpc, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2527 = mux(_T_1511, reg_dscratch, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2529 = mux(_T_1513, reg_fflags, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2531 = mux(_T_1515, reg_frm, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2533 = mux(_T_1517, _T_1377, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2535 = mux(_T_1519, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2537 = mux(_T_1521, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2539 = mux(_T_1523, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2541 = mux(_T_1525, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2543 = mux(_T_1527, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2545 = mux(_T_1529, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2547 = mux(_T_1531, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2549 = mux(_T_1533, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2551 = mux(_T_1535, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2553 = mux(_T_1537, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2555 = mux(_T_1539, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2557 = mux(_T_1541, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2559 = mux(_T_1543, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2561 = mux(_T_1545, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2563 = mux(_T_1547, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2565 = mux(_T_1549, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2567 = mux(_T_1551, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2569 = mux(_T_1553, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2571 = mux(_T_1555, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2573 = mux(_T_1557, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2575 = mux(_T_1559, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2577 = mux(_T_1561, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2579 = mux(_T_1563, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2581 = mux(_T_1565, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2583 = mux(_T_1567, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2585 = mux(_T_1569, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2587 = mux(_T_1571, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2589 = mux(_T_1573, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2591 = mux(_T_1575, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2593 = mux(_T_1577, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2595 = mux(_T_1579, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2597 = mux(_T_1581, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2599 = mux(_T_1583, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2601 = mux(_T_1585, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2603 = mux(_T_1587, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2605 = mux(_T_1589, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2607 = mux(_T_1591, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2609 = mux(_T_1593, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2611 = mux(_T_1595, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2613 = mux(_T_1597, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2615 = mux(_T_1599, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2617 = mux(_T_1601, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2619 = mux(_T_1603, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2621 = mux(_T_1605, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2623 = mux(_T_1607, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2625 = mux(_T_1609, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2627 = mux(_T_1611, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2629 = mux(_T_1613, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2631 = mux(_T_1615, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2633 = mux(_T_1617, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2635 = mux(_T_1619, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2637 = mux(_T_1621, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2639 = mux(_T_1623, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2641 = mux(_T_1625, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2643 = mux(_T_1627, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2645 = mux(_T_1629, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2647 = mux(_T_1631, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2649 = mux(_T_1633, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2651 = mux(_T_1635, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2653 = mux(_T_1637, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2655 = mux(_T_1639, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2657 = mux(_T_1641, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2659 = mux(_T_1643, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2661 = mux(_T_1645, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2663 = mux(_T_1647, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2665 = mux(_T_1649, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2667 = mux(_T_1651, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2669 = mux(_T_1653, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2671 = mux(_T_1655, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2673 = mux(_T_1657, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2675 = mux(_T_1659, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2677 = mux(_T_1661, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2679 = mux(_T_1663, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2681 = mux(_T_1665, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2683 = mux(_T_1667, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2685 = mux(_T_1669, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2687 = mux(_T_1671, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2689 = mux(_T_1673, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2691 = mux(_T_1675, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2693 = mux(_T_1677, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2695 = mux(_T_1679, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2697 = mux(_T_1681, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2699 = mux(_T_1683, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2701 = mux(_T_1685, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2703 = mux(_T_1687, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2705 = mux(_T_1689, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2707 = mux(_T_1691, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2709 = mux(_T_1693, _T_1445, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2711 = mux(_T_1695, _T_1381, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2713 = mux(_T_1697, _T_1380, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2715 = mux(_T_1699, reg_sscratch, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2717 = mux(_T_1701, reg_scause, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2719 = mux(_T_1703, _T_1451, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2721 = mux(_T_1705, _T_1453, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2723 = mux(_T_1707, _T_1459, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2725 = mux(_T_1709, _T_1465, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2727 = mux(_T_1711, reg_scounteren, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2729 = mux(_T_1713, reg_mcounteren, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2731 = mux(_T_1715, _T_950, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2733 = mux(_T_1717, _T_939, UInt<1>("h00")) @[Mux.scala 19:72]
    node _T_2735 = or(_T_2483, _T_2485) @[Mux.scala 19:72]
    node _T_2736 = or(_T_2735, _T_2487) @[Mux.scala 19:72]
    node _T_2737 = or(_T_2736, _T_2489) @[Mux.scala 19:72]
    node _T_2738 = or(_T_2737, _T_2491) @[Mux.scala 19:72]
    node _T_2739 = or(_T_2738, _T_2493) @[Mux.scala 19:72]
    node _T_2740 = or(_T_2739, _T_2495) @[Mux.scala 19:72]
    node _T_2741 = or(_T_2740, _T_2497) @[Mux.scala 19:72]
    node _T_2742 = or(_T_2741, _T_2499) @[Mux.scala 19:72]
    node _T_2743 = or(_T_2742, _T_2501) @[Mux.scala 19:72]
    node _T_2744 = or(_T_2743, _T_2503) @[Mux.scala 19:72]
    node _T_2745 = or(_T_2744, _T_2505) @[Mux.scala 19:72]
    node _T_2746 = or(_T_2745, _T_2507) @[Mux.scala 19:72]
    node _T_2747 = or(_T_2746, _T_2509) @[Mux.scala 19:72]
    node _T_2748 = or(_T_2747, _T_2511) @[Mux.scala 19:72]
    node _T_2749 = or(_T_2748, _T_2513) @[Mux.scala 19:72]
    node _T_2750 = or(_T_2749, _T_2515) @[Mux.scala 19:72]
    node _T_2751 = or(_T_2750, _T_2517) @[Mux.scala 19:72]
    node _T_2752 = or(_T_2751, _T_2519) @[Mux.scala 19:72]
    node _T_2753 = or(_T_2752, _T_2521) @[Mux.scala 19:72]
    node _T_2754 = or(_T_2753, _T_2523) @[Mux.scala 19:72]
    node _T_2755 = or(_T_2754, _T_2525) @[Mux.scala 19:72]
    node _T_2756 = or(_T_2755, _T_2527) @[Mux.scala 19:72]
    node _T_2757 = or(_T_2756, _T_2529) @[Mux.scala 19:72]
    node _T_2758 = or(_T_2757, _T_2531) @[Mux.scala 19:72]
    node _T_2759 = or(_T_2758, _T_2533) @[Mux.scala 19:72]
    node _T_2760 = or(_T_2759, _T_2535) @[Mux.scala 19:72]
    node _T_2761 = or(_T_2760, _T_2537) @[Mux.scala 19:72]
    node _T_2762 = or(_T_2761, _T_2539) @[Mux.scala 19:72]
    node _T_2763 = or(_T_2762, _T_2541) @[Mux.scala 19:72]
    node _T_2764 = or(_T_2763, _T_2543) @[Mux.scala 19:72]
    node _T_2765 = or(_T_2764, _T_2545) @[Mux.scala 19:72]
    node _T_2766 = or(_T_2765, _T_2547) @[Mux.scala 19:72]
    node _T_2767 = or(_T_2766, _T_2549) @[Mux.scala 19:72]
    node _T_2768 = or(_T_2767, _T_2551) @[Mux.scala 19:72]
    node _T_2769 = or(_T_2768, _T_2553) @[Mux.scala 19:72]
    node _T_2770 = or(_T_2769, _T_2555) @[Mux.scala 19:72]
    node _T_2771 = or(_T_2770, _T_2557) @[Mux.scala 19:72]
    node _T_2772 = or(_T_2771, _T_2559) @[Mux.scala 19:72]
    node _T_2773 = or(_T_2772, _T_2561) @[Mux.scala 19:72]
    node _T_2774 = or(_T_2773, _T_2563) @[Mux.scala 19:72]
    node _T_2775 = or(_T_2774, _T_2565) @[Mux.scala 19:72]
    node _T_2776 = or(_T_2775, _T_2567) @[Mux.scala 19:72]
    node _T_2777 = or(_T_2776, _T_2569) @[Mux.scala 19:72]
    node _T_2778 = or(_T_2777, _T_2571) @[Mux.scala 19:72]
    node _T_2779 = or(_T_2778, _T_2573) @[Mux.scala 19:72]
    node _T_2780 = or(_T_2779, _T_2575) @[Mux.scala 19:72]
    node _T_2781 = or(_T_2780, _T_2577) @[Mux.scala 19:72]
    node _T_2782 = or(_T_2781, _T_2579) @[Mux.scala 19:72]
    node _T_2783 = or(_T_2782, _T_2581) @[Mux.scala 19:72]
    node _T_2784 = or(_T_2783, _T_2583) @[Mux.scala 19:72]
    node _T_2785 = or(_T_2784, _T_2585) @[Mux.scala 19:72]
    node _T_2786 = or(_T_2785, _T_2587) @[Mux.scala 19:72]
    node _T_2787 = or(_T_2786, _T_2589) @[Mux.scala 19:72]
    node _T_2788 = or(_T_2787, _T_2591) @[Mux.scala 19:72]
    node _T_2789 = or(_T_2788, _T_2593) @[Mux.scala 19:72]
    node _T_2790 = or(_T_2789, _T_2595) @[Mux.scala 19:72]
    node _T_2791 = or(_T_2790, _T_2597) @[Mux.scala 19:72]
    node _T_2792 = or(_T_2791, _T_2599) @[Mux.scala 19:72]
    node _T_2793 = or(_T_2792, _T_2601) @[Mux.scala 19:72]
    node _T_2794 = or(_T_2793, _T_2603) @[Mux.scala 19:72]
    node _T_2795 = or(_T_2794, _T_2605) @[Mux.scala 19:72]
    node _T_2796 = or(_T_2795, _T_2607) @[Mux.scala 19:72]
    node _T_2797 = or(_T_2796, _T_2609) @[Mux.scala 19:72]
    node _T_2798 = or(_T_2797, _T_2611) @[Mux.scala 19:72]
    node _T_2799 = or(_T_2798, _T_2613) @[Mux.scala 19:72]
    node _T_2800 = or(_T_2799, _T_2615) @[Mux.scala 19:72]
    node _T_2801 = or(_T_2800, _T_2617) @[Mux.scala 19:72]
    node _T_2802 = or(_T_2801, _T_2619) @[Mux.scala 19:72]
    node _T_2803 = or(_T_2802, _T_2621) @[Mux.scala 19:72]
    node _T_2804 = or(_T_2803, _T_2623) @[Mux.scala 19:72]
    node _T_2805 = or(_T_2804, _T_2625) @[Mux.scala 19:72]
    node _T_2806 = or(_T_2805, _T_2627) @[Mux.scala 19:72]
    node _T_2807 = or(_T_2806, _T_2629) @[Mux.scala 19:72]
    node _T_2808 = or(_T_2807, _T_2631) @[Mux.scala 19:72]
    node _T_2809 = or(_T_2808, _T_2633) @[Mux.scala 19:72]
    node _T_2810 = or(_T_2809, _T_2635) @[Mux.scala 19:72]
    node _T_2811 = or(_T_2810, _T_2637) @[Mux.scala 19:72]
    node _T_2812 = or(_T_2811, _T_2639) @[Mux.scala 19:72]
    node _T_2813 = or(_T_2812, _T_2641) @[Mux.scala 19:72]
    node _T_2814 = or(_T_2813, _T_2643) @[Mux.scala 19:72]
    node _T_2815 = or(_T_2814, _T_2645) @[Mux.scala 19:72]
    node _T_2816 = or(_T_2815, _T_2647) @[Mux.scala 19:72]
    node _T_2817 = or(_T_2816, _T_2649) @[Mux.scala 19:72]
    node _T_2818 = or(_T_2817, _T_2651) @[Mux.scala 19:72]
    node _T_2819 = or(_T_2818, _T_2653) @[Mux.scala 19:72]
    node _T_2820 = or(_T_2819, _T_2655) @[Mux.scala 19:72]
    node _T_2821 = or(_T_2820, _T_2657) @[Mux.scala 19:72]
    node _T_2822 = or(_T_2821, _T_2659) @[Mux.scala 19:72]
    node _T_2823 = or(_T_2822, _T_2661) @[Mux.scala 19:72]
    node _T_2824 = or(_T_2823, _T_2663) @[Mux.scala 19:72]
    node _T_2825 = or(_T_2824, _T_2665) @[Mux.scala 19:72]
    node _T_2826 = or(_T_2825, _T_2667) @[Mux.scala 19:72]
    node _T_2827 = or(_T_2826, _T_2669) @[Mux.scala 19:72]
    node _T_2828 = or(_T_2827, _T_2671) @[Mux.scala 19:72]
    node _T_2829 = or(_T_2828, _T_2673) @[Mux.scala 19:72]
    node _T_2830 = or(_T_2829, _T_2675) @[Mux.scala 19:72]
    node _T_2831 = or(_T_2830, _T_2677) @[Mux.scala 19:72]
    node _T_2832 = or(_T_2831, _T_2679) @[Mux.scala 19:72]
    node _T_2833 = or(_T_2832, _T_2681) @[Mux.scala 19:72]
    node _T_2834 = or(_T_2833, _T_2683) @[Mux.scala 19:72]
    node _T_2835 = or(_T_2834, _T_2685) @[Mux.scala 19:72]
    node _T_2836 = or(_T_2835, _T_2687) @[Mux.scala 19:72]
    node _T_2837 = or(_T_2836, _T_2689) @[Mux.scala 19:72]
    node _T_2838 = or(_T_2837, _T_2691) @[Mux.scala 19:72]
    node _T_2839 = or(_T_2838, _T_2693) @[Mux.scala 19:72]
    node _T_2840 = or(_T_2839, _T_2695) @[Mux.scala 19:72]
    node _T_2841 = or(_T_2840, _T_2697) @[Mux.scala 19:72]
    node _T_2842 = or(_T_2841, _T_2699) @[Mux.scala 19:72]
    node _T_2843 = or(_T_2842, _T_2701) @[Mux.scala 19:72]
    node _T_2844 = or(_T_2843, _T_2703) @[Mux.scala 19:72]
    node _T_2845 = or(_T_2844, _T_2705) @[Mux.scala 19:72]
    node _T_2846 = or(_T_2845, _T_2707) @[Mux.scala 19:72]
    node _T_2847 = or(_T_2846, _T_2709) @[Mux.scala 19:72]
    node _T_2848 = or(_T_2847, _T_2711) @[Mux.scala 19:72]
    node _T_2849 = or(_T_2848, _T_2713) @[Mux.scala 19:72]
    node _T_2850 = or(_T_2849, _T_2715) @[Mux.scala 19:72]
    node _T_2851 = or(_T_2850, _T_2717) @[Mux.scala 19:72]
    node _T_2852 = or(_T_2851, _T_2719) @[Mux.scala 19:72]
    node _T_2853 = or(_T_2852, _T_2721) @[Mux.scala 19:72]
    node _T_2854 = or(_T_2853, _T_2723) @[Mux.scala 19:72]
    node _T_2855 = or(_T_2854, _T_2725) @[Mux.scala 19:72]
    node _T_2856 = or(_T_2855, _T_2727) @[Mux.scala 19:72]
    node _T_2857 = or(_T_2856, _T_2729) @[Mux.scala 19:72]
    node _T_2858 = or(_T_2857, _T_2731) @[Mux.scala 19:72]
    node _T_2859 = or(_T_2858, _T_2733) @[Mux.scala 19:72]
    wire _T_2861 : UInt @[Mux.scala 19:72]
    _T_2861 is invalid @[Mux.scala 19:72]
    _T_2861 <= _T_2859 @[Mux.scala 19:72]
    io.rw.rdata <= _T_2861 @[CSR.scala 529:15]
    io.fcsr_rm <= reg_frm @[CSR.scala 531:14]
    when io.fcsr_flags.valid : @[CSR.scala 532:30]
      node _T_2862 = or(reg_fflags, io.fcsr_flags.bits) @[CSR.scala 533:30]
      reg_fflags <= _T_2862 @[CSR.scala 533:16]
      skip @[CSR.scala 532:30]
    node _T_2866 = eq(io.rw.cmd, UInt<3>("h02")) @[Package.scala 7:47]
    node _T_2867 = eq(io.rw.cmd, UInt<3>("h03")) @[Package.scala 7:47]
    node _T_2868 = eq(io.rw.cmd, UInt<3>("h01")) @[Package.scala 7:47]
    node _T_2869 = or(_T_2866, _T_2867) @[Package.scala 7:62]
    node _T_2870 = or(_T_2869, _T_2868) @[Package.scala 7:62]
    when _T_2870 : @[CSR.scala 536:49]
      when _T_1485 : @[CSR.scala 537:39]
        wire _T_2929 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 538:47]
        _T_2929 is invalid @[CSR.scala 538:47]
        wire _T_2959 : UInt<99>
        _T_2959 is invalid
        _T_2959 <= wdata
        node _T_2960 = bits(_T_2959, 0, 0) @[CSR.scala 538:47]
        _T_2929.uie <= _T_2960 @[CSR.scala 538:47]
        node _T_2961 = bits(_T_2959, 1, 1) @[CSR.scala 538:47]
        _T_2929.sie <= _T_2961 @[CSR.scala 538:47]
        node _T_2962 = bits(_T_2959, 2, 2) @[CSR.scala 538:47]
        _T_2929.hie <= _T_2962 @[CSR.scala 538:47]
        node _T_2963 = bits(_T_2959, 3, 3) @[CSR.scala 538:47]
        _T_2929.mie <= _T_2963 @[CSR.scala 538:47]
        node _T_2964 = bits(_T_2959, 4, 4) @[CSR.scala 538:47]
        _T_2929.upie <= _T_2964 @[CSR.scala 538:47]
        node _T_2965 = bits(_T_2959, 5, 5) @[CSR.scala 538:47]
        _T_2929.spie <= _T_2965 @[CSR.scala 538:47]
        node _T_2966 = bits(_T_2959, 6, 6) @[CSR.scala 538:47]
        _T_2929.hpie <= _T_2966 @[CSR.scala 538:47]
        node _T_2967 = bits(_T_2959, 7, 7) @[CSR.scala 538:47]
        _T_2929.mpie <= _T_2967 @[CSR.scala 538:47]
        node _T_2968 = bits(_T_2959, 8, 8) @[CSR.scala 538:47]
        _T_2929.spp <= _T_2968 @[CSR.scala 538:47]
        node _T_2969 = bits(_T_2959, 10, 9) @[CSR.scala 538:47]
        _T_2929.hpp <= _T_2969 @[CSR.scala 538:47]
        node _T_2970 = bits(_T_2959, 12, 11) @[CSR.scala 538:47]
        _T_2929.mpp <= _T_2970 @[CSR.scala 538:47]
        node _T_2971 = bits(_T_2959, 14, 13) @[CSR.scala 538:47]
        _T_2929.fs <= _T_2971 @[CSR.scala 538:47]
        node _T_2972 = bits(_T_2959, 16, 15) @[CSR.scala 538:47]
        _T_2929.xs <= _T_2972 @[CSR.scala 538:47]
        node _T_2973 = bits(_T_2959, 17, 17) @[CSR.scala 538:47]
        _T_2929.mprv <= _T_2973 @[CSR.scala 538:47]
        node _T_2974 = bits(_T_2959, 18, 18) @[CSR.scala 538:47]
        _T_2929.pum <= _T_2974 @[CSR.scala 538:47]
        node _T_2975 = bits(_T_2959, 19, 19) @[CSR.scala 538:47]
        _T_2929.mxr <= _T_2975 @[CSR.scala 538:47]
        node _T_2976 = bits(_T_2959, 20, 20) @[CSR.scala 538:47]
        _T_2929.tvm <= _T_2976 @[CSR.scala 538:47]
        node _T_2977 = bits(_T_2959, 21, 21) @[CSR.scala 538:47]
        _T_2929.tw <= _T_2977 @[CSR.scala 538:47]
        node _T_2978 = bits(_T_2959, 22, 22) @[CSR.scala 538:47]
        _T_2929.tsr <= _T_2978 @[CSR.scala 538:47]
        node _T_2979 = bits(_T_2959, 30, 23) @[CSR.scala 538:47]
        _T_2929.zero1 <= _T_2979 @[CSR.scala 538:47]
        node _T_2980 = bits(_T_2959, 31, 31) @[CSR.scala 538:47]
        _T_2929.sd_rv32 <= _T_2980 @[CSR.scala 538:47]
        node _T_2981 = bits(_T_2959, 33, 32) @[CSR.scala 538:47]
        _T_2929.uxl <= _T_2981 @[CSR.scala 538:47]
        node _T_2982 = bits(_T_2959, 35, 34) @[CSR.scala 538:47]
        _T_2929.sxl <= _T_2982 @[CSR.scala 538:47]
        node _T_2983 = bits(_T_2959, 62, 36) @[CSR.scala 538:47]
        _T_2929.zero2 <= _T_2983 @[CSR.scala 538:47]
        node _T_2984 = bits(_T_2959, 63, 63) @[CSR.scala 538:47]
        _T_2929.sd <= _T_2984 @[CSR.scala 538:47]
        node _T_2985 = bits(_T_2959, 65, 64) @[CSR.scala 538:47]
        _T_2929.prv <= _T_2985 @[CSR.scala 538:47]
        node _T_2986 = bits(_T_2959, 97, 66) @[CSR.scala 538:47]
        _T_2929.isa <= _T_2986 @[CSR.scala 538:47]
        node _T_2987 = bits(_T_2959, 98, 98) @[CSR.scala 538:47]
        _T_2929.debug <= _T_2987 @[CSR.scala 538:47]
        reg_mstatus.mie <= _T_2929.mie @[CSR.scala 539:23]
        reg_mstatus.mpie <= _T_2929.mpie @[CSR.scala 540:24]
        reg_mstatus.mprv <= _T_2929.mprv @[CSR.scala 543:26]
        reg_mstatus.mpp <= _T_2929.mpp @[CSR.scala 544:25]
        reg_mstatus.mxr <= _T_2929.mxr @[CSR.scala 545:25]
        reg_mstatus.pum <= _T_2929.pum @[CSR.scala 547:27]
        reg_mstatus.spp <= _T_2929.spp @[CSR.scala 548:27]
        reg_mstatus.spie <= _T_2929.spie @[CSR.scala 549:28]
        reg_mstatus.sie <= _T_2929.sie @[CSR.scala 550:27]
        reg_mstatus.tw <= _T_2929.tw @[CSR.scala 551:26]
        reg_mstatus.tvm <= _T_2929.tvm @[CSR.scala 552:27]
        reg_mstatus.tsr <= _T_2929.tsr @[CSR.scala 553:27]
        node _T_2989 = neq(_T_2929.fs, UInt<1>("h00")) @[CSR.scala 557:73]
        node _T_2990 = bits(_T_2989, 0, 0) @[Bitwise.scala 71:15]
        node _T_2993 = mux(_T_2990, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 71:12]
        reg_mstatus.fs <= _T_2993 @[CSR.scala 557:47]
        skip @[CSR.scala 537:39]
      when _T_1483 : @[CSR.scala 560:36]
        node _T_2995 = bits(wdata, 5, 5) @[CSR.scala 562:20]
        node _T_2996 = not(wdata) @[CSR.scala 563:21]
        node _T_2998 = eq(_T_2995, UInt<1>("h00")) @[CSR.scala 563:31]
        node _T_2999 = shl(_T_2998, 3) @[CSR.scala 563:34]
        node _T_3000 = or(_T_2996, _T_2999) @[CSR.scala 563:28]
        node _T_3001 = not(_T_3000) @[CSR.scala 563:19]
        node _T_3002 = and(_T_3001, UInt<13>("h0102d")) @[CSR.scala 563:51]
        node _T_3003 = not(UInt<13>("h0102d")) @[CSR.scala 563:71]
        node _T_3004 = and(reg_misa, _T_3003) @[CSR.scala 563:69]
        node _T_3005 = or(_T_3002, _T_3004) @[CSR.scala 563:58]
        reg_misa <= _T_3005 @[CSR.scala 563:16]
        skip @[CSR.scala 560:36]
      when _T_1489 : @[CSR.scala 565:35]
        wire _T_3034 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 566:39]
        _T_3034 is invalid @[CSR.scala 566:39]
        wire _T_3049 : UInt<13>
        _T_3049 is invalid
        _T_3049 <= wdata
        node _T_3050 = bits(_T_3049, 0, 0) @[CSR.scala 566:39]
        _T_3034.usip <= _T_3050 @[CSR.scala 566:39]
        node _T_3051 = bits(_T_3049, 1, 1) @[CSR.scala 566:39]
        _T_3034.ssip <= _T_3051 @[CSR.scala 566:39]
        node _T_3052 = bits(_T_3049, 2, 2) @[CSR.scala 566:39]
        _T_3034.hsip <= _T_3052 @[CSR.scala 566:39]
        node _T_3053 = bits(_T_3049, 3, 3) @[CSR.scala 566:39]
        _T_3034.msip <= _T_3053 @[CSR.scala 566:39]
        node _T_3054 = bits(_T_3049, 4, 4) @[CSR.scala 566:39]
        _T_3034.utip <= _T_3054 @[CSR.scala 566:39]
        node _T_3055 = bits(_T_3049, 5, 5) @[CSR.scala 566:39]
        _T_3034.stip <= _T_3055 @[CSR.scala 566:39]
        node _T_3056 = bits(_T_3049, 6, 6) @[CSR.scala 566:39]
        _T_3034.htip <= _T_3056 @[CSR.scala 566:39]
        node _T_3057 = bits(_T_3049, 7, 7) @[CSR.scala 566:39]
        _T_3034.mtip <= _T_3057 @[CSR.scala 566:39]
        node _T_3058 = bits(_T_3049, 8, 8) @[CSR.scala 566:39]
        _T_3034.ueip <= _T_3058 @[CSR.scala 566:39]
        node _T_3059 = bits(_T_3049, 9, 9) @[CSR.scala 566:39]
        _T_3034.seip <= _T_3059 @[CSR.scala 566:39]
        node _T_3060 = bits(_T_3049, 10, 10) @[CSR.scala 566:39]
        _T_3034.heip <= _T_3060 @[CSR.scala 566:39]
        node _T_3061 = bits(_T_3049, 11, 11) @[CSR.scala 566:39]
        _T_3034.meip <= _T_3061 @[CSR.scala 566:39]
        node _T_3062 = bits(_T_3049, 12, 12) @[CSR.scala 566:39]
        _T_3034.rocc <= _T_3062 @[CSR.scala 566:39]
        reg_mip.ssip <= _T_3034.ssip @[CSR.scala 568:22]
        reg_mip.stip <= _T_3034.stip @[CSR.scala 569:22]
        skip @[CSR.scala 565:35]
      when _T_1491 : @[CSR.scala 572:40]
        node _T_3063 = and(wdata, supported_interrupts) @[CSR.scala 572:59]
        reg_mie <= _T_3063 @[CSR.scala 572:50]
        skip @[CSR.scala 572:40]
      when _T_1499 : @[CSR.scala 573:40]
        node _T_3064 = not(wdata) @[CSR.scala 714:28]
        node _T_3065 = bits(reg_misa, 2, 2) @[CSR.scala 714:46]
        node _T_3067 = eq(_T_3065, UInt<1>("h00")) @[CSR.scala 714:37]
        node _T_3069 = cat(_T_3067, UInt<1>("h01")) @[Cat.scala 30:58]
        node _T_3070 = or(_T_3064, _T_3069) @[CSR.scala 714:31]
        node _T_3071 = not(_T_3070) @[CSR.scala 714:26]
        reg_mepc <= _T_3071 @[CSR.scala 573:51]
        skip @[CSR.scala 573:40]
      when _T_1497 : @[CSR.scala 574:40]
        reg_mscratch <= wdata @[CSR.scala 574:55]
        skip @[CSR.scala 574:40]
      when _T_1487 : @[CSR.scala 576:40]
        node _T_3072 = shr(wdata, 2) @[CSR.scala 576:61]
        node _T_3073 = shl(_T_3072, 2) @[CSR.scala 576:66]
        reg_mtvec <= _T_3073 @[CSR.scala 576:52]
        skip @[CSR.scala 576:40]
      when _T_1503 : @[CSR.scala 577:40]
        node _T_3075 = and(wdata, UInt<64>("h0800000000000001f")) @[CSR.scala 577:62]
        reg_mcause <= _T_3075 @[CSR.scala 577:53]
        skip @[CSR.scala 577:40]
      when _T_1501 : @[CSR.scala 578:40]
        node _T_3076 = bits(wdata, 39, 0) @[CSR.scala 578:63]
        reg_mbadaddr <= _T_3076 @[CSR.scala 578:55]
        skip @[CSR.scala 578:40]
      when _T_1479 : @[CSR.scala 711:31]
        node _T_3077 = bits(wdata, 63, 0) @[CSR.scala 711:45]
        _T_942 <= _T_3077 @[Counters.scala 67:11]
        node _T_3078 = shr(_T_3077, 6) @[Counters.scala 68:28]
        _T_945 <= _T_3078 @[Counters.scala 68:23]
        skip @[CSR.scala 711:31]
      when _T_1481 : @[CSR.scala 711:31]
        node _T_3079 = bits(wdata, 63, 0) @[CSR.scala 711:45]
        _T_931 <= _T_3079 @[Counters.scala 67:11]
        node _T_3080 = shr(_T_3079, 6) @[Counters.scala 68:28]
        _T_934 <= _T_3080 @[Counters.scala 68:23]
        skip @[CSR.scala 711:31]
      when _T_1513 : @[CSR.scala 588:40]
        reg_fflags <= wdata @[CSR.scala 588:53]
        skip @[CSR.scala 588:40]
      when _T_1515 : @[CSR.scala 589:40]
        reg_frm <= wdata @[CSR.scala 589:50]
        skip @[CSR.scala 589:40]
      when _T_1517 : @[CSR.scala 590:40]
        reg_fflags <= wdata @[CSR.scala 590:53]
        node _T_3081 = shr(wdata, 5) @[CSR.scala 590:80]
        reg_frm <= _T_3081 @[CSR.scala 590:71]
        skip @[CSR.scala 590:40]
      when _T_1507 : @[CSR.scala 593:38]
        wire _T_3118 : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} @[CSR.scala 594:43]
        _T_3118 is invalid @[CSR.scala 594:43]
        wire _T_3137 : UInt<32>
        _T_3137 is invalid
        _T_3137 <= wdata
        node _T_3138 = bits(_T_3137, 1, 0) @[CSR.scala 594:43]
        _T_3118.prv <= _T_3138 @[CSR.scala 594:43]
        node _T_3139 = bits(_T_3137, 2, 2) @[CSR.scala 594:43]
        _T_3118.step <= _T_3139 @[CSR.scala 594:43]
        node _T_3140 = bits(_T_3137, 3, 3) @[CSR.scala 594:43]
        _T_3118.halt <= _T_3140 @[CSR.scala 594:43]
        node _T_3141 = bits(_T_3137, 4, 4) @[CSR.scala 594:43]
        _T_3118.zero1 <= _T_3141 @[CSR.scala 594:43]
        node _T_3142 = bits(_T_3137, 5, 5) @[CSR.scala 594:43]
        _T_3118.debugint <= _T_3142 @[CSR.scala 594:43]
        node _T_3143 = bits(_T_3137, 8, 6) @[CSR.scala 594:43]
        _T_3118.cause <= _T_3143 @[CSR.scala 594:43]
        node _T_3144 = bits(_T_3137, 9, 9) @[CSR.scala 594:43]
        _T_3118.stoptime <= _T_3144 @[CSR.scala 594:43]
        node _T_3145 = bits(_T_3137, 10, 10) @[CSR.scala 594:43]
        _T_3118.stopcycle <= _T_3145 @[CSR.scala 594:43]
        node _T_3146 = bits(_T_3137, 11, 11) @[CSR.scala 594:43]
        _T_3118.zero2 <= _T_3146 @[CSR.scala 594:43]
        node _T_3147 = bits(_T_3137, 12, 12) @[CSR.scala 594:43]
        _T_3118.ebreaku <= _T_3147 @[CSR.scala 594:43]
        node _T_3148 = bits(_T_3137, 13, 13) @[CSR.scala 594:43]
        _T_3118.ebreaks <= _T_3148 @[CSR.scala 594:43]
        node _T_3149 = bits(_T_3137, 14, 14) @[CSR.scala 594:43]
        _T_3118.ebreakh <= _T_3149 @[CSR.scala 594:43]
        node _T_3150 = bits(_T_3137, 15, 15) @[CSR.scala 594:43]
        _T_3118.ebreakm <= _T_3150 @[CSR.scala 594:43]
        node _T_3151 = bits(_T_3137, 27, 16) @[CSR.scala 594:43]
        _T_3118.zero3 <= _T_3151 @[CSR.scala 594:43]
        node _T_3152 = bits(_T_3137, 28, 28) @[CSR.scala 594:43]
        _T_3118.fullreset <= _T_3152 @[CSR.scala 594:43]
        node _T_3153 = bits(_T_3137, 29, 29) @[CSR.scala 594:43]
        _T_3118.ndreset <= _T_3153 @[CSR.scala 594:43]
        node _T_3154 = bits(_T_3137, 31, 30) @[CSR.scala 594:43]
        _T_3118.xdebugver <= _T_3154 @[CSR.scala 594:43]
        reg_dcsr.halt <= _T_3118.halt @[CSR.scala 595:23]
        reg_dcsr.step <= _T_3118.step @[CSR.scala 596:23]
        reg_dcsr.ebreakm <= _T_3118.ebreakm @[CSR.scala 597:26]
        reg_dcsr.ebreaks <= _T_3118.ebreaks @[CSR.scala 598:39]
        reg_dcsr.ebreaku <= _T_3118.ebreaku @[CSR.scala 599:41]
        reg_dcsr.prv <= _T_3118.prv @[CSR.scala 600:37]
        skip @[CSR.scala 593:38]
      when _T_1509 : @[CSR.scala 602:42]
        node _T_3155 = not(wdata) @[CSR.scala 602:57]
        node _T_3157 = or(_T_3155, UInt<1>("h01")) @[CSR.scala 602:64]
        node _T_3158 = not(_T_3157) @[CSR.scala 602:55]
        reg_dpc <= _T_3158 @[CSR.scala 602:52]
        skip @[CSR.scala 602:42]
      when _T_1511 : @[CSR.scala 603:42]
        reg_dscratch <= wdata @[CSR.scala 603:57]
        skip @[CSR.scala 603:42]
      when _T_1693 : @[CSR.scala 606:41]
        wire _T_3217 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 607:49]
        _T_3217 is invalid @[CSR.scala 607:49]
        wire _T_3247 : UInt<99>
        _T_3247 is invalid
        _T_3247 <= wdata
        node _T_3248 = bits(_T_3247, 0, 0) @[CSR.scala 607:49]
        _T_3217.uie <= _T_3248 @[CSR.scala 607:49]
        node _T_3249 = bits(_T_3247, 1, 1) @[CSR.scala 607:49]
        _T_3217.sie <= _T_3249 @[CSR.scala 607:49]
        node _T_3250 = bits(_T_3247, 2, 2) @[CSR.scala 607:49]
        _T_3217.hie <= _T_3250 @[CSR.scala 607:49]
        node _T_3251 = bits(_T_3247, 3, 3) @[CSR.scala 607:49]
        _T_3217.mie <= _T_3251 @[CSR.scala 607:49]
        node _T_3252 = bits(_T_3247, 4, 4) @[CSR.scala 607:49]
        _T_3217.upie <= _T_3252 @[CSR.scala 607:49]
        node _T_3253 = bits(_T_3247, 5, 5) @[CSR.scala 607:49]
        _T_3217.spie <= _T_3253 @[CSR.scala 607:49]
        node _T_3254 = bits(_T_3247, 6, 6) @[CSR.scala 607:49]
        _T_3217.hpie <= _T_3254 @[CSR.scala 607:49]
        node _T_3255 = bits(_T_3247, 7, 7) @[CSR.scala 607:49]
        _T_3217.mpie <= _T_3255 @[CSR.scala 607:49]
        node _T_3256 = bits(_T_3247, 8, 8) @[CSR.scala 607:49]
        _T_3217.spp <= _T_3256 @[CSR.scala 607:49]
        node _T_3257 = bits(_T_3247, 10, 9) @[CSR.scala 607:49]
        _T_3217.hpp <= _T_3257 @[CSR.scala 607:49]
        node _T_3258 = bits(_T_3247, 12, 11) @[CSR.scala 607:49]
        _T_3217.mpp <= _T_3258 @[CSR.scala 607:49]
        node _T_3259 = bits(_T_3247, 14, 13) @[CSR.scala 607:49]
        _T_3217.fs <= _T_3259 @[CSR.scala 607:49]
        node _T_3260 = bits(_T_3247, 16, 15) @[CSR.scala 607:49]
        _T_3217.xs <= _T_3260 @[CSR.scala 607:49]
        node _T_3261 = bits(_T_3247, 17, 17) @[CSR.scala 607:49]
        _T_3217.mprv <= _T_3261 @[CSR.scala 607:49]
        node _T_3262 = bits(_T_3247, 18, 18) @[CSR.scala 607:49]
        _T_3217.pum <= _T_3262 @[CSR.scala 607:49]
        node _T_3263 = bits(_T_3247, 19, 19) @[CSR.scala 607:49]
        _T_3217.mxr <= _T_3263 @[CSR.scala 607:49]
        node _T_3264 = bits(_T_3247, 20, 20) @[CSR.scala 607:49]
        _T_3217.tvm <= _T_3264 @[CSR.scala 607:49]
        node _T_3265 = bits(_T_3247, 21, 21) @[CSR.scala 607:49]
        _T_3217.tw <= _T_3265 @[CSR.scala 607:49]
        node _T_3266 = bits(_T_3247, 22, 22) @[CSR.scala 607:49]
        _T_3217.tsr <= _T_3266 @[CSR.scala 607:49]
        node _T_3267 = bits(_T_3247, 30, 23) @[CSR.scala 607:49]
        _T_3217.zero1 <= _T_3267 @[CSR.scala 607:49]
        node _T_3268 = bits(_T_3247, 31, 31) @[CSR.scala 607:49]
        _T_3217.sd_rv32 <= _T_3268 @[CSR.scala 607:49]
        node _T_3269 = bits(_T_3247, 33, 32) @[CSR.scala 607:49]
        _T_3217.uxl <= _T_3269 @[CSR.scala 607:49]
        node _T_3270 = bits(_T_3247, 35, 34) @[CSR.scala 607:49]
        _T_3217.sxl <= _T_3270 @[CSR.scala 607:49]
        node _T_3271 = bits(_T_3247, 62, 36) @[CSR.scala 607:49]
        _T_3217.zero2 <= _T_3271 @[CSR.scala 607:49]
        node _T_3272 = bits(_T_3247, 63, 63) @[CSR.scala 607:49]
        _T_3217.sd <= _T_3272 @[CSR.scala 607:49]
        node _T_3273 = bits(_T_3247, 65, 64) @[CSR.scala 607:49]
        _T_3217.prv <= _T_3273 @[CSR.scala 607:49]
        node _T_3274 = bits(_T_3247, 97, 66) @[CSR.scala 607:49]
        _T_3217.isa <= _T_3274 @[CSR.scala 607:49]
        node _T_3275 = bits(_T_3247, 98, 98) @[CSR.scala 607:49]
        _T_3217.debug <= _T_3275 @[CSR.scala 607:49]
        reg_mstatus.sie <= _T_3217.sie @[CSR.scala 608:25]
        reg_mstatus.spie <= _T_3217.spie @[CSR.scala 609:26]
        reg_mstatus.spp <= _T_3217.spp @[CSR.scala 610:25]
        reg_mstatus.pum <= _T_3217.pum @[CSR.scala 611:25]
        node _T_3277 = neq(_T_3217.fs, UInt<1>("h00")) @[CSR.scala 612:50]
        node _T_3278 = bits(_T_3277, 0, 0) @[Bitwise.scala 71:15]
        node _T_3281 = mux(_T_3278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 71:12]
        reg_mstatus.fs <= _T_3281 @[CSR.scala 612:24]
        skip @[CSR.scala 606:41]
      when _T_1695 : @[CSR.scala 615:37]
        wire _T_3310 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 616:41]
        _T_3310 is invalid @[CSR.scala 616:41]
        wire _T_3325 : UInt<13>
        _T_3325 is invalid
        _T_3325 <= wdata
        node _T_3326 = bits(_T_3325, 0, 0) @[CSR.scala 616:41]
        _T_3310.usip <= _T_3326 @[CSR.scala 616:41]
        node _T_3327 = bits(_T_3325, 1, 1) @[CSR.scala 616:41]
        _T_3310.ssip <= _T_3327 @[CSR.scala 616:41]
        node _T_3328 = bits(_T_3325, 2, 2) @[CSR.scala 616:41]
        _T_3310.hsip <= _T_3328 @[CSR.scala 616:41]
        node _T_3329 = bits(_T_3325, 3, 3) @[CSR.scala 616:41]
        _T_3310.msip <= _T_3329 @[CSR.scala 616:41]
        node _T_3330 = bits(_T_3325, 4, 4) @[CSR.scala 616:41]
        _T_3310.utip <= _T_3330 @[CSR.scala 616:41]
        node _T_3331 = bits(_T_3325, 5, 5) @[CSR.scala 616:41]
        _T_3310.stip <= _T_3331 @[CSR.scala 616:41]
        node _T_3332 = bits(_T_3325, 6, 6) @[CSR.scala 616:41]
        _T_3310.htip <= _T_3332 @[CSR.scala 616:41]
        node _T_3333 = bits(_T_3325, 7, 7) @[CSR.scala 616:41]
        _T_3310.mtip <= _T_3333 @[CSR.scala 616:41]
        node _T_3334 = bits(_T_3325, 8, 8) @[CSR.scala 616:41]
        _T_3310.ueip <= _T_3334 @[CSR.scala 616:41]
        node _T_3335 = bits(_T_3325, 9, 9) @[CSR.scala 616:41]
        _T_3310.seip <= _T_3335 @[CSR.scala 616:41]
        node _T_3336 = bits(_T_3325, 10, 10) @[CSR.scala 616:41]
        _T_3310.heip <= _T_3336 @[CSR.scala 616:41]
        node _T_3337 = bits(_T_3325, 11, 11) @[CSR.scala 616:41]
        _T_3310.meip <= _T_3337 @[CSR.scala 616:41]
        node _T_3338 = bits(_T_3325, 12, 12) @[CSR.scala 616:41]
        _T_3310.rocc <= _T_3338 @[CSR.scala 616:41]
        reg_mip.ssip <= _T_3310.ssip @[CSR.scala 617:22]
        skip @[CSR.scala 615:37]
      when _T_1705 : @[CSR.scala 619:39]
        wire _T_3347 : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>} @[CSR.scala 620:44]
        _T_3347 is invalid @[CSR.scala 620:44]
        wire _T_3352 : UInt<64>
        _T_3352 is invalid
        _T_3352 <= wdata
        node _T_3353 = bits(_T_3352, 43, 0) @[CSR.scala 620:44]
        _T_3347.ppn <= _T_3353 @[CSR.scala 620:44]
        node _T_3354 = bits(_T_3352, 59, 44) @[CSR.scala 620:44]
        _T_3347.asid <= _T_3354 @[CSR.scala 620:44]
        node _T_3355 = bits(_T_3352, 63, 60) @[CSR.scala 620:44]
        _T_3347.mode <= _T_3355 @[CSR.scala 620:44]
        node _T_3357 = eq(_T_3347.mode, UInt<1>("h00")) @[CSR.scala 622:30]
        when _T_3357 : @[CSR.scala 622:37]
          reg_sptbr.mode <= UInt<1>("h00") @[CSR.scala 622:54]
          skip @[CSR.scala 622:37]
        node _T_3360 = eq(_T_3347.mode, UInt<4>("h08")) @[CSR.scala 623:30]
        when _T_3360 : @[CSR.scala 623:46]
          reg_sptbr.mode <= UInt<4>("h08") @[CSR.scala 623:63]
          skip @[CSR.scala 623:46]
        node _T_3363 = eq(_T_3347.mode, UInt<1>("h00")) @[CSR.scala 624:30]
        node _T_3365 = eq(_T_3347.mode, UInt<4>("h08")) @[CSR.scala 624:54]
        node _T_3366 = or(_T_3363, _T_3365) @[CSR.scala 624:36]
        when _T_3366 : @[CSR.scala 624:70]
          node _T_3367 = bits(_T_3347.ppn, 19, 0) @[CSR.scala 625:41]
          reg_sptbr.ppn <= _T_3367 @[CSR.scala 625:25]
          skip @[CSR.scala 624:70]
        skip @[CSR.scala 619:39]
      when _T_1697 : @[CSR.scala 629:42]
        node _T_3368 = not(reg_mideleg) @[CSR.scala 629:66]
        node _T_3369 = and(reg_mie, _T_3368) @[CSR.scala 629:64]
        node _T_3370 = and(wdata, reg_mideleg) @[CSR.scala 629:89]
        node _T_3371 = or(_T_3369, _T_3370) @[CSR.scala 629:80]
        reg_mie <= _T_3371 @[CSR.scala 629:52]
        skip @[CSR.scala 629:42]
      when _T_1699 : @[CSR.scala 630:42]
        reg_sscratch <= wdata @[CSR.scala 630:57]
        skip @[CSR.scala 630:42]
      when _T_1707 : @[CSR.scala 631:42]
        node _T_3372 = not(wdata) @[CSR.scala 714:28]
        node _T_3373 = bits(reg_misa, 2, 2) @[CSR.scala 714:46]
        node _T_3375 = eq(_T_3373, UInt<1>("h00")) @[CSR.scala 714:37]
        node _T_3377 = cat(_T_3375, UInt<1>("h01")) @[Cat.scala 30:58]
        node _T_3378 = or(_T_3372, _T_3377) @[CSR.scala 714:31]
        node _T_3379 = not(_T_3378) @[CSR.scala 714:26]
        reg_sepc <= _T_3379 @[CSR.scala 631:53]
        skip @[CSR.scala 631:42]
      when _T_1709 : @[CSR.scala 632:42]
        node _T_3380 = shr(wdata, 2) @[CSR.scala 632:63]
        node _T_3381 = shl(_T_3380, 2) @[CSR.scala 632:68]
        reg_stvec <= _T_3381 @[CSR.scala 632:54]
        skip @[CSR.scala 632:42]
      when _T_1701 : @[CSR.scala 633:42]
        node _T_3383 = and(wdata, UInt<64>("h0800000000000001f")) @[CSR.scala 633:64]
        reg_scause <= _T_3383 @[CSR.scala 633:55]
        skip @[CSR.scala 633:42]
      when _T_1703 : @[CSR.scala 634:42]
        node _T_3384 = bits(wdata, 39, 0) @[CSR.scala 634:65]
        reg_sbadaddr <= _T_3384 @[CSR.scala 634:57]
        skip @[CSR.scala 634:42]
      when _T_1493 : @[CSR.scala 635:42]
        node _T_3385 = and(wdata, delegable_interrupts) @[CSR.scala 635:65]
        reg_mideleg <= _T_3385 @[CSR.scala 635:56]
        skip @[CSR.scala 635:42]
      when _T_1495 : @[CSR.scala 636:42]
        node _T_3386 = and(wdata, UInt<9>("h01ab")) @[CSR.scala 636:65]
        reg_medeleg <= _T_3386 @[CSR.scala 636:56]
        skip @[CSR.scala 636:42]
      when _T_1711 : @[CSR.scala 637:44]
        node _T_3388 = and(wdata, UInt<3>("h07")) @[CSR.scala 637:70]
        reg_scounteren <= _T_3388 @[CSR.scala 637:61]
        skip @[CSR.scala 637:44]
      when _T_1713 : @[CSR.scala 640:44]
        node _T_3390 = and(wdata, UInt<3>("h07")) @[CSR.scala 640:70]
        reg_mcounteren <= _T_3390 @[CSR.scala 640:61]
        skip @[CSR.scala 640:44]
      when _T_1467 : @[CSR.scala 643:41]
        reg_tselect <= wdata @[CSR.scala 643:55]
        skip @[CSR.scala 643:41]
      node _T_3427 = eq(reg_bp[reg_tselect].control.dmode, UInt<1>("h00")) @[CSR.scala 646:13]
      node _T_3428 = or(_T_3427, reg_debug) @[CSR.scala 646:31]
      when _T_3428 : @[CSR.scala 646:45]
        when _T_1469 : @[CSR.scala 647:42]
          wire _T_3461 : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[CSR.scala 648:48]
          _T_3461 is invalid @[CSR.scala 648:48]
          wire _T_3478 : UInt<64>
          _T_3478 is invalid
          _T_3478 <= wdata
          node _T_3479 = bits(_T_3478, 0, 0) @[CSR.scala 648:48]
          _T_3461.r <= _T_3479 @[CSR.scala 648:48]
          node _T_3480 = bits(_T_3478, 1, 1) @[CSR.scala 648:48]
          _T_3461.w <= _T_3480 @[CSR.scala 648:48]
          node _T_3481 = bits(_T_3478, 2, 2) @[CSR.scala 648:48]
          _T_3461.x <= _T_3481 @[CSR.scala 648:48]
          node _T_3482 = bits(_T_3478, 3, 3) @[CSR.scala 648:48]
          _T_3461.u <= _T_3482 @[CSR.scala 648:48]
          node _T_3483 = bits(_T_3478, 4, 4) @[CSR.scala 648:48]
          _T_3461.s <= _T_3483 @[CSR.scala 648:48]
          node _T_3484 = bits(_T_3478, 5, 5) @[CSR.scala 648:48]
          _T_3461.h <= _T_3484 @[CSR.scala 648:48]
          node _T_3485 = bits(_T_3478, 6, 6) @[CSR.scala 648:48]
          _T_3461.m <= _T_3485 @[CSR.scala 648:48]
          node _T_3486 = bits(_T_3478, 8, 7) @[CSR.scala 648:48]
          _T_3461.tmatch <= _T_3486 @[CSR.scala 648:48]
          node _T_3487 = bits(_T_3478, 10, 9) @[CSR.scala 648:48]
          _T_3461.zero <= _T_3487 @[CSR.scala 648:48]
          node _T_3488 = bits(_T_3478, 11, 11) @[CSR.scala 648:48]
          _T_3461.chain <= _T_3488 @[CSR.scala 648:48]
          node _T_3489 = bits(_T_3478, 12, 12) @[CSR.scala 648:48]
          _T_3461.action <= _T_3489 @[CSR.scala 648:48]
          node _T_3490 = bits(_T_3478, 52, 13) @[CSR.scala 648:48]
          _T_3461.reserved <= _T_3490 @[CSR.scala 648:48]
          node _T_3491 = bits(_T_3478, 58, 53) @[CSR.scala 648:48]
          _T_3461.maskmax <= _T_3491 @[CSR.scala 648:48]
          node _T_3492 = bits(_T_3478, 59, 59) @[CSR.scala 648:48]
          _T_3461.dmode <= _T_3492 @[CSR.scala 648:48]
          node _T_3493 = bits(_T_3478, 63, 60) @[CSR.scala 648:48]
          _T_3461.ttype <= _T_3493 @[CSR.scala 648:48]
          node _T_3494 = and(_T_3461.dmode, reg_debug) @[CSR.scala 649:36]
          reg_bp[reg_tselect].control <- _T_3461 @[CSR.scala 650:22]
          reg_bp[reg_tselect].control.dmode <= _T_3494 @[CSR.scala 651:28]
          node _T_3495 = and(_T_3494, _T_3461.action) @[CSR.scala 652:38]
          reg_bp[reg_tselect].control.action <= _T_3495 @[CSR.scala 652:29]
          skip @[CSR.scala 647:42]
        when _T_1471 : @[CSR.scala 654:42]
          reg_bp[reg_tselect].address <= wdata @[CSR.scala 654:55]
          skip @[CSR.scala 654:42]
        skip @[CSR.scala 646:45]
      skip @[CSR.scala 536:49]
    reg_mip <- io.interrupts @[CSR.scala 659:11]
    reg_dcsr.debugint <= io.interrupts.debug @[CSR.scala 660:21]
    reg_sptbr.asid <= UInt<1>("h00") @[CSR.scala 672:18]
    reg_tselect <= UInt<1>("h00") @[CSR.scala 673:38]
    reg_bp[0].control.chain <= UInt<1>("h00") @[CSR.scala 675:42]
    reg_bp[0].control.ttype <= UInt<2>("h02") @[CSR.scala 677:15]
    reg_bp[0].control.maskmax <= UInt<3>("h04") @[CSR.scala 678:17]
    reg_bp[0].control.reserved <= UInt<1>("h00") @[CSR.scala 679:18]
    reg_bp[0].control.zero <= UInt<1>("h00") @[CSR.scala 680:14]
    reg_bp[0].control.h <= UInt<1>("h00") @[CSR.scala 681:11]
    when reset : @[CSR.scala 685:18]
      reg_bp[0].control.action <= UInt<1>("h00") @[CSR.scala 686:18]
      reg_bp[0].control.dmode <= UInt<1>("h00") @[CSR.scala 687:17]
      reg_bp[0].control.r <= UInt<1>("h00") @[CSR.scala 688:13]
      reg_bp[0].control.w <= UInt<1>("h00") @[CSR.scala 689:13]
      reg_bp[0].control.x <= UInt<1>("h00") @[CSR.scala 690:13]
      skip @[CSR.scala 685:18]
    reg_bp[1].control.ttype <= UInt<2>("h02") @[CSR.scala 677:15]
    reg_bp[1].control.maskmax <= UInt<3>("h04") @[CSR.scala 678:17]
    reg_bp[1].control.reserved <= UInt<1>("h00") @[CSR.scala 679:18]
    reg_bp[1].control.zero <= UInt<1>("h00") @[CSR.scala 680:14]
    reg_bp[1].control.h <= UInt<1>("h00") @[CSR.scala 681:11]
    when reset : @[CSR.scala 685:18]
      reg_bp[1].control.action <= UInt<1>("h00") @[CSR.scala 686:18]
      reg_bp[1].control.dmode <= UInt<1>("h00") @[CSR.scala 687:17]
      reg_bp[1].control.r <= UInt<1>("h00") @[CSR.scala 688:13]
      reg_bp[1].control.w <= UInt<1>("h00") @[CSR.scala 689:13]
      reg_bp[1].control.x <= UInt<1>("h00") @[CSR.scala 690:13]
      skip @[CSR.scala 685:18]
    wire _T_3556 : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>} @[CSR.scala 694:28]
    _T_3556 is invalid @[CSR.scala 694:28]
    wire _T_3575 : UInt<103>
    _T_3575 is invalid
    _T_3575 <= UInt<1>("h00")
    node _T_3576 = bits(_T_3575, 38, 0) @[CSR.scala 694:28]
    _T_3556.address <= _T_3576 @[CSR.scala 694:28]
    node _T_3577 = bits(_T_3575, 102, 39) @[CSR.scala 694:28]
    wire _T_3579 : UInt<64>
    _T_3579 is invalid
    _T_3579 <= _T_3577
    node _T_3580 = bits(_T_3579, 0, 0) @[CSR.scala 694:28]
    _T_3556.control.r <= _T_3580 @[CSR.scala 694:28]
    node _T_3581 = bits(_T_3579, 1, 1) @[CSR.scala 694:28]
    _T_3556.control.w <= _T_3581 @[CSR.scala 694:28]
    node _T_3582 = bits(_T_3579, 2, 2) @[CSR.scala 694:28]
    _T_3556.control.x <= _T_3582 @[CSR.scala 694:28]
    node _T_3583 = bits(_T_3579, 3, 3) @[CSR.scala 694:28]
    _T_3556.control.u <= _T_3583 @[CSR.scala 694:28]
    node _T_3584 = bits(_T_3579, 4, 4) @[CSR.scala 694:28]
    _T_3556.control.s <= _T_3584 @[CSR.scala 694:28]
    node _T_3585 = bits(_T_3579, 5, 5) @[CSR.scala 694:28]
    _T_3556.control.h <= _T_3585 @[CSR.scala 694:28]
    node _T_3586 = bits(_T_3579, 6, 6) @[CSR.scala 694:28]
    _T_3556.control.m <= _T_3586 @[CSR.scala 694:28]
    node _T_3587 = bits(_T_3579, 8, 7) @[CSR.scala 694:28]
    _T_3556.control.tmatch <= _T_3587 @[CSR.scala 694:28]
    node _T_3588 = bits(_T_3579, 10, 9) @[CSR.scala 694:28]
    _T_3556.control.zero <= _T_3588 @[CSR.scala 694:28]
    node _T_3589 = bits(_T_3579, 11, 11) @[CSR.scala 694:28]
    _T_3556.control.chain <= _T_3589 @[CSR.scala 694:28]
    node _T_3590 = bits(_T_3579, 12, 12) @[CSR.scala 694:28]
    _T_3556.control.action <= _T_3590 @[CSR.scala 694:28]
    node _T_3591 = bits(_T_3579, 52, 13) @[CSR.scala 694:28]
    _T_3556.control.reserved <= _T_3591 @[CSR.scala 694:28]
    node _T_3592 = bits(_T_3579, 58, 53) @[CSR.scala 694:28]
    _T_3556.control.maskmax <= _T_3592 @[CSR.scala 694:28]
    node _T_3593 = bits(_T_3579, 59, 59) @[CSR.scala 694:28]
    _T_3556.control.dmode <= _T_3593 @[CSR.scala 694:28]
    node _T_3594 = bits(_T_3579, 63, 60) @[CSR.scala 694:28]
    _T_3556.control.ttype <= _T_3594 @[CSR.scala 694:28]
    reg_bp[1] <- _T_3556 @[CSR.scala 694:8]
    
  module BreakpointUnit : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], flip pc : UInt<39>, flip ea : UInt<39>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>}
    
    io is invalid
    io is invalid
    io.xcpt_if <= UInt<1>("h00") @[Breakpoint.scala 64:14]
    io.xcpt_ld <= UInt<1>("h00") @[Breakpoint.scala 65:14]
    io.xcpt_st <= UInt<1>("h00") @[Breakpoint.scala 66:14]
    io.debug_if <= UInt<1>("h00") @[Breakpoint.scala 67:15]
    io.debug_ld <= UInt<1>("h00") @[Breakpoint.scala 68:15]
    io.debug_st <= UInt<1>("h00") @[Breakpoint.scala 69:15]
    node _T_212 = eq(io.status.debug, UInt<1>("h00")) @[Breakpoint.scala 30:35]
    node _T_213 = cat(io.bp[0].control.s, io.bp[0].control.u) @[Cat.scala 30:58]
    node _T_214 = cat(io.bp[0].control.m, io.bp[0].control.h) @[Cat.scala 30:58]
    node _T_215 = cat(_T_214, _T_213) @[Cat.scala 30:58]
    node _T_216 = dshr(_T_215, io.status.prv) @[Breakpoint.scala 30:68]
    node _T_217 = bits(_T_216, 0, 0) @[Breakpoint.scala 30:68]
    node _T_218 = and(_T_212, _T_217) @[Breakpoint.scala 30:50]
    node _T_219 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 73:16]
    node _T_220 = and(_T_219, io.bp[0].control.r) @[Breakpoint.scala 73:22]
    node _T_221 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23]
    node _T_222 = geq(io.ea, io.bp[0].address) @[Breakpoint.scala 44:8]
    node _T_223 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36]
    node _T_224 = xor(_T_222, _T_223) @[Breakpoint.scala 44:20]
    node _T_225 = not(io.ea) @[Breakpoint.scala 41:6]
    node _T_226 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56]
    node _T_227 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83]
    node _T_228 = and(_T_226, _T_227) @[Breakpoint.scala 38:73]
    node _T_229 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83]
    node _T_230 = and(_T_228, _T_229) @[Breakpoint.scala 38:73]
    node _T_231 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83]
    node _T_232 = and(_T_230, _T_231) @[Breakpoint.scala 38:73]
    node _T_233 = cat(_T_228, _T_226) @[Cat.scala 30:58]
    node _T_234 = cat(_T_232, _T_230) @[Cat.scala 30:58]
    node _T_235 = cat(_T_234, _T_233) @[Cat.scala 30:58]
    node _T_236 = or(_T_225, _T_235) @[Breakpoint.scala 41:9]
    node _T_237 = not(io.bp[0].address) @[Breakpoint.scala 41:24]
    node _T_238 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56]
    node _T_239 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83]
    node _T_240 = and(_T_238, _T_239) @[Breakpoint.scala 38:73]
    node _T_241 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83]
    node _T_242 = and(_T_240, _T_241) @[Breakpoint.scala 38:73]
    node _T_243 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83]
    node _T_244 = and(_T_242, _T_243) @[Breakpoint.scala 38:73]
    node _T_245 = cat(_T_240, _T_238) @[Cat.scala 30:58]
    node _T_246 = cat(_T_244, _T_242) @[Cat.scala 30:58]
    node _T_247 = cat(_T_246, _T_245) @[Cat.scala 30:58]
    node _T_248 = or(_T_237, _T_247) @[Breakpoint.scala 41:33]
    node _T_249 = eq(_T_236, _T_248) @[Breakpoint.scala 41:19]
    node _T_250 = mux(_T_221, _T_224, _T_249) @[Breakpoint.scala 47:8]
    node _T_251 = and(_T_220, _T_250) @[Breakpoint.scala 73:38]
    node _T_252 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 74:16]
    node _T_253 = and(_T_252, io.bp[0].control.w) @[Breakpoint.scala 74:22]
    node _T_254 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23]
    node _T_255 = geq(io.ea, io.bp[0].address) @[Breakpoint.scala 44:8]
    node _T_256 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36]
    node _T_257 = xor(_T_255, _T_256) @[Breakpoint.scala 44:20]
    node _T_258 = not(io.ea) @[Breakpoint.scala 41:6]
    node _T_259 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56]
    node _T_260 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83]
    node _T_261 = and(_T_259, _T_260) @[Breakpoint.scala 38:73]
    node _T_262 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83]
    node _T_263 = and(_T_261, _T_262) @[Breakpoint.scala 38:73]
    node _T_264 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83]
    node _T_265 = and(_T_263, _T_264) @[Breakpoint.scala 38:73]
    node _T_266 = cat(_T_261, _T_259) @[Cat.scala 30:58]
    node _T_267 = cat(_T_265, _T_263) @[Cat.scala 30:58]
    node _T_268 = cat(_T_267, _T_266) @[Cat.scala 30:58]
    node _T_269 = or(_T_258, _T_268) @[Breakpoint.scala 41:9]
    node _T_270 = not(io.bp[0].address) @[Breakpoint.scala 41:24]
    node _T_271 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56]
    node _T_272 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83]
    node _T_273 = and(_T_271, _T_272) @[Breakpoint.scala 38:73]
    node _T_274 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83]
    node _T_275 = and(_T_273, _T_274) @[Breakpoint.scala 38:73]
    node _T_276 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83]
    node _T_277 = and(_T_275, _T_276) @[Breakpoint.scala 38:73]
    node _T_278 = cat(_T_273, _T_271) @[Cat.scala 30:58]
    node _T_279 = cat(_T_277, _T_275) @[Cat.scala 30:58]
    node _T_280 = cat(_T_279, _T_278) @[Cat.scala 30:58]
    node _T_281 = or(_T_270, _T_280) @[Breakpoint.scala 41:33]
    node _T_282 = eq(_T_269, _T_281) @[Breakpoint.scala 41:19]
    node _T_283 = mux(_T_254, _T_257, _T_282) @[Breakpoint.scala 47:8]
    node _T_284 = and(_T_253, _T_283) @[Breakpoint.scala 74:38]
    node _T_285 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 75:16]
    node _T_286 = and(_T_285, io.bp[0].control.x) @[Breakpoint.scala 75:22]
    node _T_287 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23]
    node _T_288 = geq(io.pc, io.bp[0].address) @[Breakpoint.scala 44:8]
    node _T_289 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36]
    node _T_290 = xor(_T_288, _T_289) @[Breakpoint.scala 44:20]
    node _T_291 = not(io.pc) @[Breakpoint.scala 41:6]
    node _T_292 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56]
    node _T_293 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83]
    node _T_294 = and(_T_292, _T_293) @[Breakpoint.scala 38:73]
    node _T_295 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83]
    node _T_296 = and(_T_294, _T_295) @[Breakpoint.scala 38:73]
    node _T_297 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83]
    node _T_298 = and(_T_296, _T_297) @[Breakpoint.scala 38:73]
    node _T_299 = cat(_T_294, _T_292) @[Cat.scala 30:58]
    node _T_300 = cat(_T_298, _T_296) @[Cat.scala 30:58]
    node _T_301 = cat(_T_300, _T_299) @[Cat.scala 30:58]
    node _T_302 = or(_T_291, _T_301) @[Breakpoint.scala 41:9]
    node _T_303 = not(io.bp[0].address) @[Breakpoint.scala 41:24]
    node _T_304 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56]
    node _T_305 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83]
    node _T_306 = and(_T_304, _T_305) @[Breakpoint.scala 38:73]
    node _T_307 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83]
    node _T_308 = and(_T_306, _T_307) @[Breakpoint.scala 38:73]
    node _T_309 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83]
    node _T_310 = and(_T_308, _T_309) @[Breakpoint.scala 38:73]
    node _T_311 = cat(_T_306, _T_304) @[Cat.scala 30:58]
    node _T_312 = cat(_T_310, _T_308) @[Cat.scala 30:58]
    node _T_313 = cat(_T_312, _T_311) @[Cat.scala 30:58]
    node _T_314 = or(_T_303, _T_313) @[Breakpoint.scala 41:33]
    node _T_315 = eq(_T_302, _T_314) @[Breakpoint.scala 41:19]
    node _T_316 = mux(_T_287, _T_290, _T_315) @[Breakpoint.scala 47:8]
    node _T_317 = and(_T_286, _T_316) @[Breakpoint.scala 75:38]
    node _T_319 = eq(io.bp[0].control.chain, UInt<1>("h00")) @[Breakpoint.scala 76:15]
    node _T_320 = and(_T_319, _T_251) @[Breakpoint.scala 78:15]
    when _T_320 : @[Breakpoint.scala 78:21]
      node _T_322 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 78:37]
      io.xcpt_ld <= _T_322 @[Breakpoint.scala 78:34]
      io.debug_ld <= io.bp[0].control.action @[Breakpoint.scala 78:69]
      skip @[Breakpoint.scala 78:21]
    node _T_323 = and(_T_319, _T_284) @[Breakpoint.scala 79:15]
    when _T_323 : @[Breakpoint.scala 79:21]
      node _T_325 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 79:37]
      io.xcpt_st <= _T_325 @[Breakpoint.scala 79:34]
      io.debug_st <= io.bp[0].control.action @[Breakpoint.scala 79:69]
      skip @[Breakpoint.scala 79:21]
    node _T_326 = and(_T_319, _T_317) @[Breakpoint.scala 80:15]
    when _T_326 : @[Breakpoint.scala 80:21]
      node _T_328 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 80:37]
      io.xcpt_if <= _T_328 @[Breakpoint.scala 80:34]
      io.debug_if <= io.bp[0].control.action @[Breakpoint.scala 80:69]
      skip @[Breakpoint.scala 80:21]
    node _T_329 = or(_T_319, _T_251) @[Breakpoint.scala 82:10]
    node _T_330 = or(_T_319, _T_284) @[Breakpoint.scala 82:20]
    node _T_331 = or(_T_319, _T_317) @[Breakpoint.scala 82:30]
    
  module ALU : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>}
    
    io is invalid
    io is invalid
    node _T_16 = bits(io.fn, 3, 3) @[ALU.scala 41:29]
    node _T_17 = not(io.in2) @[ALU.scala 61:35]
    node in2_inv = mux(_T_16, _T_17, io.in2) @[ALU.scala 61:20]
    node in1_xor_in2 = xor(io.in1, in2_inv) @[ALU.scala 62:28]
    node _T_18 = add(io.in1, in2_inv) @[ALU.scala 63:26]
    node _T_19 = tail(_T_18, 1) @[ALU.scala 63:26]
    node _T_20 = bits(io.fn, 3, 3) @[ALU.scala 41:29]
    node _T_21 = add(_T_19, _T_20) @[ALU.scala 63:36]
    node _T_22 = tail(_T_21, 1) @[ALU.scala 63:36]
    io.adder_out <= _T_22 @[ALU.scala 63:16]
    node _T_23 = bits(io.fn, 0, 0) @[ALU.scala 44:35]
    node _T_24 = bits(io.fn, 3, 3) @[ALU.scala 45:30]
    node _T_26 = eq(_T_24, UInt<1>("h00")) @[ALU.scala 45:26]
    node _T_28 = eq(in1_xor_in2, UInt<1>("h00")) @[ALU.scala 67:35]
    node _T_29 = bits(io.in1, 63, 63) @[ALU.scala 68:15]
    node _T_30 = bits(io.in2, 63, 63) @[ALU.scala 68:34]
    node _T_31 = eq(_T_29, _T_30) @[ALU.scala 68:24]
    node _T_32 = bits(io.adder_out, 63, 63) @[ALU.scala 68:56]
    node _T_33 = bits(io.fn, 1, 1) @[ALU.scala 43:35]
    node _T_34 = bits(io.in2, 63, 63) @[ALU.scala 69:35]
    node _T_35 = bits(io.in1, 63, 63) @[ALU.scala 69:51]
    node _T_36 = mux(_T_33, _T_34, _T_35) @[ALU.scala 69:8]
    node _T_37 = mux(_T_31, _T_32, _T_36) @[ALU.scala 68:8]
    node _T_38 = mux(_T_26, _T_28, _T_37) @[ALU.scala 67:8]
    node _T_39 = xor(_T_23, _T_38) @[ALU.scala 66:36]
    io.cmp_out <= _T_39 @[ALU.scala 66:14]
    node _T_40 = bits(io.fn, 3, 3) @[ALU.scala 41:29]
    node _T_41 = bits(io.in1, 31, 31) @[ALU.scala 76:55]
    node _T_42 = and(_T_40, _T_41) @[ALU.scala 76:46]
    node _T_43 = bits(_T_42, 0, 0) @[Bitwise.scala 71:15]
    node _T_46 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12]
    node _T_48 = eq(io.dw, UInt<1>("h01")) @[ALU.scala 77:31]
    node _T_49 = bits(io.in1, 63, 32) @[ALU.scala 77:48]
    node _T_50 = mux(_T_48, _T_49, _T_46) @[ALU.scala 77:24]
    node _T_51 = bits(io.in2, 5, 5) @[ALU.scala 78:29]
    node _T_53 = eq(io.dw, UInt<1>("h01")) @[ALU.scala 78:42]
    node _T_54 = and(_T_51, _T_53) @[ALU.scala 78:33]
    node _T_55 = bits(io.in2, 4, 0) @[ALU.scala 78:60]
    node shamt = cat(_T_54, _T_55) @[Cat.scala 30:58]
    node _T_56 = bits(io.in1, 31, 0) @[ALU.scala 79:34]
    node shin_r = cat(_T_50, _T_56) @[Cat.scala 30:58]
    node _T_58 = eq(io.fn, UInt<3>("h05")) @[ALU.scala 81:24]
    node _T_60 = eq(io.fn, UInt<4>("h0b")) @[ALU.scala 81:44]
    node _T_61 = or(_T_58, _T_60) @[ALU.scala 81:35]
    node _T_64 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 101:47]
    node _T_65 = xor(UInt<64>("h0ffffffffffffffff"), _T_64) @[Bitwise.scala 101:21]
    node _T_66 = shr(shin_r, 32) @[Bitwise.scala 102:21]
    node _T_67 = and(_T_66, _T_65) @[Bitwise.scala 102:31]
    node _T_68 = bits(shin_r, 31, 0) @[Bitwise.scala 102:46]
    node _T_69 = shl(_T_68, 32) @[Bitwise.scala 102:65]
    node _T_70 = not(_T_65) @[Bitwise.scala 102:77]
    node _T_71 = and(_T_69, _T_70) @[Bitwise.scala 102:75]
    node _T_72 = or(_T_67, _T_71) @[Bitwise.scala 102:39]
    node _T_73 = bits(_T_65, 47, 0) @[Bitwise.scala 101:28]
    node _T_74 = shl(_T_73, 16) @[Bitwise.scala 101:47]
    node _T_75 = xor(_T_65, _T_74) @[Bitwise.scala 101:21]
    node _T_76 = shr(_T_72, 16) @[Bitwise.scala 102:21]
    node _T_77 = and(_T_76, _T_75) @[Bitwise.scala 102:31]
    node _T_78 = bits(_T_72, 47, 0) @[Bitwise.scala 102:46]
    node _T_79 = shl(_T_78, 16) @[Bitwise.scala 102:65]
    node _T_80 = not(_T_75) @[Bitwise.scala 102:77]
    node _T_81 = and(_T_79, _T_80) @[Bitwise.scala 102:75]
    node _T_82 = or(_T_77, _T_81) @[Bitwise.scala 102:39]
    node _T_83 = bits(_T_75, 55, 0) @[Bitwise.scala 101:28]
    node _T_84 = shl(_T_83, 8) @[Bitwise.scala 101:47]
    node _T_85 = xor(_T_75, _T_84) @[Bitwise.scala 101:21]
    node _T_86 = shr(_T_82, 8) @[Bitwise.scala 102:21]
    node _T_87 = and(_T_86, _T_85) @[Bitwise.scala 102:31]
    node _T_88 = bits(_T_82, 55, 0) @[Bitwise.scala 102:46]
    node _T_89 = shl(_T_88, 8) @[Bitwise.scala 102:65]
    node _T_90 = not(_T_85) @[Bitwise.scala 102:77]
    node _T_91 = and(_T_89, _T_90) @[Bitwise.scala 102:75]
    node _T_92 = or(_T_87, _T_91) @[Bitwise.scala 102:39]
    node _T_93 = bits(_T_85, 59, 0) @[Bitwise.scala 101:28]
    node _T_94 = shl(_T_93, 4) @[Bitwise.scala 101:47]
    node _T_95 = xor(_T_85, _T_94) @[Bitwise.scala 101:21]
    node _T_96 = shr(_T_92, 4) @[Bitwise.scala 102:21]
    node _T_97 = and(_T_96, _T_95) @[Bitwise.scala 102:31]
    node _T_98 = bits(_T_92, 59, 0) @[Bitwise.scala 102:46]
    node _T_99 = shl(_T_98, 4) @[Bitwise.scala 102:65]
    node _T_100 = not(_T_95) @[Bitwise.scala 102:77]
    node _T_101 = and(_T_99, _T_100) @[Bitwise.scala 102:75]
    node _T_102 = or(_T_97, _T_101) @[Bitwise.scala 102:39]
    node _T_103 = bits(_T_95, 61, 0) @[Bitwise.scala 101:28]
    node _T_104 = shl(_T_103, 2) @[Bitwise.scala 101:47]
    node _T_105 = xor(_T_95, _T_104) @[Bitwise.scala 101:21]
    node _T_106 = shr(_T_102, 2) @[Bitwise.scala 102:21]
    node _T_107 = and(_T_106, _T_105) @[Bitwise.scala 102:31]
    node _T_108 = bits(_T_102, 61, 0) @[Bitwise.scala 102:46]
    node _T_109 = shl(_T_108, 2) @[Bitwise.scala 102:65]
    node _T_110 = not(_T_105) @[Bitwise.scala 102:77]
    node _T_111 = and(_T_109, _T_110) @[Bitwise.scala 102:75]
    node _T_112 = or(_T_107, _T_111) @[Bitwise.scala 102:39]
    node _T_113 = bits(_T_105, 62, 0) @[Bitwise.scala 101:28]
    node _T_114 = shl(_T_113, 1) @[Bitwise.scala 101:47]
    node _T_115 = xor(_T_105, _T_114) @[Bitwise.scala 101:21]
    node _T_116 = shr(_T_112, 1) @[Bitwise.scala 102:21]
    node _T_117 = and(_T_116, _T_115) @[Bitwise.scala 102:31]
    node _T_118 = bits(_T_112, 62, 0) @[Bitwise.scala 102:46]
    node _T_119 = shl(_T_118, 1) @[Bitwise.scala 102:65]
    node _T_120 = not(_T_115) @[Bitwise.scala 102:77]
    node _T_121 = and(_T_119, _T_120) @[Bitwise.scala 102:75]
    node _T_122 = or(_T_117, _T_121) @[Bitwise.scala 102:39]
    node shin = mux(_T_61, shin_r, _T_122) @[ALU.scala 81:17]
    node _T_123 = bits(io.fn, 3, 3) @[ALU.scala 41:29]
    node _T_124 = bits(shin, 63, 63) @[ALU.scala 82:41]
    node _T_125 = and(_T_123, _T_124) @[ALU.scala 82:35]
    node _T_126 = cat(_T_125, shin) @[Cat.scala 30:58]
    node _T_127 = asSInt(_T_126) @[ALU.scala 82:57]
    node _T_128 = dshr(_T_127, shamt) @[ALU.scala 82:64]
    node shout_r = bits(_T_128, 63, 0) @[ALU.scala 82:73]
    node _T_131 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 101:47]
    node _T_132 = xor(UInt<64>("h0ffffffffffffffff"), _T_131) @[Bitwise.scala 101:21]
    node _T_133 = shr(shout_r, 32) @[Bitwise.scala 102:21]
    node _T_134 = and(_T_133, _T_132) @[Bitwise.scala 102:31]
    node _T_135 = bits(shout_r, 31, 0) @[Bitwise.scala 102:46]
    node _T_136 = shl(_T_135, 32) @[Bitwise.scala 102:65]
    node _T_137 = not(_T_132) @[Bitwise.scala 102:77]
    node _T_138 = and(_T_136, _T_137) @[Bitwise.scala 102:75]
    node _T_139 = or(_T_134, _T_138) @[Bitwise.scala 102:39]
    node _T_140 = bits(_T_132, 47, 0) @[Bitwise.scala 101:28]
    node _T_141 = shl(_T_140, 16) @[Bitwise.scala 101:47]
    node _T_142 = xor(_T_132, _T_141) @[Bitwise.scala 101:21]
    node _T_143 = shr(_T_139, 16) @[Bitwise.scala 102:21]
    node _T_144 = and(_T_143, _T_142) @[Bitwise.scala 102:31]
    node _T_145 = bits(_T_139, 47, 0) @[Bitwise.scala 102:46]
    node _T_146 = shl(_T_145, 16) @[Bitwise.scala 102:65]
    node _T_147 = not(_T_142) @[Bitwise.scala 102:77]
    node _T_148 = and(_T_146, _T_147) @[Bitwise.scala 102:75]
    node _T_149 = or(_T_144, _T_148) @[Bitwise.scala 102:39]
    node _T_150 = bits(_T_142, 55, 0) @[Bitwise.scala 101:28]
    node _T_151 = shl(_T_150, 8) @[Bitwise.scala 101:47]
    node _T_152 = xor(_T_142, _T_151) @[Bitwise.scala 101:21]
    node _T_153 = shr(_T_149, 8) @[Bitwise.scala 102:21]
    node _T_154 = and(_T_153, _T_152) @[Bitwise.scala 102:31]
    node _T_155 = bits(_T_149, 55, 0) @[Bitwise.scala 102:46]
    node _T_156 = shl(_T_155, 8) @[Bitwise.scala 102:65]
    node _T_157 = not(_T_152) @[Bitwise.scala 102:77]
    node _T_158 = and(_T_156, _T_157) @[Bitwise.scala 102:75]
    node _T_159 = or(_T_154, _T_158) @[Bitwise.scala 102:39]
    node _T_160 = bits(_T_152, 59, 0) @[Bitwise.scala 101:28]
    node _T_161 = shl(_T_160, 4) @[Bitwise.scala 101:47]
    node _T_162 = xor(_T_152, _T_161) @[Bitwise.scala 101:21]
    node _T_163 = shr(_T_159, 4) @[Bitwise.scala 102:21]
    node _T_164 = and(_T_163, _T_162) @[Bitwise.scala 102:31]
    node _T_165 = bits(_T_159, 59, 0) @[Bitwise.scala 102:46]
    node _T_166 = shl(_T_165, 4) @[Bitwise.scala 102:65]
    node _T_167 = not(_T_162) @[Bitwise.scala 102:77]
    node _T_168 = and(_T_166, _T_167) @[Bitwise.scala 102:75]
    node _T_169 = or(_T_164, _T_168) @[Bitwise.scala 102:39]
    node _T_170 = bits(_T_162, 61, 0) @[Bitwise.scala 101:28]
    node _T_171 = shl(_T_170, 2) @[Bitwise.scala 101:47]
    node _T_172 = xor(_T_162, _T_171) @[Bitwise.scala 101:21]
    node _T_173 = shr(_T_169, 2) @[Bitwise.scala 102:21]
    node _T_174 = and(_T_173, _T_172) @[Bitwise.scala 102:31]
    node _T_175 = bits(_T_169, 61, 0) @[Bitwise.scala 102:46]
    node _T_176 = shl(_T_175, 2) @[Bitwise.scala 102:65]
    node _T_177 = not(_T_172) @[Bitwise.scala 102:77]
    node _T_178 = and(_T_176, _T_177) @[Bitwise.scala 102:75]
    node _T_179 = or(_T_174, _T_178) @[Bitwise.scala 102:39]
    node _T_180 = bits(_T_172, 62, 0) @[Bitwise.scala 101:28]
    node _T_181 = shl(_T_180, 1) @[Bitwise.scala 101:47]
    node _T_182 = xor(_T_172, _T_181) @[Bitwise.scala 101:21]
    node _T_183 = shr(_T_179, 1) @[Bitwise.scala 102:21]
    node _T_184 = and(_T_183, _T_182) @[Bitwise.scala 102:31]
    node _T_185 = bits(_T_179, 62, 0) @[Bitwise.scala 102:46]
    node _T_186 = shl(_T_185, 1) @[Bitwise.scala 102:65]
    node _T_187 = not(_T_182) @[Bitwise.scala 102:77]
    node _T_188 = and(_T_186, _T_187) @[Bitwise.scala 102:75]
    node shout_l = or(_T_184, _T_188) @[Bitwise.scala 102:39]
    node _T_190 = eq(io.fn, UInt<3>("h05")) @[ALU.scala 84:25]
    node _T_192 = eq(io.fn, UInt<4>("h0b")) @[ALU.scala 84:44]
    node _T_193 = or(_T_190, _T_192) @[ALU.scala 84:35]
    node _T_195 = mux(_T_193, shout_r, UInt<1>("h00")) @[ALU.scala 84:18]
    node _T_197 = eq(io.fn, UInt<1>("h01")) @[ALU.scala 85:25]
    node _T_199 = mux(_T_197, shout_l, UInt<1>("h00")) @[ALU.scala 85:18]
    node shout = or(_T_195, _T_199) @[ALU.scala 84:74]
    node _T_201 = eq(io.fn, UInt<3>("h04")) @[ALU.scala 88:25]
    node _T_203 = eq(io.fn, UInt<3>("h06")) @[ALU.scala 88:45]
    node _T_204 = or(_T_201, _T_203) @[ALU.scala 88:36]
    node _T_206 = mux(_T_204, in1_xor_in2, UInt<1>("h00")) @[ALU.scala 88:18]
    node _T_208 = eq(io.fn, UInt<3>("h06")) @[ALU.scala 89:25]
    node _T_210 = eq(io.fn, UInt<3>("h07")) @[ALU.scala 89:44]
    node _T_211 = or(_T_208, _T_210) @[ALU.scala 89:35]
    node _T_212 = and(io.in1, io.in2) @[ALU.scala 89:63]
    node _T_214 = mux(_T_211, _T_212, UInt<1>("h00")) @[ALU.scala 89:18]
    node logic = or(_T_206, _T_214) @[ALU.scala 88:78]
    node _T_216 = eq(io.fn, UInt<2>("h02")) @[ALU.scala 42:30]
    node _T_218 = eq(io.fn, UInt<2>("h03")) @[ALU.scala 42:48]
    node _T_219 = or(_T_216, _T_218) @[ALU.scala 42:41]
    node _T_221 = geq(io.fn, UInt<4>("h0c")) @[ALU.scala 42:66]
    node _T_222 = or(_T_219, _T_221) @[ALU.scala 42:59]
    node _T_223 = and(_T_222, io.cmp_out) @[ALU.scala 90:35]
    node _T_224 = or(_T_223, logic) @[ALU.scala 90:50]
    node shift_logic = or(_T_224, shout) @[ALU.scala 90:58]
    node _T_226 = eq(io.fn, UInt<1>("h00")) @[ALU.scala 91:23]
    node _T_228 = eq(io.fn, UInt<4>("h0a")) @[ALU.scala 91:43]
    node _T_229 = or(_T_226, _T_228) @[ALU.scala 91:34]
    node out = mux(_T_229, io.adder_out, shift_logic) @[ALU.scala 91:16]
    io.out <= out @[ALU.scala 93:10]
    node _T_231 = eq(io.dw, UInt<1>("h00")) @[ALU.scala 96:17]
    when _T_231 : @[ALU.scala 96:28]
      node _T_232 = bits(out, 31, 31) @[ALU.scala 96:56]
      node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 71:15]
      node _T_236 = mux(_T_233, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12]
      node _T_237 = bits(out, 31, 0) @[ALU.scala 96:66]
      node _T_238 = cat(_T_236, _T_237) @[Cat.scala 30:58]
      io.out <= _T_238 @[ALU.scala 96:37]
      skip @[ALU.scala 96:28]
    
  module MulDiv : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}
    
    io is invalid
    io is invalid
    reg state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Multiplier.scala 45:18]
    reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock @[Multiplier.scala 47:16]
    reg count : UInt<7>, clock @[Multiplier.scala 48:18]
    reg neg_out : UInt<1>, clock @[Multiplier.scala 49:20]
    reg isMul : UInt<1>, clock @[Multiplier.scala 50:18]
    reg isHi : UInt<1>, clock @[Multiplier.scala 51:17]
    reg divisor : UInt<65>, clock @[Multiplier.scala 52:20]
    reg remainder : UInt<130>, clock @[Multiplier.scala 53:22]
    node _T_79 = and(io.req.bits.fn, UInt<4>("h04")) @[Decode.scala 13:65]
    node _T_81 = eq(_T_79, UInt<4>("h00")) @[Decode.scala 13:121]
    node _T_83 = and(io.req.bits.fn, UInt<4>("h08")) @[Decode.scala 13:65]
    node _T_85 = eq(_T_83, UInt<4>("h08")) @[Decode.scala 13:121]
    node _T_87 = or(UInt<1>("h00"), _T_81) @[Decode.scala 14:30]
    node _T_88 = or(_T_87, _T_85) @[Decode.scala 14:30]
    node _T_90 = and(io.req.bits.fn, UInt<4>("h05")) @[Decode.scala 13:65]
    node _T_92 = eq(_T_90, UInt<4>("h01")) @[Decode.scala 13:121]
    node _T_94 = and(io.req.bits.fn, UInt<4>("h02")) @[Decode.scala 13:65]
    node _T_96 = eq(_T_94, UInt<4>("h02")) @[Decode.scala 13:121]
    node _T_98 = or(UInt<1>("h00"), _T_92) @[Decode.scala 14:30]
    node _T_99 = or(_T_98, _T_96) @[Decode.scala 14:30]
    node _T_100 = or(_T_99, _T_85) @[Decode.scala 14:30]
    node _T_102 = and(io.req.bits.fn, UInt<4>("h09")) @[Decode.scala 13:65]
    node _T_104 = eq(_T_102, UInt<4>("h00")) @[Decode.scala 13:121]
    node _T_106 = and(io.req.bits.fn, UInt<4>("h03")) @[Decode.scala 13:65]
    node _T_108 = eq(_T_106, UInt<4>("h00")) @[Decode.scala 13:121]
    node _T_110 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30]
    node _T_111 = or(_T_110, _T_81) @[Decode.scala 14:30]
    node _T_112 = or(_T_111, _T_108) @[Decode.scala 14:30]
    node _T_114 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30]
    node _T_115 = or(_T_114, _T_81) @[Decode.scala 14:30]
    node cmdMul = bits(_T_88, 0, 0) @[Multiplier.scala 64:58]
    node cmdHi = bits(_T_100, 0, 0) @[Multiplier.scala 64:58]
    node lhsSigned = bits(_T_112, 0, 0) @[Multiplier.scala 64:58]
    node rhsSigned = bits(_T_115, 0, 0) @[Multiplier.scala 64:58]
    node _T_118 = eq(io.req.bits.dw, UInt<1>("h00")) @[Multiplier.scala 67:62]
    node _T_119 = and(UInt<1>("h01"), _T_118) @[Multiplier.scala 67:52]
    node _T_120 = bits(io.req.bits.in1, 31, 31) @[Multiplier.scala 70:38]
    node _T_121 = bits(io.req.bits.in1, 63, 63) @[Multiplier.scala 70:48]
    node _T_122 = mux(_T_119, _T_120, _T_121) @[Multiplier.scala 70:29]
    node lhs_sign = and(lhsSigned, _T_122) @[Multiplier.scala 70:23]
    node _T_123 = bits(lhs_sign, 0, 0) @[Bitwise.scala 71:15]
    node _T_126 = mux(_T_123, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12]
    node _T_127 = bits(io.req.bits.in1, 63, 32) @[Multiplier.scala 71:43]
    node _T_128 = mux(_T_119, _T_126, _T_127) @[Multiplier.scala 71:17]
    node _T_129 = bits(io.req.bits.in1, 31, 0) @[Multiplier.scala 72:15]
    node lhs_in = cat(_T_128, _T_129) @[Cat.scala 30:58]
    node _T_132 = eq(io.req.bits.dw, UInt<1>("h00")) @[Multiplier.scala 67:62]
    node _T_133 = and(UInt<1>("h01"), _T_132) @[Multiplier.scala 67:52]
    node _T_134 = bits(io.req.bits.in2, 31, 31) @[Multiplier.scala 70:38]
    node _T_135 = bits(io.req.bits.in2, 63, 63) @[Multiplier.scala 70:48]
    node _T_136 = mux(_T_133, _T_134, _T_135) @[Multiplier.scala 70:29]
    node rhs_sign = and(rhsSigned, _T_136) @[Multiplier.scala 70:23]
    node _T_137 = bits(rhs_sign, 0, 0) @[Bitwise.scala 71:15]
    node _T_140 = mux(_T_137, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12]
    node _T_141 = bits(io.req.bits.in2, 63, 32) @[Multiplier.scala 71:43]
    node _T_142 = mux(_T_133, _T_140, _T_141) @[Multiplier.scala 71:17]
    node _T_143 = bits(io.req.bits.in2, 31, 0) @[Multiplier.scala 72:15]
    node rhs_in = cat(_T_142, _T_143) @[Cat.scala 30:58]
    node _T_144 = bits(remainder, 128, 64) @[Multiplier.scala 77:29]
    node _T_145 = sub(_T_144, divisor) @[Multiplier.scala 77:37]
    node _T_146 = asUInt(_T_145) @[Multiplier.scala 77:37]
    node subtractor = tail(_T_146, 1) @[Multiplier.scala 77:37]
    node _T_147 = bits(remainder, 63, 0) @[Multiplier.scala 78:37]
    node _T_149 = sub(UInt<1>("h00"), _T_147) @[Multiplier.scala 78:27]
    node _T_150 = asUInt(_T_149) @[Multiplier.scala 78:27]
    node negated_remainder = tail(_T_150, 1) @[Multiplier.scala 78:27]
    node _T_151 = eq(state, UInt<3>("h01")) @[Multiplier.scala 80:15]
    when _T_151 : @[Multiplier.scala 80:33]
      node _T_152 = bits(remainder, 63, 63) @[Multiplier.scala 81:20]
      node _T_153 = or(_T_152, isMul) @[Multiplier.scala 81:26]
      when _T_153 : @[Multiplier.scala 81:36]
        remainder <= negated_remainder @[Multiplier.scala 82:17]
        skip @[Multiplier.scala 81:36]
      node _T_154 = bits(divisor, 63, 63) @[Multiplier.scala 84:18]
      node _T_155 = or(_T_154, isMul) @[Multiplier.scala 84:24]
      when _T_155 : @[Multiplier.scala 84:34]
        divisor <= subtractor @[Multiplier.scala 85:15]
        skip @[Multiplier.scala 84:34]
      state <= UInt<3>("h02") @[Multiplier.scala 87:11]
      skip @[Multiplier.scala 80:33]
    node _T_156 = eq(state, UInt<3>("h04")) @[Multiplier.scala 90:15]
    when _T_156 : @[Multiplier.scala 90:33]
      remainder <= negated_remainder @[Multiplier.scala 91:15]
      state <= UInt<3>("h05") @[Multiplier.scala 92:11]
      skip @[Multiplier.scala 90:33]
    node _T_157 = eq(state, UInt<3>("h03")) @[Multiplier.scala 94:15]
    when _T_157 : @[Multiplier.scala 94:31]
      node _T_158 = bits(remainder, 128, 65) @[Multiplier.scala 95:27]
      remainder <= _T_158 @[Multiplier.scala 95:15]
      node _T_159 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) @[Multiplier.scala 96:17]
      state <= _T_159 @[Multiplier.scala 96:11]
      skip @[Multiplier.scala 94:31]
    node _T_160 = eq(state, UInt<3>("h02")) @[Multiplier.scala 98:15]
    node _T_161 = and(_T_160, isMul) @[Multiplier.scala 98:26]
    when _T_161 : @[Multiplier.scala 98:36]
      node _T_162 = bits(remainder, 129, 65) @[Multiplier.scala 99:31]
      node _T_163 = bits(remainder, 63, 0) @[Multiplier.scala 99:55]
      node _T_164 = cat(_T_162, _T_163) @[Cat.scala 30:58]
      node _T_165 = bits(_T_164, 63, 0) @[Multiplier.scala 100:24]
      node _T_166 = bits(_T_164, 128, 64) @[Multiplier.scala 101:23]
      node _T_167 = asSInt(_T_166) @[Multiplier.scala 101:37]
      node _T_168 = asSInt(divisor) @[Multiplier.scala 102:26]
      node _T_169 = bits(_T_165, 7, 0) @[Multiplier.scala 103:22]
      node _M_170 = asSInt(_T_169) @[Multiplier.scala 103:22]
      node _T_170 = mul(_T_168, _M_170) @[Multiplier.scala 103:43]
      node _T_171 = add(_T_170, _T_167) @[Multiplier.scala 103:52]
      node _T_172 = tail(_T_171, 1) @[Multiplier.scala 103:52]
      node _T_173 = asSInt(_T_172) @[Multiplier.scala 103:52]
      node _T_174 = bits(_T_165, 63, 8) @[Multiplier.scala 104:38]
      node _T_175 = asUInt(_T_173) @[Cat.scala 30:58]
      node _T_176 = cat(_T_175, _T_174) @[Cat.scala 30:58]
      node _T_179 = mul(count, UInt<4>("h08")) @[Multiplier.scala 106:56]
      node _T_180 = bits(_T_179, 5, 0) @[Multiplier.scala 106:72]
      node _T_181 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_180) @[Multiplier.scala 106:46]
      node _T_182 = bits(_T_181, 63, 0) @[Multiplier.scala 106:91]
      node _T_185 = neq(count, UInt<3>("h07")) @[Multiplier.scala 107:47]
      node _T_186 = and(UInt<1>("h01"), _T_185) @[Multiplier.scala 107:38]
      node _T_188 = neq(count, UInt<1>("h00")) @[Multiplier.scala 107:81]
      node _T_189 = and(_T_186, _T_188) @[Multiplier.scala 107:72]
      node _T_191 = eq(isHi, UInt<1>("h00")) @[Multiplier.scala 108:7]
      node _T_192 = and(_T_189, _T_191) @[Multiplier.scala 107:87]
      node _T_193 = not(_T_182) @[Multiplier.scala 108:26]
      node _T_194 = and(_T_165, _T_193) @[Multiplier.scala 108:24]
      node _T_196 = eq(_T_194, UInt<1>("h00")) @[Multiplier.scala 108:37]
      node _T_197 = and(_T_192, _T_196) @[Multiplier.scala 108:13]
      node _T_200 = mul(count, UInt<4>("h08")) @[Multiplier.scala 109:44]
      node _T_201 = sub(UInt<7>("h040"), _T_200) @[Multiplier.scala 109:36]
      node _T_202 = asUInt(_T_201) @[Multiplier.scala 109:36]
      node _T_203 = tail(_T_202, 1) @[Multiplier.scala 109:36]
      node _T_204 = bits(_T_203, 5, 0) @[Multiplier.scala 109:60]
      node _T_205 = dshr(_T_164, _T_204) @[Multiplier.scala 109:27]
      node _T_206 = bits(_T_176, 128, 64) @[Multiplier.scala 110:37]
      node _T_207 = mux(_T_197, _T_205, _T_176) @[Multiplier.scala 110:55]
      node _T_208 = bits(_T_207, 63, 0) @[Multiplier.scala 110:82]
      node _T_209 = cat(_T_206, _T_208) @[Cat.scala 30:58]
      node _T_210 = shr(_T_209, 64) @[Multiplier.scala 111:34]
      node _T_212 = bits(_T_209, 63, 0) @[Multiplier.scala 111:64]
      node _T_213 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 30:58]
      node _T_214 = cat(_T_213, _T_212) @[Cat.scala 30:58]
      remainder <= _T_214 @[Multiplier.scala 111:15]
      node _T_216 = add(count, UInt<1>("h01")) @[Multiplier.scala 113:20]
      node _T_217 = tail(_T_216, 1) @[Multiplier.scala 113:20]
      count <= _T_217 @[Multiplier.scala 113:11]
      node _T_219 = eq(count, UInt<3>("h07")) @[Multiplier.scala 114:25]
      node _T_220 = or(_T_197, _T_219) @[Multiplier.scala 114:16]
      when _T_220 : @[Multiplier.scala 114:51]
        node _T_221 = mux(isHi, UInt<3>("h03"), UInt<3>("h05")) @[Multiplier.scala 115:19]
        state <= _T_221 @[Multiplier.scala 115:13]
        skip @[Multiplier.scala 114:51]
      skip @[Multiplier.scala 98:36]
    node _T_222 = eq(state, UInt<3>("h02")) @[Multiplier.scala 118:15]
    node _T_224 = eq(isMul, UInt<1>("h00")) @[Multiplier.scala 118:29]
    node _T_225 = and(_T_222, _T_224) @[Multiplier.scala 118:26]
    when _T_225 : @[Multiplier.scala 118:37]
      node _T_226 = bits(subtractor, 64, 64) @[Multiplier.scala 122:28]
      node _T_227 = bits(remainder, 127, 64) @[Multiplier.scala 123:24]
      node _T_228 = bits(subtractor, 63, 0) @[Multiplier.scala 123:45]
      node _T_229 = mux(_T_226, _T_227, _T_228) @[Multiplier.scala 123:14]
      node _T_230 = bits(remainder, 63, 0) @[Multiplier.scala 123:58]
      node _T_232 = eq(_T_226, UInt<1>("h00")) @[Multiplier.scala 123:67]
      node _T_233 = cat(_T_229, _T_230) @[Cat.scala 30:58]
      node _T_234 = cat(_T_233, _T_232) @[Cat.scala 30:58]
      remainder <= _T_234 @[Multiplier.scala 126:15]
      node _T_236 = eq(count, UInt<7>("h040")) @[Multiplier.scala 127:17]
      when _T_236 : @[Multiplier.scala 127:38]
        node _T_237 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) @[Multiplier.scala 128:41]
        node _T_238 = mux(isHi, UInt<3>("h03"), _T_237) @[Multiplier.scala 128:19]
        state <= _T_238 @[Multiplier.scala 128:13]
        skip @[Multiplier.scala 127:38]
      node _T_240 = add(count, UInt<1>("h01")) @[Multiplier.scala 132:20]
      node _T_241 = tail(_T_240, 1) @[Multiplier.scala 132:20]
      count <= _T_241 @[Multiplier.scala 132:11]
      node _T_243 = eq(count, UInt<1>("h00")) @[Multiplier.scala 134:24]
      node _T_244 = bits(subtractor, 64, 64) @[Multiplier.scala 134:44]
      node _T_246 = eq(_T_244, UInt<1>("h00")) @[Multiplier.scala 134:33]
      node _T_247 = and(_T_243, _T_246) @[Multiplier.scala 134:30]
      node _T_248 = bits(divisor, 63, 0) @[Multiplier.scala 136:36]
      node _T_249 = bits(_T_248, 63, 32) @[CircuitMath.scala 35:17]
      node _T_250 = bits(_T_248, 31, 0) @[CircuitMath.scala 36:17]
      node _T_252 = neq(_T_249, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_253 = bits(_T_249, 31, 16) @[CircuitMath.scala 35:17]
      node _T_254 = bits(_T_249, 15, 0) @[CircuitMath.scala 36:17]
      node _T_256 = neq(_T_253, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_257 = bits(_T_253, 15, 8) @[CircuitMath.scala 35:17]
      node _T_258 = bits(_T_253, 7, 0) @[CircuitMath.scala 36:17]
      node _T_260 = neq(_T_257, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_261 = bits(_T_257, 7, 4) @[CircuitMath.scala 35:17]
      node _T_262 = bits(_T_257, 3, 0) @[CircuitMath.scala 36:17]
      node _T_264 = neq(_T_261, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_265 = bits(_T_261, 3, 3) @[CircuitMath.scala 32:12]
      node _T_267 = bits(_T_261, 2, 2) @[CircuitMath.scala 32:12]
      node _T_269 = bits(_T_261, 1, 1) @[CircuitMath.scala 30:8]
      node _T_270 = mux(_T_267, UInt<2>("h02"), _T_269) @[CircuitMath.scala 32:10]
      node _T_271 = mux(_T_265, UInt<2>("h03"), _T_270) @[CircuitMath.scala 32:10]
      node _T_272 = bits(_T_262, 3, 3) @[CircuitMath.scala 32:12]
      node _T_274 = bits(_T_262, 2, 2) @[CircuitMath.scala 32:12]
      node _T_276 = bits(_T_262, 1, 1) @[CircuitMath.scala 30:8]
      node _T_277 = mux(_T_274, UInt<2>("h02"), _T_276) @[CircuitMath.scala 32:10]
      node _T_278 = mux(_T_272, UInt<2>("h03"), _T_277) @[CircuitMath.scala 32:10]
      node _T_279 = mux(_T_264, _T_271, _T_278) @[CircuitMath.scala 38:21]
      node _T_280 = cat(_T_264, _T_279) @[Cat.scala 30:58]
      node _T_281 = bits(_T_258, 7, 4) @[CircuitMath.scala 35:17]
      node _T_282 = bits(_T_258, 3, 0) @[CircuitMath.scala 36:17]
      node _T_284 = neq(_T_281, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_285 = bits(_T_281, 3, 3) @[CircuitMath.scala 32:12]
      node _T_287 = bits(_T_281, 2, 2) @[CircuitMath.scala 32:12]
      node _T_289 = bits(_T_281, 1, 1) @[CircuitMath.scala 30:8]
      node _T_290 = mux(_T_287, UInt<2>("h02"), _T_289) @[CircuitMath.scala 32:10]
      node _T_291 = mux(_T_285, UInt<2>("h03"), _T_290) @[CircuitMath.scala 32:10]
      node _T_292 = bits(_T_282, 3, 3) @[CircuitMath.scala 32:12]
      node _T_294 = bits(_T_282, 2, 2) @[CircuitMath.scala 32:12]
      node _T_296 = bits(_T_282, 1, 1) @[CircuitMath.scala 30:8]
      node _T_297 = mux(_T_294, UInt<2>("h02"), _T_296) @[CircuitMath.scala 32:10]
      node _T_298 = mux(_T_292, UInt<2>("h03"), _T_297) @[CircuitMath.scala 32:10]
      node _T_299 = mux(_T_284, _T_291, _T_298) @[CircuitMath.scala 38:21]
      node _T_300 = cat(_T_284, _T_299) @[Cat.scala 30:58]
      node _T_301 = mux(_T_260, _T_280, _T_300) @[CircuitMath.scala 38:21]
      node _T_302 = cat(_T_260, _T_301) @[Cat.scala 30:58]
      node _T_303 = bits(_T_254, 15, 8) @[CircuitMath.scala 35:17]
      node _T_304 = bits(_T_254, 7, 0) @[CircuitMath.scala 36:17]
      node _T_306 = neq(_T_303, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_307 = bits(_T_303, 7, 4) @[CircuitMath.scala 35:17]
      node _T_308 = bits(_T_303, 3, 0) @[CircuitMath.scala 36:17]
      node _T_310 = neq(_T_307, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_311 = bits(_T_307, 3, 3) @[CircuitMath.scala 32:12]
      node _T_313 = bits(_T_307, 2, 2) @[CircuitMath.scala 32:12]
      node _T_315 = bits(_T_307, 1, 1) @[CircuitMath.scala 30:8]
      node _T_316 = mux(_T_313, UInt<2>("h02"), _T_315) @[CircuitMath.scala 32:10]
      node _T_317 = mux(_T_311, UInt<2>("h03"), _T_316) @[CircuitMath.scala 32:10]
      node _T_318 = bits(_T_308, 3, 3) @[CircuitMath.scala 32:12]
      node _T_320 = bits(_T_308, 2, 2) @[CircuitMath.scala 32:12]
      node _T_322 = bits(_T_308, 1, 1) @[CircuitMath.scala 30:8]
      node _T_323 = mux(_T_320, UInt<2>("h02"), _T_322) @[CircuitMath.scala 32:10]
      node _T_324 = mux(_T_318, UInt<2>("h03"), _T_323) @[CircuitMath.scala 32:10]
      node _T_325 = mux(_T_310, _T_317, _T_324) @[CircuitMath.scala 38:21]
      node _T_326 = cat(_T_310, _T_325) @[Cat.scala 30:58]
      node _T_327 = bits(_T_304, 7, 4) @[CircuitMath.scala 35:17]
      node _T_328 = bits(_T_304, 3, 0) @[CircuitMath.scala 36:17]
      node _T_330 = neq(_T_327, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_331 = bits(_T_327, 3, 3) @[CircuitMath.scala 32:12]
      node _T_333 = bits(_T_327, 2, 2) @[CircuitMath.scala 32:12]
      node _T_335 = bits(_T_327, 1, 1) @[CircuitMath.scala 30:8]
      node _T_336 = mux(_T_333, UInt<2>("h02"), _T_335) @[CircuitMath.scala 32:10]
      node _T_337 = mux(_T_331, UInt<2>("h03"), _T_336) @[CircuitMath.scala 32:10]
      node _T_338 = bits(_T_328, 3, 3) @[CircuitMath.scala 32:12]
      node _T_340 = bits(_T_328, 2, 2) @[CircuitMath.scala 32:12]
      node _T_342 = bits(_T_328, 1, 1) @[CircuitMath.scala 30:8]
      node _T_343 = mux(_T_340, UInt<2>("h02"), _T_342) @[CircuitMath.scala 32:10]
      node _T_344 = mux(_T_338, UInt<2>("h03"), _T_343) @[CircuitMath.scala 32:10]
      node _T_345 = mux(_T_330, _T_337, _T_344) @[CircuitMath.scala 38:21]
      node _T_346 = cat(_T_330, _T_345) @[Cat.scala 30:58]
      node _T_347 = mux(_T_306, _T_326, _T_346) @[CircuitMath.scala 38:21]
      node _T_348 = cat(_T_306, _T_347) @[Cat.scala 30:58]
      node _T_349 = mux(_T_256, _T_302, _T_348) @[CircuitMath.scala 38:21]
      node _T_350 = cat(_T_256, _T_349) @[Cat.scala 30:58]
      node _T_351 = bits(_T_250, 31, 16) @[CircuitMath.scala 35:17]
      node _T_352 = bits(_T_250, 15, 0) @[CircuitMath.scala 36:17]
      node _T_354 = neq(_T_351, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_355 = bits(_T_351, 15, 8) @[CircuitMath.scala 35:17]
      node _T_356 = bits(_T_351, 7, 0) @[CircuitMath.scala 36:17]
      node _T_358 = neq(_T_355, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_359 = bits(_T_355, 7, 4) @[CircuitMath.scala 35:17]
      node _T_360 = bits(_T_355, 3, 0) @[CircuitMath.scala 36:17]
      node _T_362 = neq(_T_359, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_363 = bits(_T_359, 3, 3) @[CircuitMath.scala 32:12]
      node _T_365 = bits(_T_359, 2, 2) @[CircuitMath.scala 32:12]
      node _T_367 = bits(_T_359, 1, 1) @[CircuitMath.scala 30:8]
      node _T_368 = mux(_T_365, UInt<2>("h02"), _T_367) @[CircuitMath.scala 32:10]
      node _T_369 = mux(_T_363, UInt<2>("h03"), _T_368) @[CircuitMath.scala 32:10]
      node _T_370 = bits(_T_360, 3, 3) @[CircuitMath.scala 32:12]
      node _T_372 = bits(_T_360, 2, 2) @[CircuitMath.scala 32:12]
      node _T_374 = bits(_T_360, 1, 1) @[CircuitMath.scala 30:8]
      node _T_375 = mux(_T_372, UInt<2>("h02"), _T_374) @[CircuitMath.scala 32:10]
      node _T_376 = mux(_T_370, UInt<2>("h03"), _T_375) @[CircuitMath.scala 32:10]
      node _T_377 = mux(_T_362, _T_369, _T_376) @[CircuitMath.scala 38:21]
      node _T_378 = cat(_T_362, _T_377) @[Cat.scala 30:58]
      node _T_379 = bits(_T_356, 7, 4) @[CircuitMath.scala 35:17]
      node _T_380 = bits(_T_356, 3, 0) @[CircuitMath.scala 36:17]
      node _T_382 = neq(_T_379, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_383 = bits(_T_379, 3, 3) @[CircuitMath.scala 32:12]
      node _T_385 = bits(_T_379, 2, 2) @[CircuitMath.scala 32:12]
      node _T_387 = bits(_T_379, 1, 1) @[CircuitMath.scala 30:8]
      node _T_388 = mux(_T_385, UInt<2>("h02"), _T_387) @[CircuitMath.scala 32:10]
      node _T_389 = mux(_T_383, UInt<2>("h03"), _T_388) @[CircuitMath.scala 32:10]
      node _T_390 = bits(_T_380, 3, 3) @[CircuitMath.scala 32:12]
      node _T_392 = bits(_T_380, 2, 2) @[CircuitMath.scala 32:12]
      node _T_394 = bits(_T_380, 1, 1) @[CircuitMath.scala 30:8]
      node _T_395 = mux(_T_392, UInt<2>("h02"), _T_394) @[CircuitMath.scala 32:10]
      node _T_396 = mux(_T_390, UInt<2>("h03"), _T_395) @[CircuitMath.scala 32:10]
      node _T_397 = mux(_T_382, _T_389, _T_396) @[CircuitMath.scala 38:21]
      node _T_398 = cat(_T_382, _T_397) @[Cat.scala 30:58]
      node _T_399 = mux(_T_358, _T_378, _T_398) @[CircuitMath.scala 38:21]
      node _T_400 = cat(_T_358, _T_399) @[Cat.scala 30:58]
      node _T_401 = bits(_T_352, 15, 8) @[CircuitMath.scala 35:17]
      node _T_402 = bits(_T_352, 7, 0) @[CircuitMath.scala 36:17]
      node _T_404 = neq(_T_401, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_405 = bits(_T_401, 7, 4) @[CircuitMath.scala 35:17]
      node _T_406 = bits(_T_401, 3, 0) @[CircuitMath.scala 36:17]
      node _T_408 = neq(_T_405, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_409 = bits(_T_405, 3, 3) @[CircuitMath.scala 32:12]
      node _T_411 = bits(_T_405, 2, 2) @[CircuitMath.scala 32:12]
      node _T_413 = bits(_T_405, 1, 1) @[CircuitMath.scala 30:8]
      node _T_414 = mux(_T_411, UInt<2>("h02"), _T_413) @[CircuitMath.scala 32:10]
      node _T_415 = mux(_T_409, UInt<2>("h03"), _T_414) @[CircuitMath.scala 32:10]
      node _T_416 = bits(_T_406, 3, 3) @[CircuitMath.scala 32:12]
      node _T_418 = bits(_T_406, 2, 2) @[CircuitMath.scala 32:12]
      node _T_420 = bits(_T_406, 1, 1) @[CircuitMath.scala 30:8]
      node _T_421 = mux(_T_418, UInt<2>("h02"), _T_420) @[CircuitMath.scala 32:10]
      node _T_422 = mux(_T_416, UInt<2>("h03"), _T_421) @[CircuitMath.scala 32:10]
      node _T_423 = mux(_T_408, _T_415, _T_422) @[CircuitMath.scala 38:21]
      node _T_424 = cat(_T_408, _T_423) @[Cat.scala 30:58]
      node _T_425 = bits(_T_402, 7, 4) @[CircuitMath.scala 35:17]
      node _T_426 = bits(_T_402, 3, 0) @[CircuitMath.scala 36:17]
      node _T_428 = neq(_T_425, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_429 = bits(_T_425, 3, 3) @[CircuitMath.scala 32:12]
      node _T_431 = bits(_T_425, 2, 2) @[CircuitMath.scala 32:12]
      node _T_433 = bits(_T_425, 1, 1) @[CircuitMath.scala 30:8]
      node _T_434 = mux(_T_431, UInt<2>("h02"), _T_433) @[CircuitMath.scala 32:10]
      node _T_435 = mux(_T_429, UInt<2>("h03"), _T_434) @[CircuitMath.scala 32:10]
      node _T_436 = bits(_T_426, 3, 3) @[CircuitMath.scala 32:12]
      node _T_438 = bits(_T_426, 2, 2) @[CircuitMath.scala 32:12]
      node _T_440 = bits(_T_426, 1, 1) @[CircuitMath.scala 30:8]
      node _T_441 = mux(_T_438, UInt<2>("h02"), _T_440) @[CircuitMath.scala 32:10]
      node _T_442 = mux(_T_436, UInt<2>("h03"), _T_441) @[CircuitMath.scala 32:10]
      node _T_443 = mux(_T_428, _T_435, _T_442) @[CircuitMath.scala 38:21]
      node _T_444 = cat(_T_428, _T_443) @[Cat.scala 30:58]
      node _T_445 = mux(_T_404, _T_424, _T_444) @[CircuitMath.scala 38:21]
      node _T_446 = cat(_T_404, _T_445) @[Cat.scala 30:58]
      node _T_447 = mux(_T_354, _T_400, _T_446) @[CircuitMath.scala 38:21]
      node _T_448 = cat(_T_354, _T_447) @[Cat.scala 30:58]
      node _T_449 = mux(_T_252, _T_350, _T_448) @[CircuitMath.scala 38:21]
      node _T_450 = cat(_T_252, _T_449) @[Cat.scala 30:58]
      node _T_451 = bits(remainder, 63, 0) @[Multiplier.scala 137:39]
      node _T_452 = bits(_T_451, 63, 32) @[CircuitMath.scala 35:17]
      node _T_453 = bits(_T_451, 31, 0) @[CircuitMath.scala 36:17]
      node _T_455 = neq(_T_452, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_456 = bits(_T_452, 31, 16) @[CircuitMath.scala 35:17]
      node _T_457 = bits(_T_452, 15, 0) @[CircuitMath.scala 36:17]
      node _T_459 = neq(_T_456, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_460 = bits(_T_456, 15, 8) @[CircuitMath.scala 35:17]
      node _T_461 = bits(_T_456, 7, 0) @[CircuitMath.scala 36:17]
      node _T_463 = neq(_T_460, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_464 = bits(_T_460, 7, 4) @[CircuitMath.scala 35:17]
      node _T_465 = bits(_T_460, 3, 0) @[CircuitMath.scala 36:17]
      node _T_467 = neq(_T_464, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_468 = bits(_T_464, 3, 3) @[CircuitMath.scala 32:12]
      node _T_470 = bits(_T_464, 2, 2) @[CircuitMath.scala 32:12]
      node _T_472 = bits(_T_464, 1, 1) @[CircuitMath.scala 30:8]
      node _T_473 = mux(_T_470, UInt<2>("h02"), _T_472) @[CircuitMath.scala 32:10]
      node _T_474 = mux(_T_468, UInt<2>("h03"), _T_473) @[CircuitMath.scala 32:10]
      node _T_475 = bits(_T_465, 3, 3) @[CircuitMath.scala 32:12]
      node _T_477 = bits(_T_465, 2, 2) @[CircuitMath.scala 32:12]
      node _T_479 = bits(_T_465, 1, 1) @[CircuitMath.scala 30:8]
      node _T_480 = mux(_T_477, UInt<2>("h02"), _T_479) @[CircuitMath.scala 32:10]
      node _T_481 = mux(_T_475, UInt<2>("h03"), _T_480) @[CircuitMath.scala 32:10]
      node _T_482 = mux(_T_467, _T_474, _T_481) @[CircuitMath.scala 38:21]
      node _T_483 = cat(_T_467, _T_482) @[Cat.scala 30:58]
      node _T_484 = bits(_T_461, 7, 4) @[CircuitMath.scala 35:17]
      node _T_485 = bits(_T_461, 3, 0) @[CircuitMath.scala 36:17]
      node _T_487 = neq(_T_484, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_488 = bits(_T_484, 3, 3) @[CircuitMath.scala 32:12]
      node _T_490 = bits(_T_484, 2, 2) @[CircuitMath.scala 32:12]
      node _T_492 = bits(_T_484, 1, 1) @[CircuitMath.scala 30:8]
      node _T_493 = mux(_T_490, UInt<2>("h02"), _T_492) @[CircuitMath.scala 32:10]
      node _T_494 = mux(_T_488, UInt<2>("h03"), _T_493) @[CircuitMath.scala 32:10]
      node _T_495 = bits(_T_485, 3, 3) @[CircuitMath.scala 32:12]
      node _T_497 = bits(_T_485, 2, 2) @[CircuitMath.scala 32:12]
      node _T_499 = bits(_T_485, 1, 1) @[CircuitMath.scala 30:8]
      node _T_500 = mux(_T_497, UInt<2>("h02"), _T_499) @[CircuitMath.scala 32:10]
      node _T_501 = mux(_T_495, UInt<2>("h03"), _T_500) @[CircuitMath.scala 32:10]
      node _T_502 = mux(_T_487, _T_494, _T_501) @[CircuitMath.scala 38:21]
      node _T_503 = cat(_T_487, _T_502) @[Cat.scala 30:58]
      node _T_504 = mux(_T_463, _T_483, _T_503) @[CircuitMath.scala 38:21]
      node _T_505 = cat(_T_463, _T_504) @[Cat.scala 30:58]
      node _T_506 = bits(_T_457, 15, 8) @[CircuitMath.scala 35:17]
      node _T_507 = bits(_T_457, 7, 0) @[CircuitMath.scala 36:17]
      node _T_509 = neq(_T_506, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_510 = bits(_T_506, 7, 4) @[CircuitMath.scala 35:17]
      node _T_511 = bits(_T_506, 3, 0) @[CircuitMath.scala 36:17]
      node _T_513 = neq(_T_510, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_514 = bits(_T_510, 3, 3) @[CircuitMath.scala 32:12]
      node _T_516 = bits(_T_510, 2, 2) @[CircuitMath.scala 32:12]
      node _T_518 = bits(_T_510, 1, 1) @[CircuitMath.scala 30:8]
      node _T_519 = mux(_T_516, UInt<2>("h02"), _T_518) @[CircuitMath.scala 32:10]
      node _T_520 = mux(_T_514, UInt<2>("h03"), _T_519) @[CircuitMath.scala 32:10]
      node _T_521 = bits(_T_511, 3, 3) @[CircuitMath.scala 32:12]
      node _T_523 = bits(_T_511, 2, 2) @[CircuitMath.scala 32:12]
      node _T_525 = bits(_T_511, 1, 1) @[CircuitMath.scala 30:8]
      node _T_526 = mux(_T_523, UInt<2>("h02"), _T_525) @[CircuitMath.scala 32:10]
      node _T_527 = mux(_T_521, UInt<2>("h03"), _T_526) @[CircuitMath.scala 32:10]
      node _T_528 = mux(_T_513, _T_520, _T_527) @[CircuitMath.scala 38:21]
      node _T_529 = cat(_T_513, _T_528) @[Cat.scala 30:58]
      node _T_530 = bits(_T_507, 7, 4) @[CircuitMath.scala 35:17]
      node _T_531 = bits(_T_507, 3, 0) @[CircuitMath.scala 36:17]
      node _T_533 = neq(_T_530, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_534 = bits(_T_530, 3, 3) @[CircuitMath.scala 32:12]
      node _T_536 = bits(_T_530, 2, 2) @[CircuitMath.scala 32:12]
      node _T_538 = bits(_T_530, 1, 1) @[CircuitMath.scala 30:8]
      node _T_539 = mux(_T_536, UInt<2>("h02"), _T_538) @[CircuitMath.scala 32:10]
      node _T_540 = mux(_T_534, UInt<2>("h03"), _T_539) @[CircuitMath.scala 32:10]
      node _T_541 = bits(_T_531, 3, 3) @[CircuitMath.scala 32:12]
      node _T_543 = bits(_T_531, 2, 2) @[CircuitMath.scala 32:12]
      node _T_545 = bits(_T_531, 1, 1) @[CircuitMath.scala 30:8]
      node _T_546 = mux(_T_543, UInt<2>("h02"), _T_545) @[CircuitMath.scala 32:10]
      node _T_547 = mux(_T_541, UInt<2>("h03"), _T_546) @[CircuitMath.scala 32:10]
      node _T_548 = mux(_T_533, _T_540, _T_547) @[CircuitMath.scala 38:21]
      node _T_549 = cat(_T_533, _T_548) @[Cat.scala 30:58]
      node _T_550 = mux(_T_509, _T_529, _T_549) @[CircuitMath.scala 38:21]
      node _T_551 = cat(_T_509, _T_550) @[Cat.scala 30:58]
      node _T_552 = mux(_T_459, _T_505, _T_551) @[CircuitMath.scala 38:21]
      node _T_553 = cat(_T_459, _T_552) @[Cat.scala 30:58]
      node _T_554 = bits(_T_453, 31, 16) @[CircuitMath.scala 35:17]
      node _T_555 = bits(_T_453, 15, 0) @[CircuitMath.scala 36:17]
      node _T_557 = neq(_T_554, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_558 = bits(_T_554, 15, 8) @[CircuitMath.scala 35:17]
      node _T_559 = bits(_T_554, 7, 0) @[CircuitMath.scala 36:17]
      node _T_561 = neq(_T_558, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_562 = bits(_T_558, 7, 4) @[CircuitMath.scala 35:17]
      node _T_563 = bits(_T_558, 3, 0) @[CircuitMath.scala 36:17]
      node _T_565 = neq(_T_562, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_566 = bits(_T_562, 3, 3) @[CircuitMath.scala 32:12]
      node _T_568 = bits(_T_562, 2, 2) @[CircuitMath.scala 32:12]
      node _T_570 = bits(_T_562, 1, 1) @[CircuitMath.scala 30:8]
      node _T_571 = mux(_T_568, UInt<2>("h02"), _T_570) @[CircuitMath.scala 32:10]
      node _T_572 = mux(_T_566, UInt<2>("h03"), _T_571) @[CircuitMath.scala 32:10]
      node _T_573 = bits(_T_563, 3, 3) @[CircuitMath.scala 32:12]
      node _T_575 = bits(_T_563, 2, 2) @[CircuitMath.scala 32:12]
      node _T_577 = bits(_T_563, 1, 1) @[CircuitMath.scala 30:8]
      node _T_578 = mux(_T_575, UInt<2>("h02"), _T_577) @[CircuitMath.scala 32:10]
      node _T_579 = mux(_T_573, UInt<2>("h03"), _T_578) @[CircuitMath.scala 32:10]
      node _T_580 = mux(_T_565, _T_572, _T_579) @[CircuitMath.scala 38:21]
      node _T_581 = cat(_T_565, _T_580) @[Cat.scala 30:58]
      node _T_582 = bits(_T_559, 7, 4) @[CircuitMath.scala 35:17]
      node _T_583 = bits(_T_559, 3, 0) @[CircuitMath.scala 36:17]
      node _T_585 = neq(_T_582, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_586 = bits(_T_582, 3, 3) @[CircuitMath.scala 32:12]
      node _T_588 = bits(_T_582, 2, 2) @[CircuitMath.scala 32:12]
      node _T_590 = bits(_T_582, 1, 1) @[CircuitMath.scala 30:8]
      node _T_591 = mux(_T_588, UInt<2>("h02"), _T_590) @[CircuitMath.scala 32:10]
      node _T_592 = mux(_T_586, UInt<2>("h03"), _T_591) @[CircuitMath.scala 32:10]
      node _T_593 = bits(_T_583, 3, 3) @[CircuitMath.scala 32:12]
      node _T_595 = bits(_T_583, 2, 2) @[CircuitMath.scala 32:12]
      node _T_597 = bits(_T_583, 1, 1) @[CircuitMath.scala 30:8]
      node _T_598 = mux(_T_595, UInt<2>("h02"), _T_597) @[CircuitMath.scala 32:10]
      node _T_599 = mux(_T_593, UInt<2>("h03"), _T_598) @[CircuitMath.scala 32:10]
      node _T_600 = mux(_T_585, _T_592, _T_599) @[CircuitMath.scala 38:21]
      node _T_601 = cat(_T_585, _T_600) @[Cat.scala 30:58]
      node _T_602 = mux(_T_561, _T_581, _T_601) @[CircuitMath.scala 38:21]
      node _T_603 = cat(_T_561, _T_602) @[Cat.scala 30:58]
      node _T_604 = bits(_T_555, 15, 8) @[CircuitMath.scala 35:17]
      node _T_605 = bits(_T_555, 7, 0) @[CircuitMath.scala 36:17]
      node _T_607 = neq(_T_604, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_608 = bits(_T_604, 7, 4) @[CircuitMath.scala 35:17]
      node _T_609 = bits(_T_604, 3, 0) @[CircuitMath.scala 36:17]
      node _T_611 = neq(_T_608, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_612 = bits(_T_608, 3, 3) @[CircuitMath.scala 32:12]
      node _T_614 = bits(_T_608, 2, 2) @[CircuitMath.scala 32:12]
      node _T_616 = bits(_T_608, 1, 1) @[CircuitMath.scala 30:8]
      node _T_617 = mux(_T_614, UInt<2>("h02"), _T_616) @[CircuitMath.scala 32:10]
      node _T_618 = mux(_T_612, UInt<2>("h03"), _T_617) @[CircuitMath.scala 32:10]
      node _T_619 = bits(_T_609, 3, 3) @[CircuitMath.scala 32:12]
      node _T_621 = bits(_T_609, 2, 2) @[CircuitMath.scala 32:12]
      node _T_623 = bits(_T_609, 1, 1) @[CircuitMath.scala 30:8]
      node _T_624 = mux(_T_621, UInt<2>("h02"), _T_623) @[CircuitMath.scala 32:10]
      node _T_625 = mux(_T_619, UInt<2>("h03"), _T_624) @[CircuitMath.scala 32:10]
      node _T_626 = mux(_T_611, _T_618, _T_625) @[CircuitMath.scala 38:21]
      node _T_627 = cat(_T_611, _T_626) @[Cat.scala 30:58]
      node _T_628 = bits(_T_605, 7, 4) @[CircuitMath.scala 35:17]
      node _T_629 = bits(_T_605, 3, 0) @[CircuitMath.scala 36:17]
      node _T_631 = neq(_T_628, UInt<1>("h00")) @[CircuitMath.scala 37:22]
      node _T_632 = bits(_T_628, 3, 3) @[CircuitMath.scala 32:12]
      node _T_634 = bits(_T_628, 2, 2) @[CircuitMath.scala 32:12]
      node _T_636 = bits(_T_628, 1, 1) @[CircuitMath.scala 30:8]
      node _T_637 = mux(_T_634, UInt<2>("h02"), _T_636) @[CircuitMath.scala 32:10]
      node _T_638 = mux(_T_632, UInt<2>("h03"), _T_637) @[CircuitMath.scala 32:10]
      node _T_639 = bits(_T_629, 3, 3) @[CircuitMath.scala 32:12]
      node _T_641 = bits(_T_629, 2, 2) @[CircuitMath.scala 32:12]
      node _T_643 = bits(_T_629, 1, 1) @[CircuitMath.scala 30:8]
      node _T_644 = mux(_T_641, UInt<2>("h02"), _T_643) @[CircuitMath.scala 32:10]
      node _T_645 = mux(_T_639, UInt<2>("h03"), _T_644) @[CircuitMath.scala 32:10]
      node _T_646 = mux(_T_631, _T_638, _T_645) @[CircuitMath.scala 38:21]
      node _T_647 = cat(_T_631, _T_646) @[Cat.scala 30:58]
      node _T_648 = mux(_T_607, _T_627, _T_647) @[CircuitMath.scala 38:21]
      node _T_649 = cat(_T_607, _T_648) @[Cat.scala 30:58]
      node _T_650 = mux(_T_557, _T_603, _T_649) @[CircuitMath.scala 38:21]
      node _T_651 = cat(_T_557, _T_650) @[Cat.scala 30:58]
      node _T_652 = mux(_T_455, _T_553, _T_651) @[CircuitMath.scala 38:21]
      node _T_653 = cat(_T_455, _T_652) @[Cat.scala 30:58]
      node _T_655 = add(UInt<6>("h03f"), _T_450) @[Multiplier.scala 138:31]
      node _T_656 = tail(_T_655, 1) @[Multiplier.scala 138:31]
      node _T_657 = sub(_T_656, _T_653) @[Multiplier.scala 138:44]
      node _T_658 = asUInt(_T_657) @[Multiplier.scala 138:44]
      node _T_659 = tail(_T_658, 1) @[Multiplier.scala 138:44]
      node _T_660 = gt(_T_450, _T_653) @[Multiplier.scala 139:33]
      node _T_662 = eq(count, UInt<1>("h00")) @[Multiplier.scala 140:24]
      node _T_664 = eq(_T_247, UInt<1>("h00")) @[Multiplier.scala 140:33]
      node _T_665 = and(_T_662, _T_664) @[Multiplier.scala 140:30]
      node _T_667 = geq(_T_659, UInt<1>("h01")) @[Multiplier.scala 140:53]
      node _T_668 = or(_T_667, _T_660) @[Multiplier.scala 140:70]
      node _T_669 = and(_T_665, _T_668) @[Multiplier.scala 140:41]
      when _T_669 : @[Multiplier.scala 141:19]
        node _T_671 = mux(_T_660, UInt<6>("h03f"), _T_659) @[Multiplier.scala 142:22]
        node _T_672 = shr(_T_671, 0) @[Multiplier.scala 142:53]
        node _T_673 = shl(_T_672, 0) @[Multiplier.scala 143:25]
        node _T_674 = bits(remainder, 63, 0) @[Multiplier.scala 144:31]
        node _T_675 = dshl(_T_674, _T_673) @[Multiplier.scala 144:39]
        remainder <= _T_675 @[Multiplier.scala 144:19]
        count <= _T_672 @[Multiplier.scala 145:15]
        skip @[Multiplier.scala 141:19]
      node _T_677 = eq(isHi, UInt<1>("h00")) @[Multiplier.scala 148:21]
      node _T_678 = and(_T_247, _T_677) @[Multiplier.scala 148:18]
      when _T_678 : @[Multiplier.scala 148:28]
        neg_out <= UInt<1>("h00") @[Multiplier.scala 148:38]
        skip @[Multiplier.scala 148:28]
      skip @[Multiplier.scala 118:37]
    node _T_680 = and(io.resp.ready, io.resp.valid) @[Decoupled.scala 30:37]
    node _T_681 = or(_T_680, io.kill) @[Multiplier.scala 150:24]
    when _T_681 : @[Multiplier.scala 150:36]
      state <= UInt<3>("h00") @[Multiplier.scala 151:11]
      skip @[Multiplier.scala 150:36]
    node _T_682 = and(io.req.ready, io.req.valid) @[Decoupled.scala 30:37]
    when _T_682 : @[Multiplier.scala 153:24]
      node _T_684 = eq(cmdMul, UInt<1>("h00")) @[Multiplier.scala 154:42]
      node _T_685 = and(rhs_sign, _T_684) @[Multiplier.scala 154:39]
      node _T_686 = or(lhs_sign, _T_685) @[Multiplier.scala 154:27]
      node _T_687 = mux(_T_686, UInt<3>("h01"), UInt<3>("h02")) @[Multiplier.scala 154:17]
      state <= _T_687 @[Multiplier.scala 154:11]
      isMul <= cmdMul @[Multiplier.scala 155:11]
      isHi <= cmdHi @[Multiplier.scala 156:10]
      count <= UInt<1>("h00") @[Multiplier.scala 157:11]
      node _T_690 = eq(cmdMul, UInt<1>("h00")) @[Multiplier.scala 158:16]
      node _T_691 = neq(lhs_sign, rhs_sign) @[Multiplier.scala 158:57]
      node _T_692 = mux(cmdHi, lhs_sign, _T_691) @[Multiplier.scala 158:30]
      node _T_693 = and(_T_690, _T_692) @[Multiplier.scala 158:24]
      neg_out <= _T_693 @[Multiplier.scala 158:13]
      node _T_694 = cat(rhs_sign, rhs_in) @[Cat.scala 30:58]
      divisor <= _T_694 @[Multiplier.scala 159:13]
      remainder <= lhs_in @[Multiplier.scala 160:15]
      req <- io.req.bits @[Multiplier.scala 161:9]
      skip @[Multiplier.scala 153:24]
    io.resp.bits <- req @[Multiplier.scala 164:16]
    node _T_697 = eq(req.dw, UInt<1>("h00")) @[Multiplier.scala 67:62]
    node _T_698 = and(UInt<1>("h01"), _T_697) @[Multiplier.scala 67:52]
    node _T_699 = bits(remainder, 31, 31) @[Multiplier.scala 165:67]
    node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 71:15]
    node _T_703 = mux(_T_700, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12]
    node _T_704 = bits(remainder, 31, 0) @[Multiplier.scala 165:86]
    node _T_705 = cat(_T_703, _T_704) @[Cat.scala 30:58]
    node _T_706 = bits(remainder, 63, 0) @[Multiplier.scala 165:107]
    node _T_707 = mux(_T_698, _T_705, _T_706) @[Multiplier.scala 165:27]
    io.resp.bits.data <= _T_707 @[Multiplier.scala 165:21]
    node _T_708 = eq(state, UInt<3>("h05")) @[Multiplier.scala 166:26]
    io.resp.valid <= _T_708 @[Multiplier.scala 166:17]
    node _T_709 = eq(state, UInt<3>("h00")) @[Multiplier.scala 167:25]
    io.req.ready <= _T_709 @[Multiplier.scala 167:16]
    
  module RVCExpander : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip in : UInt<32>, out : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>}
    
    io is invalid
    io is invalid
    node _T_12 = bits(io.in, 1, 0) @[RVC.scala 162:20]
    node _T_14 = neq(_T_12, UInt<2>("h03")) @[RVC.scala 162:26]
    io.rvc <= _T_14 @[RVC.scala 162:12]
    node _T_15 = bits(io.in, 12, 5) @[RVC.scala 53:22]
    node _T_17 = neq(_T_15, UInt<1>("h00")) @[RVC.scala 53:29]
    node _T_20 = mux(_T_17, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 53:20]
    node _T_21 = bits(io.in, 10, 7) @[RVC.scala 34:26]
    node _T_22 = bits(io.in, 12, 11) @[RVC.scala 34:35]
    node _T_23 = bits(io.in, 5, 5) @[RVC.scala 34:45]
    node _T_24 = bits(io.in, 6, 6) @[RVC.scala 34:51]
    node _T_26 = cat(_T_24, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_27 = cat(_T_21, _T_22) @[Cat.scala 30:58]
    node _T_28 = cat(_T_27, _T_23) @[Cat.scala 30:58]
    node _T_29 = cat(_T_28, _T_26) @[Cat.scala 30:58]
    node _T_33 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_34 = cat(UInt<2>("h01"), _T_33) @[Cat.scala 30:58]
    node _T_35 = cat(_T_34, _T_20) @[Cat.scala 30:58]
    node _T_36 = cat(_T_29, UInt<5>("h02")) @[Cat.scala 30:58]
    node _T_37 = cat(_T_36, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_38 = cat(_T_37, _T_35) @[Cat.scala 30:58]
    node _T_40 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_41 = cat(UInt<2>("h01"), _T_40) @[Cat.scala 30:58]
    node _T_44 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_45 = cat(UInt<2>("h01"), _T_44) @[Cat.scala 30:58]
    node _T_46 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_53 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_53 is invalid @[RVC.scala 21:19]
    _T_53.bits <= _T_38 @[RVC.scala 22:14]
    _T_53.rd <= _T_41 @[RVC.scala 23:12]
    _T_53.rs1 <= UInt<5>("h02") @[RVC.scala 24:13]
    _T_53.rs2 <= _T_45 @[RVC.scala 25:13]
    _T_53.rs3 <= _T_46 @[RVC.scala 26:13]
    node _T_59 = bits(io.in, 6, 5) @[RVC.scala 36:20]
    node _T_60 = bits(io.in, 12, 10) @[RVC.scala 36:28]
    node _T_62 = cat(_T_59, _T_60) @[Cat.scala 30:58]
    node _T_63 = cat(_T_62, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_65 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_66 = cat(UInt<2>("h01"), _T_65) @[Cat.scala 30:58]
    node _T_69 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_70 = cat(UInt<2>("h01"), _T_69) @[Cat.scala 30:58]
    node _T_72 = cat(_T_70, UInt<7>("h07")) @[Cat.scala 30:58]
    node _T_73 = cat(_T_63, _T_66) @[Cat.scala 30:58]
    node _T_74 = cat(_T_73, UInt<3>("h03")) @[Cat.scala 30:58]
    node _T_75 = cat(_T_74, _T_72) @[Cat.scala 30:58]
    node _T_77 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_78 = cat(UInt<2>("h01"), _T_77) @[Cat.scala 30:58]
    node _T_80 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_81 = cat(UInt<2>("h01"), _T_80) @[Cat.scala 30:58]
    node _T_83 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_84 = cat(UInt<2>("h01"), _T_83) @[Cat.scala 30:58]
    node _T_85 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_92 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_92 is invalid @[RVC.scala 21:19]
    _T_92.bits <= _T_75 @[RVC.scala 22:14]
    _T_92.rd <= _T_78 @[RVC.scala 23:12]
    _T_92.rs1 <= _T_81 @[RVC.scala 24:13]
    _T_92.rs2 <= _T_84 @[RVC.scala 25:13]
    _T_92.rs3 <= _T_85 @[RVC.scala 26:13]
    node _T_98 = bits(io.in, 5, 5) @[RVC.scala 35:20]
    node _T_99 = bits(io.in, 12, 10) @[RVC.scala 35:26]
    node _T_100 = bits(io.in, 6, 6) @[RVC.scala 35:36]
    node _T_102 = cat(_T_100, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_103 = cat(_T_98, _T_99) @[Cat.scala 30:58]
    node _T_104 = cat(_T_103, _T_102) @[Cat.scala 30:58]
    node _T_106 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_107 = cat(UInt<2>("h01"), _T_106) @[Cat.scala 30:58]
    node _T_110 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_111 = cat(UInt<2>("h01"), _T_110) @[Cat.scala 30:58]
    node _T_113 = cat(_T_111, UInt<7>("h03")) @[Cat.scala 30:58]
    node _T_114 = cat(_T_104, _T_107) @[Cat.scala 30:58]
    node _T_115 = cat(_T_114, UInt<3>("h02")) @[Cat.scala 30:58]
    node _T_116 = cat(_T_115, _T_113) @[Cat.scala 30:58]
    node _T_118 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_119 = cat(UInt<2>("h01"), _T_118) @[Cat.scala 30:58]
    node _T_121 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_122 = cat(UInt<2>("h01"), _T_121) @[Cat.scala 30:58]
    node _T_124 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_125 = cat(UInt<2>("h01"), _T_124) @[Cat.scala 30:58]
    node _T_126 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_133 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_133 is invalid @[RVC.scala 21:19]
    _T_133.bits <= _T_116 @[RVC.scala 22:14]
    _T_133.rd <= _T_119 @[RVC.scala 23:12]
    _T_133.rs1 <= _T_122 @[RVC.scala 24:13]
    _T_133.rs2 <= _T_125 @[RVC.scala 25:13]
    _T_133.rs3 <= _T_126 @[RVC.scala 26:13]
    node _T_139 = bits(io.in, 6, 5) @[RVC.scala 36:20]
    node _T_140 = bits(io.in, 12, 10) @[RVC.scala 36:28]
    node _T_142 = cat(_T_139, _T_140) @[Cat.scala 30:58]
    node _T_143 = cat(_T_142, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_145 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_146 = cat(UInt<2>("h01"), _T_145) @[Cat.scala 30:58]
    node _T_149 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_150 = cat(UInt<2>("h01"), _T_149) @[Cat.scala 30:58]
    node _T_152 = cat(_T_150, UInt<7>("h03")) @[Cat.scala 30:58]
    node _T_153 = cat(_T_143, _T_146) @[Cat.scala 30:58]
    node _T_154 = cat(_T_153, UInt<3>("h03")) @[Cat.scala 30:58]
    node _T_155 = cat(_T_154, _T_152) @[Cat.scala 30:58]
    node _T_157 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_158 = cat(UInt<2>("h01"), _T_157) @[Cat.scala 30:58]
    node _T_160 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_161 = cat(UInt<2>("h01"), _T_160) @[Cat.scala 30:58]
    node _T_163 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_164 = cat(UInt<2>("h01"), _T_163) @[Cat.scala 30:58]
    node _T_165 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_172 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_172 is invalid @[RVC.scala 21:19]
    _T_172.bits <= _T_155 @[RVC.scala 22:14]
    _T_172.rd <= _T_158 @[RVC.scala 23:12]
    _T_172.rs1 <= _T_161 @[RVC.scala 24:13]
    _T_172.rs2 <= _T_164 @[RVC.scala 25:13]
    _T_172.rs3 <= _T_165 @[RVC.scala 26:13]
    node _T_178 = bits(io.in, 5, 5) @[RVC.scala 35:20]
    node _T_179 = bits(io.in, 12, 10) @[RVC.scala 35:26]
    node _T_180 = bits(io.in, 6, 6) @[RVC.scala 35:36]
    node _T_182 = cat(_T_180, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_183 = cat(_T_178, _T_179) @[Cat.scala 30:58]
    node _T_184 = cat(_T_183, _T_182) @[Cat.scala 30:58]
    node _T_185 = shr(_T_184, 5) @[RVC.scala 63:32]
    node _T_187 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_188 = cat(UInt<2>("h01"), _T_187) @[Cat.scala 30:58]
    node _T_190 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_191 = cat(UInt<2>("h01"), _T_190) @[Cat.scala 30:58]
    node _T_193 = bits(io.in, 5, 5) @[RVC.scala 35:20]
    node _T_194 = bits(io.in, 12, 10) @[RVC.scala 35:26]
    node _T_195 = bits(io.in, 6, 6) @[RVC.scala 35:36]
    node _T_197 = cat(_T_195, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_198 = cat(_T_193, _T_194) @[Cat.scala 30:58]
    node _T_199 = cat(_T_198, _T_197) @[Cat.scala 30:58]
    node _T_200 = bits(_T_199, 4, 0) @[RVC.scala 63:66]
    node _T_202 = cat(UInt<3>("h02"), _T_200) @[Cat.scala 30:58]
    node _T_203 = cat(_T_202, UInt<7>("h02f")) @[Cat.scala 30:58]
    node _T_204 = cat(_T_185, _T_188) @[Cat.scala 30:58]
    node _T_205 = cat(_T_204, _T_191) @[Cat.scala 30:58]
    node _T_206 = cat(_T_205, _T_203) @[Cat.scala 30:58]
    node _T_208 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_209 = cat(UInt<2>("h01"), _T_208) @[Cat.scala 30:58]
    node _T_211 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_212 = cat(UInt<2>("h01"), _T_211) @[Cat.scala 30:58]
    node _T_214 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_215 = cat(UInt<2>("h01"), _T_214) @[Cat.scala 30:58]
    node _T_216 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_223 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_223 is invalid @[RVC.scala 21:19]
    _T_223.bits <= _T_206 @[RVC.scala 22:14]
    _T_223.rd <= _T_209 @[RVC.scala 23:12]
    _T_223.rs1 <= _T_212 @[RVC.scala 24:13]
    _T_223.rs2 <= _T_215 @[RVC.scala 25:13]
    _T_223.rs3 <= _T_216 @[RVC.scala 26:13]
    node _T_229 = bits(io.in, 6, 5) @[RVC.scala 36:20]
    node _T_230 = bits(io.in, 12, 10) @[RVC.scala 36:28]
    node _T_232 = cat(_T_229, _T_230) @[Cat.scala 30:58]
    node _T_233 = cat(_T_232, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_234 = shr(_T_233, 5) @[RVC.scala 66:30]
    node _T_236 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_237 = cat(UInt<2>("h01"), _T_236) @[Cat.scala 30:58]
    node _T_239 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_240 = cat(UInt<2>("h01"), _T_239) @[Cat.scala 30:58]
    node _T_242 = bits(io.in, 6, 5) @[RVC.scala 36:20]
    node _T_243 = bits(io.in, 12, 10) @[RVC.scala 36:28]
    node _T_245 = cat(_T_242, _T_243) @[Cat.scala 30:58]
    node _T_246 = cat(_T_245, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_247 = bits(_T_246, 4, 0) @[RVC.scala 66:64]
    node _T_249 = cat(UInt<3>("h03"), _T_247) @[Cat.scala 30:58]
    node _T_250 = cat(_T_249, UInt<7>("h027")) @[Cat.scala 30:58]
    node _T_251 = cat(_T_234, _T_237) @[Cat.scala 30:58]
    node _T_252 = cat(_T_251, _T_240) @[Cat.scala 30:58]
    node _T_253 = cat(_T_252, _T_250) @[Cat.scala 30:58]
    node _T_255 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_256 = cat(UInt<2>("h01"), _T_255) @[Cat.scala 30:58]
    node _T_258 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_259 = cat(UInt<2>("h01"), _T_258) @[Cat.scala 30:58]
    node _T_261 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_262 = cat(UInt<2>("h01"), _T_261) @[Cat.scala 30:58]
    node _T_263 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_270 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_270 is invalid @[RVC.scala 21:19]
    _T_270.bits <= _T_253 @[RVC.scala 22:14]
    _T_270.rd <= _T_256 @[RVC.scala 23:12]
    _T_270.rs1 <= _T_259 @[RVC.scala 24:13]
    _T_270.rs2 <= _T_262 @[RVC.scala 25:13]
    _T_270.rs3 <= _T_263 @[RVC.scala 26:13]
    node _T_276 = bits(io.in, 5, 5) @[RVC.scala 35:20]
    node _T_277 = bits(io.in, 12, 10) @[RVC.scala 35:26]
    node _T_278 = bits(io.in, 6, 6) @[RVC.scala 35:36]
    node _T_280 = cat(_T_278, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_281 = cat(_T_276, _T_277) @[Cat.scala 30:58]
    node _T_282 = cat(_T_281, _T_280) @[Cat.scala 30:58]
    node _T_283 = shr(_T_282, 5) @[RVC.scala 65:29]
    node _T_285 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_286 = cat(UInt<2>("h01"), _T_285) @[Cat.scala 30:58]
    node _T_288 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_289 = cat(UInt<2>("h01"), _T_288) @[Cat.scala 30:58]
    node _T_291 = bits(io.in, 5, 5) @[RVC.scala 35:20]
    node _T_292 = bits(io.in, 12, 10) @[RVC.scala 35:26]
    node _T_293 = bits(io.in, 6, 6) @[RVC.scala 35:36]
    node _T_295 = cat(_T_293, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_296 = cat(_T_291, _T_292) @[Cat.scala 30:58]
    node _T_297 = cat(_T_296, _T_295) @[Cat.scala 30:58]
    node _T_298 = bits(_T_297, 4, 0) @[RVC.scala 65:63]
    node _T_300 = cat(UInt<3>("h02"), _T_298) @[Cat.scala 30:58]
    node _T_301 = cat(_T_300, UInt<7>("h023")) @[Cat.scala 30:58]
    node _T_302 = cat(_T_283, _T_286) @[Cat.scala 30:58]
    node _T_303 = cat(_T_302, _T_289) @[Cat.scala 30:58]
    node _T_304 = cat(_T_303, _T_301) @[Cat.scala 30:58]
    node _T_306 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_307 = cat(UInt<2>("h01"), _T_306) @[Cat.scala 30:58]
    node _T_309 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_310 = cat(UInt<2>("h01"), _T_309) @[Cat.scala 30:58]
    node _T_312 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_313 = cat(UInt<2>("h01"), _T_312) @[Cat.scala 30:58]
    node _T_314 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_321 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_321 is invalid @[RVC.scala 21:19]
    _T_321.bits <= _T_304 @[RVC.scala 22:14]
    _T_321.rd <= _T_307 @[RVC.scala 23:12]
    _T_321.rs1 <= _T_310 @[RVC.scala 24:13]
    _T_321.rs2 <= _T_313 @[RVC.scala 25:13]
    _T_321.rs3 <= _T_314 @[RVC.scala 26:13]
    node _T_327 = bits(io.in, 6, 5) @[RVC.scala 36:20]
    node _T_328 = bits(io.in, 12, 10) @[RVC.scala 36:28]
    node _T_330 = cat(_T_327, _T_328) @[Cat.scala 30:58]
    node _T_331 = cat(_T_330, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_332 = shr(_T_331, 5) @[RVC.scala 64:29]
    node _T_334 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_335 = cat(UInt<2>("h01"), _T_334) @[Cat.scala 30:58]
    node _T_337 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_338 = cat(UInt<2>("h01"), _T_337) @[Cat.scala 30:58]
    node _T_340 = bits(io.in, 6, 5) @[RVC.scala 36:20]
    node _T_341 = bits(io.in, 12, 10) @[RVC.scala 36:28]
    node _T_343 = cat(_T_340, _T_341) @[Cat.scala 30:58]
    node _T_344 = cat(_T_343, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_345 = bits(_T_344, 4, 0) @[RVC.scala 64:63]
    node _T_347 = cat(UInt<3>("h03"), _T_345) @[Cat.scala 30:58]
    node _T_348 = cat(_T_347, UInt<7>("h023")) @[Cat.scala 30:58]
    node _T_349 = cat(_T_332, _T_335) @[Cat.scala 30:58]
    node _T_350 = cat(_T_349, _T_338) @[Cat.scala 30:58]
    node _T_351 = cat(_T_350, _T_348) @[Cat.scala 30:58]
    node _T_353 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_354 = cat(UInt<2>("h01"), _T_353) @[Cat.scala 30:58]
    node _T_356 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_357 = cat(UInt<2>("h01"), _T_356) @[Cat.scala 30:58]
    node _T_359 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_360 = cat(UInt<2>("h01"), _T_359) @[Cat.scala 30:58]
    node _T_361 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_368 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_368 is invalid @[RVC.scala 21:19]
    _T_368.bits <= _T_351 @[RVC.scala 22:14]
    _T_368.rd <= _T_354 @[RVC.scala 23:12]
    _T_368.rs1 <= _T_357 @[RVC.scala 24:13]
    _T_368.rs2 <= _T_360 @[RVC.scala 25:13]
    _T_368.rs3 <= _T_361 @[RVC.scala 26:13]
    node _T_374 = bits(io.in, 12, 12) @[RVC.scala 43:30]
    node _T_375 = bits(_T_374, 0, 0) @[Bitwise.scala 71:15]
    node _T_378 = mux(_T_375, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12]
    node _T_379 = bits(io.in, 6, 2) @[RVC.scala 43:38]
    node _T_380 = cat(_T_378, _T_379) @[Cat.scala 30:58]
    node _T_381 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_383 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_385 = cat(_T_383, UInt<7>("h013")) @[Cat.scala 30:58]
    node _T_386 = cat(_T_380, _T_381) @[Cat.scala 30:58]
    node _T_387 = cat(_T_386, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_388 = cat(_T_387, _T_385) @[Cat.scala 30:58]
    node _T_389 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_390 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_392 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_393 = cat(UInt<2>("h01"), _T_392) @[Cat.scala 30:58]
    node _T_394 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_401 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_401 is invalid @[RVC.scala 21:19]
    _T_401.bits <= _T_388 @[RVC.scala 22:14]
    _T_401.rd <= _T_389 @[RVC.scala 23:12]
    _T_401.rs1 <= _T_390 @[RVC.scala 24:13]
    _T_401.rs2 <= _T_393 @[RVC.scala 25:13]
    _T_401.rs3 <= _T_394 @[RVC.scala 26:13]
    node _T_407 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_409 = neq(_T_407, UInt<1>("h00")) @[RVC.scala 77:24]
    node _T_412 = mux(_T_409, UInt<7>("h01b"), UInt<7>("h01f")) @[RVC.scala 77:20]
    node _T_413 = bits(io.in, 12, 12) @[RVC.scala 43:30]
    node _T_414 = bits(_T_413, 0, 0) @[Bitwise.scala 71:15]
    node _T_417 = mux(_T_414, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12]
    node _T_418 = bits(io.in, 6, 2) @[RVC.scala 43:38]
    node _T_419 = cat(_T_417, _T_418) @[Cat.scala 30:58]
    node _T_420 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_422 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_423 = cat(_T_422, _T_412) @[Cat.scala 30:58]
    node _T_424 = cat(_T_419, _T_420) @[Cat.scala 30:58]
    node _T_425 = cat(_T_424, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_426 = cat(_T_425, _T_423) @[Cat.scala 30:58]
    node _T_427 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_428 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_430 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_431 = cat(UInt<2>("h01"), _T_430) @[Cat.scala 30:58]
    node _T_432 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_439 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_439 is invalid @[RVC.scala 21:19]
    _T_439.bits <= _T_426 @[RVC.scala 22:14]
    _T_439.rd <= _T_427 @[RVC.scala 23:12]
    _T_439.rs1 <= _T_428 @[RVC.scala 24:13]
    _T_439.rs2 <= _T_431 @[RVC.scala 25:13]
    _T_439.rs3 <= _T_432 @[RVC.scala 26:13]
    node _T_445 = bits(io.in, 12, 12) @[RVC.scala 43:30]
    node _T_446 = bits(_T_445, 0, 0) @[Bitwise.scala 71:15]
    node _T_449 = mux(_T_446, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12]
    node _T_450 = bits(io.in, 6, 2) @[RVC.scala 43:38]
    node _T_451 = cat(_T_449, _T_450) @[Cat.scala 30:58]
    node _T_454 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_456 = cat(_T_454, UInt<7>("h013")) @[Cat.scala 30:58]
    node _T_457 = cat(_T_451, UInt<5>("h00")) @[Cat.scala 30:58]
    node _T_458 = cat(_T_457, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_459 = cat(_T_458, _T_456) @[Cat.scala 30:58]
    node _T_460 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_463 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_464 = cat(UInt<2>("h01"), _T_463) @[Cat.scala 30:58]
    node _T_465 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_472 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_472 is invalid @[RVC.scala 21:19]
    _T_472.bits <= _T_459 @[RVC.scala 22:14]
    _T_472.rd <= _T_460 @[RVC.scala 23:12]
    _T_472.rs1 <= UInt<5>("h00") @[RVC.scala 24:13]
    _T_472.rs2 <= _T_464 @[RVC.scala 25:13]
    _T_472.rs3 <= _T_465 @[RVC.scala 26:13]
    node _T_478 = bits(io.in, 12, 12) @[RVC.scala 43:30]
    node _T_479 = bits(_T_478, 0, 0) @[Bitwise.scala 71:15]
    node _T_482 = mux(_T_479, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12]
    node _T_483 = bits(io.in, 6, 2) @[RVC.scala 43:38]
    node _T_484 = cat(_T_482, _T_483) @[Cat.scala 30:58]
    node _T_486 = neq(_T_484, UInt<1>("h00")) @[RVC.scala 90:29]
    node _T_489 = mux(_T_486, UInt<7>("h037"), UInt<7>("h03f")) @[RVC.scala 90:20]
    node _T_490 = bits(io.in, 12, 12) @[RVC.scala 41:30]
    node _T_491 = bits(_T_490, 0, 0) @[Bitwise.scala 71:15]
    node _T_494 = mux(_T_491, UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 71:12]
    node _T_495 = bits(io.in, 6, 2) @[RVC.scala 41:38]
    node _T_497 = cat(_T_494, _T_495) @[Cat.scala 30:58]
    node _T_498 = cat(_T_497, UInt<12>("h00")) @[Cat.scala 30:58]
    node _T_499 = bits(_T_498, 31, 12) @[RVC.scala 91:31]
    node _T_500 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_501 = cat(_T_499, _T_500) @[Cat.scala 30:58]
    node _T_502 = cat(_T_501, _T_489) @[Cat.scala 30:58]
    node _T_503 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_504 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_506 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_507 = cat(UInt<2>("h01"), _T_506) @[Cat.scala 30:58]
    node _T_508 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_515 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_515 is invalid @[RVC.scala 21:19]
    _T_515.bits <= _T_502 @[RVC.scala 22:14]
    _T_515.rd <= _T_503 @[RVC.scala 23:12]
    _T_515.rs1 <= _T_504 @[RVC.scala 24:13]
    _T_515.rs2 <= _T_507 @[RVC.scala 25:13]
    _T_515.rs3 <= _T_508 @[RVC.scala 26:13]
    node _T_521 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_523 = eq(_T_521, UInt<5>("h00")) @[RVC.scala 92:14]
    node _T_524 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_526 = eq(_T_524, UInt<5>("h02")) @[RVC.scala 92:27]
    node _T_527 = or(_T_523, _T_526) @[RVC.scala 92:21]
    node _T_528 = bits(io.in, 12, 12) @[RVC.scala 43:30]
    node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 71:15]
    node _T_532 = mux(_T_529, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12]
    node _T_533 = bits(io.in, 6, 2) @[RVC.scala 43:38]
    node _T_534 = cat(_T_532, _T_533) @[Cat.scala 30:58]
    node _T_536 = neq(_T_534, UInt<1>("h00")) @[RVC.scala 86:29]
    node _T_539 = mux(_T_536, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 86:20]
    node _T_540 = bits(io.in, 12, 12) @[RVC.scala 42:34]
    node _T_541 = bits(_T_540, 0, 0) @[Bitwise.scala 71:15]
    node _T_544 = mux(_T_541, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12]
    node _T_545 = bits(io.in, 4, 3) @[RVC.scala 42:42]
    node _T_546 = bits(io.in, 5, 5) @[RVC.scala 42:50]
    node _T_547 = bits(io.in, 2, 2) @[RVC.scala 42:56]
    node _T_548 = bits(io.in, 6, 6) @[RVC.scala 42:62]
    node _T_550 = cat(_T_547, _T_548) @[Cat.scala 30:58]
    node _T_551 = cat(_T_550, UInt<4>("h00")) @[Cat.scala 30:58]
    node _T_552 = cat(_T_544, _T_545) @[Cat.scala 30:58]
    node _T_553 = cat(_T_552, _T_546) @[Cat.scala 30:58]
    node _T_554 = cat(_T_553, _T_551) @[Cat.scala 30:58]
    node _T_555 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_557 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_558 = cat(_T_557, _T_539) @[Cat.scala 30:58]
    node _T_559 = cat(_T_554, _T_555) @[Cat.scala 30:58]
    node _T_560 = cat(_T_559, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_561 = cat(_T_560, _T_558) @[Cat.scala 30:58]
    node _T_562 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_563 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_565 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_566 = cat(UInt<2>("h01"), _T_565) @[Cat.scala 30:58]
    node _T_567 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_574 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_574 is invalid @[RVC.scala 21:19]
    _T_574.bits <= _T_561 @[RVC.scala 22:14]
    _T_574.rd <= _T_562 @[RVC.scala 23:12]
    _T_574.rs1 <= _T_563 @[RVC.scala 24:13]
    _T_574.rs2 <= _T_566 @[RVC.scala 25:13]
    _T_574.rs3 <= _T_567 @[RVC.scala 26:13]
    node _T_580 = mux(_T_527, _T_574, _T_515) @[RVC.scala 92:10]
    node _T_586 = bits(io.in, 12, 12) @[RVC.scala 46:20]
    node _T_587 = bits(io.in, 6, 2) @[RVC.scala 46:27]
    node _T_588 = cat(_T_586, _T_587) @[Cat.scala 30:58]
    node _T_590 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_591 = cat(UInt<2>("h01"), _T_590) @[Cat.scala 30:58]
    node _T_594 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_595 = cat(UInt<2>("h01"), _T_594) @[Cat.scala 30:58]
    node _T_597 = cat(_T_595, UInt<7>("h013")) @[Cat.scala 30:58]
    node _T_598 = cat(_T_588, _T_591) @[Cat.scala 30:58]
    node _T_599 = cat(_T_598, UInt<3>("h05")) @[Cat.scala 30:58]
    node _T_600 = cat(_T_599, _T_597) @[Cat.scala 30:58]
    node _T_601 = bits(io.in, 12, 12) @[RVC.scala 46:20]
    node _T_602 = bits(io.in, 6, 2) @[RVC.scala 46:27]
    node _T_603 = cat(_T_601, _T_602) @[Cat.scala 30:58]
    node _T_605 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_606 = cat(UInt<2>("h01"), _T_605) @[Cat.scala 30:58]
    node _T_609 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_610 = cat(UInt<2>("h01"), _T_609) @[Cat.scala 30:58]
    node _T_612 = cat(_T_610, UInt<7>("h013")) @[Cat.scala 30:58]
    node _T_613 = cat(_T_603, _T_606) @[Cat.scala 30:58]
    node _T_614 = cat(_T_613, UInt<3>("h05")) @[Cat.scala 30:58]
    node _T_615 = cat(_T_614, _T_612) @[Cat.scala 30:58]
    node _T_617 = or(_T_615, UInt<31>("h040000000")) @[RVC.scala 99:23]
    node _T_618 = bits(io.in, 12, 12) @[RVC.scala 43:30]
    node _T_619 = bits(_T_618, 0, 0) @[Bitwise.scala 71:15]
    node _T_622 = mux(_T_619, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12]
    node _T_623 = bits(io.in, 6, 2) @[RVC.scala 43:38]
    node _T_624 = cat(_T_622, _T_623) @[Cat.scala 30:58]
    node _T_626 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_627 = cat(UInt<2>("h01"), _T_626) @[Cat.scala 30:58]
    node _T_630 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_631 = cat(UInt<2>("h01"), _T_630) @[Cat.scala 30:58]
    node _T_633 = cat(_T_631, UInt<7>("h013")) @[Cat.scala 30:58]
    node _T_634 = cat(_T_624, _T_627) @[Cat.scala 30:58]
    node _T_635 = cat(_T_634, UInt<3>("h07")) @[Cat.scala 30:58]
    node _T_636 = cat(_T_635, _T_633) @[Cat.scala 30:58]
    node _T_645 = bits(io.in, 12, 12) @[RVC.scala 102:70]
    node _T_646 = bits(io.in, 6, 5) @[RVC.scala 102:77]
    node _T_647 = cat(_T_645, _T_646) @[Cat.scala 30:58]
    node _T_649 = and(_T_647, UInt<2>("h03")) @[Package.scala 18:26]
    node _T_651 = geq(_T_647, UInt<3>("h04")) @[Package.scala 19:17]
    node _T_653 = and(_T_649, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_655 = geq(_T_649, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_657 = and(_T_653, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_659 = geq(_T_653, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_660 = mux(_T_659, UInt<2>("h03"), UInt<2>("h02")) @[Package.scala 19:12]
    node _T_662 = and(_T_653, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_664 = geq(_T_653, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_665 = mux(_T_664, UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 19:12]
    node _T_666 = mux(_T_655, _T_660, _T_665) @[Package.scala 19:12]
    node _T_668 = and(_T_649, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_670 = geq(_T_649, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_672 = and(_T_668, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_674 = geq(_T_668, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_675 = mux(_T_674, UInt<3>("h07"), UInt<3>("h06")) @[Package.scala 19:12]
    node _T_677 = and(_T_668, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_679 = geq(_T_668, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_680 = mux(_T_679, UInt<3>("h04"), UInt<1>("h00")) @[Package.scala 19:12]
    node _T_681 = mux(_T_670, _T_675, _T_680) @[Package.scala 19:12]
    node _T_682 = mux(_T_651, _T_666, _T_681) @[Package.scala 19:12]
    node _T_683 = bits(io.in, 6, 5) @[RVC.scala 103:24]
    node _T_685 = eq(_T_683, UInt<1>("h00")) @[RVC.scala 103:30]
    node _T_688 = mux(_T_685, UInt<31>("h040000000"), UInt<1>("h00")) @[RVC.scala 103:22]
    node _T_689 = bits(io.in, 12, 12) @[RVC.scala 104:24]
    node _T_692 = mux(_T_689, UInt<7>("h03b"), UInt<7>("h033")) @[RVC.scala 104:22]
    node _T_694 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_695 = cat(UInt<2>("h01"), _T_694) @[Cat.scala 30:58]
    node _T_697 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_698 = cat(UInt<2>("h01"), _T_697) @[Cat.scala 30:58]
    node _T_700 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_701 = cat(UInt<2>("h01"), _T_700) @[Cat.scala 30:58]
    node _T_702 = cat(_T_701, _T_692) @[Cat.scala 30:58]
    node _T_703 = cat(_T_695, _T_698) @[Cat.scala 30:58]
    node _T_704 = cat(_T_703, _T_682) @[Cat.scala 30:58]
    node _T_705 = cat(_T_704, _T_702) @[Cat.scala 30:58]
    node _T_706 = or(_T_705, _T_688) @[RVC.scala 105:43]
    node _T_707 = bits(io.in, 11, 10) @[RVC.scala 107:42]
    node _T_709 = and(_T_707, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_711 = geq(_T_707, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_713 = and(_T_709, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_715 = geq(_T_709, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_716 = mux(_T_715, _T_706, _T_636) @[Package.scala 19:12]
    node _T_718 = and(_T_709, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_720 = geq(_T_709, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_721 = mux(_T_720, _T_617, _T_600) @[Package.scala 19:12]
    node _T_722 = mux(_T_711, _T_716, _T_721) @[Package.scala 19:12]
    node _T_724 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_725 = cat(UInt<2>("h01"), _T_724) @[Cat.scala 30:58]
    node _T_727 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_728 = cat(UInt<2>("h01"), _T_727) @[Cat.scala 30:58]
    node _T_730 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_731 = cat(UInt<2>("h01"), _T_730) @[Cat.scala 30:58]
    node _T_732 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_739 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_739 is invalid @[RVC.scala 21:19]
    _T_739.bits <= _T_722 @[RVC.scala 22:14]
    _T_739.rd <= _T_725 @[RVC.scala 23:12]
    _T_739.rs1 <= _T_728 @[RVC.scala 24:13]
    _T_739.rs2 <= _T_731 @[RVC.scala 25:13]
    _T_739.rs3 <= _T_732 @[RVC.scala 26:13]
    node _T_745 = bits(io.in, 12, 12) @[RVC.scala 44:28]
    node _T_746 = bits(_T_745, 0, 0) @[Bitwise.scala 71:15]
    node _T_749 = mux(_T_746, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12]
    node _T_750 = bits(io.in, 8, 8) @[RVC.scala 44:36]
    node _T_751 = bits(io.in, 10, 9) @[RVC.scala 44:42]
    node _T_752 = bits(io.in, 6, 6) @[RVC.scala 44:51]
    node _T_753 = bits(io.in, 7, 7) @[RVC.scala 44:57]
    node _T_754 = bits(io.in, 2, 2) @[RVC.scala 44:63]
    node _T_755 = bits(io.in, 11, 11) @[RVC.scala 44:69]
    node _T_756 = bits(io.in, 5, 3) @[RVC.scala 44:76]
    node _T_758 = cat(_T_756, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_759 = cat(_T_754, _T_755) @[Cat.scala 30:58]
    node _T_760 = cat(_T_759, _T_758) @[Cat.scala 30:58]
    node _T_761 = cat(_T_752, _T_753) @[Cat.scala 30:58]
    node _T_762 = cat(_T_749, _T_750) @[Cat.scala 30:58]
    node _T_763 = cat(_T_762, _T_751) @[Cat.scala 30:58]
    node _T_764 = cat(_T_763, _T_761) @[Cat.scala 30:58]
    node _T_765 = cat(_T_764, _T_760) @[Cat.scala 30:58]
    node _T_766 = bits(_T_765, 20, 20) @[RVC.scala 94:26]
    node _T_767 = bits(io.in, 12, 12) @[RVC.scala 44:28]
    node _T_768 = bits(_T_767, 0, 0) @[Bitwise.scala 71:15]
    node _T_771 = mux(_T_768, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12]
    node _T_772 = bits(io.in, 8, 8) @[RVC.scala 44:36]
    node _T_773 = bits(io.in, 10, 9) @[RVC.scala 44:42]
    node _T_774 = bits(io.in, 6, 6) @[RVC.scala 44:51]
    node _T_775 = bits(io.in, 7, 7) @[RVC.scala 44:57]
    node _T_776 = bits(io.in, 2, 2) @[RVC.scala 44:63]
    node _T_777 = bits(io.in, 11, 11) @[RVC.scala 44:69]
    node _T_778 = bits(io.in, 5, 3) @[RVC.scala 44:76]
    node _T_780 = cat(_T_778, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_781 = cat(_T_776, _T_777) @[Cat.scala 30:58]
    node _T_782 = cat(_T_781, _T_780) @[Cat.scala 30:58]
    node _T_783 = cat(_T_774, _T_775) @[Cat.scala 30:58]
    node _T_784 = cat(_T_771, _T_772) @[Cat.scala 30:58]
    node _T_785 = cat(_T_784, _T_773) @[Cat.scala 30:58]
    node _T_786 = cat(_T_785, _T_783) @[Cat.scala 30:58]
    node _T_787 = cat(_T_786, _T_782) @[Cat.scala 30:58]
    node _T_788 = bits(_T_787, 10, 1) @[RVC.scala 94:36]
    node _T_789 = bits(io.in, 12, 12) @[RVC.scala 44:28]
    node _T_790 = bits(_T_789, 0, 0) @[Bitwise.scala 71:15]
    node _T_793 = mux(_T_790, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12]
    node _T_794 = bits(io.in, 8, 8) @[RVC.scala 44:36]
    node _T_795 = bits(io.in, 10, 9) @[RVC.scala 44:42]
    node _T_796 = bits(io.in, 6, 6) @[RVC.scala 44:51]
    node _T_797 = bits(io.in, 7, 7) @[RVC.scala 44:57]
    node _T_798 = bits(io.in, 2, 2) @[RVC.scala 44:63]
    node _T_799 = bits(io.in, 11, 11) @[RVC.scala 44:69]
    node _T_800 = bits(io.in, 5, 3) @[RVC.scala 44:76]
    node _T_802 = cat(_T_800, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_803 = cat(_T_798, _T_799) @[Cat.scala 30:58]
    node _T_804 = cat(_T_803, _T_802) @[Cat.scala 30:58]
    node _T_805 = cat(_T_796, _T_797) @[Cat.scala 30:58]
    node _T_806 = cat(_T_793, _T_794) @[Cat.scala 30:58]
    node _T_807 = cat(_T_806, _T_795) @[Cat.scala 30:58]
    node _T_808 = cat(_T_807, _T_805) @[Cat.scala 30:58]
    node _T_809 = cat(_T_808, _T_804) @[Cat.scala 30:58]
    node _T_810 = bits(_T_809, 11, 11) @[RVC.scala 94:48]
    node _T_811 = bits(io.in, 12, 12) @[RVC.scala 44:28]
    node _T_812 = bits(_T_811, 0, 0) @[Bitwise.scala 71:15]
    node _T_815 = mux(_T_812, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12]
    node _T_816 = bits(io.in, 8, 8) @[RVC.scala 44:36]
    node _T_817 = bits(io.in, 10, 9) @[RVC.scala 44:42]
    node _T_818 = bits(io.in, 6, 6) @[RVC.scala 44:51]
    node _T_819 = bits(io.in, 7, 7) @[RVC.scala 44:57]
    node _T_820 = bits(io.in, 2, 2) @[RVC.scala 44:63]
    node _T_821 = bits(io.in, 11, 11) @[RVC.scala 44:69]
    node _T_822 = bits(io.in, 5, 3) @[RVC.scala 44:76]
    node _T_824 = cat(_T_822, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_825 = cat(_T_820, _T_821) @[Cat.scala 30:58]
    node _T_826 = cat(_T_825, _T_824) @[Cat.scala 30:58]
    node _T_827 = cat(_T_818, _T_819) @[Cat.scala 30:58]
    node _T_828 = cat(_T_815, _T_816) @[Cat.scala 30:58]
    node _T_829 = cat(_T_828, _T_817) @[Cat.scala 30:58]
    node _T_830 = cat(_T_829, _T_827) @[Cat.scala 30:58]
    node _T_831 = cat(_T_830, _T_826) @[Cat.scala 30:58]
    node _T_832 = bits(_T_831, 19, 12) @[RVC.scala 94:58]
    node _T_835 = cat(_T_832, UInt<5>("h00")) @[Cat.scala 30:58]
    node _T_836 = cat(_T_835, UInt<7>("h06f")) @[Cat.scala 30:58]
    node _T_837 = cat(_T_766, _T_788) @[Cat.scala 30:58]
    node _T_838 = cat(_T_837, _T_810) @[Cat.scala 30:58]
    node _T_839 = cat(_T_838, _T_836) @[Cat.scala 30:58]
    node _T_842 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_843 = cat(UInt<2>("h01"), _T_842) @[Cat.scala 30:58]
    node _T_845 = bits(io.in, 4, 2) @[RVC.scala 31:30]
    node _T_846 = cat(UInt<2>("h01"), _T_845) @[Cat.scala 30:58]
    node _T_847 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_854 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_854 is invalid @[RVC.scala 21:19]
    _T_854.bits <= _T_839 @[RVC.scala 22:14]
    _T_854.rd <= UInt<5>("h00") @[RVC.scala 23:12]
    _T_854.rs1 <= _T_843 @[RVC.scala 24:13]
    _T_854.rs2 <= _T_846 @[RVC.scala 25:13]
    _T_854.rs3 <= _T_847 @[RVC.scala 26:13]
    node _T_860 = bits(io.in, 12, 12) @[RVC.scala 45:27]
    node _T_861 = bits(_T_860, 0, 0) @[Bitwise.scala 71:15]
    node _T_864 = mux(_T_861, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
    node _T_865 = bits(io.in, 6, 5) @[RVC.scala 45:35]
    node _T_866 = bits(io.in, 2, 2) @[RVC.scala 45:43]
    node _T_867 = bits(io.in, 11, 10) @[RVC.scala 45:49]
    node _T_868 = bits(io.in, 4, 3) @[RVC.scala 45:59]
    node _T_870 = cat(_T_867, _T_868) @[Cat.scala 30:58]
    node _T_871 = cat(_T_870, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_872 = cat(_T_864, _T_865) @[Cat.scala 30:58]
    node _T_873 = cat(_T_872, _T_866) @[Cat.scala 30:58]
    node _T_874 = cat(_T_873, _T_871) @[Cat.scala 30:58]
    node _T_875 = bits(_T_874, 12, 12) @[RVC.scala 95:29]
    node _T_876 = bits(io.in, 12, 12) @[RVC.scala 45:27]
    node _T_877 = bits(_T_876, 0, 0) @[Bitwise.scala 71:15]
    node _T_880 = mux(_T_877, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
    node _T_881 = bits(io.in, 6, 5) @[RVC.scala 45:35]
    node _T_882 = bits(io.in, 2, 2) @[RVC.scala 45:43]
    node _T_883 = bits(io.in, 11, 10) @[RVC.scala 45:49]
    node _T_884 = bits(io.in, 4, 3) @[RVC.scala 45:59]
    node _T_886 = cat(_T_883, _T_884) @[Cat.scala 30:58]
    node _T_887 = cat(_T_886, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_888 = cat(_T_880, _T_881) @[Cat.scala 30:58]
    node _T_889 = cat(_T_888, _T_882) @[Cat.scala 30:58]
    node _T_890 = cat(_T_889, _T_887) @[Cat.scala 30:58]
    node _T_891 = bits(_T_890, 10, 5) @[RVC.scala 95:39]
    node _T_894 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_895 = cat(UInt<2>("h01"), _T_894) @[Cat.scala 30:58]
    node _T_897 = bits(io.in, 12, 12) @[RVC.scala 45:27]
    node _T_898 = bits(_T_897, 0, 0) @[Bitwise.scala 71:15]
    node _T_901 = mux(_T_898, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
    node _T_902 = bits(io.in, 6, 5) @[RVC.scala 45:35]
    node _T_903 = bits(io.in, 2, 2) @[RVC.scala 45:43]
    node _T_904 = bits(io.in, 11, 10) @[RVC.scala 45:49]
    node _T_905 = bits(io.in, 4, 3) @[RVC.scala 45:59]
    node _T_907 = cat(_T_904, _T_905) @[Cat.scala 30:58]
    node _T_908 = cat(_T_907, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_909 = cat(_T_901, _T_902) @[Cat.scala 30:58]
    node _T_910 = cat(_T_909, _T_903) @[Cat.scala 30:58]
    node _T_911 = cat(_T_910, _T_908) @[Cat.scala 30:58]
    node _T_912 = bits(_T_911, 4, 1) @[RVC.scala 95:72]
    node _T_913 = bits(io.in, 12, 12) @[RVC.scala 45:27]
    node _T_914 = bits(_T_913, 0, 0) @[Bitwise.scala 71:15]
    node _T_917 = mux(_T_914, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
    node _T_918 = bits(io.in, 6, 5) @[RVC.scala 45:35]
    node _T_919 = bits(io.in, 2, 2) @[RVC.scala 45:43]
    node _T_920 = bits(io.in, 11, 10) @[RVC.scala 45:49]
    node _T_921 = bits(io.in, 4, 3) @[RVC.scala 45:59]
    node _T_923 = cat(_T_920, _T_921) @[Cat.scala 30:58]
    node _T_924 = cat(_T_923, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_925 = cat(_T_917, _T_918) @[Cat.scala 30:58]
    node _T_926 = cat(_T_925, _T_919) @[Cat.scala 30:58]
    node _T_927 = cat(_T_926, _T_924) @[Cat.scala 30:58]
    node _T_928 = bits(_T_927, 11, 11) @[RVC.scala 95:83]
    node _T_930 = cat(_T_928, UInt<7>("h063")) @[Cat.scala 30:58]
    node _T_931 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 30:58]
    node _T_932 = cat(_T_931, _T_930) @[Cat.scala 30:58]
    node _T_933 = cat(UInt<5>("h00"), _T_895) @[Cat.scala 30:58]
    node _T_934 = cat(_T_875, _T_891) @[Cat.scala 30:58]
    node _T_935 = cat(_T_934, _T_933) @[Cat.scala 30:58]
    node _T_936 = cat(_T_935, _T_932) @[Cat.scala 30:58]
    node _T_938 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_939 = cat(UInt<2>("h01"), _T_938) @[Cat.scala 30:58]
    node _T_941 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_942 = cat(UInt<2>("h01"), _T_941) @[Cat.scala 30:58]
    node _T_944 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_951 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_951 is invalid @[RVC.scala 21:19]
    _T_951.bits <= _T_936 @[RVC.scala 22:14]
    _T_951.rd <= _T_939 @[RVC.scala 23:12]
    _T_951.rs1 <= _T_942 @[RVC.scala 24:13]
    _T_951.rs2 <= UInt<5>("h00") @[RVC.scala 25:13]
    _T_951.rs3 <= _T_944 @[RVC.scala 26:13]
    node _T_957 = bits(io.in, 12, 12) @[RVC.scala 45:27]
    node _T_958 = bits(_T_957, 0, 0) @[Bitwise.scala 71:15]
    node _T_961 = mux(_T_958, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
    node _T_962 = bits(io.in, 6, 5) @[RVC.scala 45:35]
    node _T_963 = bits(io.in, 2, 2) @[RVC.scala 45:43]
    node _T_964 = bits(io.in, 11, 10) @[RVC.scala 45:49]
    node _T_965 = bits(io.in, 4, 3) @[RVC.scala 45:59]
    node _T_967 = cat(_T_964, _T_965) @[Cat.scala 30:58]
    node _T_968 = cat(_T_967, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_969 = cat(_T_961, _T_962) @[Cat.scala 30:58]
    node _T_970 = cat(_T_969, _T_963) @[Cat.scala 30:58]
    node _T_971 = cat(_T_970, _T_968) @[Cat.scala 30:58]
    node _T_972 = bits(_T_971, 12, 12) @[RVC.scala 96:29]
    node _T_973 = bits(io.in, 12, 12) @[RVC.scala 45:27]
    node _T_974 = bits(_T_973, 0, 0) @[Bitwise.scala 71:15]
    node _T_977 = mux(_T_974, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
    node _T_978 = bits(io.in, 6, 5) @[RVC.scala 45:35]
    node _T_979 = bits(io.in, 2, 2) @[RVC.scala 45:43]
    node _T_980 = bits(io.in, 11, 10) @[RVC.scala 45:49]
    node _T_981 = bits(io.in, 4, 3) @[RVC.scala 45:59]
    node _T_983 = cat(_T_980, _T_981) @[Cat.scala 30:58]
    node _T_984 = cat(_T_983, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_985 = cat(_T_977, _T_978) @[Cat.scala 30:58]
    node _T_986 = cat(_T_985, _T_979) @[Cat.scala 30:58]
    node _T_987 = cat(_T_986, _T_984) @[Cat.scala 30:58]
    node _T_988 = bits(_T_987, 10, 5) @[RVC.scala 96:39]
    node _T_991 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_992 = cat(UInt<2>("h01"), _T_991) @[Cat.scala 30:58]
    node _T_994 = bits(io.in, 12, 12) @[RVC.scala 45:27]
    node _T_995 = bits(_T_994, 0, 0) @[Bitwise.scala 71:15]
    node _T_998 = mux(_T_995, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
    node _T_999 = bits(io.in, 6, 5) @[RVC.scala 45:35]
    node _T_1000 = bits(io.in, 2, 2) @[RVC.scala 45:43]
    node _T_1001 = bits(io.in, 11, 10) @[RVC.scala 45:49]
    node _T_1002 = bits(io.in, 4, 3) @[RVC.scala 45:59]
    node _T_1004 = cat(_T_1001, _T_1002) @[Cat.scala 30:58]
    node _T_1005 = cat(_T_1004, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_1006 = cat(_T_998, _T_999) @[Cat.scala 30:58]
    node _T_1007 = cat(_T_1006, _T_1000) @[Cat.scala 30:58]
    node _T_1008 = cat(_T_1007, _T_1005) @[Cat.scala 30:58]
    node _T_1009 = bits(_T_1008, 4, 1) @[RVC.scala 96:72]
    node _T_1010 = bits(io.in, 12, 12) @[RVC.scala 45:27]
    node _T_1011 = bits(_T_1010, 0, 0) @[Bitwise.scala 71:15]
    node _T_1014 = mux(_T_1011, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12]
    node _T_1015 = bits(io.in, 6, 5) @[RVC.scala 45:35]
    node _T_1016 = bits(io.in, 2, 2) @[RVC.scala 45:43]
    node _T_1017 = bits(io.in, 11, 10) @[RVC.scala 45:49]
    node _T_1018 = bits(io.in, 4, 3) @[RVC.scala 45:59]
    node _T_1020 = cat(_T_1017, _T_1018) @[Cat.scala 30:58]
    node _T_1021 = cat(_T_1020, UInt<1>("h00")) @[Cat.scala 30:58]
    node _T_1022 = cat(_T_1014, _T_1015) @[Cat.scala 30:58]
    node _T_1023 = cat(_T_1022, _T_1016) @[Cat.scala 30:58]
    node _T_1024 = cat(_T_1023, _T_1021) @[Cat.scala 30:58]
    node _T_1025 = bits(_T_1024, 11, 11) @[RVC.scala 96:83]
    node _T_1027 = cat(_T_1025, UInt<7>("h063")) @[Cat.scala 30:58]
    node _T_1028 = cat(UInt<3>("h01"), _T_1009) @[Cat.scala 30:58]
    node _T_1029 = cat(_T_1028, _T_1027) @[Cat.scala 30:58]
    node _T_1030 = cat(UInt<5>("h00"), _T_992) @[Cat.scala 30:58]
    node _T_1031 = cat(_T_972, _T_988) @[Cat.scala 30:58]
    node _T_1032 = cat(_T_1031, _T_1030) @[Cat.scala 30:58]
    node _T_1033 = cat(_T_1032, _T_1029) @[Cat.scala 30:58]
    node _T_1036 = bits(io.in, 9, 7) @[RVC.scala 30:30]
    node _T_1037 = cat(UInt<2>("h01"), _T_1036) @[Cat.scala 30:58]
    node _T_1039 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1046 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1046 is invalid @[RVC.scala 21:19]
    _T_1046.bits <= _T_1033 @[RVC.scala 22:14]
    _T_1046.rd <= UInt<5>("h00") @[RVC.scala 23:12]
    _T_1046.rs1 <= _T_1037 @[RVC.scala 24:13]
    _T_1046.rs2 <= UInt<5>("h00") @[RVC.scala 25:13]
    _T_1046.rs3 <= _T_1039 @[RVC.scala 26:13]
    node _T_1052 = bits(io.in, 12, 12) @[RVC.scala 46:20]
    node _T_1053 = bits(io.in, 6, 2) @[RVC.scala 46:27]
    node _T_1054 = cat(_T_1052, _T_1053) @[Cat.scala 30:58]
    node _T_1055 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1057 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1059 = cat(_T_1057, UInt<7>("h013")) @[Cat.scala 30:58]
    node _T_1060 = cat(_T_1054, _T_1055) @[Cat.scala 30:58]
    node _T_1061 = cat(_T_1060, UInt<3>("h01")) @[Cat.scala 30:58]
    node _T_1062 = cat(_T_1061, _T_1059) @[Cat.scala 30:58]
    node _T_1063 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1064 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1065 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1066 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1073 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1073 is invalid @[RVC.scala 21:19]
    _T_1073.bits <= _T_1062 @[RVC.scala 22:14]
    _T_1073.rd <= _T_1063 @[RVC.scala 23:12]
    _T_1073.rs1 <= _T_1064 @[RVC.scala 24:13]
    _T_1073.rs2 <= _T_1065 @[RVC.scala 25:13]
    _T_1073.rs3 <= _T_1066 @[RVC.scala 26:13]
    node _T_1079 = bits(io.in, 4, 2) @[RVC.scala 38:22]
    node _T_1080 = bits(io.in, 12, 12) @[RVC.scala 38:30]
    node _T_1081 = bits(io.in, 6, 5) @[RVC.scala 38:37]
    node _T_1083 = cat(_T_1081, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1084 = cat(_T_1079, _T_1080) @[Cat.scala 30:58]
    node _T_1085 = cat(_T_1084, _T_1083) @[Cat.scala 30:58]
    node _T_1088 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1090 = cat(_T_1088, UInt<7>("h07")) @[Cat.scala 30:58]
    node _T_1091 = cat(_T_1085, UInt<5>("h02")) @[Cat.scala 30:58]
    node _T_1092 = cat(_T_1091, UInt<3>("h03")) @[Cat.scala 30:58]
    node _T_1093 = cat(_T_1092, _T_1090) @[Cat.scala 30:58]
    node _T_1094 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1096 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1097 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1104 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1104 is invalid @[RVC.scala 21:19]
    _T_1104.bits <= _T_1093 @[RVC.scala 22:14]
    _T_1104.rd <= _T_1094 @[RVC.scala 23:12]
    _T_1104.rs1 <= UInt<5>("h02") @[RVC.scala 24:13]
    _T_1104.rs2 <= _T_1096 @[RVC.scala 25:13]
    _T_1104.rs3 <= _T_1097 @[RVC.scala 26:13]
    node _T_1110 = bits(io.in, 3, 2) @[RVC.scala 37:22]
    node _T_1111 = bits(io.in, 12, 12) @[RVC.scala 37:30]
    node _T_1112 = bits(io.in, 6, 4) @[RVC.scala 37:37]
    node _T_1114 = cat(_T_1112, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_1115 = cat(_T_1110, _T_1111) @[Cat.scala 30:58]
    node _T_1116 = cat(_T_1115, _T_1114) @[Cat.scala 30:58]
    node _T_1119 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1121 = cat(_T_1119, UInt<7>("h03")) @[Cat.scala 30:58]
    node _T_1122 = cat(_T_1116, UInt<5>("h02")) @[Cat.scala 30:58]
    node _T_1123 = cat(_T_1122, UInt<3>("h02")) @[Cat.scala 30:58]
    node _T_1124 = cat(_T_1123, _T_1121) @[Cat.scala 30:58]
    node _T_1125 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1127 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1128 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1135 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1135 is invalid @[RVC.scala 21:19]
    _T_1135.bits <= _T_1124 @[RVC.scala 22:14]
    _T_1135.rd <= _T_1125 @[RVC.scala 23:12]
    _T_1135.rs1 <= UInt<5>("h02") @[RVC.scala 24:13]
    _T_1135.rs2 <= _T_1127 @[RVC.scala 25:13]
    _T_1135.rs3 <= _T_1128 @[RVC.scala 26:13]
    node _T_1141 = bits(io.in, 4, 2) @[RVC.scala 38:22]
    node _T_1142 = bits(io.in, 12, 12) @[RVC.scala 38:30]
    node _T_1143 = bits(io.in, 6, 5) @[RVC.scala 38:37]
    node _T_1145 = cat(_T_1143, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1146 = cat(_T_1141, _T_1142) @[Cat.scala 30:58]
    node _T_1147 = cat(_T_1146, _T_1145) @[Cat.scala 30:58]
    node _T_1150 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1152 = cat(_T_1150, UInt<7>("h03")) @[Cat.scala 30:58]
    node _T_1153 = cat(_T_1147, UInt<5>("h02")) @[Cat.scala 30:58]
    node _T_1154 = cat(_T_1153, UInt<3>("h03")) @[Cat.scala 30:58]
    node _T_1155 = cat(_T_1154, _T_1152) @[Cat.scala 30:58]
    node _T_1156 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1158 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1159 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1166 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1166 is invalid @[RVC.scala 21:19]
    _T_1166.bits <= _T_1155 @[RVC.scala 22:14]
    _T_1166.rd <= _T_1156 @[RVC.scala 23:12]
    _T_1166.rs1 <= UInt<5>("h02") @[RVC.scala 24:13]
    _T_1166.rs2 <= _T_1158 @[RVC.scala 25:13]
    _T_1166.rs3 <= _T_1159 @[RVC.scala 26:13]
    node _T_1172 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1175 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1177 = cat(_T_1175, UInt<7>("h033")) @[Cat.scala 30:58]
    node _T_1178 = cat(_T_1172, UInt<5>("h00")) @[Cat.scala 30:58]
    node _T_1179 = cat(_T_1178, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1180 = cat(_T_1179, _T_1177) @[Cat.scala 30:58]
    node _T_1181 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1183 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1184 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1191 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1191 is invalid @[RVC.scala 21:19]
    _T_1191.bits <= _T_1180 @[RVC.scala 22:14]
    _T_1191.rd <= _T_1181 @[RVC.scala 23:12]
    _T_1191.rs1 <= UInt<5>("h00") @[RVC.scala 24:13]
    _T_1191.rs2 <= _T_1183 @[RVC.scala 25:13]
    _T_1191.rs3 <= _T_1184 @[RVC.scala 26:13]
    node _T_1197 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1198 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1200 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1202 = cat(_T_1200, UInt<7>("h033")) @[Cat.scala 30:58]
    node _T_1203 = cat(_T_1197, _T_1198) @[Cat.scala 30:58]
    node _T_1204 = cat(_T_1203, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1205 = cat(_T_1204, _T_1202) @[Cat.scala 30:58]
    node _T_1206 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1207 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1208 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1209 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1216 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1216 is invalid @[RVC.scala 21:19]
    _T_1216.bits <= _T_1205 @[RVC.scala 22:14]
    _T_1216.rd <= _T_1206 @[RVC.scala 23:12]
    _T_1216.rs1 <= _T_1207 @[RVC.scala 24:13]
    _T_1216.rs2 <= _T_1208 @[RVC.scala 25:13]
    _T_1216.rs3 <= _T_1209 @[RVC.scala 26:13]
    node _T_1222 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1223 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1227 = cat(UInt<5>("h00"), UInt<7>("h067")) @[Cat.scala 30:58]
    node _T_1228 = cat(_T_1222, _T_1223) @[Cat.scala 30:58]
    node _T_1229 = cat(_T_1228, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1230 = cat(_T_1229, _T_1227) @[Cat.scala 30:58]
    node _T_1231 = shr(_T_1230, 7) @[RVC.scala 132:29]
    node _T_1233 = cat(_T_1231, UInt<7>("h01f")) @[Cat.scala 30:58]
    node _T_1234 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1236 = neq(_T_1234, UInt<1>("h00")) @[RVC.scala 133:37]
    node _T_1237 = mux(_T_1236, _T_1230, _T_1233) @[RVC.scala 133:33]
    node _T_1239 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1240 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1241 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1248 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1248 is invalid @[RVC.scala 21:19]
    _T_1248.bits <= _T_1237 @[RVC.scala 22:14]
    _T_1248.rd <= UInt<5>("h00") @[RVC.scala 23:12]
    _T_1248.rs1 <= _T_1239 @[RVC.scala 24:13]
    _T_1248.rs2 <= _T_1240 @[RVC.scala 25:13]
    _T_1248.rs3 <= _T_1241 @[RVC.scala 26:13]
    node _T_1254 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1256 = neq(_T_1254, UInt<1>("h00")) @[RVC.scala 134:27]
    node _T_1257 = mux(_T_1256, _T_1191, _T_1248) @[RVC.scala 134:22]
    node _T_1263 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1264 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1268 = cat(UInt<5>("h01"), UInt<7>("h067")) @[Cat.scala 30:58]
    node _T_1269 = cat(_T_1263, _T_1264) @[Cat.scala 30:58]
    node _T_1270 = cat(_T_1269, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1271 = cat(_T_1270, _T_1268) @[Cat.scala 30:58]
    node _T_1272 = shr(_T_1230, 7) @[RVC.scala 136:27]
    node _T_1274 = cat(_T_1272, UInt<7>("h073")) @[Cat.scala 30:58]
    node _T_1276 = or(_T_1274, UInt<21>("h0100000")) @[RVC.scala 136:47]
    node _T_1277 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1279 = neq(_T_1277, UInt<1>("h00")) @[RVC.scala 137:37]
    node _T_1280 = mux(_T_1279, _T_1271, _T_1276) @[RVC.scala 137:33]
    node _T_1282 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1283 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1284 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1291 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1291 is invalid @[RVC.scala 21:19]
    _T_1291.bits <= _T_1280 @[RVC.scala 22:14]
    _T_1291.rd <= UInt<5>("h01") @[RVC.scala 23:12]
    _T_1291.rs1 <= _T_1282 @[RVC.scala 24:13]
    _T_1291.rs2 <= _T_1283 @[RVC.scala 25:13]
    _T_1291.rs3 <= _T_1284 @[RVC.scala 26:13]
    node _T_1297 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1299 = neq(_T_1297, UInt<1>("h00")) @[RVC.scala 138:30]
    node _T_1300 = mux(_T_1299, _T_1216, _T_1291) @[RVC.scala 138:25]
    node _T_1306 = bits(io.in, 12, 12) @[RVC.scala 139:12]
    node _T_1307 = mux(_T_1306, _T_1300, _T_1257) @[RVC.scala 139:10]
    node _T_1313 = bits(io.in, 9, 7) @[RVC.scala 40:22]
    node _T_1314 = bits(io.in, 12, 10) @[RVC.scala 40:30]
    node _T_1316 = cat(_T_1313, _T_1314) @[Cat.scala 30:58]
    node _T_1317 = cat(_T_1316, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1318 = shr(_T_1317, 5) @[RVC.scala 123:34]
    node _T_1319 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1322 = bits(io.in, 9, 7) @[RVC.scala 40:22]
    node _T_1323 = bits(io.in, 12, 10) @[RVC.scala 40:30]
    node _T_1325 = cat(_T_1322, _T_1323) @[Cat.scala 30:58]
    node _T_1326 = cat(_T_1325, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1327 = bits(_T_1326, 4, 0) @[RVC.scala 123:67]
    node _T_1329 = cat(UInt<3>("h03"), _T_1327) @[Cat.scala 30:58]
    node _T_1330 = cat(_T_1329, UInt<7>("h027")) @[Cat.scala 30:58]
    node _T_1331 = cat(_T_1318, _T_1319) @[Cat.scala 30:58]
    node _T_1332 = cat(_T_1331, UInt<5>("h02")) @[Cat.scala 30:58]
    node _T_1333 = cat(_T_1332, _T_1330) @[Cat.scala 30:58]
    node _T_1334 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1336 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1337 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1344 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1344 is invalid @[RVC.scala 21:19]
    _T_1344.bits <= _T_1333 @[RVC.scala 22:14]
    _T_1344.rd <= _T_1334 @[RVC.scala 23:12]
    _T_1344.rs1 <= UInt<5>("h02") @[RVC.scala 24:13]
    _T_1344.rs2 <= _T_1336 @[RVC.scala 25:13]
    _T_1344.rs3 <= _T_1337 @[RVC.scala 26:13]
    node _T_1350 = bits(io.in, 8, 7) @[RVC.scala 39:22]
    node _T_1351 = bits(io.in, 12, 9) @[RVC.scala 39:30]
    node _T_1353 = cat(_T_1350, _T_1351) @[Cat.scala 30:58]
    node _T_1354 = cat(_T_1353, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_1355 = shr(_T_1354, 5) @[RVC.scala 122:33]
    node _T_1356 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1359 = bits(io.in, 8, 7) @[RVC.scala 39:22]
    node _T_1360 = bits(io.in, 12, 9) @[RVC.scala 39:30]
    node _T_1362 = cat(_T_1359, _T_1360) @[Cat.scala 30:58]
    node _T_1363 = cat(_T_1362, UInt<2>("h00")) @[Cat.scala 30:58]
    node _T_1364 = bits(_T_1363, 4, 0) @[RVC.scala 122:66]
    node _T_1366 = cat(UInt<3>("h02"), _T_1364) @[Cat.scala 30:58]
    node _T_1367 = cat(_T_1366, UInt<7>("h023")) @[Cat.scala 30:58]
    node _T_1368 = cat(_T_1355, _T_1356) @[Cat.scala 30:58]
    node _T_1369 = cat(_T_1368, UInt<5>("h02")) @[Cat.scala 30:58]
    node _T_1370 = cat(_T_1369, _T_1367) @[Cat.scala 30:58]
    node _T_1371 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1373 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1374 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1381 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1381 is invalid @[RVC.scala 21:19]
    _T_1381.bits <= _T_1370 @[RVC.scala 22:14]
    _T_1381.rd <= _T_1371 @[RVC.scala 23:12]
    _T_1381.rs1 <= UInt<5>("h02") @[RVC.scala 24:13]
    _T_1381.rs2 <= _T_1373 @[RVC.scala 25:13]
    _T_1381.rs3 <= _T_1374 @[RVC.scala 26:13]
    node _T_1387 = bits(io.in, 9, 7) @[RVC.scala 40:22]
    node _T_1388 = bits(io.in, 12, 10) @[RVC.scala 40:30]
    node _T_1390 = cat(_T_1387, _T_1388) @[Cat.scala 30:58]
    node _T_1391 = cat(_T_1390, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1392 = shr(_T_1391, 5) @[RVC.scala 121:33]
    node _T_1393 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1396 = bits(io.in, 9, 7) @[RVC.scala 40:22]
    node _T_1397 = bits(io.in, 12, 10) @[RVC.scala 40:30]
    node _T_1399 = cat(_T_1396, _T_1397) @[Cat.scala 30:58]
    node _T_1400 = cat(_T_1399, UInt<3>("h00")) @[Cat.scala 30:58]
    node _T_1401 = bits(_T_1400, 4, 0) @[RVC.scala 121:66]
    node _T_1403 = cat(UInt<3>("h03"), _T_1401) @[Cat.scala 30:58]
    node _T_1404 = cat(_T_1403, UInt<7>("h023")) @[Cat.scala 30:58]
    node _T_1405 = cat(_T_1392, _T_1393) @[Cat.scala 30:58]
    node _T_1406 = cat(_T_1405, UInt<5>("h02")) @[Cat.scala 30:58]
    node _T_1407 = cat(_T_1406, _T_1404) @[Cat.scala 30:58]
    node _T_1408 = bits(io.in, 11, 7) @[RVC.scala 33:13]
    node _T_1410 = bits(io.in, 6, 2) @[RVC.scala 32:14]
    node _T_1411 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1418 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1418 is invalid @[RVC.scala 21:19]
    _T_1418.bits <= _T_1407 @[RVC.scala 22:14]
    _T_1418.rd <= _T_1408 @[RVC.scala 23:12]
    _T_1418.rs1 <= UInt<5>("h02") @[RVC.scala 24:13]
    _T_1418.rs2 <= _T_1410 @[RVC.scala 25:13]
    _T_1418.rs3 <= _T_1411 @[RVC.scala 26:13]
    node _T_1424 = bits(io.in, 11, 7) @[RVC.scala 20:36]
    node _T_1425 = bits(io.in, 19, 15) @[RVC.scala 20:57]
    node _T_1426 = bits(io.in, 24, 20) @[RVC.scala 20:79]
    node _T_1427 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1434 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1434 is invalid @[RVC.scala 21:19]
    _T_1434.bits <= io.in @[RVC.scala 22:14]
    _T_1434.rd <= _T_1424 @[RVC.scala 23:12]
    _T_1434.rs1 <= _T_1425 @[RVC.scala 24:13]
    _T_1434.rs2 <= _T_1426 @[RVC.scala 25:13]
    _T_1434.rs3 <= _T_1427 @[RVC.scala 26:13]
    node _T_1440 = bits(io.in, 11, 7) @[RVC.scala 20:36]
    node _T_1441 = bits(io.in, 19, 15) @[RVC.scala 20:57]
    node _T_1442 = bits(io.in, 24, 20) @[RVC.scala 20:79]
    node _T_1443 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1450 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1450 is invalid @[RVC.scala 21:19]
    _T_1450.bits <= io.in @[RVC.scala 22:14]
    _T_1450.rd <= _T_1440 @[RVC.scala 23:12]
    _T_1450.rs1 <= _T_1441 @[RVC.scala 24:13]
    _T_1450.rs2 <= _T_1442 @[RVC.scala 25:13]
    _T_1450.rs3 <= _T_1443 @[RVC.scala 26:13]
    node _T_1456 = bits(io.in, 11, 7) @[RVC.scala 20:36]
    node _T_1457 = bits(io.in, 19, 15) @[RVC.scala 20:57]
    node _T_1458 = bits(io.in, 24, 20) @[RVC.scala 20:79]
    node _T_1459 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1466 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1466 is invalid @[RVC.scala 21:19]
    _T_1466.bits <= io.in @[RVC.scala 22:14]
    _T_1466.rd <= _T_1456 @[RVC.scala 23:12]
    _T_1466.rs1 <= _T_1457 @[RVC.scala 24:13]
    _T_1466.rs2 <= _T_1458 @[RVC.scala 25:13]
    _T_1466.rs3 <= _T_1459 @[RVC.scala 26:13]
    node _T_1472 = bits(io.in, 11, 7) @[RVC.scala 20:36]
    node _T_1473 = bits(io.in, 19, 15) @[RVC.scala 20:57]
    node _T_1474 = bits(io.in, 24, 20) @[RVC.scala 20:79]
    node _T_1475 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1482 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1482 is invalid @[RVC.scala 21:19]
    _T_1482.bits <= io.in @[RVC.scala 22:14]
    _T_1482.rd <= _T_1472 @[RVC.scala 23:12]
    _T_1482.rs1 <= _T_1473 @[RVC.scala 24:13]
    _T_1482.rs2 <= _T_1474 @[RVC.scala 25:13]
    _T_1482.rs3 <= _T_1475 @[RVC.scala 26:13]
    node _T_1488 = bits(io.in, 11, 7) @[RVC.scala 20:36]
    node _T_1489 = bits(io.in, 19, 15) @[RVC.scala 20:57]
    node _T_1490 = bits(io.in, 24, 20) @[RVC.scala 20:79]
    node _T_1491 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1498 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1498 is invalid @[RVC.scala 21:19]
    _T_1498.bits <= io.in @[RVC.scala 22:14]
    _T_1498.rd <= _T_1488 @[RVC.scala 23:12]
    _T_1498.rs1 <= _T_1489 @[RVC.scala 24:13]
    _T_1498.rs2 <= _T_1490 @[RVC.scala 25:13]
    _T_1498.rs3 <= _T_1491 @[RVC.scala 26:13]
    node _T_1504 = bits(io.in, 11, 7) @[RVC.scala 20:36]
    node _T_1505 = bits(io.in, 19, 15) @[RVC.scala 20:57]
    node _T_1506 = bits(io.in, 24, 20) @[RVC.scala 20:79]
    node _T_1507 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1514 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1514 is invalid @[RVC.scala 21:19]
    _T_1514.bits <= io.in @[RVC.scala 22:14]
    _T_1514.rd <= _T_1504 @[RVC.scala 23:12]
    _T_1514.rs1 <= _T_1505 @[RVC.scala 24:13]
    _T_1514.rs2 <= _T_1506 @[RVC.scala 25:13]
    _T_1514.rs3 <= _T_1507 @[RVC.scala 26:13]
    node _T_1520 = bits(io.in, 11, 7) @[RVC.scala 20:36]
    node _T_1521 = bits(io.in, 19, 15) @[RVC.scala 20:57]
    node _T_1522 = bits(io.in, 24, 20) @[RVC.scala 20:79]
    node _T_1523 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1530 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1530 is invalid @[RVC.scala 21:19]
    _T_1530.bits <= io.in @[RVC.scala 22:14]
    _T_1530.rd <= _T_1520 @[RVC.scala 23:12]
    _T_1530.rs1 <= _T_1521 @[RVC.scala 24:13]
    _T_1530.rs2 <= _T_1522 @[RVC.scala 25:13]
    _T_1530.rs3 <= _T_1523 @[RVC.scala 26:13]
    node _T_1536 = bits(io.in, 11, 7) @[RVC.scala 20:36]
    node _T_1537 = bits(io.in, 19, 15) @[RVC.scala 20:57]
    node _T_1538 = bits(io.in, 24, 20) @[RVC.scala 20:79]
    node _T_1539 = bits(io.in, 31, 27) @[RVC.scala 20:101]
    wire _T_1546 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19]
    _T_1546 is invalid @[RVC.scala 21:19]
    _T_1546.bits <= io.in @[RVC.scala 22:14]
    _T_1546.rd <= _T_1536 @[RVC.scala 23:12]
    _T_1546.rs1 <= _T_1537 @[RVC.scala 24:13]
    _T_1546.rs2 <= _T_1538 @[RVC.scala 25:13]
    _T_1546.rs3 <= _T_1539 @[RVC.scala 26:13]
    node _T_1552 = bits(io.in, 1, 0) @[RVC.scala 150:12]
    node _T_1553 = bits(io.in, 15, 13) @[RVC.scala 150:20]
    node _T_1554 = cat(_T_1552, _T_1553) @[Cat.scala 30:58]
    node _T_1556 = and(_T_1554, UInt<4>("h0f")) @[Package.scala 18:26]
    node _T_1558 = geq(_T_1554, UInt<5>("h010")) @[Package.scala 19:17]
    node _T_1560 = and(_T_1556, UInt<3>("h07")) @[Package.scala 18:26]
    node _T_1562 = geq(_T_1556, UInt<4>("h08")) @[Package.scala 19:17]
    node _T_1564 = and(_T_1560, UInt<2>("h03")) @[Package.scala 18:26]
    node _T_1566 = geq(_T_1560, UInt<3>("h04")) @[Package.scala 19:17]
    node _T_1568 = and(_T_1564, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_1570 = geq(_T_1564, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_1572 = and(_T_1568, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1574 = geq(_T_1568, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1575 = mux(_T_1574, _T_1546, _T_1530) @[Package.scala 19:12]
    node _T_1582 = and(_T_1568, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1584 = geq(_T_1568, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1585 = mux(_T_1584, _T_1514, _T_1498) @[Package.scala 19:12]
    node _T_1591 = mux(_T_1570, _T_1575, _T_1585) @[Package.scala 19:12]
    node _T_1598 = and(_T_1564, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_1600 = geq(_T_1564, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_1602 = and(_T_1598, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1604 = geq(_T_1598, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1605 = mux(_T_1604, _T_1482, _T_1466) @[Package.scala 19:12]
    node _T_1612 = and(_T_1598, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1614 = geq(_T_1598, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1615 = mux(_T_1614, _T_1450, _T_1434) @[Package.scala 19:12]
    node _T_1621 = mux(_T_1600, _T_1605, _T_1615) @[Package.scala 19:12]
    node _T_1627 = mux(_T_1566, _T_1591, _T_1621) @[Package.scala 19:12]
    node _T_1634 = and(_T_1560, UInt<2>("h03")) @[Package.scala 18:26]
    node _T_1636 = geq(_T_1560, UInt<3>("h04")) @[Package.scala 19:17]
    node _T_1638 = and(_T_1634, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_1640 = geq(_T_1634, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_1642 = and(_T_1638, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1644 = geq(_T_1638, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1645 = mux(_T_1644, _T_1418, _T_1381) @[Package.scala 19:12]
    node _T_1652 = and(_T_1638, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1654 = geq(_T_1638, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1655 = mux(_T_1654, _T_1344, _T_1307) @[Package.scala 19:12]
    node _T_1661 = mux(_T_1640, _T_1645, _T_1655) @[Package.scala 19:12]
    node _T_1668 = and(_T_1634, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_1670 = geq(_T_1634, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_1672 = and(_T_1668, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1674 = geq(_T_1668, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1675 = mux(_T_1674, _T_1166, _T_1135) @[Package.scala 19:12]
    node _T_1682 = and(_T_1668, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1684 = geq(_T_1668, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1685 = mux(_T_1684, _T_1104, _T_1073) @[Package.scala 19:12]
    node _T_1691 = mux(_T_1670, _T_1675, _T_1685) @[Package.scala 19:12]
    node _T_1697 = mux(_T_1636, _T_1661, _T_1691) @[Package.scala 19:12]
    node _T_1703 = mux(_T_1562, _T_1627, _T_1697) @[Package.scala 19:12]
    node _T_1710 = and(_T_1556, UInt<3>("h07")) @[Package.scala 18:26]
    node _T_1712 = geq(_T_1556, UInt<4>("h08")) @[Package.scala 19:17]
    node _T_1714 = and(_T_1710, UInt<2>("h03")) @[Package.scala 18:26]
    node _T_1716 = geq(_T_1710, UInt<3>("h04")) @[Package.scala 19:17]
    node _T_1718 = and(_T_1714, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_1720 = geq(_T_1714, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_1722 = and(_T_1718, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1724 = geq(_T_1718, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1725 = mux(_T_1724, _T_1046, _T_951) @[Package.scala 19:12]
    node _T_1732 = and(_T_1718, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1734 = geq(_T_1718, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1735 = mux(_T_1734, _T_854, _T_739) @[Package.scala 19:12]
    node _T_1741 = mux(_T_1720, _T_1725, _T_1735) @[Package.scala 19:12]
    node _T_1748 = and(_T_1714, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_1750 = geq(_T_1714, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_1752 = and(_T_1748, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1754 = geq(_T_1748, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1755 = mux(_T_1754, _T_580, _T_472) @[Package.scala 19:12]
    node _T_1762 = and(_T_1748, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1764 = geq(_T_1748, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1765 = mux(_T_1764, _T_439, _T_401) @[Package.scala 19:12]
    node _T_1771 = mux(_T_1750, _T_1755, _T_1765) @[Package.scala 19:12]
    node _T_1777 = mux(_T_1716, _T_1741, _T_1771) @[Package.scala 19:12]
    node _T_1784 = and(_T_1710, UInt<2>("h03")) @[Package.scala 18:26]
    node _T_1786 = geq(_T_1710, UInt<3>("h04")) @[Package.scala 19:17]
    node _T_1788 = and(_T_1784, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_1790 = geq(_T_1784, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_1792 = and(_T_1788, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1794 = geq(_T_1788, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1795 = mux(_T_1794, _T_368, _T_321) @[Package.scala 19:12]
    node _T_1802 = and(_T_1788, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1804 = geq(_T_1788, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1805 = mux(_T_1804, _T_270, _T_223) @[Package.scala 19:12]
    node _T_1811 = mux(_T_1790, _T_1795, _T_1805) @[Package.scala 19:12]
    node _T_1818 = and(_T_1784, UInt<1>("h01")) @[Package.scala 18:26]
    node _T_1820 = geq(_T_1784, UInt<2>("h02")) @[Package.scala 19:17]
    node _T_1822 = and(_T_1818, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1824 = geq(_T_1818, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1825 = mux(_T_1824, _T_172, _T_133) @[Package.scala 19:12]
    node _T_1832 = and(_T_1818, UInt<1>("h00")) @[Package.scala 18:26]
    node _T_1834 = geq(_T_1818, UInt<1>("h01")) @[Package.scala 19:17]
    node _T_1835 = mux(_T_1834, _T_92, _T_53) @[Package.scala 19:12]
    node _T_1841 = mux(_T_1820, _T_1825, _T_1835) @[Package.scala 19:12]
    node _T_1847 = mux(_T_1786, _T_1811, _T_1841) @[Package.scala 19:12]
    node _T_1853 = mux(_T_1712, _T_1777, _T_1847) @[Package.scala 19:12]
    node _T_1859 = mux(_T_1558, _T_1703, _T_1853) @[Package.scala 19:12]
    io.out <- _T_1859 @[RVC.scala 163:12]