| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ... | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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