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smem. Added firrtl-gensym utility to generate a hashmap of names
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instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
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strict. Have not tested this
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reasonable verilog. Requires inlining, future versions will instantiate modules
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flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
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plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
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Should show up with check passes
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isn't duplicated for all the whens
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chisel3/ModuleVec.fir doesn't work because incorrecly generated?
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Conflicts:
TODO
src/main/stanza/passes.stanza
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not propogating to the input widths, for primops
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and alternate were always assumed different, causing a huge blow-up in logic
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correctly handle it in compiler.
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missing primops
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referenced, has an inferred kind
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generate flo
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instructions and renamed concat -> cat, equal -> eq, and added neq and neg
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lowering. Finished expand-whens. Needs more thorough testing of instances
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WRegInit and removing Null and initialize-register pass
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all pass. Minimal removal of letrec to get WritePort to work correctly - a more thorough removeal is still needed
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