sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
2016-01-28	Updated all tests to pass	azidar
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2016-01-16	WIP need to correctly output readwrite ports	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar
2015-05-18	First pass at a Verilog Backend. Not tested, but compiles and generates reaso...	azidar
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be flexible...	azidar
2015-04-28	Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec....	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-04-17	Fixed bug in primop lowering during type inference. Added reduce instructions...	azidar
2015-04-10	Updated Stanza	Patrick Li
2015-04-08	Added test to show correctness of gender inference and lowering	azidar
2015-04-08	Fixed bug in lowering that incorrectly determined genders when subfielded	azidar
2015-03-27	Corrected register init by adding initialization of registers pass after lowe...	azidar
2015-03-12	Switched bundles from gender to flip	azidar
2015-03-10	Finished resolve genders	azidar