| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-19 | Updated tests | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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