sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2015-09-29	Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching...	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-08-20	Added tests, cleaned up repo	azidar
2015-08-18	Fixed so its length is greater than what it connects to. Changed shr to be e...	azidar
2015-08-03	Changed name mangling to use _ as a delin. Fixed bug in checking for	azidar
2015-08-03	Fixed performance bug in Split Expressions. Changed delin for connect indexed...	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-30	Added eqv for bitwise equality, and change eq to be arithmetic equality	azidar
2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar
2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added te...	azidar
2015-07-14	Still partial commit, many tests pass. Many tests fail.	azidar
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ...	azidar
2015-05-20	Added Pad pass to flo.stanza, which pads widths to make := and primops strict...	azidar
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be flexible...	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-05-02	Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn...	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-04-17	Fixed bug in primop lowering during type inference. Added reduce instructions...	azidar
2015-04-08	Fixed bug in lowering that incorrectly determined genders when subfielded	azidar
2015-03-23	Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit...	azidar