sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-01-16	Updated passes so they test new-mem	azidar
2016-01-16	Fixed a test	azidar
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
2015-09-29	Fixed final bug. All tests pass. Accessors are a go.	azidar
2015-09-29	Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching...	azidar
2015-08-24	Changed all tests to use verilog backend.	azidar
2015-07-31	Updated tests to pipe from stderr to stdout	azidar
2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar
2015-07-14	Added clock support	azidar
2015-07-14	Still partial commit, many tests pass. Many tests fail.	azidar
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-05-13	Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...	azidar
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-03-18	Finished expand accessors and lower to ground	azidar
2015-03-11	Finished expand accessors pass. Fixed bug in resolve-gender. Added tests, all...	azidar