| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar | |
| Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables | |||
| 2015-10-01 | Updated tests for previous change that removed RemoveScope test from the ↵ | azidar | |
| StandardVerilogCompiler | |||
| 2015-07-30 | Added module name to error messages. | azidar | |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added ↵ | azidar | |
| tests. Made more tests pass | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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