| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-01-24 | Added muxing on passive aggregate types | azidar | |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar | |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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