| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar | |
| Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables | |||
| 2015-08-24 | Changed all tests to use verilog backend. | azidar | |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops ↵ | azidar | |
| strict. Have not tested this | |||
| 2015-05-05 | Added a bunch of tests. In the middle of implementing check kinds and check ↵ | azidar | |
| types. Does not compile | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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