sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar

2015-05-02	Now when expanding ConnectFrom/ToIndex, create a node for the index so it ↵	azidar
	isn't duplicated for all the whens
2015-05-01	Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be ↵	azidar
	simplified earlier, and also now have equal? defined so mMaxWidth doesn't blow up during width inference
2015-05-01	Fixed bug where the enable was looked at for lowering MUX.	azidar

2015-04-29	Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct	azidar

2015-04-28	Instances are now male. Reworked lowering pass to be sane. ↵	azidar
	chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-22	Added new test that breaks current parser. updated todo	azidar

2015-04-21	Added new test	azidar

2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar

2015-04-16	Updated parser to correctly read empty statements	azidar

2015-04-13	new chisel3 tests	jackbackrack