sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2015-08-24	Removed old chisel3 tests that all failed for syntax reasons. Tests should ↵	azidar
	now be small examples, categorized by either passes, errors, or features.
2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar

2015-07-29	Finished supporting Chisel 2.0 Ref Chip	Adam Izraelevitz

2015-07-29	Add bigint support.	Adam Izraelevitz

2015-07-28	Integrated bigint. Mostly works, but getting "cast" error for make Test.	Adam Izraelevitz

2015-07-14	Added clock support	azidar

2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar

2015-07-14	Added chisel feedback to firrtl spec. Datapath_new triggers too large a ↵	azidar
	width error
2015-06-12	Major revisions to spec. Bumped to v0.1.2	azidar

2015-06-04	Fixed fir files so they correctly compile to verilog! Front-end needs to ↵	azidar
	generate as-SInt instead of convert, always. Added fast build to Makefile
2015-06-03	Fixed verilog backend bugs. Passes ALU. Fails Datapath	azidar

2015-06-02	Added sequential/combinational memories. Started debugging verilog backend. ↵	azidar
	Added Long support so UInt(LARGENUMBER) works
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar

2015-05-21	Added pad pass, used for flo backend	azidar

2015-05-13	Added source indicators from FIRRTL files. Pass in -p i to get them printed. ↵	azidar
	Should show up with check passes
2015-05-13	Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug	azidar

2015-05-04	Added new Control.fir with reduced padding	azidar

2015-05-04	Fixed bug where instance types were not lowered	azidar

2015-05-04	Updated stuff	azidar

2015-05-04	Fixed change where type of mux-ss was incorrect	azidar

2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar

2015-05-02	Now when expanding ConnectFrom/ToIndex, create a node for the index so it ↵	azidar
	isn't duplicated for all the whens
2015-05-01	Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be ↵	azidar
	simplified earlier, and also now have equal? defined so mMaxWidth doesn't blow up during width inference
2015-05-01	Fixed bug where the enable was looked at for lowering MUX.	azidar

2015-04-29	Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct	azidar

2015-04-28	Instances are now male. Reworked lowering pass to be sane. ↵	azidar
	chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-22	Added new test that breaks current parser. updated todo	azidar

2015-04-21	Added new test	azidar

2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar

2015-04-16	Updated parser to correctly read empty statements	azidar

2015-04-13	new chisel3 tests	jackbackrack