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AgeCommit message (Expand)Author
2015-08-24Removed old chisel3 tests that all failed for syntax reasons. Tests should no...azidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-29Add bigint support.Adam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-14Added clock supportazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Added chisel feedback to firrtl spec. Datapath_new triggers too large a width...azidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-04Fixed fir files so they correctly compile to verilog! Front-end needs to gene...azidar
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. A...azidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-21Added pad pass, used for flo backendazidar
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...azidar
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-05-04Added new Control.fir with reduced paddingazidar
2015-05-04Fixed bug where instance types were not loweredazidar
2015-05-04Updated stuffazidar
2015-05-04Fixed change where type of mux-ss was incorrectazidar
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
2015-05-02Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn...azidar
2015-05-01Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be simp...azidar
2015-05-01Fixed bug where the enable was looked at for lowering MUX.azidar
2015-04-29Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correctazidar
2015-04-28Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec....azidar
2015-04-22Added new test that breaks current parser. updated todoazidar
2015-04-21Added new testazidar
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-16Updated parser to correctly read empty statementsazidar
2015-04-13new chisel3 testsjackbackrack
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