| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-08-24 | Removed old chisel3 tests that all failed for syntax reasons. Tests should no... | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-21 | Added pad pass, used for flo backend | azidar |
| 2015-05-01 | Fixed bug where the enable was looked at for lowering MUX. | azidar |
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar |
| 2015-04-13 | new chisel3 tests | jackbackrack |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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