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AgeCommit message (Expand)Author
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
2018-03-02Fix annotation deserialization of component subfields (#750)Jack Koenig
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-26Rename loadAnnotations -> getAnnotations (#747)Jack Koenig
2018-02-23Add graph summation "+" to DiGraph (#744)Schuyler Eldridge
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-21Change primop arg type (#587)Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
2018-02-08CheckHighForm should check that Bits MSB >= LSB (#738)Schuyler Eldridge
2018-02-07Fix EulerTour for circuits with one module (#736)Schuyler Eldridge
2018-01-30Make Constant Propagation respect dontTouch on registersJack Koenig
2018-01-30Fix bug incorrectly propagating constants on submodule inputsJack Koenig
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
2018-01-08Typo: ExecutionOptionManager -> ExecutionOptionsManager.Leway Colin
2017-12-29Add support for multiple annotation filesJack
2017-12-29Remove option --force-append-anno-file, make defaultJack Koenig
2017-12-27Removed top preamble (#640)Adam Izraelevitz
2017-12-22API change: out-of-bounds vec accesses now invalid, not first element (#685)Adam Izraelevitz
2017-12-20Verify shl/shr amount is > 0 (#710)Jim Lawson
2017-12-20Fix bug in ConstProp where module dependency edges were dropped (#696)Jack Koenig
2017-12-20Make submodule inputs void in ExpandWhens (#706)Jack Koenig
2017-12-19Make toNamed invert serialize (#709)Schuyler Eldridge
2017-12-12Add RemoveWires transformJack Koenig
2017-11-28Have DedupModules report renamingJack
2017-11-28Refactor RenameMap to rename Components if their Module is renamedJack
2017-11-16Move digraph exceptions out of digraph class (#688)Albert Magyar
2017-11-10Make digraph methods deterministic (#653)Albert Magyar
2017-11-08Add InfoSpec for checking Info propagationJack Koenig
2017-11-08Add FirrtlCheckers and scalatest helpers for testingJack Koenig
2017-10-31Fix bug emitting and reparsing ExtModule String parameters (#675)Jack Koenig
2017-09-30Make ReplaceAccesses optimize multi-dimensional accesses (#665)Albert Magyar
2017-09-30Fixed zero width cat but (#651)Adam Izraelevitz
2017-09-29StringLit.verilogEscape should support all printable ASCII chars (#668)Jack Koenig
2017-09-29Namespace - only save suffix for temp names (#667)Jack Koenig
2017-09-22Fix string lit (#663)Jack Koenig
2017-09-19Create way of collecting program arguments in Driver (#659)Chick Markley
2017-09-06Write tests on multi-rooted circuits for ConstPropEdward Wang
2017-09-05Add InstanceGraph testsEdward Wang
2017-08-23Reorder port and wire assignments in Verilog (#641)Adam Izraelevitz
2017-08-14Constant propagation across module boundaries (#633)Jack Koenig
2017-08-04bug fix for cases when we want to flatten a module in which a module is insta...Andrey Ayupov
2017-08-01DCE for IsInvalid (#629)Donggyu
2017-07-26Flatten transformation (#631)Andrey Ayupov
2017-07-17do not swap wire names with node namesDonggyu Kim
2017-07-17Fix ConstProp bug where multiple names would swap with oneJack Koenig
2017-07-14Fix bug in DiGraph.reverse on an graph with one vertex, no edges (#628)Jack Koenig
2017-07-06Fixed inability to disable combo loop check (#619)Chick Markley
2017-06-29ConstProp registers that are only connected to or reset to a consantJack Koenig
2017-06-29Add test for padding constant connections to wires in ConstPropJack Koenig
2017-06-29Preserve "better" names in Constant PropagationJack Koenig
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