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2020-07-01Fix unchecked type in ManipulateNames (#1726)Schuyler Eldridge
Fix a bug where a type check would always yield true. This caused a bug where allow/block-list annotations would be incorrectly applied to all subtypes of ManipulateNames. The tests are updated to check that this now works. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-26Enable ConvertAsserts in default Verilog compilerAlbert Magyar
2020-06-26Add test for ConvertAssertsAlbert Magyar
* Add testcase for empty message
2020-06-25Test both LowerCaseNames and UpperCaseNamesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-25Add a second instance to Verilog keyword testSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-25Test ManipulateNamesAllowlistResultAnnotationSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-25Test ManipulateNamesSpecSchuyler Eldridge
Add tests for the ManipulateNames transform. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-23Don't Dedup modules if it would change semantics (#1713)Jack Koenig
If a module has ports of type Bundle that are used in aggregate connections in parent modules, Dedup cannot change the names of the fields of the Bundle or it would change the semantics of the connection. Dedup now detects this case and refrains from agnostifying the ports of such modules to prevent this issue.
2020-06-23Basic model checking API (#1653)Tom Alcorn
* Add assume, assert, cover statements * Assert submodule assumptions * Add warning when removing verification statements * Remove System Verilog behaviour emitter warning * Add option to disable AssertSubmoduleAssumptions * Document verification statements in the spec The syntax for the new statements is assert(clk, cond, en, msg) assume(clk, cond, en, msg) cover(clk, cond, en, msg) With assert as a representative example, the semantics is as follows: `clk` is the clock, `cond` is the expression being asserted, `en` is the enable signal (if `en` is low then the assert is not checked) and `msg` is a string message intended to be reported as an error message by the model checker if the assertion fails. In the Verilog emitter, the new statements are handled by a new `formals` map, which groups the statements by clock domain. All model checking statements are then emitted within the context of an `ifdef FORMAL` block, which allows model checking tools (like Symbiyosys) to utilize the statements while keeping them out of synthesis flows. Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-06-23Add support for ValidIf to ProtoBuf [de]serializationJack Koenig
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Support Memory Initialization for Simulation and FPGA Flows (#1645)Kevin Laeufer
* Support Memory Initialization for Simulation and FPGA Flows This adds a minimal annotation that allows users to influence if memories are randomly initialized, if all entries are initialized to the same scalar or if each entry should be initialized to a different value. We use the init block in order to initialize memories which is supported by verilator as well as yosys and has previously been used to randomize the initial memory contents. * LowerTypes: error when trying to split up a memory with MemoryInitAnnotation Currently the MemoryInitAnnotation only works for ground-type memories. We catch misuse of this annotation at the point of the firrtl compiler at which memories on non-ground type get split up, i.e., the LowerTypes transform. Chisel should try to prevent annotating non-ground type memories in the frontend, but it is nice to have an additional check. * MemoryInitSpec: test JSON deserialization * MemoryInitAnnotation: split up into three different annotations instead of exposing MemoryInitValue Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-22recore of Attributes (#1643)Jiuyang Liu
* Add attributes, ifdefs to emitter. * Make ifdef API a little cleaner. * Remove references to ifdefs. * Remove more of the ifdef stuff I missed * Fix up failing tests * Add multiple attribute test case * Remove tpe as a parameter from Annotations. Some general refactoring. * Add some documentation. * Incorporate some feedback * Expand some spaghetti code, add comments * Fix type signature by removing it * bug fix in test * Fix unchecked type parameter matches in AddDescriptionNodes. * use target to replace name Co-authored-by: Paul Rigge <rigge@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-19RemoveIntervals: invalidate InferTypes and ResolveKinds (#1689)Albert Chen
2020-06-10Build ArrayBuffers in Block.mapStmt (#1669)Jack Koenig
* Build ArrayBuffers in Block.mapStmt * Have empty Block serialize as "skip" The FIRRTL parser requires at least one indented line in each module. Sometimes tests emit and parse modules with no contents; this ensures there's always at least a "skip" in empty modules. Also fix tests that expected certain skips * Use var List as stack in Block.mapStmt impl This replaces Iterator concatenation. In Scala 2.11, RHS recursion on Iterators is not stack safe. This seems to have been fixed in 2.12 by Scala PR 5033. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-04Add test case for retype-based component renaming in DedupModulesAlbert Magyar
2020-06-04Add unit test for Utils.expandRefAlbert Magyar
2020-06-03Revert: Generalize keyword collision to name manipulation, Add ↵Schuyler Eldridge
{Lower,Upper}CaseNames Transforms (#1651) * Revert "Add test of {Lower, Upper}CaseNames" This reverts commit 93c078b8469bc55cd2d33147c33e2b5421fda9d9. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Add --change-name-case <lower|upper> option" This reverts commit d3ab7e2db66fe3a63778f427dad6c08f64695ba5. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Add features.{LowerCaseNames, UpperCaseNames} transforms" This reverts commit c8dcdacf313f19a4d0238be694478a325432edd4. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Refactor RemoveKeywordCollisions->ManipulateNames" This reverts commit c534c5abae7b80a725ec9925569b3383b3c24a34. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-28Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths (#1539)Albert Chen
- RenameMap Behavior -- Prevent transitive renaming A -> B -> C (continueRenaming) -- Prevent transitive renaming for self-renames - Target -- Override toString as serialize for CompleteTarget -- Expansion of stripHierarchy to enable stripping InstanceTargets to become ModuleTargets Annotations -- Bugfix in extractComponents where Products were not iterated over -- Converts renamed targets to local targets using Target.referringModule to preserve sticky behavior - Eliminate Target Paths -- Make DuplicationHelper use LinkedHashMap, as we iterate over its contents and convert to Seq in def makePathless -- Add DupedResult to map original module to new module targets -- Update renaming to record a map from all relative instance paths to original module, to new module target -- Consumes DedupedResult to give better name to new duplicated module if it was originally deduplicated -- Reorder modules in attempt to preserve original ordering, pre-deduplication -- Move utility functions to object -- Bugfix: add self-renames to prevent ofModule _ of target _ cannot be renamed to Vector(_, _, _, ...) errors - Dedup -- Changed NoDedupAnnotation to contain ModuleTarget, rather than ModuleName -- Added DedupedResult to map original module to the duplicate module -- Consumes DupedResult to pick better name, if it existed -- Updates renaming to chain the following: instancify deduped modules, remap differently named internal signals, then remap AST modules -- Move utility functions to object -- Remove annotations as part of determination of dedup correctness -- Bugfix: add instance renames so that deduped modules have their instances properly renamed - Dead Code Elimination -- Add deletion of ASTModules - Tests -- Morphism Spec to ensure Dedup -> EliminateTargetPaths and EliminateTargetPaths -> Dedup patterns work properly -- Update existing tests to make sure they work properly -- Add Dedup tests to demonstrate instance renaming bug, EliminateTargetPaths for ofModule rename bug, and update RenameMap tests Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com> Co-authored-by: Adam Izraelevitz <azidar@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
* Absorb WRef into Reference * Absorb WSubField into SubField * Absorb WSubIndex into SubIndex * Absorb WSubAccess into SubAccess * Absorb WDefInstance into DefInstance ------------------------- API CHANGE SEVERITY -------------------------- This is projected to not break source-level compatibility with any known user code. However, it will break *binary* compatibility with all existing user FIRRTL passes, as is generally allowed with major releases of FIRRTL. --------------------------- DESCRIPTION -------------------------------- Previously, there were several nodes in WIR.scala that had a one-to-one correspondance with existing nodes in the standard firrtl.ir hierarchy. These nodes would have a case class resembling the corresponding standard IR node, but with the addition of one or more "analysis" fields. Since these fields (such as kind) represent helpful info that can be invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not cause any issues to simply include these fields on any in-memory representation of FIRRTL IR. Although other systems for tracking FIRRTL analyses have evolved over time, the ubiquity of pattern-matching on these fields has lead most core and custom transforms to be written against WIR, rather than IR. This PR unifies the IRs by adding the fields that would be in an "augmented" WIR node directly into the corresponding IR node; i.e., the "type" and "kind" fields from WRef are added directly to the definition of the Reference case class, while these "repetitive" WIR case classes are removed entirely. -------------------- SOURCE-COMPATIBILITY ADAPTERS --------------------- Several object methods are added to WIR.scala to maintain source-compatiblity for passes that used WIR. These objects define factory methods and unapply methods, so passes that relied on implicit case class factories or pattern matching for the removed WIR types will remain perfectly source-compatible. However, these do not guarantee compatibility at the binary level. The types of the removed WIR case classes are also added as type aliases to the top-level firrtl package, which allows code that relies on explicit constructor calls or reflection to retain source-compatibility. Finally, additional explicit factory methods are added to the companion objects of the newly-augmented IR case classes, which allows user code to avoid having to specify any of the new analysis fields. Existing code that created non-WIR IR nodes will be able to continue using the previous factory signatures, which will cause all omitted analysis fields to be set to Unknown. ---------------------- UNMITIGATED API CHANGES ------------------------- While passes that used WIR will be source-compatible with this change, there is one significant change that affects any pass currently using non-WIR IR: the signatures of pattern-matching cases for Reference, SubField, SubIndex, SubAccess, and DefInstance must change to accommodate the extra fields. This cannot be worked at the API level due to restrictions on unapply overloading, but it could theoretically be solved with macros or other static rewriting. However, only four core transforms (RemoveProto, ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is expected that no user code currently relies on it, so the expected migration strategy is simply to change the small fraction of code relying on these nodes.
2020-05-22Do not throw NonFatal exceptions in annotation loggingJack Koenig
If an annotation cannot be serialized by json4s, we should not throw exceptions when doing trace-level logging.
2020-05-21RenameMap: remove implicit rename chaining (#1591)Albert Chen
* RenameMap: remove implicit rename chaining * RenameMap: remove trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-18Don't try deduping the main module of a circuit (#1594)Albert Magyar
2020-05-18Fix equivalence tests (#853)Albert Chen
* - modify firrtlEquivalenceTest to use yosys equiv_simple/equiv_induct instead of miter - add RemoveValidIf pass to MinimumLowFirrtlOptimization * add EquivalenceTest to FirrtlSpec.scala, make classes in IntegrationSpec.scala abstract * change types of inputForm/outputForm to CircuitForm * change EquivalenceTest message * remove ICache equivalence tests * fix rebase errors * Add Ops scalatests to LEC suite * Only run compiler-path-comparison LEC tests on Ops design * Fixup issues with merge Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-18Canonicalize init of regs with zero as reset in RemoveReset (#1627)Albert Magyar
* Fixes #1561 * Add test for zero-reset reg from #1561
2020-05-13Add test of {Lower, Upper}CaseNamesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
* consolidated wire <type> x; assign x = y; to wire <type> x = y; * Remove dead code from Emitter.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-11Have AppendInfo use MultiInfo, rather than appending with : (#1580)Adam Izraelevitz
* Bugfix - have AppendInfo use MultiInfo, rather than appending with : * Address reviewer feedback Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-11Add andr, orr, xorr literal const prop testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-08deprecating BackendCompilationUtilities trait for object (#1575)Deborah Soung
2020-05-06Update scalatest to 3.1.1 (#1405)Scala Steward
* Update scalatest to 3.1.1 * Update scalatest to 3.1.1 * Update scalatest to 3.1.1 Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-05before/after initial block macros (#1550)Deborah Soung
* adding init macros * fix missing tick * adding more documentation; fixing up emitter tests * adding initial-guarding macro test * prefixing macros with FIRRTL * cleanup * typo fix Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-04Add LegalizeAndReductionsTransformJack Koenig
Workaround for https://github.com/verilator/verilator #2300 present in Verilator versions v4.026 - v4.032. This transform turns AND reductions for expressions > 64-bits into an equality check with all ones. It is included as a prerequisite for all Verilog emitters.
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
This adds missing invalidations to four transforms: - ExpandConnects - RemoveAccesses - SplitExpressions - VerilogMemDelays This necessarily updates test cases which expect exact transform orders to reflect the new order. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-20Add test cases for illegal casts to AsyncReset / ClockAlbert Magyar
2020-04-20Remove repetitive pass lists from WidthTestsAlbert Magyar
2020-04-20Avoid casting 2-bit interval to AsyncReset in testAlbert Magyar
2020-04-14Add Paul's async-reset self-init case as a testAlbert Magyar
2020-04-14Allow casts in AsyncReset literal value check (#1523)Jack Koenig
Chisel emits all literals as UInts cast to the correct type, make CheckResets support casts when checking that async reset registers are reset to literal values. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Add test-case for explicit padding of SInts in mverilog compilerAlbert Magyar
2020-04-13Ensure PadWidths is run in mverilog compilerAlbert Magyar
2020-04-13Add test of mixing -e with -E in FirrtlMainSpecSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-11EliminateTargetPaths: don't duplicate modules with only one instance (#1504)Albert Chen
* EliminateTargetPaths: add lone instance test cases * EliminateTargetPaths: don't rename lone instances * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Add ground type serializer (#1502)Albert Chen
* update JsonProtocolSpec to test GroundType * add custom serializer for GroundType * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-07Fix dynamic SubAccess of zero-length vectors (#1450)Albert Magyar
* Fix dynamic SubAccess of zero-length vectors * Fixes #230 * Add new ZeroLengthVecs pass that occurs before RemoveAccesses * Include this in stage.Forms.MidForm * Add to High->Mid order in compiler test based on @seldridge feedback * Use validif to produce out-of-bounds value in ZeroLengthVecs * Update scaladoc * Fix test imports
2020-04-06Remove deprecated ResolveGenders and CheckGendersAlbert Magyar
* Remove few remaining uses of these passes from FIRRTL codebase
2020-03-30Add previously failing pad(cast(lit)) example as a test caseAlbert Magyar
* Previously, this test failed whenever InlineCasts was run
2020-03-26Support octal and binary literal formats as described in the specAlbert Magyar
* Fixes #1464
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