| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-03-02 | Fold VerilogModulusCleanup into LegalizeVerilog (#2485) | Jack Koenig |
| 2021-12-18 | Fix width of signed addition when input to mux (#2440) | Jack Koenig |
| 2021-02-17 | Allow Side Effecting Statement to have Names (#2057) | Kevin Laeufer |
| 2021-01-28 | Stop padding multiply and divide ops (#2058) | Jack Koenig |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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