sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2021-06-18	Fix MultiInfo parser + serialization bug (#2265)	Jared Barocsi
2021-05-13	Implement MFC-style source locator compression (#2212)	Jared Barocsi
2021-04-19	Don't use declaration-assigns for wires representing mem ports (#2189)	Albert Magyar
2021-04-05	Allow direct emission of sync-read memories to Verilog	Albert Magyar
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley
2020-08-14	All of src/ formatted with scalafmt	chick
2020-07-17	Propagate source locators to register update always blocks (#1743)	Jack Koenig
2020-07-15	ir: store FileInfo string in escaped format (#1690)	Kevin Laeufer
2020-05-13	consolidated wire+assign to just wire, with expression inlined (#1600)	Murali Vijayaraghavan
2020-05-11	Have AppendInfo use MultiInfo, rather than appending with : (#1580)	Adam Izraelevitz
2020-03-17	[RFC] Factor out common test classes; package them (#1412)	David Biancolin
2019-10-18	Upstream intervals (#870)	Adam Izraelevitz
2018-05-30	Makes ExpandWhens preserve connect Infos	chick
2017-12-12	Add RemoveWires transform	Jack Koenig
2017-11-08	Add InfoSpec for checking Info propagation	Jack Koenig