| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-09-26 | Enforce port uniqueness in Chirrtl/High Checks | Schuyler Eldridge |
| 2018-02-08 | CheckHighForm should check that Bits MSB >= LSB (#738) | Schuyler Eldridge |
| 2017-12-20 | Verify shl/shr amount is > 0 (#710) | Jim Lawson |
| 2017-05-03 | Add checks on register clock and reset types (#33) (#553) | Albert Magyar |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-08-16 | add test case for clock type connection (#239) | mwachs5 |
| 2016-07-25 | Detects and flags cyclic module loops | chick |
| 2016-06-10 | API Cleanup - AST | Jack |
| 2016-05-24 | Added Errors class and fixed tests. | azidar |
| 2016-05-12 | Implement File Info | jackkoenig |
| 2016-04-26 | Add test for recursive check for whether BundleType contains flips | Adam Izraelevitz |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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