sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2021-04-16	Make InferTypes error on enable conditions > 1-bit wide (#2182)	Jack Koenig
2021-02-17	Allow Side Effecting Statement to have Names (#2057)	Kevin Laeufer
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley
2020-08-14	All of src/ formatted with scalafmt	chick
2020-08-01	Error on ExtModules w/ same defname, diff. ports (#1734)	Schuyler Eldridge
2020-07-27	Add Conditionally scoping tests to CheckSpec	Albert Magyar
2020-03-25	Update scalatest 3.1.0 (#1383)	Jim Lawson
2020-03-16	Check for collision of defnames with Module names	Albert Magyar
2020-03-16	Check for module name conflicts	Albert Magyar
2020-03-06	Check sign of primop constants where appropriate (#1421)	Albert Magyar
2019-09-16	Rename gender to flow	Schuyler Eldridge
2019-08-07	Check mems for legal latencies; ban zero write latency. (#1147)	Albert Magyar
2019-08-07	DRY check chirrtl (#1148)	Albert Magyar
2019-02-25	Detect and error on registers with flip in type (#1031)	Albert Magyar
2019-02-22	Add Width Constraints with Annotations (#956)	Albert Chen
2018-09-26	Enforce port uniqueness in Chirrtl/High Checks	Schuyler Eldridge
2018-02-08	CheckHighForm should check that Bits MSB >= LSB (#738)	Schuyler Eldridge
2017-12-20	Verify shl/shr amount is > 0 (#710)	Jim Lawson
2017-05-03	Add checks on register clock and reset types (#33) (#553)	Albert Magyar
2016-12-08	Clk2clock - rename the implicit "clk" module input "clock" (#387)	Jim Lawson
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
2016-08-16	add test case for clock type connection (#239)	mwachs5
2016-07-25	Detects and flags cyclic module loops	chick
2016-06-10	API Cleanup - AST	Jack
2016-05-24	Added Errors class and fixed tests.	azidar
2016-05-12	Implement File Info	jackkoenig
2016-04-26	Add test for recursive check for whether BundleType contains flips	Adam Izraelevitz