| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-09-12 | Add LegalizeSpec for testing Verilog Legalization pass | Jack |
| 2016-05-12 | Restructured Compiler to use Transforms. Added an InlineInstance pass. | Adam Izraelevitz |
| 2016-05-03 | Add Expand Whens test | jackkoenig |
| 2016-05-03 | Make simulations that time out fail when run in firrtlTests | jackkoenig |
| 2016-04-20 | Add tests for CHIRRTL mem port definitions. | jackkoenig |
| 2016-04-20 | Fix top.cpp reset race condition #137 | jackkoenig |
| 2016-04-08 | Add small test for issue #105 | jackkoenig |
| 2016-03-15 | Revamp string literal handling | jackkoenig |
| 2016-03-03 | Add some integration tests: successful compilation and execution | jackkoenig |
| 2016-02-23 | Add rocket regression, just runs rocket.fir through Verilog compiler and comp... | Jack |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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