| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-05-21 | Fix more problems with zero width things. (#779) | grebe |
| 2018-03-19 | Masks for zero-width fields of mems should be width zero. (#763) | grebe |
| 2017-06-21 | Add --no-dce command-line option to skip DCE | Jack Koenig |
| 2017-06-12 | Add option to disable combinational loop detection | Jack Koenig |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson |
| 2016-11-05 | Fix CHIRRTL bugs (#355) | Donggyu |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-10-07 | Add test for Firrtl mems with no ports (#327) | Jack Koenig |
| 2016-05-12 | Restructured Compiler to use Transforms. Added an InlineInstance pass. | Adam Izraelevitz |
| 2016-04-20 | Add tests for CHIRRTL mem port definitions. | jackkoenig |
| 2016-04-08 | Add small test for issue #105 | jackkoenig |
| 2016-03-15 | Revamp string literal handling | jackkoenig |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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