sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley
2020-08-01	Error on ExtModules w/ same defname, diff. ports (#1734)	Schuyler Eldridge
2019-05-24	Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)	Jack Koenig
2018-10-31	Don't include verilog header files in "FileList" for VCS/Verilator. (#918)	Jim Lawson
2018-06-11	Allow escaped single quotes in RawParams (#820)	Richard Lin
2016-12-08	Clk2clock - rename the implicit "clk" module input "clock" (#387)	Jim Lawson
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
2016-10-26	Add RawString ExtModule parameter support	jackkoenig
2016-10-26	Add Support for Parameterized ExtModules and Name Override	jackkoenig
2016-10-26	Add ExtModule Tests	jackkoenig