sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-08-04	Added RemoveEmpty.scala, which removes Empty and nested Blocks (#218)	Adam Izraelevitz
	* Added RemoveEmpty.scala, which removes Empty and nested Blocks * Reused squashEmpty from ExpandWhens by moving it to Utils * Squash EmptyStmts in ExpandWhens correctly
2016-08-04	Addd check: bits, tail, head arg width	azidar

2016-08-04	Bugfix: recursing stmts to remove unknown widths	azidar

2016-08-03	fixes small mistakes in serialize (#216)	Donggyu

2016-08-02	Merge pull request #215 from ucb-bar/new-serialize	Adam Izraelevitz
	Change serialize to abstract method on FirrtlNode
2016-08-02	Merge pull request #203 from ucb-bar/fix_mem_infer	Adam Izraelevitz
	Fix mem infer
2016-08-02	make infer readwrite ports optional	Donggyu Kim
	turned on with '--inferRW <circuit name>'
2016-08-02	Change serialize to abstract method on FirrtlNode	Jack Koenig

2016-08-02	Merge pull request #214 from ucb-bar/fix-thread-unsafety	Adam Izraelevitz
	Fix use of global state in instance loop checking
2016-08-02	Merge pull request #213 from ucb-bar/default-to-warn	Adam Izraelevitz
	Change default log level to warn
2016-08-02	Merge pull request #211 from ucb-bar/fix-subaccess	Adam Izraelevitz
	Refactor RemoveAccesses and fix bug #210.
2016-08-02	Fix use of global state in instance loop checking	jackkoenig
	Also increase sensitivity of thread safety checking Fixes #159
2016-08-01	Added minor cosmetic changes to RemoveAccesses	azidar

2016-08-01	Change default log level to warn	Jack Koenig

2016-08-01	Refactor RemoveAccesses and fix bug #210.	azidar
	Added corresponding unit test.
2016-07-29	remove ConstProp in HighFirrtlToMiddleFirrtl	Donggyu Kim
	ConstProp before width padding causes errors for SIntLiteral
2016-07-28	InferWidths now only fixes declaration widths	azidar
	Then calls InferTypes to propagate inferred widths to expressions. Required upgrading InferTypes to do simple width propagation. Fixes #206 and #200.
2016-07-27	infer readwrite ports for backward compatibility	Donggyu Kim

2016-07-27	fix read port enables in RemoveCHIRRTL	Donggyu Kim
	read ports are declared outside when clauses and used multiple times, so their enables should be inserted when being replaced
2016-07-27	Forgot to add Annotations.scala	Adam Izraelevitz

2016-07-27	Reworked annotation system. Added tenacity and permissibility	Adam Izraelevitz
	Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala
2016-07-27	Merge pull request #198 from ucb-bar/add-chirrtl-check	Adam Izraelevitz
	Added a Chirrtl check for undeclared wires, etc.
2016-07-25	Changed InferTypes to update types if UnknownType or has an UnknownWidth	azidar
	Removed InferWidths after ExpandWhens
2016-07-25	Detects and flags cyclic module loops	chick

2016-07-21	Added a Chirrtl check for undeclared wires, etc.	azidar

2016-07-21	Indentation support for the ANTLR parser (as discussed in #192) (#194)	Kamyar Mohajerani
	Indentation support for the ANTLR parser - some clean-up of the parser code (TODO: file input could be improved, more clean-up) - get rid of Translator and specify all syntactic rules in antlr4 grammer - support for else-when shorthand in the grammar - rename Begin to Block which makes more sense
2016-07-07	Guard register randomization with RANDOMIZE, rather than SYNTHESIS	Andrew Waterman
	Randomization should be controllable separately. Verilator, for example, already does this if it is passed --x-assign unique; doing it redundantly reduces simulation performance.
2016-07-07	Re-run constant propagation after pad widths	Andrew Waterman

2016-07-07	Generalize and clean up constant propagation pass	Andrew Waterman

2016-07-06	Emit correct Verilog for SIntLiteral	Andrew Waterman

2016-07-06	Only assign garbage to Mem reads for non-power-of-2 depths	Andrew Waterman

2016-07-06	Avoid width warnings on Mem garbage assignment	Andrew Waterman

2016-07-06	Rely on $fatal vs. $finish, rather than stderr, for stop codes	Andrew Waterman
	This approach uses the normal Unix mechanisms, rather than log grepping.
2016-07-04	printf: support '%c' for printing characters	Wesley W. Terpstra

2016-06-27	Optionally guard stop with `STOP_COND macro	Andrew Waterman
	This allows for testbench handling of pipelined reset, independently of `PRINTF_COND.
2016-06-23	Emit more useful code for stop	Andrew Waterman
	- Based upon stop value, use $fatal instead of $finish. This causes the Verilog simulator to signal an error to the OS as appropriate. - Don't guard stop with `PRINTF_COND (only not-`SYNTHESIS).
2016-06-10	Change BoolType from method to val	Jack Koenig

2016-06-10	API Cleanup - AST	Jack
	trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-06-10	API Cleanup - PrimOp & PrimOps	Jack
	Add simple documentation trait PrimOp -> abstract class PrimOp Move PrimOp case objects to object PrimOps Rename PrimOp case objects to match concrete syntax Overrwrite toString for more canonical serialization Update some PrimOps utility functions
2016-06-10	API Cleanup - Expression	Jack
	trait Expression -> abstract class Expression Ref -> Reference abbrev. exp -> expr Add abstract class Literal UIntValue -> UIntLiteral extends Literal SIntValue -> SIntLiteral extends Literal
2016-06-10	API Cleanup - Statement	Jack
	trait Stmt -> abstract class Statement (to match Expression) abbrev. exp -> expr BulkConnect -> PartialConnect camelCase things that were snake_case case class Empty() -> case object EmptyStmt Change >120 character Statements to multiline
2016-06-10	API Cleanup - Width	Jack
	Add simple documentation trait Width -> abstract class Width case class UnknownWidth -> case object UnknownWidth
2016-06-10	API Cleanup - Field & Flip	Jack
	Add simple documentation Flip -> Orientation trait Orientation -> abstract class Orientation Orientation case objects to upper camel case REVERSE -> Flip
2016-06-10	API Cleanup - Type	Jack
	trait Type -> abstract class Type case class ClockType() -> case object ClockType case class UnknownType() -> case object UnknownType Add GroundType and AggregateType ClockType has width of IntWidth(1)
2016-06-10	API Cleanup - Port & Direction	Jack
	Add simple documentation Change Direction case objects to upper camel case
2016-06-10	API Cleanup - Module	Jack
	trait Module -> abstract class DefModule InModule -> Module (match concrete syntax) ExModule -> ExtModule (match concrete syntax) Add simple scaladoc for each one
2016-06-10	Avoid exponential growth in reg code emission	Andrew Waterman
	In 7afe9f6180a53fd9f024c67d78289689a601c8b7, I reintroduced a performance pathology when recursing through Mux trees. This patch prevents redundantly expanding the same Mux more than a constant number of times, preserving linear runtime but still resulting in acceptable QoR.
2016-06-10	Fix Verilog codegen for reg	Andrew Waterman
	Previously, we emitted if-else sequences for reg updates. Recent improvements to FIRRTL resulted in the emission of explicit mux networks instead. While equivalent, doing so reduces QoR, presumably because ECAD tools are tuned to the habits of manual Verilog coders. This seems to be a result of WRefs appearing between the regs and muxes. Chasing down the sources of the WRefs corrects the code generation. This patch reduces the Rocket pipeline area by about 2% and improves rocket-chip's Verilator performance by about 8%.
2016-06-09	Initializes register addresses. (#189)	Adam Izraelevitz
	Fixes #187.
2016-06-09	Merge branch 'master' into fix-warning	Adam Izraelevitz