sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2015-07-02	Fixed performance bugs, runs 7x faster	azidar
2015-06-02	Added low firrtl check. Corrected bug in prefix matching in high firrtl check	azidar
2015-06-02	Added sequential/combinational memories. Started debugging verilog backend. A...	azidar
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ...	azidar
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar
2015-05-19	get flo backend running again with no pads and generic operators	jackbackrack
2015-05-18	get coercion running for flo backend and disable negative lit check	jackbackrack
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be flexible...	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-05-13	Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...	azidar
2015-05-13	Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug	azidar
2015-05-05	Added a bunch of tests. In the middle of implementing check kinds and check t...	azidar
2015-05-04	Updated stuff	azidar
2015-05-04	Added a few more error checks. Not tested yet. Fixed bug in pad type inference	azidar
2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar