aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala
AgeCommit message (Expand)Author
2017-09-21Some ScalaDoc warning fixesEdward Wang
2017-09-21Fix problem where wrong verilog file is used. (#661)Chick Markley
2017-09-19Provide mechanism so that programs can optionally (#660)Chick Markley
2017-09-19Create way of collecting program arguments in Driver (#659)Chick Markley
2017-09-12Make pathsInDAG walk all possible paths (#655)Schuyler Eldridge
2017-09-05Make InstanceGraph track module hierarchies not contained in the top-level hi...Albert Magyar
2017-08-31Added option to emit final annotations (#649)Adam Izraelevitz
2017-08-23Reorder port and wire assignments in Verilog (#641)Adam Izraelevitz
2017-08-14Constant propagation across module boundaries (#633)Jack Koenig
2017-08-04bug fix for cases when we want to flatten a module in which a module is insta...Andrey Ayupov
2017-08-01DCE for IsInvalid (#629)Donggyu
2017-07-26Flatten transformation (#631)Andrey Ayupov
2017-07-17do not swap wire names with node namesDonggyu Kim
2017-07-17Fix ConstProp bug where multiple names would swap with oneJack Koenig
2017-07-14Fix bug in DiGraph.reverse on an graph with one vertex, no edges (#628)Jack Koenig
2017-07-06Fixed inability to disable combo loop check (#619)Chick Markley
2017-06-29ConstProp registers that are only connected to or reset to a consantJack Koenig
2017-06-29Connect registers with no connections to zeroJack Koenig
2017-06-29Preserve "better" names in Constant PropagationJack Koenig
2017-06-28Make Constant Propagation respect dontTouchJack Koenig
2017-06-28Promote ConstProp to a transformJack Koenig
2017-06-27Add RemoveReset transform to replace register reset with a MuxJack Koenig
2017-06-27Emitting reg update mux tree, only walk netlist for wires and nodesJack Koenig
2017-06-26Add support for wires in ConstPropJack Koenig
2017-06-26Speed up ConstProp by doing ConstProp before recording nodeJack Koenig
2017-06-21Add --no-dce command-line option to skip DCEJack Koenig
2017-06-13Replace IsInvalids on LowForm with connection to zeroJack Koenig
2017-06-13Canonicalize spacing in RemoveValidIfJack Koenig
2017-06-13Make ExpandWhens delete 'is invalid' for attached Analog componentsJack Koenig
2017-06-12Add option to disable combinational loop detectionJack Koenig
2017-06-12Move CheckCombLoops from passes/ to transforms/Jack Koenig
2017-06-12Change CheckCombLoops to a TransformJack Koenig
2017-06-12Fixes a typo in the verilog `elsif code generation (#603)Shreesha Srinath
2017-06-06Display the total time firrtl took to compile (#599)Colin Schmidt
2017-05-30Change base of randomization values to _RAND instead of _GENJack Koenig
2017-05-30Add some comments to `endifJack Koenig
2017-05-27Prep for Scala 2.12 (#557)Jim Lawson
2017-05-25Fix performance bug in DCE (#596)Jack Koenig
2017-05-25Fix performance bug in ZeroWidth (#594)Jack Koenig
2017-05-19Delete black_box_verilog_files.f if we aren't going to create it - fixes #504...Jim Lawson
2017-05-18Upgrade Logging facility (#488)Chick Markley
2017-05-17Make sure not to DCE input-only extmodules unless specified (#590)Jack Koenig
2017-05-12Bugfix: renaming instance ports was broken. (#588)Adam Izraelevitz
2017-05-12Fix pad, second try (#465)Adam Izraelevitz
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-05-10Fix typo in ExecutionOptionsManager comment (#520)Colin Schmidt
2017-05-10Update rename2 (#478)Adam Izraelevitz
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
2017-04-20move circuit dumping to trace so debug gives annos only (#524)Colin Schmidt
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-02 13:25:48 +0000