| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-11-23 | Enable memory initialization in synthesis for FPGA targets (#2430) | Carlos Eduardo |
| 2021-04-05 | Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDoc | Albert Magyar |
| 2021-04-05 | Add --target:fpga flag to prioritize FPGA-friendly compilation | Albert Magyar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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