| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-10-23 | Fix bitmask (#346) | Angie Wang |
| 2016-10-17 | Reorganized memory blackboxing (#336) | Adam Izraelevitz |
| 2016-10-11 | Scala style cleanup take 5 (#324) | Chick Markley |
| 2016-09-25 | use sys.error instead of deprecated error | chick |
| 2016-09-25 | implicit functions should specify return type | chick |
| 2016-09-23 | use .head instead of (0) | chick |
| 2016-09-21 | Fix clock connections in InferReadWrite (#310) | Donggyu |
| 2016-09-21 | refactor InferReadWrite | Donggyu Kim |
| 2016-09-21 | generalize Analysis.getConnects for code resuse | Donggyu Kim |
| 2016-09-13 | use case object for Kind (#267) | Donggyu |
| 2016-08-17 | Change RW port names (#236) | Angie Wang |
| 2016-08-02 | make infer readwrite ports optional | Donggyu Kim |
| 2016-07-27 | infer readwrite ports for backward compatibility | Donggyu Kim |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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