| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-11-19 | Disable random init (#2396) | Jiuyang Liu |
| 2021-03-09 | Create annotation to allow inline readmem in Verilog (#2107) | Carlos Eduardo |
| 2020-09-16 | Change to Apache 2.0 License (#1901) | Chick Markley |
| 2020-08-14 | All of src/ formatted with scalafmt | chick |
| 2020-06-22 | Support Memory Initialization for Simulation and FPGA Flows (#1645) | Kevin Laeufer |
| 2020-03-12 | Add Support for FPGA Bitstream Preset-registers (#1050) | John's Brew |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
| aboutsummaryrefslogtreecommitdiff |