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AgeCommit message (Expand)Author
2022-03-04[spec] Remove FIRRTL Specification (#2488)Schuyler Eldridge
2022-03-01Convert firrtl specification to Markdown file (#2236)Jared Barocsi
2021-11-12Update spec on extmodule with defname, parameter (#2413)Schuyler Eldridge
2021-09-24spec: Fix formatting of example of memory port types. (#2368)Richard Xia
2021-08-05Fix Specification Memory Port Types (#2319)Schuyler Eldridge
2021-08-02Update spec to disallow 0-bit mux sel (#2305)Schuyler Eldridge
2021-06-30Relax spec on 0-bit mux select, use SFC behaviorSchuyler Eldridge
2021-06-21[spec] Explicit widths may be non-negative, not just positive (#2277)Albert Magyar
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
2020-07-31Fixed typo in fixed-point type parameter examples (#1816)Kevin Laeufer
2020-07-15ir: store FileInfo string in escaped format (#1690)Kevin Laeufer
2020-07-13[spec] Specify execution order of side-effect-having statements (#1724)Albert Magyar
2020-07-09[spec] Explicitly disallow shadowing of component names (#1749)Albert Magyar
2020-05-18Fix typo in spec description of 'tail' (#1626)Albert Magyar
2020-05-06Update spec.pdfSchuyler Eldridge
2020-04-13[spec] Add Fixed to spec (#1456)Albert Magyar
2020-03-26Update spec to clarify sign and use 'h' for hex throughoutAlbert Magyar
2020-03-13[spec] Update Mid FIRRTL spec to reflect removal of subaccesses (#1451)Albert Magyar
2020-03-02Update single-line when/else example in spec to match implementation (#1414)Albert Magyar
2020-02-24[spec] clarify that div-by-zero is undefined (#1409)Albert Magyar
2020-02-11[spec] Change sub(UInt, UInt) output type to UInt (#1378)Albert Magyar
2020-02-06Add note to spec about reductions on zero-width wiresAlbert Magyar
2020-01-15improve the tail ir usability. (#1241)Sequencer
2019-11-13Add spec for Analog type and attach statement (#1222)Albert Magyar
2019-09-30Define read-write collison for independently clocked mem ports (#1188)Albert Magyar
2019-09-16Update Spec from Gender to FlowSchuyler Eldridge
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
2019-07-30Make write-under-write section for mems in spec (#1140)Albert Magyar
2019-01-31Add MidFIRRTL spec (#1003)Albert Magyar
2018-09-27Number all code examples & add specification build to Makefile (#894)Ben Marshall
2018-02-16Update spec for rhsSchuyler Eldridge
2017-12-24Spec erroneously says mod instead of rem.Paul Rigge
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
2016-07-27Fixed reg concrete syntax. #197.azidar
2016-05-23Updated spec. Changed dshl width to w(e) + 2^w(n) - 1. Changed fileinfo to ju...azidar
2016-02-23Updated pdfazidar
2016-02-09Added changes that addressed feedback, spec ready for releaseazidar
2016-01-22Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-memazidar
2016-01-22Added pdfazidar
2016-01-22Added funding number, as well as additional acknowledgementsazidar
2016-01-22Finished version 0.2.0. Included leftovers for future user manual.azidar
2016-01-21First cut, some unfinished sections but readableazidar
2016-01-20WIP, almost finished with expressions. Removed poison, add is invalid and val...azidar
2016-01-20WIP, need to update chirrtl with new mask syntaxazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks t...azidar
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16WIP adding chirrtlazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2015-10-06Updated spec to mention sign extending widths of operand inputsazidar
2015-08-31Changed Bulk to Partial, <> to <-, and := to <=azidar
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