sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-09-14	Added Rob.fir for regression testing (#258)	Donggyu

2016-02-25	Remove brittle rocket comparison to expected verilog test.	jackkoenig

2016-02-24	Make rocket-golden.v match output of #75	jackkoenig

2016-02-23	Add rocket regression, just runs rocket.fir through Verilog compiler and ↵	Jack
	compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
2016-02-09	CHIRRTL passes work, parser is updated	azidar

2016-02-09	Added rocket minus chirrtl features	azidar

2016-01-28	Update rocket regression	Andrew Waterman

2016-01-23	Update rocket regression	Andrew Waterman

2016-01-16	WIP need to correctly output readwrite ports	azidar

2015-08-26	Added regression test	azidar