| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-09-13 | Merge pull request #285 from ucb-bar/more_passes_cleanups | Donggyu | |
| More passes cleanups | |||
| 2016-09-13 | use case object for Kind | Donggyu Kim | |
| 2016-09-13 | clean up PadWidth | Donggyu Kim | |
| 2016-09-13 | clean up LowerTypes | Donggyu Kim | |
| no vars for mname, info | |||
| 2016-09-13 | clean up Passes.scala | Donggyu Kim | |
| 2016-09-13 | type aliases | Donggyu Kim | |
| 2016-09-13 | Merge pull request #284 from ucb-bar/more_utils_cleanups | Donggyu | |
| More utils cleanups | |||
| 2016-09-13 | remove Utils.{width_BANG, long_BANG} | Donggyu Kim | |
| 2016-09-13 | remove Utils.get_type | Donggyu Kim | |
| 2016-09-13 | use MemPortUtils.memType for DefMemory | Donggyu Kim | |
| 2016-09-13 | remove Utils.{mapr, get_name} and fix spaces | Donggyu Kim | |
| 2016-09-13 | MemPortUtils: return correct memory types | Donggyu Kim | |
| 2016-09-13 | clean up MemUtils | Donggyu Kim | |
| 2016-09-13 | Merge pull request #296 from ucb-bar/fix-bits-type-take3 | Jack Koenig | |
| Fix bits type | |||
| 2016-09-12 | Add LegalizeSpec for testing Verilog Legalization pass | Jack | |
| 2016-09-12 | Add legalization of pad operation on literals. | Jack | |
| Performing a pad on SInt literals results in linting warnings in Verilator. This commit replaces pad operations on literal values with a literal of the correct width. | |||
| 2016-09-12 | Cast bit select of SInt in PadWidths to SInt | Jack | |
| Fixes #172 | |||
| 2016-09-12 | Legalize bit select. Run Legalize after PadWidths. | Jack | |
| Bit selecting a literal resulted in invalid Verilog. Legalize now deals with this by replacing any bits select of UInt or SInt literals with a new literal composed of the selected bits. Legalize also is now run after PadWidths because that pass introduces this issue. Fixes #170 | |||
| 2016-09-12 | Change Legalize Connect to respect SInt | Jack | |
| Legalize will wrap the rhs of a connect statement with a bit select primop if the lhs is of smaller width than the rhs. This bit select is now wrapped in a asSInt cast if the original rhs was an SInt so that is has the correct type. Fixes #173 | |||
| 2016-09-12 | Change Legalize Shift Right to respect SInt | jackkoenig | |
| Fix bug where Legalize was generating a bit select for SInts without then casting to SInt Fixes #169 | |||
| 2016-09-12 | Change bitWidth to support ClockType | jackkoenig | |
| Match on GroundType instead of UIntType and SIntType | |||
| 2016-09-12 | Add unapply for GroundType | jackkoenig | |
| 2016-09-12 | Merge pull request #266 from ucb-bar/revamp-mappers | Donggyu | |
| Revamp mappers | |||
| 2016-09-12 | Change Mappers to Value Classes | jackkoenig | |
| 2016-09-12 | Rework map functions as class methods | jackkoenig | |
| Changed code from match statements in Mappers.scala to methods on the various IR classes. This allows custom IR nodes to implement the mapper functions and thus work (ie. not match error) when map is called on them. This also should have a marginal performance increase because of use of virtual function calls rather than match statements. | |||
| 2016-09-12 | Merge pull request #247 from ucb-bar/fix-invalid | Donggyu | |
| Bugfix: ExpandWhen was emitting WInvalid() | |||
| 2016-09-12 | Added test to check invalid bug was fixed | azidar | |
| 2016-09-12 | Fixed bug where nodes of Invalids where created | azidar | |
| 2016-09-12 | Bug fix -- remove all empty expressions after ReplSeqMem passes (#294) | Angie Wang | |
| * Bug fix -- remove all empty expressions after ReplSeqMem passes * Added test to make sure ReplSeqMem can handle BundleType SMem (EmptyExpression leakage) | |||
| 2016-09-08 | Merge pull request #288 from ucb-bar/revert-to-keyset-fix | Donggyu | |
| Revert to keyset | |||
| 2016-09-08 | Revert Expand Whens to process a set of connection lhs | jackkoenig | |
| 2016-09-08 | Remove brittle ReplSeqMemTest | jackkoenig | |
| This test is breaks with any minor change to code generation. It should be replaced with a more robust test. | |||
| 2016-09-08 | Merge pull request #283 from ucb-bar/refactor_expand_whens | Donggyu | |
| Refactor Passes | |||
| 2016-09-08 | memoize nodes in ExpandWhens | Donggyu Kim | |
| 2016-09-08 | remove Utils.{AND, OR, NOT, EQV} | Donggyu Kim | |
| hidden const props not desirable | |||
| 2016-09-08 | clean up ExpandWhens | Donggyu Kim | |
| 2016-09-08 | refactor RemoveCHIRRTL | Donggyu Kim | |
| 2016-09-08 | refactor resolves | Donggyu Kim | |
| 2016-09-08 | refactor InferTypes | Donggyu Kim | |
| 2016-09-08 | split Passes.scala into multiple files(InferTypes.scala, Resolves.scala, ↵ | Donggyu Kim | |
| RemoveCHIRRTL.scala) | |||
| 2016-09-08 | refactor InferWidths | Donggyu Kim | |
| 2016-09-07 | put InferWidths in a seperate file and fix spaces | Donggyu Kim | |
| 2016-09-07 | Merge pull request #282 from ucb-bar/refactor_checks | Donggyu | |
| Refactor checks | |||
| 2016-09-07 | refactor checks | Donggyu Kim | |
| 2016-09-07 | Merge pull request #276 from ucb-bar/cleanup_miscs | Donggyu | |
| Clean up WIR, PrimOps | |||
| 2016-09-07 | clean up PrimOps | Donggyu Kim | |
| 2016-09-07 | clean up miscs | Donggyu Kim | |
| 2016-09-07 | clean up WIR.scala | Donggyu Kim | |
| 2016-09-07 | Merge pull request #280 from ucb-bar/cleanup_passes | Donggyu | |
| Clean up passes | |||
| 2016-09-07 | Merge branch 'master' into cleanup_passes | Adam Izraelevitz | |
