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2018-10-03Make some Uniquify methods private [firrtl]Schuyler Eldridge
This makes findValidPrefix and enumerateNames both private to FIRRTL (previously, these were private). This enables their use for name generation by other FIRRTL passes/transforms. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-03Add cloneUnderlying method to NamespaceSchuyler Eldridge
This adds a method, cloneUnderlying, to Namespace that returns a copy of the underlying mutable.HashSet. This is useful for constructing a Namespace that you would like to manipulate manually without using Namespace's methods to generate temporaries. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
2018-09-27Number all code examples & add specification build to Makefile (#894)Ben Marshall
* Merge makefile changes from dev/specification-fixes - New top level makefile target: `specification` - Builds the specification document. * Number all code examples. This is more a change of convenience than anything. Referring to syntax examples is much easier when they are numbered! This commit is in the context of freechipsproject/firrtl#890 - Updating examples and syntax specification is made easier if they are numbered. - Change `verbatim` environments to `lstlisting` - Add very basic keyword highlighting. - Rebuild specification PDF. On branch dev/number-code-examples Changes to be committed: modified: spec/spec.pdf modified: spec/spec.tex
2018-09-27Add Utils.expandPrefixes as Prefix Unique helper (#900)Schuyler Eldridge
This adds a utility, expandPrefixes, that expands a string into all possible prefixes based on a delimiter. Any repeated occurrence of the delimiter is viewed as a contributing to a prefix. E.g., "foo_bar" expands to Seq("foo_", "foo_bar"). This is useful for inlining and keyword mangling on LowForm. You would like to be able to generate a new name that is prefix unique with respect to a namespace. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-26Merge pull request #898 from seldridge/port-uniqueness-checksSchuyler Eldridge
Enforce port uniqueness in Chirrtl/High Checks
2018-09-26Enforce port uniqueness in Chirrtl/High ChecksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-26Another TopWiring Bug Fix (Multi-Level Annotations) (#889)alonamid
When different levels of the circuit were annotated, the TopWiring signals of the lower levels would "run-over" the TopWiring signals of the higher levels
2018-09-21Add CODEOWNERS file (#895)Albert Magyar
2018-09-13Do not remove ExtMods with no ports by default (#888)albertchen-sifive
2018-09-07Bug Fixes in TopWiring (#885)alonamid
* bug fixes in TopWiring
2018-08-30Emit Verilog Comments (#874)albertchen-sifive
add description nodes, transform; modify VerilogEmitter to emit comments
2018-08-29Merge pull request #878 from ↵Schuyler Eldridge
seldridge/issue-764-refactor-pr-pointer-systemVerilogCompiler [F764.3] Add explicit SystemVerilogCompiler class Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-29Add SystemVerilogCompiler classSchuyler Eldridge
This adds a SystemVerilogCompiler class that extends, without modifying, the existing VerilogCompiler. This is used by FIRRTL's Driver and will cause a warning to be emitted indicating that the SystemVerilogCompiler behaves the same as the VerilogCompiler. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-29Merge pull request #875 from seldridge/issue-764-refactor-pr-pointerSchuyler Eldridge
[F764.1] Bump scopt from 3.6.0 -> 3.7.0 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-29Bump scopt from 3.6.0 -> 3.7.0Schuyler Eldridge
This provides support for increased introspection of options inside of scopt, e.g., getting an options short option (shortOpt). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-29Filter resource file names to avoid including the same file multiple times. ↵Jim Lawson
(#883) * Filter resource file names to avoid including the same file multiple times. Addresses issue #882. * Use a Set instead of a Map to filter Verilog files. * Use canonical paths for file name comparison and unify name generation. Provide a common method for copying resources to a directory to ensure the same resource ends up with the same name if it's copied by multiple clients. * Reduce confusion - another absolute -> canonical switch. Use the canonical path on the verilator command line for the filter additional Verilog sources.
2018-08-24Update DontTouchAnnotation not found error message (#864)Jack Koenig
2018-08-23Fix NoDedupMem to be cognizant of Module scope (#876)Jack Koenig
Previously, mems marked no dedup would prevent mems with the same instance name in other modules from deduping
2018-08-23Merge pull request #877 from seldridge/issue-764-refactor-pr-pointer-loglevelSchuyler Eldridge
[764: opts/annos] Easy conversion of String => LogLevel.value
2018-08-23Add LogLevel apply for String => LogLevel.ValueSchuyler Eldridge
This adds an apply method to the LogLevel object for conversion from a String to a LogLevel.value. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-21Merge pull request #872 from freechipsproject/randomize-delayAndrew Waterman
Allow the #delay before random initialization to be overridden
2018-08-21Allow the #delay before random initialization to be overriddenAndrew Waterman
The default of 0.002 can be less than the Verilog time precision, which effectively causes it to be rounded down to 0. So, allow the user to `define RANDOMIZE_DELAY to some other value. If the macro is not defined, the old behavior is preserved.
2018-08-21Make Scala 2.12.4 the default. (#848)Jim Lawson
* Bump to Scala 2.12.6 and make it the default. * Use Scala 2.11.12 for chisel tests. * Try with Scala 2.12.4.
2018-08-17Binding support (#854)Chick Markley
- Fixed edge case file name that starts with . and has no suffix
2018-08-14Add targetDirName test (#869)Leway Colin
2018-08-10allowing overrides to $random (#859)Deborah Soung
2018-08-08Use LinkedHashSet in propagateAnnotations (#855)albertchen-sifive
Fixes #780
2018-08-07Respect register references in RemoveWires (#868)Schuyler Eldridge
- makes RemoveWires properly include registers in dependency graph - adds an apply method to WRef for DefNode - adds a test case requiring register reordering
2018-08-07Make RemoveWires properly include registers in dependency graphJack Koenig
Fixes a bug where registers could be instantiated after nodes that referred to them Also add WRef.apply utility for nodes
2018-08-03add link to repo for firrtl syntax highlighting in sublime text 3kritik bhimani
2018-08-03Fix Travis (#858)Jack Koenig
2018-07-26Support for load memory annotations in chisel (#833)Chick Markley
* Support for load memory annotations in chisel This PR * Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler * remove from VerilogCompiler * move to VerilogEmitter * Changes the verilog emitter to allow programmatic access to the verilog module declaration * Creating a bindable module requires headers to match * Provides a unit test that shows how to generate a bindable module. * Binding support Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading * Binding support - Fixed bug that handled suffixes on memory initializing files * Binding support - Add a bit more doc to the API provided by the VerilogRenderer
2018-07-20Constant prop add (#849)albertchen-sifive
* add FoldADD to const prop, add yosys miter tests * add option for verilog compiler without optimizations * rename FoldLogicalOp to FoldCommutativeOp * add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation * add constant propagation for Tail DoPrims * add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim * add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
2018-07-11Make InstanceGraph have deterministic and use defined iteration order (#843)Jack Koenig
2018-07-10Fix bug in zero-width renaming (#845)Jack Koenig
Previously, Vecs of Bundles that contained a zero-width element would result in a ClassCastException
2018-07-10Combinational Dependency Annotation (#809)Adam Izraelevitz
2018-07-10InferWidths: improve performance (#846)edwardcwang
On circuits with large numbers of width inferences, prepend to a linked list instead of appending and having to make a copy. Fixes #842
2018-07-07Missing match on PassExceptions fixed. (#844)Chick Markley
This caused wrong message: "File a Firrtl Issue" Instead of the correct "Reference XX is not fully initialized"
2018-07-03Improve code generation for smem wmode and [w]mask ports (#834)Andrew Waterman
[skip formal checks] LEC passes with Formality * Improve code generation for smem RW-port wmode port A common case for these port-enables is wen = valid & write ren = valid & !write which the RW-port transform currently turns into en = (valid & write) | (valid & !write) wmode = valid & write because it proved `wen` and `ren` are mutually exclusive via `write`. Synthesis tools can trivially optimize `en` to `valid`, so that's not a problem, but the wmode field can't be optimized if going into a black box. This PR instead sets `wmode` to whatever node was used to prove mutual exclusion, which is always a simpler expression. In this case: en = (valid & write) | (valid & !write) wmode = write * In RemoveCHIRRTL, infer mask relative to port definition Previously, it was inferred relative to the memory definition causing the mask condition to be redundantly conjoined with the enable signal. Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to improve QoR.
2018-07-02Make ZeroWidth properly rename removed empty aggregates (#839)Jack Koenig
Fixes #756
2018-06-28Make CheckCombLoops find combinational nodes with self-edges (#837)Albert Magyar
2018-06-28Protobuf (#832)Jack Koenig
Add support for ProtoBuf serialization and deserialization * Add support for additional features in .proto description Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params * Add support for .pb input files This involves an API change where FIRRTL no longer implicitly adds .fir to input file names
2018-06-22Remove checkboxes from issue/pr templatesedwardcwang
Match https://github.com/freechipsproject/chisel3/pull/783
2018-06-21Provide a ProcessLogger() ot capture all output in isCommandAvailable(). (#831)Jim Lawson
2018-06-21--infer-rw should take no argument (#829)Schuyler Eldridge
This fixes --infer-rw to not expect an argument. After the annotations refactor, no option was required, but some legacy code remained. This also updates the test cases to be more correct and not specify an option to --infer-rw. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-06-18Bump ANTLR version and change directory to play nice with IntelliJ (#824)Jack Koenig
2018-06-15Improve Parser and Visitor (#819)Jack Koenig
* Update Parser to use ANTLR CharStreams This removes some unnecessary object creation in String reading and manipulation * Remove two unnecessary traversals from Block construction in Visitor
2018-06-14Fix TopWiringTests use of /tmp. (#825)Jim Lawson
Relying on /tmp as a place for test output will fail on multiuser systems and may fail if multiple instances of tests are running for the same user.
2018-06-13Resolve register clock dependencies in RemoveWires (#823)Schuyler Eldridge
Candidate fix for #749 This adds DefRegister netlist ordering to RemoveWires Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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