| Age | Commit message (Expand) | Author |
|---|
| 2016-01-24 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-mem | azidar |
| 2016-01-24 | Removed hashing as it made refchip slower to compile | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fix Verilog syntax errors for print/stop | Andrew Waterman |
| 2016-01-23 | Update rocket regression | Andrew Waterman |
| 2016-01-23 | Removed buggy optimization of dshr and dshl | azidar |
| 2016-01-23 | Moved inst declarations after other declarations | azidar |
| 2016-01-23 | Fixed commas for instances in verilog | azidar |
| 2016-01-23 | Added more semicolons | azidar |
| 2016-01-23 | Added semicolon after assigns in verilog | azidar |
| 2016-01-23 | off by one error when emitting ports in verilog | azidar |
| 2016-01-23 | Fixed combinational read verilog backend | azidar |
| 2016-01-23 | Removed more prints ;) | azidar |
| 2016-01-23 | Removed print statements | azidar |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar |
| 2016-01-23 | Removed debugging printlns | azidar |
| 2016-01-23 | Added inference to mports | azidar |
| 2016-01-23 | Added prefix checker, now compliant with firrtl spec | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-22 | Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-mem | azidar |
| 2016-01-22 | Added pdf | azidar |
| 2016-01-22 | Added a word | azidar |
| 2016-01-22 | Added funding number, as well as additional acknowledgements | azidar |
| 2016-01-22 | Finished version 0.2.0. Included leftovers for future user manual. | azidar |
| 2016-01-21 | First cut, some unfinished sections but readable | azidar |
| 2016-01-20 | WIP, almost finished with expressions. Removed poison, add is invalid and val... | azidar |
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar |
| 2016-01-20 | WIP: finished partial connect | azidar |
| 2016-01-19 | WIP: Writing new spec. | azidar |
| 2016-01-17 | Forgot to add the changes | azidar |
| 2016-01-17 | Fixed error where memory of size 1 would create an index of size 0. This can ... | azidar |
| 2016-01-17 | Added check for uint on access index type | azidar |
| 2016-01-17 | Removed temporary files | azidar |
| 2016-01-17 | BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests | azidar |
| 2016-01-16 | Add warning that -p unused | ducky |
| 2016-01-16 | Clean up old logging remnants | ducky |
| 2016-01-16 | Merge branch 'scala-new-mem' of github.com:ucb-bar/firrtl into scala-new-mem | ducky |
| 2016-01-16 | Ignore eclipse .project | ducky |
| 2016-01-16 | Import a logging library so we don't reinvent the wheel and have implicits fl... | ducky |
| 2016-01-16 | Refactor passes system | ducky |
| 2016-01-16 | Default platform-agnostic, ignore platform-specific FileCheck | ducky |
| 2016-01-16 | Update README with better Linux and Scala instructions | ducky |
| 2016-01-16 | Added notes for Richard to work on | azidar |
| 2016-01-16 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-mem | azidar |
| 2016-01-16 | Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignore | azidar |
| 2016-01-16 | Standard Verilog doesn't use Resolve(), but lists out the resolution passes i... | azidar |
| 2016-01-16 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-mem | azidar |
| 2016-01-16 | Fixed all tests so they either pass are marked as expected failures | azidar |
| 2016-01-16 | Added notes for Richard to work on | azidar |
| 2016-01-16 | Updated passes so they test new-mem | azidar |
