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2021-05-14Add JsonProtocol.serializeRecover (#2227)Jack Koenig
This function will safely wrap any unserializeable annotations in UnserializeableAnnotations so that they can be safely serialized to JSON for logging.
2021-05-14Update scala-parallel-collections to 1.0.3 (#2225)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-14Update sbt-mima-plugin to 0.9.1 (#2224)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-13Implement MFC-style source locator compression (#2212)Jared Barocsi
* Implement MFC-style source locator compression * Fix formatting issues * Fix emitting empty FileInfo if the firrtl doesn't have one * Remove '.scala' requirement in FileInfo parsing regex * Handle parsing of FileInfos with no line/col nums * Split FileInfos only if they match This should fix any issues with FileInfos that do not use the "file line:col" format, and allow any valid firrtl using these info comments to compile. * Add unit tests for locator compression * Move InfoTests to InfoSpec class * Fix existing unit tests with fileinfo comments * Add unit tests to ignore the algorithm's own output
2021-05-11Update sbt-scoverage to 1.8.0 (#2221)Scala Steward
2021-05-10Update sbt to 1.5.2 (#2220)Scala Steward
2021-05-09Update sbt-mima-plugin to 0.9.0 (#2217)Scala Steward
2021-05-04Make MustDeduplicateAnnotation deletable (#2215)Jack Koenig
2021-05-04Fix SBT deprecation warnings (#2214)Jack Koenig
2021-05-04Update sbt-scoverage to 1.7.3 (#2213)Scala Steward
2021-04-28Update sbt to 1.5.1 (#2205)Scala Steward
2021-04-28Update json4s-native to 3.6.11 (#2138)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Update sbt to 1.3.13 (#1730)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-04-28Update sbt-protobuf to 0.7.0 (#2134)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Update sbt-ci-release to 1.5.7 (#2148)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Update sbt-scalafix to 0.9.27 (#2161)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-04-28Update antlr4, antlr4-runtime to 4.9.2 (#2137)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Update sbt-scoverage to 1.7.0 (#2204)Scala Steward
2021-04-28Update scala-parallel-collections to 1.0.2 (#2163)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-04-28Update scalatest to 3.2.8 (#2194)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
* remove all deprecations, switch to new API. * Add MemLibOutConfigFileAnnotation to replace ConfWriter. * Inline CreateMemoryAnnotations in ReplSeqMem. * Dont use ConfWriter anymore. * Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation. * Fix for review. 0. Since DependencyAPI only initiate transform only once, ListBuffer is dangerous to use, remove defAnnotatedMemories from Transform. 1. Add trait HasAnnotatedMemories to store ListBuffer, MemLibOutConfigFileAnnotation also extends from which now. * Use two annotations converting and storing DefMemory. 0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation creating PinAnnotation. 1. add DumpMemoryAnnotations to convert from AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation 2. refactor MemLibOutConfigFileAnnotation and remove HasAnnotatedMemories 3. add private AnnotatedMemoriesCollectorAnnotation to store mutable DefAnnotatedMemory 4. change ReplSeqMem to SeqTransform * Fix for review. 0. replace AnnotatedMemoriesCollectorAnnotation with immutable AnnotatedMemoriesAnnotation. 1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute. * private functions in ReplaceMemMacros transform. * scalafmt * remove ConfWriter API.
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-22Fix CheckWidths error message for uninferred width (#2196)Fabian Schuiki
Looks like a typo/auto-merge hiccup.
2021-04-19Update .mergify.yml (#2181)github-actions[bot]
Co-authored-by: jackkoenig <jackkoenig@users.noreply.github.com>
2021-04-19Hoist Transform timing to the Phase level (#2190)Jack Koenig
With Stage/Phase, users can provide complex functionality at the phase level rather than just the transform level. It is useful to have the same logging information at that level. Note that this change still logs transforms in the same way, but now the time in inclusive of annotation renaming which can also [unfortunately] be slow. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-19Simplify "update .mergify.yml" workflow (#2192)Jack Koenig
2021-04-19Don't use declaration-assigns for wires representing mem ports (#2189)Albert Magyar
* Fixes #2173
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-04-16Fix signedness of xor const prop with zero (#2179)Fabian Schuiki
Constant propagation of the Xor op folds `xor(a, SInt(0))` to `asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can be a problem in the following case: circuit Foo : module Foo : input a: UInt<3> output b: UInt<4> b <= asUInt(xor(asSInt(a), SInt<4>(0))) This would emit the assignment as `b = a` instead of the sign-extended `b = {{1{a[2]}},a}`. This requires adjusting the `pad(e, t)` function use in const prop, which currently just inserts a `Pad` prim op with the requested output type. However, the function advertises that it pads *to the width* of the type `t`. Some of the folds rely on this and request the padding of a SInt<N> to the width of a UInt<M>. But the current implementation then then actually returns a `Pad` op with type UInt<M>, instead of the SInt<M> that was requested.
2021-04-15Add Workflow to automatically update .mergify.yml (#2180)Jack Koenig
Also make minor updates to CI workflow
2021-04-13Add indent parameter to Serializer.serialize() (#2177)Jared Barocsi
Using Utils.indent() gives deprecation warnings to use Serializer instead. However, the Serializer class itself doesn't provide a means to manually indent a FirrtlNode string a certain number of times. The indent variable, previously hardcoded to 0, is now exposed as a second parameter for the modified serialize function, and the old serialize function just calls the modified serialize with indents = 0 for binary compatibility Co-authored-by: Megan Wachs <megan@sifive.com>
2021-04-11smt: use existing bitWidth API (#2175)edwardcwang
* bitWidth: add scaladoc * smt: use existing bitWidth API
2021-04-06Deprecate InlineCasts, add InlineAcrossCasts (#2146)Jack Koenig
To maintain binary compatibility, InlineAcrossCasts is just aliases to the now deprecated InlineCasts. We can make the binary incompatible change of renaming the class and object for 1.5. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-05Merge pull request #2111 from chipsalliance/fpga-backendAlbert Magyar
Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)
2021-04-05Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDocAlbert Magyar
2021-04-05Add test for SeparateWriteClocksAlbert Magyar
2021-04-05Add --target:fpga flag to prioritize FPGA-friendly compilationAlbert Magyar
* Update name of FPGA flag based on Jack's comment * Add Scaladoc to describe what each constituent transform does * Add SeparateWriteClocks to --target:fpga
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
* Address @ekiwi comments from review * Change match cases to scalafmt-mandated lined-up style
2021-04-05Add tests for same-address readwrite inferenceAlbert Magyar
* Update test to include both 'old' and 'new' read-under-write values
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
* Optionally defines read-under-write behavior for all 'undefined' memories * Use DefaultReadFirstAnnotation to choose read-first default * Use DefaultWriteFirstAnnotation to choose write-first default * Seal DefaultReadUnderWriteAnnotation based on Jack's feedback
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
* This is enabled by adding a PassthroughSimpleSyncReadMemsAnnotation * Can be emitted directly with new changes to the Verilog emitter * Add some new deprecations to VerilogMemDelays * Run scalafmt on VerilogMemDelays
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
* Emit readwrite ports, if applicable * Does not change VerilogMemDelays -> no effect on default flow * Use more single-line declare-and-assign statements for mem wires * Update error messages for too-complex memories in VerilogEmitter * Run scalafmt on VerilogEmitter
2021-04-05Specify that SimplifyMems invalidates InferTypesAlbert Magyar
2021-04-04Fix mill cache download (#2171)Jiuyang Liu
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
This PR adds options for memory initialization inside or outside the `ifndef SYNTHESIS` block.
2021-03-30Fix Mill support for non-M1 Macs (#2165)Jack Koenig
* Fix Mill support for non-M1 Macs * Update build.sc Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com> Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com>
2021-03-30Update README.md (#2164)Jack Koenig
2021-03-30don't use protoc-jar anymore, mill can handle it better. (#2162)Jiuyang Liu
2021-03-29Update protobuf-java to 3.15.6 (#2136)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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