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2020-02-11Update junit to 4.13 (#1332)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-11Update protoc-jar to 3.11.1 (#1330)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-11Update sbt-unidoc to 0.4.2 (#1329)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-11Update sbt-buildinfo to 0.9.0 (#1328)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-11Update sbt-assembly to 0.14.10 (#1327)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
2020-02-11Update sbt-scalafix to 0.9.11 (#1326)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
2020-02-11[spec] Change sub(UInt, UInt) output type to UInt (#1378)Albert Magyar
2020-02-10Merge pull request #1370 from freechipsproject/issue-1309Schuyler Eldridge
Rename Modules Duplicated by EliminateTargetPaths
2020-02-10Test EliminateTargetPaths ModuleTarget anno dupingSchuyler Eldridge
Add a test that EliminateTargetPaths properly duplicates an annotation pointing at a ModuleTarget. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-10Rename modules when duplicating instancesSchuyler Eldridge
Change the behavior of EliminateTargetPaths to generate ModuleTarget renames when instances are duplicated. Previously, only InstanceTarget renames would be generated. In effect, annotations targeting a duplicated module when be duplicated to point at the original and duplicated module. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-10Add Target utility referringModuleSchuyler Eldridge
This adds a utility method, referringModule, to the Target object that behaves like IsMember.pathlessTarget except that it returns the module of an InstanceTarget. This is useful for situations where you want to get at "the module" a target is pointing at, but you want behavior to get an actual module from an instance. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-07Merge pull request #1366 from freechipsproject/dueling-const-propAlbert Magyar
Better register const prop through speculative de-optimization
2020-02-07Add extra 'de-optimization' opportunity for register const prop testAlbert Magyar
2020-02-07Refactor handling of reg const prop entries to cover more casesAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
* Fixes #1240 * Add failing reg const prop test case from #1240
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
* Add constant prop to async regs * Added another test of no reset value but constant assignment * Clarify name of updateNodeMap * Update constant assignment of async reset to not be inferred as a latch, works with donttouch * Revert "Update constant assignment of async reset to not be inferred as a latch, works with donttouch" This reverts commit 952bf38127cb32f814496a2b4b3bfb173d532728.
2020-02-06Merge pull request #1362 from freechipsproject/andr-reduction-base-caseSchuyler Eldridge
Change zero-width base case for Andr
2020-02-06Add note to spec about reductions on zero-width wiresAlbert Magyar
2020-02-06[Behavior change] Andr of zero-width wire now returns UIntLiteral(1)Albert Magyar
* Fixes #1344
2020-02-06Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)Albert Magyar
2020-02-03Dedup: check if moduleOpt exists before getting (#1323)Albert Chen
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-03Fix conversion of Reference-containing expressions to ReferenceTargets (#1349)Albert Magyar
2020-01-28add IsModule, IsMember, CompleteTarget serializers (#1321)Albert Chen
2020-01-21Refactoring checkCatArgumentLegality (#1317)Derek Pappas
2020-01-20clean up warnings: trim unused imports (#1315)John Ingalls
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
* transform InlineBitExtractions * InlineNotsTransform, InlineBitExtractionsTransform: inputForm/outputForm = UnknownForm * clean up some minor redundancies from Adam review * clarifications from Seldrige review
2020-01-15improve the tail ir usability. (#1241)Sequencer
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-15Filter ResolvePaths in EliminateTargetPaths (#1310)Schuyler Eldridge
Change EliminateTargetPaths to remove ResolvePaths annotations in the output AnnotationSeq. This prevents a bug whereby the upstream ResolvePaths annotations from previous runs of EliminateTargetPaths can result in unexpected duplication. Adds a test that checks that ResolvePaths annotations are actually removed. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-10Change LoggerState.globalLevel to Warn (#1307)Jim Lawson
* Change LoggerState.globalLevel to Warn PR #1305 changes the `globalLogLevel` in `LogLevelAnnotation` to from `None` to `Warn`. Update the default `LoggerState.globalLevel` to `Warn` as well. * Update LoggerSpec tests to match globalLogLevel of Warn * Add test of behavior for LogLevel.None
2020-01-10Change default LogLevel to Warn (#1305)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-01-09Dedup PassTests, add NoCircuitDedupAnnotations (#1302)Schuyler Eldridge
Change PassTests to include Dedup when running transforms. This makes PassTests behave more like an actual compiler. Fixes bugs in Inline, Flatten, and Grouping tests where the tests would only work without deduplication. This adds NoCircuiDedupAnnotations to prevent deduplication for the offending tests. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-01-07Merge pull request #1259 from freechipsproject/cleanup-testing-consoleJack Koenig
Cleanup testing console
2020-01-07Change printing of FIRRTL runtime from error to warnJack Koenig
2020-01-07Remove printlns from testsJack Koenig
2020-01-07Switch compileFirrtlTest from Driver to FirrtlStageJack Koenig
2020-01-07Redirect testing shell commands to loggerJack Koenig
This includes the built-in functions in BackendCompilationUtilities which are a public API
2020-01-07Merge pull request #1264 from freechipsproject/cleanup-verilog-emitter-castsJack Koenig
Cleanup verilog emitter casts
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
Many tools don't except 'always @(posedge 1'h0)' so we assign the literal to a wire and use that as the posedge target.
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
[skip formal checks] Adds new InlineCastsTransform to the VerilogEmitter which removes Statements that do nothing but cast by inlining the cast Expression
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-07Fix .run_formal_checks.sh skipping logic (#1297)Jack Koenig
Fetch and checkout the base branch before attempting to inspect the log
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
[skip formal checks] * ConstProp FoldEqual/FoldNotEqual propagate boolean (non-)equality with true/false * transform InlineNots * transform back-to-back Nots into straight rename * swap mux with inverted select Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2020-01-06Remove incorrect --firrtl-source option (#1266)Schuyler Eldridge
This removes the incorrect short --firrtl-source option. This was supposed to be the helpValueName. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-06Make EmittedAnnotation Unserializable (#1288)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-12-31Merge pull request #1291 from ↵Jack Koenig
freechipsproject/infer-resets-last-connect-semantics Infer resets last connect semantics
2019-12-30Minor code cleansup in InferResetsJack Koenig
* Move Map lookup into closure so it only occurs if necessary * Replace gender with flow and improve code clarity
2019-12-30Respect last connect semantics in InferResetsJack Koenig
InferResets will now support last connect semantics (within the same scope) when determining the concrete reset type for components of type Reset. This only includes *unconditional* last connects; it remains illegal to drive a component of type Reset with different concrete types under differing when conditions. For example, the following is now legal: input a : UInt<1> input b : AsyncReset output z : Reset z <= a z <= b The second connect will when and z will be of type AsyncReset. The following remains illegal: input a : UInt<1> input b : AsyncReset input c : UInt<1> output z : Reset z <= a when c : z <= b This commit also ensures that components of type Reset with no drivers (or only invalidation) default to type UInt<1>. This fixes a bug where the transform would crash with such input.
2019-12-18Improve Scaladoc (#1284)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-18Fix incorrect ScalaDoc link (#1282)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-16{Firrtl, Circuit}Option should be Unserializable (#1278)Schuyler Eldridge
FirrtlOption and CircuitOption represent, respectively, something that is convertible to FirrtlOptions or something that is convertible to a FirrtlCircuitAnnotation. Neither of these is intended to be serialized automatically in output JSON. This has the effect of *not* JSON-serializing the FirrtlCircuitAnnotation. This serialization is supposed to be to a file via an emitter. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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