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2021-04-28Update sbt to 1.3.13 (#1730)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-04-28Update sbt-protobuf to 0.7.0 (#2134)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Update sbt-ci-release to 1.5.7 (#2148)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Update sbt-scalafix to 0.9.27 (#2161)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-04-28Update antlr4, antlr4-runtime to 4.9.2 (#2137)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Update sbt-scoverage to 1.7.0 (#2204)Scala Steward
2021-04-28Update scala-parallel-collections to 1.0.2 (#2163)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-04-28Update scalatest to 3.2.8 (#2194)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
* remove all deprecations, switch to new API. * Add MemLibOutConfigFileAnnotation to replace ConfWriter. * Inline CreateMemoryAnnotations in ReplSeqMem. * Dont use ConfWriter anymore. * Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation. * Fix for review. 0. Since DependencyAPI only initiate transform only once, ListBuffer is dangerous to use, remove defAnnotatedMemories from Transform. 1. Add trait HasAnnotatedMemories to store ListBuffer, MemLibOutConfigFileAnnotation also extends from which now. * Use two annotations converting and storing DefMemory. 0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation creating PinAnnotation. 1. add DumpMemoryAnnotations to convert from AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation 2. refactor MemLibOutConfigFileAnnotation and remove HasAnnotatedMemories 3. add private AnnotatedMemoriesCollectorAnnotation to store mutable DefAnnotatedMemory 4. change ReplSeqMem to SeqTransform * Fix for review. 0. replace AnnotatedMemoriesCollectorAnnotation with immutable AnnotatedMemoriesAnnotation. 1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute. * private functions in ReplaceMemMacros transform. * scalafmt * remove ConfWriter API.
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-22Fix CheckWidths error message for uninferred width (#2196)Fabian Schuiki
Looks like a typo/auto-merge hiccup.
2021-04-19Update .mergify.yml (#2181)github-actions[bot]
Co-authored-by: jackkoenig <jackkoenig@users.noreply.github.com>
2021-04-19Hoist Transform timing to the Phase level (#2190)Jack Koenig
With Stage/Phase, users can provide complex functionality at the phase level rather than just the transform level. It is useful to have the same logging information at that level. Note that this change still logs transforms in the same way, but now the time in inclusive of annotation renaming which can also [unfortunately] be slow. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-19Simplify "update .mergify.yml" workflow (#2192)Jack Koenig
2021-04-19Don't use declaration-assigns for wires representing mem ports (#2189)Albert Magyar
* Fixes #2173
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-04-16Fix signedness of xor const prop with zero (#2179)Fabian Schuiki
Constant propagation of the Xor op folds `xor(a, SInt(0))` to `asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can be a problem in the following case: circuit Foo : module Foo : input a: UInt<3> output b: UInt<4> b <= asUInt(xor(asSInt(a), SInt<4>(0))) This would emit the assignment as `b = a` instead of the sign-extended `b = {{1{a[2]}},a}`. This requires adjusting the `pad(e, t)` function use in const prop, which currently just inserts a `Pad` prim op with the requested output type. However, the function advertises that it pads *to the width* of the type `t`. Some of the folds rely on this and request the padding of a SInt<N> to the width of a UInt<M>. But the current implementation then then actually returns a `Pad` op with type UInt<M>, instead of the SInt<M> that was requested.
2021-04-15Add Workflow to automatically update .mergify.yml (#2180)Jack Koenig
Also make minor updates to CI workflow
2021-04-13Add indent parameter to Serializer.serialize() (#2177)Jared Barocsi
Using Utils.indent() gives deprecation warnings to use Serializer instead. However, the Serializer class itself doesn't provide a means to manually indent a FirrtlNode string a certain number of times. The indent variable, previously hardcoded to 0, is now exposed as a second parameter for the modified serialize function, and the old serialize function just calls the modified serialize with indents = 0 for binary compatibility Co-authored-by: Megan Wachs <megan@sifive.com>
2021-04-11smt: use existing bitWidth API (#2175)edwardcwang
* bitWidth: add scaladoc * smt: use existing bitWidth API
2021-04-06Deprecate InlineCasts, add InlineAcrossCasts (#2146)Jack Koenig
To maintain binary compatibility, InlineAcrossCasts is just aliases to the now deprecated InlineCasts. We can make the binary incompatible change of renaming the class and object for 1.5. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-05Merge pull request #2111 from chipsalliance/fpga-backendAlbert Magyar
Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)
2021-04-05Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDocAlbert Magyar
2021-04-05Add test for SeparateWriteClocksAlbert Magyar
2021-04-05Add --target:fpga flag to prioritize FPGA-friendly compilationAlbert Magyar
* Update name of FPGA flag based on Jack's comment * Add Scaladoc to describe what each constituent transform does * Add SeparateWriteClocks to --target:fpga
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
* Address @ekiwi comments from review * Change match cases to scalafmt-mandated lined-up style
2021-04-05Add tests for same-address readwrite inferenceAlbert Magyar
* Update test to include both 'old' and 'new' read-under-write values
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
* Optionally defines read-under-write behavior for all 'undefined' memories * Use DefaultReadFirstAnnotation to choose read-first default * Use DefaultWriteFirstAnnotation to choose write-first default * Seal DefaultReadUnderWriteAnnotation based on Jack's feedback
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
* This is enabled by adding a PassthroughSimpleSyncReadMemsAnnotation * Can be emitted directly with new changes to the Verilog emitter * Add some new deprecations to VerilogMemDelays * Run scalafmt on VerilogMemDelays
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
* Emit readwrite ports, if applicable * Does not change VerilogMemDelays -> no effect on default flow * Use more single-line declare-and-assign statements for mem wires * Update error messages for too-complex memories in VerilogEmitter * Run scalafmt on VerilogEmitter
2021-04-05Specify that SimplifyMems invalidates InferTypesAlbert Magyar
2021-04-04Fix mill cache download (#2171)Jiuyang Liu
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
This PR adds options for memory initialization inside or outside the `ifndef SYNTHESIS` block.
2021-03-30Fix Mill support for non-M1 Macs (#2165)Jack Koenig
* Fix Mill support for non-M1 Macs * Update build.sc Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com> Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com>
2021-03-30Update README.md (#2164)Jack Koenig
2021-03-30don't use protoc-jar anymore, mill can handle it better. (#2162)Jiuyang Liu
2021-03-29Update protobuf-java to 3.15.6 (#2136)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
CSESubAccesses was intended to be a simple workaround for a quadratic performance bug in RemoveAccesses but ended up having tricky corner cases and was hard to get right. The solution to the RemoveAccesses bug--quadratic expansion of dynamic indexes of vecs of aggreate type--turned out to be quite simple and makes CSESubAccesses much less useful and not worth fixing. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-27Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)Jiuyang Liu
* add --no-constant-propagation to disable constant propagation * add test * deprecate DisableFold. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
* Fix bug in zero-width memory removal Correctly remove all extraneous connections to all types of memory ports (read, write, readwrite) for zero-width memories. Previously, only read ports were correctly handled. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Fix bug in zero-width memory removal
2021-03-25add scalafmt to mill (#2151)Jiuyang Liu
2021-03-22Fix mill compile and add to CI (#2147)Jiuyang Liu
* fix for #2071 * add mill compile to CI
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
This fixes an error with negating a negative SInt literal and a [debatable] lint warning in Verilator when negating any value. This behavior matches that of Chisel (which directly emits the 0 - x already).
2021-03-18Ensure InlineCasts does not inline complex Expressions (#2130)Jack Koenig
Previously, InlineCasts could inline complex (ie. non-cast) Expressions into other complex Expressions. Now it will only inline so long as there no more than 1 complex Expression in the current nested Expression. Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
Due to inlining of Boolean expressions, the following circuit is handled directly by the VerilogEmitter: input a: UInt<4> input b: SInt<1> output o: UInt<5> o <= dshl(a, asUInt(cvt(b))) Priot to this change, this could crash due to mishandling of cvt in the logic to inject parentheses based on Verilog precedence rules. This is a corner case, but similar bugs would drop up if we open up the VerilogEmitter to more expression inlining.
2021-03-14Fix width of constant propagation of SInt with zero (#2120)Jack Koenig
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
Previously, concatenating two SInts where one is of zero-width would return the non-zero-width SInt. This is incorrect because the output of Cat should be of type UInt. Now the ZeroWidth transform will introduce a cast when removing a Cat when the argument type is non-UInt.
2021-03-11Fix CSESubAccesses for SubAccesses with flips (#2112)Jack Koenig
The flow of a LHS SubAccess node may still be SourceFlow if the type of the Vec element has a flip. Tweak the logic of CSESubAccesses to check every Expression flow while recursing instead of just the flow of the final SubAccess. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-09Fix the readmem statements in nested block (#2109)Carlos Eduardo
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