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Fix ScalaDoc complaints; add sbt-site, sbt-ghpages boilerplate.
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Add support for top-level use of MiddleFirrtlCompiler.
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* Add pass that fixes up widths with modulus operator for verilog
* Add basic test for Verilog emission of Rem
* Oops, left in some printlns.
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Also base max dshl check on MaxWidth instead of just 31 bits
Resolves #320
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Also, delete run regression part of Installation since `sbt test` does that anyway
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If we execute tests somewhere other than the root of the firrtl project directory (in a parent project directory for examples), the resource file may not be where we expect it.
Also clean up imports.
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* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.
* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
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* Fixes for Annotation serialized/deserialize
Made serializer agree with deserializer on text representation
Re-ordered serializations of Named subclasses to be C or C.m or C.m.c where C=circuit, m=module, c=component
Note: component may contain dots
Added serialize deserialize tests to AnnotationSpec
Did some style cleanup on AnnotationSpec
Added explicit return tupe on SimpleTransformSpec#execute
* Make explicit Util.error
remove commented code
* Make Annotation#serialize a nicer format
fix import there and remove new on case class
* In firrtl Driver.execute use annotations passed in through optionsManager#firrtlOptions if nonEmpty
otherwise read the annotations in from an annotations file
Add new option to override this behavior, --force-append-anno-file will append annotations in file
to any that are passed in
A few other style fixes to Driver: remove new with case classes. don't use match when if(boolean) will do
* Added tests of malformed component and circuit names
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* Copy firrtl.jar to chisel3/lib to ensure correct version of Firrtl is used by
chisel3 tests
* Remove make commands in favor staying in current sbt session and warmed JVM
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Capitalize Firrtl and add Travis build status
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Also run CheckTypes after ExpandWhens
Fixes #330
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we will leave cleaning up their voluminous output for later
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FileInfo is merged
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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* Rewrote inline xform to fix quadratic perf. bug
Turns out caching previously inlined modules is not useful
The previous algorithm in a module, would flatten an instance's children, then
flatten that instance. This caused all instances to be effectively
inlined the number of times of its depth in the instance hierarchy,
making it O(n*d*s), where n is the number of instances, and d is the depth
of the instance, and s is the number of statements in the instance.
The new algorithm directly inlines a module by keeping track of the
parents of that instance, making it constant time with the number of
instantiated instances.
* Minor style fixes
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* Fixed multi wiring
* Minor style changes
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* Fix wrong omitting same clocked nondirect children
* Minor style fixes
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* Bugfix: removed recursive removal in infer widths
This will certainly lead to more uninferred width errors, but now widths
that were previously incorrectly inferred are now correctly uninferred.
An example is:
reg r : UInt, clock with: (reset => (reset, UInt<2>(3)))
node x = add(r, r)
r <= x
Here, r's width follows the following formula, which cannot be solved:
rWidth >= max(max(rWidth, rWidth) + 1, 2)
* Added optimizations to for better width inference
Also added exceptions for uninferred widths when checking DoPrim width
legality to not trigger compiler error
* Added additional optimizations
Required for passing all chisel3 tests
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Required for passing all chisel3 tests
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Also added exceptions for uninferred widths when checking DoPrim width
legality to not trigger compiler error
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This will certainly lead to more uninferred width errors, but now widths
that were previously incorrectly inferred are now correctly uninferred.
An example is:
reg r : UInt, clock with: (reset => (reset, UInt<2>(3)))
node x = add(r, r)
r <= x
Here, r's width follows the following formula, which cannot be solved:
rWidth >= max(max(rWidth, rWidth) + 1, 2)
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Added clocklist transform
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getMyAnnotations now returns Seq[Annotation]
Changed test to check number of annotations is the same
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Prefix temporary names with underscores so Verilator won't trace them
Use verilator argument "--trace-underscore" if you want to trace these
signals
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* handle uninferred ports gracefully in RemoveCHIRRTL
memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL
* fix CInferTypes
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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Add Legalize to MiddleToLowFirrtl
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Makes low firrtl more like a netlist, should probably update spec
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Fixes #329
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