diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/chirrtl/wacc-wdc.fir | 33 | ||||
| -rw-r--r-- | test/passes/expand-accessors/accessor-mem.fir | 36 |
2 files changed, 47 insertions, 22 deletions
diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir index 71b86d70..32b61c3b 100644 --- a/test/chirrtl/wacc-wdc.fir +++ b/test/chirrtl/wacc-wdc.fir @@ -6,19 +6,32 @@ circuit top : cmem m : UInt<4>[10] p <= UInt(1) when p : - write mport a = m[UInt(3)],clk + write mport a = m[UInt(3)],clk,UInt(1) a <= UInt(2) -; CHECK: Expand Whens +; CHECK: To FIRRTL -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: cmem m : UInt<4>[10], clk -; CHECK: write accessor a = m[UInt("h3")] -; CHECK: p <= UInt("h1") -; CHECK: when p : a <= UInt("h2") +; CHECK: mem m : +; CHECK: data-type: UInt<4> +; CHECK: depth: 10 +; CHECK: write-latency: 1 +; CHECK: read-latency: 0 +; CHECK: writer: a +; CHECK: poison GEN : UInt<4> +; CHECK: poison GEN_1 : UInt<4> +; CHECK: m.a.addr <= GEN +; CHECK: m.a.clk <= clk +; CHECK: m.a.en <= UInt("h0") +; CHECK: m.a.data <= GEN_1 +; CHECK: m.a.mask <= UInt("h0") +; CHECK: p <= UInt("h1") +; CHECK: when p : +; CHECK: m.a.addr <= UInt("h3") +; CHECK: m.a.en <= UInt("h1") +; CHECK: m.a.mask <= UInt("h1") +; CHECK: m.a.data <= UInt("h2") -; CHECK: Finished Expand Whens +; CHECK: Finished To FIRRTL +; CHECK: Done! diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index 6f64f57d..ce1d8da3 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -1,24 +1,36 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Accessors circuit top : module top : input clk : Clock - cmem m : UInt<32>[2][2][2], clk wire i : UInt<4> - i <= UInt(1) - infer accessor a = m[i] ;CHECK: read accessor a = m[i] - infer accessor b = a[i] ;CHECK: indexer b = (a[0] a[1])[i] : UInt<32>[2] - infer accessor c = b[i] ;CHECK: indexer c = (b[0] b[1])[i] : UInt<32> wire j : UInt<32> + wire z : UInt<32> + i <= UInt(1) + mem m : + data-type => UInt<32>[2] + depth => 2 + reader => a + writer => x + read-latency => 0 + write-latency => 1 + m.a.addr <= i + m.a.clk <= clk + m.a.en <= UInt(1) + m.x.addr <= i + m.x.clk <= clk + m.x.en <= UInt(1) + m.x.mask[0] <= UInt(1) + m.x.mask[1] <= UInt(1) + wire b : UInt<32>[2] + b <= m.a.data + node c = b[i] + z <= j j <= c - - infer accessor x = m[i] ;CHECK: write accessor x = m[i] - infer accessor y = x[i] ;CHECK: indexer (x[0] x[1])[i] = y : UInt<32>[2] + wire y : UInt<32>[2] y[0] <= UInt(1) y[1] <= UInt(1) - infer accessor z = y[i] ;CHECK: indexer (y[0] y[1])[i] = z : UInt<32> - z <= j + m.x.data <= y + y[i] <= z -; CHECK: Finished Expand Accessors ; CHECK: Done! |