5 files changed, 116 insertions, 17 deletions
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 3e1a02f5..2adba2b8 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -6,7 +6,7 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := sub-wrap(x, y)
+      q := sub-wrap-uu(x, y)
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -17,7 +17,7 @@ circuit top :
       reg y : UInt
       x.init := UInt(0)
       y.init := UInt(42)
-      when gt(x, y) :
+      when gt-uu(x, y) :
          inst s of subtracter
          s.x := x
          s.y := y
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal(v, UInt(0))
+      v := equal-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
new file mode 100644
index 00000000..f98d98da
--- /dev/null
+++ b/test/passes/infer-widths/simple.fir
@@ -0,0 +1,13 @@
+; RUN: firrtl %s abcefghipjk cT | tee %s.out | FileCheck %s
+
+;CHECK: Infer Widths
+circuit top :
+   module top :
+      wire e : UInt
+      wire x : UInt
+      reg y : UInt
+      y := mux-uu(e, UInt(1), equal-uu(gt-uu(x, x), UInt(0)))
+   
+
+; CHECK: Finished Infer Widths
+
diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir
index 0356597e..18e246a9 100644
--- a/test/passes/jacktest/bundlewire.fir
+++ b/test/passes/jacktest/bundlewire.fir
@@ -2,19 +2,16 @@
 
 ; CHECK: Expand Whens
 
-circuit BundleWire : 
-  module BundleWire : 
-    input in : { y : UInt(32), x : UInt(32) }
-    output outs : { y : UInt(32), x : UInt(32) }[4]
-    
-    wire coords : { y : UInt(32), x : UInt(32) }[4]
-    coords.0 := in
-    outs.0 := coords.0
-    coords.1 := in
-    outs.1 := coords.1
-    coords.2 := in
-    outs.2 := coords.2
-    coords.3 := in
-    outs.3 := coords.3
+circuit TestLower : 
+  module Inst :
+     input x : UInt
+     output y : UInt
+  module TestLower : 
+     mem m : {data : { w : UInt , x : UInt } tag : { y : UInt, z : UInt }}[8]
+     wire index : UInt
+     accessor r = m[index]
+
+     inst i of Inst
+     i.x := r
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
new file mode 100644
index 00000000..d8197112
--- /dev/null
+++ b/test/passes/jacktest/risc.fir
@@ -0,0 +1,69 @@
+; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s 
+; CHECK: Expand Whens
+circuit Risc : 
+  module Risc : 
+    output out : UInt(32)
+    output valid : UInt(1)
+    input boot : UInt(1)
+    input isWr : UInt(1)
+    input wrAddr : UInt(8)
+    input wrData : UInt(32)
+    
+    mem file : UInt(32)[256]
+    mem code : UInt(32)[256]
+    node T_51 = UInt(0, 8)
+    reg pc : UInt(8)
+    pc.init := T_51
+    node add_op = UInt(0, 1)
+    node imm_op = UInt(1, 1)
+    accessor inst = code[pc]
+    node op = bits(inst, 31, 24)
+    node rci = bits(inst, 23, 16)
+    node rai = bits(inst, 15, 8)
+    node rbi = bits(inst, 7, 0)
+    node T_52 = UInt(0, 1)
+    node T_53 = equal(rai, T_52)
+    node T_54 = UInt(0, 1)
+    accessor T_55 = file[rai]
+    node ra = mux(T_53, T_54, T_55)
+    node T_56 = UInt(0, 1)
+    node T_57 = equal(rbi, T_56)
+    node T_58 = UInt(0, 1)
+    accessor T_59 = file[rbi]
+    node rb = mux(T_57, T_58, T_59)
+    wire rc : UInt(32)
+    node T_60 = UInt(0, 1)
+    valid := T_60
+    node T_61 = UInt(0, 1)
+    out := T_61
+    node T_62 = UInt(0, 1)
+    rc := T_62
+    when isWr : 
+      accessor T_63 = code[wrAddr]
+      T_63 := wrData
+    else : when boot : 
+        node T_64 = UInt(0, 1)
+        pc := T_64
+      else : 
+        node T_65 = equal(add_op, op)
+        when T_65 : 
+          node T_66 = add-wrap(ra, rb)
+          rc := T_66
+        node T_67 = equal(imm_op, op)
+        when T_67 : 
+          node T_68 = shl(rai, 8)
+          node T_69 = bit-or(T_68, rbi)
+          rc := T_69
+        out := rc
+        node T_70 = UInt(255, 8)
+        node T_71 = equal(rci, T_70)
+        when T_71 : 
+          node T_72 = UInt(1, 1)
+          valid := T_72
+        else : 
+          accessor T_73 = file[rci]
+          T_73 := rc
+        node T_74 = UInt(1, 1)
+        node T_75 = add-wrap(pc, T_74)
+        pc := T_75
+; CHECK: Finished Expand Whens
diff --git a/test/passes/jacktest/testlower.fir b/test/passes/jacktest/testlower.fir
new file mode 100644
index 00000000..0356597e
--- /dev/null
+++ b/test/passes/jacktest/testlower.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl %s abcefghipj cg | tee %s.out | FileCheck %s 
+
+; CHECK: Expand Whens
+
+circuit BundleWire : 
+  module BundleWire : 
+    input in : { y : UInt(32), x : UInt(32) }
+    output outs : { y : UInt(32), x : UInt(32) }[4]
+    
+    wire coords : { y : UInt(32), x : UInt(32) }[4]
+    coords.0 := in
+    outs.0 := coords.0
+    coords.1 := in
+    outs.1 := coords.1
+    coords.2 := in
+    outs.2 := coords.2
+    coords.3 := in
+    outs.3 := coords.3
+
+; CHECK: Finished Expand Whens