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-rw-r--r--test/features/VerilogReg.fir17
-rw-r--r--test/passes/remove-accesses/bundle-vecs.fir44
-rw-r--r--test/passes/remove-accesses/init-vecs.fir15
-rw-r--r--test/passes/remove-accesses/simple.fir14
-rw-r--r--test/passes/remove-accesses/simple10.fir16
-rw-r--r--test/passes/remove-accesses/simple11.fir142
-rw-r--r--test/passes/remove-accesses/simple2.fir16
-rw-r--r--test/passes/remove-accesses/simple3.fir24
-rw-r--r--test/passes/remove-accesses/simple4.fir22
-rw-r--r--test/passes/remove-accesses/simple5.fir21
-rw-r--r--test/passes/remove-accesses/simple6.fir21
-rw-r--r--test/passes/remove-accesses/simple7.fir11
-rw-r--r--test/passes/remove-accesses/simple8.fir235
-rw-r--r--test/passes/remove-accesses/simple9.fir16
14 files changed, 614 insertions, 0 deletions
diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir
new file mode 100644
index 00000000..33c4417f
--- /dev/null
+++ b/test/features/VerilogReg.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit Poison :
+ module Poison :
+ input clk : Clock
+ input reset : UInt<1>
+ input p1 : UInt<1>
+ input p2 : UInt<1>
+ input p3 : UInt<1>
+ reg r : UInt<32>,clk,reset,r
+ when p1 :
+ r <= UInt(1)
+ when p2 :
+ r <= UInt(2)
+ when p3 :
+ r <= UInt(3)
+
diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir
new file mode 100644
index 00000000..13f9d8d6
--- /dev/null
+++ b/test/passes/remove-accesses/bundle-vecs.fir
@@ -0,0 +1,44 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+; CHECK: Remove Accesses
+circuit top :
+ module top :
+ wire i : UInt
+ i <= UInt(1)
+ wire j : UInt
+ j <= UInt(1)
+
+ wire a : { x : UInt<32>, flip y : UInt<32> }[2]
+ a[0].x <= UInt(1)
+ a[0].y <= UInt(1)
+ a[1].x <= UInt(1)
+ a[1].y <= UInt(1)
+
+ wire b : { x : UInt<32>, flip y : UInt<32> }
+ b <= a[i]
+ j <= b.x
+ b.y <= UInt(1)
+
+; CHECK: wire i : UInt<1>
+; CHECK: i <= UInt("h1")
+; CHECK: wire j : UInt<32>
+; CHECK: j <= UInt("h1")
+; CHECK: wire a : { x : UInt<32>, flip y : UInt<32>}[2]
+; CHECK: a[0].x <= UInt("h1")
+; CHECK: a[0].y <= UInt("h1")
+; CHECK: a[1].x <= UInt("h1")
+; CHECK: a[1].y <= UInt("h1")
+; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>}
+; CHECK: wire GEN : UInt<32>
+; CHECK: GEN <= a[0].x
+; CHECK: when eqv(UInt("h1"), i) : GEN <= a[1].x
+; CHECK: b.x <= GEN
+; CHECK: wire GEN_1 : UInt<32>
+; CHECK: when eqv(UInt("h0"), i) : a[0].y <= GEN_1
+; CHECK: when eqv(UInt("h1"), i) : a[1].y <= GEN_1
+; CHECK: GEN_1 <= b.y
+; CHECK: j <= b.x
+; CHECK: b.y <= UInt("h1")
+; CHECK: Finished Remove Access
+; CHECK: Done!
+
diff --git a/test/passes/remove-accesses/init-vecs.fir b/test/passes/remove-accesses/init-vecs.fir
new file mode 100644
index 00000000..d8eeec88
--- /dev/null
+++ b/test/passes/remove-accesses/init-vecs.fir
@@ -0,0 +1,15 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+ module top :
+ wire outs : UInt<32>[2][1]
+ outs[0][0] <= UInt(1)
+ outs[0][1] <= UInt(1)
+
+ wire out : UInt<32>[2]
+ out <= outs[UInt(0)]
+ out[0] <= UInt(1)
+
+; CHECK: Done!
+
+
diff --git a/test/passes/remove-accesses/simple.fir b/test/passes/remove-accesses/simple.fir
new file mode 100644
index 00000000..1a64d321
--- /dev/null
+++ b/test/passes/remove-accesses/simple.fir
@@ -0,0 +1,14 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+ module top :
+ output o : UInt
+ wire m : UInt<32>[2]
+ wire i : UInt
+ m[0] <= UInt("h1")
+ m[1] <= UInt("h1")
+ i <= UInt("h1")
+ node a = m[i]
+ o <= a
+
+;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple10.fir b/test/passes/remove-accesses/simple10.fir
new file mode 100644
index 00000000..b213f372
--- /dev/null
+++ b/test/passes/remove-accesses/simple10.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Done!
+
+circuit DecoupledAdderTests :
+ module DecoupledAdderTests :
+ input clock : Clock
+ input reset : UInt<1>
+ input T_31 : UInt<1>
+ input T_68 : UInt<1>
+ output out : UInt
+ output io : {}
+ wire T_43 : {flip ready : UInt<1>}[1]
+ T_43[0].ready <= UInt(0)
+ node T_78 = and(T_68, T_43[T_31].ready)
+ out <= T_78
diff --git a/test/passes/remove-accesses/simple11.fir b/test/passes/remove-accesses/simple11.fir
new file mode 100644
index 00000000..e35bfb3c
--- /dev/null
+++ b/test/passes/remove-accesses/simple11.fir
@@ -0,0 +1,142 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Done!
+
+circuit DecoupledAdderTests :
+ module NewDecoupledAdder :
+ input clock : Clock
+ input reset : UInt<1>
+ output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {c : UInt<16>}}}
+
+ io.out.bits.c <= UInt<1>("h00")
+ io.out.valid <= UInt<1>("h00")
+ io.in.ready <= UInt<1>("h00")
+ reg ready : UInt<1>, clock, reset, ready
+ reg busy : UInt<1>, clock, reset, busy
+ reg a_reg : UInt<16>, clock, reset, a_reg
+ reg b_reg : UInt<16>, clock, reset, b_reg
+ io.in.ready <= ready
+ when io.in.valid :
+ a_reg <= io.in.bits.a
+ b_reg <= io.in.bits.b
+ io.in.ready <= UInt<1>("h00")
+ ready <= UInt<1>("h00")
+ busy <= UInt<1>("h01")
+ skip
+ node T_45 = and(busy, io.out.ready)
+ when T_45 :
+ node T_46 = addw(a_reg, b_reg)
+ io.out.bits.c <= T_46
+ io.out.valid <= UInt<1>("h01")
+ io.in.ready <= UInt<1>("h01")
+ busy <= UInt<1>("h00")
+ skip
+
+ module DecoupledAdderTests :
+ input clock : Clock
+ input reset : UInt<1>
+ output io : {}
+
+ inst device_under_test of NewDecoupledAdder
+ device_under_test.io.out.ready <= UInt<1>("h00")
+ device_under_test.io.in.bits.b <= UInt<1>("h00")
+ device_under_test.io.in.bits.a <= UInt<1>("h00")
+ device_under_test.io.in.valid <= UInt<1>("h00")
+ device_under_test.clock <= clock
+ device_under_test.reset <= reset
+ reg T_10 : UInt<33>, clock, reset, UInt<33>("h00")
+ node T_12 = addw(T_10, UInt<1>("h01"))
+ T_10 <= T_12
+ node T_14 = eq(reset, UInt<1>("h00"))
+ when T_14 :
+ printf(clock,UInt(1), "ticker %d", T_10)
+ skip
+ node T_16 = gt(T_10, UInt<7>("h064"))
+ when T_16 :
+ node T_18 = eq(reset, UInt<1>("h00"))
+ when T_18 :
+ stop(clock,UInt(1), 0)
+ skip
+ skip
+ node T_20 = eq(reset, UInt<1>("h00"))
+ when T_20 :
+ printf(clock,UInt(1), "device out ready %d, valid %d", device_under_test.io.out.ready, device_under_test.io.out.valid)
+ skip
+ node T_22 = eq(reset, UInt<1>("h00"))
+ when T_22 :
+ printf(clock,UInt(1), "device in ready %d, valid %d", device_under_test.io.in.ready, device_under_test.io.in.valid)
+ skip
+ reg T_24 : UInt<1>, clock, reset, UInt<1>("h00")
+ reg T_26 : UInt<1>, clock, reset, UInt<1>("h00")
+ node T_27 = and(T_24, T_26)
+ when T_27 :
+ node T_29 = eq(reset, UInt<1>("h00"))
+ when T_29 :
+ stop(clock,UInt(1), 0)
+ skip
+ skip
+ reg T_31 : UInt<1>, clock, reset, UInt<1>("h00")
+ reg T_33 : UInt<1>, clock, reset, UInt<1>("h00")
+ wire T_43 : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}[1]
+ T_43[0].bits.b <= UInt(0)
+ T_43[0].bits.a <= UInt(1)
+ T_43[0].valid <= UInt(1)
+ device_under_test.io.in <- T_43[0]
+ wire T_64 : UInt<16>[1]
+ T_64[0] <= UInt<16>("h04")
+ node T_68 = eq(T_24, UInt<1>("h00"))
+ node T_78 = and(T_68, T_43[T_31].ready)
+ when T_78 :
+ node T_80 = eq(reset, UInt<1>("h00"))
+ when T_80 :
+ printf(clock,UInt(1), "input_event_counter %d", T_31)
+ skip
+ device_under_test.io.in.bits.a <= T_64[T_31]
+ skip
+ wire T_84 : UInt<16>[1]
+ T_84[0] <= UInt<16>("h07")
+ node T_88 = eq(T_24, UInt<1>("h00"))
+ node T_98 = and(T_88, T_43[T_31].ready)
+ when T_98 :
+ node T_100 = eq(reset, UInt<1>("h00"))
+ when T_100 :
+ printf(clock,UInt(1), "input_event_counter %d", T_31)
+ skip
+ device_under_test.io.in.bits.b <= T_84[T_31]
+ skip
+ node T_103 = eq(T_24, UInt<1>("h00"))
+ node T_113 = and(T_103, T_43[T_31].ready)
+ when T_113 :
+ T_43[T_31].valid <= UInt<1>("h01")
+ node T_125 = addw(T_31, UInt<1>("h01"))
+ T_31 <= T_125
+ node T_127 = geq(T_31, UInt<1>("h00"))
+ T_24 <= T_127
+ skip
+ node T_129 = eq(T_26, UInt<1>("h00"))
+ when T_129 :
+ node T_131 = addw(T_33, UInt<1>("h01"))
+ T_33 <= T_131
+ node T_133 = geq(T_33, UInt<1>("h00"))
+ T_26 <= T_133
+ skip
+ wire T_136 : UInt<1>[1]
+ T_136[0] <= UInt<1>("h01")
+ wire T_141 : UInt<16>[1]
+ T_141[0] <= UInt<16>("h03")
+ node T_145 = eq(T_26, UInt<1>("h00"))
+ node T_147 = and(T_145, T_136[T_33])
+ node T_148 = and(T_147, device_under_test.io.out.valid)
+ when T_148 :
+ node T_150 = eq(reset, UInt<1>("h00"))
+ when T_150 :
+ printf(clock,UInt(1), "output_event_counter %d", T_33)
+ skip
+ node T_152 = neq(device_under_test.io.out.bits.c, T_141[T_33])
+ when T_152 :
+ node T_155 = eq(reset, UInt<1>("h00"))
+ when T_155 :
+ printf(clock,UInt(1), "Error: event %d out.bits.c was %x should be %x", T_33, device_under_test.io.out.bits.c, T_141[T_33])
+ skip
+ skip
+ skip
diff --git a/test/passes/remove-accesses/simple2.fir b/test/passes/remove-accesses/simple2.fir
new file mode 100644
index 00000000..ee6b5923
--- /dev/null
+++ b/test/passes/remove-accesses/simple2.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+ module top :
+ output o1 : UInt
+ output o2 : UInt
+ wire m : UInt<32>[2]
+ wire i : UInt
+ m[0] <= UInt("h1")
+ m[1] <= UInt("h1")
+ i <= UInt("h1")
+ node a = m[i]
+ o1 <= a
+ o2 <= a
+
+;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir
new file mode 100644
index 00000000..c7d00aff
--- /dev/null
+++ b/test/passes/remove-accesses/simple3.fir
@@ -0,0 +1,24 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Remove Accesses
+circuit top :
+ module top :
+ input in : UInt<32>
+ input i : UInt<1>
+ wire m : UInt<32>[2]
+ m[0] <= UInt("h1")
+ m[1] <= UInt("h1")
+ wire a : UInt<32>
+ m[i] <= a
+ a <= in
+
+;CHECK: wire GEN : UInt<32>
+;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN
+;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN
+;CHECK: GEN <= a
+
+;CHECK: Finished Remove Accesses
+
+
+
+;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir
new file mode 100644
index 00000000..4772c549
--- /dev/null
+++ b/test/passes/remove-accesses/simple4.fir
@@ -0,0 +1,22 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Remove Accesses
+circuit top :
+ module top :
+ input in : {x : UInt<32>, y : UInt<32>}
+ input i : UInt<1>
+ wire m : {x : UInt<32>, y : UInt<32>}[2]
+ m[0].x <= UInt("h1")
+ m[0].y <= UInt("h1")
+ m[1].x <= UInt("h1")
+ m[1].y <= UInt("h1")
+ m[i].x <= in.x
+
+;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN
+;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN
+;CHECK: GEN <= in
+;CHECK: Finished Remove Accesses
+;CHECK: Done!
+
+
+
diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir
new file mode 100644
index 00000000..099f020c
--- /dev/null
+++ b/test/passes/remove-accesses/simple5.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Remove Accesses
+circuit top :
+ module top :
+ output o : UInt
+ o <= UInt(1)
+ wire m : UInt<32>[2]
+ wire i : UInt
+ m[0] <= UInt("h1")
+ m[1] <= UInt("h1")
+ i <= UInt("h1")
+ when i :
+ o <= m[i]
+
+;CHECK: when i :
+;CHECK: GEN <= m[0]
+;CHECK: when eqv(UInt("h1"), i) : GEN <= m[1]
+;CHECK: o <= GEN
+;CHECK: Finished Remove Accesses
+;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple6.fir b/test/passes/remove-accesses/simple6.fir
new file mode 100644
index 00000000..eee62681
--- /dev/null
+++ b/test/passes/remove-accesses/simple6.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Remove Accesses
+circuit top :
+ module top :
+ input value : UInt<32>
+ input in : {x : UInt<32>, y : UInt<32>}
+ wire m :{x : UInt<32>, y : UInt<32>}[2][2]
+ wire i : UInt
+ wire j : UInt
+
+ m[0][0] <= in
+ m[1][0] <= in
+ m[0][1] <= in
+ m[1][1] <= in
+ i <= UInt("h1")
+ j <= UInt("h1")
+
+ m[i][j].x <= value
+
+;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple7.fir b/test/passes/remove-accesses/simple7.fir
new file mode 100644
index 00000000..5dfd5ce3
--- /dev/null
+++ b/test/passes/remove-accesses/simple7.fir
@@ -0,0 +1,11 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+ module top :
+ output out : UInt<64>
+ input index : UInt<1>
+ wire T_292 : UInt<64>[2]
+ T_292[0] <= UInt(1)
+ T_292[1] <= UInt(1)
+ out <= T_292[index]
+;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple8.fir b/test/passes/remove-accesses/simple8.fir
new file mode 100644
index 00000000..ae0d1ffd
--- /dev/null
+++ b/test/passes/remove-accesses/simple8.fir
@@ -0,0 +1,235 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+ module top :
+ output resp : UInt<128>[4]
+ input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}
+ input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}
+ input clock : Clock
+ input reset : UInt<1>
+
+ resp[0] <= UInt<1>("h00")
+ resp[1] <= UInt<1>("h00")
+ resp[2] <= UInt<1>("h00")
+ resp[3] <= UInt<1>("h00")
+ write.ready <= UInt<1>("h00")
+ read.ready <= UInt<1>("h00")
+ node waddr = shr(write.bits.addr, 4)
+ node raddr = shr(read.bits.addr, 4)
+ node T_65 = bits(write.bits.way_en, 1, 0)
+ node T_66 = bits(read.bits.way_en, 1, 0)
+ wire T_75 : UInt<128>[2]
+ T_75[0] <= UInt<1>("h00")
+ T_75[1] <= UInt<1>("h00")
+ reg T_81 : UInt<12>, clock, reset, T_81
+ when read.valid :
+ T_81 <= read.bits.addr
+ skip
+ cmem T_84 : UInt<128>[256]
+ node T_86 = neq(T_65, UInt<1>("h00"))
+ node T_87 = and(T_86, write.valid)
+ node T_88 = bit(write.bits.wmask, 0)
+ node T_89 = and(T_87, T_88)
+ when T_89 :
+ node T_90 = bits(write.bits.data, 63, 0)
+ node T_91 = cat(T_90, T_90)
+ node T_92 = bit(T_65, 0)
+ node T_93 = bit(T_65, 1)
+ wire T_95 : UInt<1>[2]
+ T_95[0] <= T_92
+ T_95[1] <= T_93
+ node T_100 = subw(UInt<64>("h00"), T_95[0])
+ node T_102 = subw(UInt<64>("h00"), T_95[1])
+ wire T_104 : UInt<64>[2]
+ T_104[0] <= T_100
+ T_104[1] <= T_102
+ node T_108 = cat(T_104[1], T_104[0])
+ read mport T_109 = T_84[waddr],clock
+ node T_110 = not(T_108)
+ node T_111 = and(T_109, T_110)
+ node T_112 = and(T_91, T_108)
+ node T_113 = or(T_111, T_112)
+ wire T_114 : UInt<128>
+ T_114 <= UInt<1>("h00")
+ T_114 <= T_113
+ write mport T_116 = T_84[waddr],clock,UInt(1)
+ T_116 <= T_114
+ skip
+ node T_118 = neq(T_66, UInt<1>("h00"))
+ node T_119 = and(T_118, read.valid)
+ reg T_120 : UInt<8>, clock, reset, T_120
+ when T_119 :
+ T_120 <= raddr
+ skip
+ read mport T_121 = T_84[T_120],clock
+ T_75[0] <= T_121
+ cmem T_124 : UInt<128>[256]
+ node T_126 = neq(T_65, UInt<1>("h00"))
+ node T_127 = and(T_126, write.valid)
+ node T_128 = bit(write.bits.wmask, 1)
+ node T_129 = and(T_127, T_128)
+ when T_129 :
+ node T_130 = bits(write.bits.data, 127, 64)
+ node T_131 = cat(T_130, T_130)
+ node T_132 = bit(T_65, 0)
+ node T_133 = bit(T_65, 1)
+ wire T_135 : UInt<1>[2]
+ T_135[0] <= T_132
+ T_135[1] <= T_133
+ node T_140 = subw(UInt<64>("h00"), T_135[0])
+ node T_142 = subw(UInt<64>("h00"), T_135[1])
+ wire T_144 : UInt<64>[2]
+ T_144[0] <= T_140
+ T_144[1] <= T_142
+ node T_148 = cat(T_144[1], T_144[0])
+ read mport T_149 = T_124[waddr],clock
+ node T_150 = not(T_148)
+ node T_151 = and(T_149, T_150)
+ node T_152 = and(T_131, T_148)
+ node T_153 = or(T_151, T_152)
+ wire T_154 : UInt<128>
+ T_154 <= UInt<1>("h00")
+ T_154 <= T_153
+ write mport T_156 = T_124[waddr],clock,UInt(1)
+ T_156 <= T_154
+ skip
+ node T_158 = neq(T_66, UInt<1>("h00"))
+ node T_159 = and(T_158, read.valid)
+ reg T_160 : UInt<8>, clock, reset, T_160
+ when T_159 :
+ T_160 <= raddr
+ skip
+ read mport T_161 = T_124[T_160],clock
+ T_75[1] <= T_161
+ node T_162 = bits(T_75[0], 63, 0)
+ node T_163 = bits(T_75[1], 63, 0)
+ wire T_165 : UInt<64>[2]
+ T_165[0] <= T_162
+ T_165[1] <= T_163
+ node T_169 = bits(T_81, 3, 3)
+ wire T_172 : UInt<64>[2]
+ T_172[0] <= T_165[T_169]
+ T_172[1] <= T_165[1]
+ node T_176 = cat(T_172[1], T_172[0])
+ resp[0] <= T_176
+ node T_177 = bits(T_75[0], 127, 64)
+ node T_178 = bits(T_75[1], 127, 64)
+ wire T_180 : UInt<64>[2]
+ T_180[0] <= T_177
+ T_180[1] <= T_178
+ node T_184 = bits(T_81, 3, 3)
+ wire T_187 : UInt<64>[2]
+ T_187[0] <= T_180[T_184]
+ T_187[1] <= T_180[1]
+ node T_191 = cat(T_187[1], T_187[0])
+ resp[1] <= T_191
+ node T_192 = bits(write.bits.way_en, 3, 2)
+ node T_193 = bits(read.bits.way_en, 3, 2)
+ wire T_202 : UInt<128>[2]
+ T_202[0] <= UInt<1>("h00")
+ T_202[1] <= UInt<1>("h00")
+ reg T_208 : UInt<12>, clock, reset, T_208
+ when read.valid :
+ T_208 <= read.bits.addr
+ skip
+ cmem T_211 : UInt<128>[256]
+ node T_213 = neq(T_192, UInt<1>("h00"))
+ node T_214 = and(T_213, write.valid)
+ node T_215 = bit(write.bits.wmask, 0)
+ node T_216 = and(T_214, T_215)
+ when T_216 :
+ node T_217 = bits(write.bits.data, 63, 0)
+ node T_218 = cat(T_217, T_217)
+ node T_219 = bit(T_192, 0)
+ node T_220 = bit(T_192, 1)
+ wire T_222 : UInt<1>[2]
+ T_222[0] <= T_219
+ T_222[1] <= T_220
+ node T_227 = subw(UInt<64>("h00"), T_222[0])
+ node T_229 = subw(UInt<64>("h00"), T_222[1])
+ wire T_231 : UInt<64>[2]
+ T_231[0] <= T_227
+ T_231[1] <= T_229
+ node T_235 = cat(T_231[1], T_231[0])
+ read mport T_236 = T_211[waddr],clock
+ node T_237 = not(T_235)
+ node T_238 = and(T_236, T_237)
+ node T_239 = and(T_218, T_235)
+ node T_240 = or(T_238, T_239)
+ wire T_241 : UInt<128>
+ T_241 <= UInt<1>("h00")
+ T_241 <= T_240
+ write mport T_243 = T_211[waddr],clock,UInt(1)
+ T_243 <= T_241
+ skip
+ node T_245 = neq(T_193, UInt<1>("h00"))
+ node T_246 = and(T_245, read.valid)
+ reg T_247 : UInt<8>, clock, reset, T_247
+ when T_246 :
+ T_247 <= raddr
+ skip
+ read mport T_248 = T_211[T_247],clock
+ T_202[0] <= T_248
+ cmem T_251 : UInt<128>[256]
+ node T_253 = neq(T_192, UInt<1>("h00"))
+ node T_254 = and(T_253, write.valid)
+ node T_255 = bit(write.bits.wmask, 1)
+ node T_256 = and(T_254, T_255)
+ when T_256 :
+ node T_257 = bits(write.bits.data, 127, 64)
+ node T_258 = cat(T_257, T_257)
+ node T_259 = bit(T_192, 0)
+ node T_260 = bit(T_192, 1)
+ wire T_262 : UInt<1>[2]
+ T_262[0] <= T_259
+ T_262[1] <= T_260
+ node T_267 = subw(UInt<64>("h00"), T_262[0])
+ node T_269 = subw(UInt<64>("h00"), T_262[1])
+ wire T_271 : UInt<64>[2]
+ T_271[0] <= T_267
+ T_271[1] <= T_269
+ node T_275 = cat(T_271[1], T_271[0])
+ read mport T_276 = T_251[waddr],clock
+ node T_277 = not(T_275)
+ node T_278 = and(T_276, T_277)
+ node T_279 = and(T_258, T_275)
+ node T_280 = or(T_278, T_279)
+ wire T_281 : UInt<128>
+ T_281 <= UInt<1>("h00")
+ T_281 <= T_280
+ write mport T_283 = T_251[waddr],clock,UInt(1)
+ T_283 <= T_281
+ skip
+ node T_285 = neq(T_193, UInt<1>("h00"))
+ node T_286 = and(T_285, read.valid)
+ reg T_287 : UInt<8>, clock, reset, T_287
+ when T_286 :
+ T_287 <= raddr
+ skip
+ read mport T_288 = T_251[T_287],clock
+ T_202[1] <= T_288
+ node T_289 = bits(T_202[0], 63, 0)
+ node T_290 = bits(T_202[1], 63, 0)
+ wire T_292 : UInt<64>[2]
+ T_292[0] <= T_289
+ T_292[1] <= T_290
+ node T_296 = bits(T_208, 3, 3)
+ wire T_299 : UInt<64>[2]
+ T_299[0] <= T_292[T_296]
+ T_299[1] <= T_292[1]
+ node T_303 = cat(T_299[1], T_299[0])
+ resp[2] <= T_303
+ node T_304 = bits(T_202[0], 127, 64)
+ node T_305 = bits(T_202[1], 127, 64)
+ wire T_307 : UInt<64>[2]
+ T_307[0] <= T_304
+ T_307[1] <= T_305
+ node T_311 = bits(T_208, 3, 3)
+ wire T_314 : UInt<64>[2]
+ T_314[0] <= T_307[T_311]
+ T_314[1] <= T_307[1]
+ node T_318 = cat(T_314[1], T_314[0])
+ resp[3] <= T_318
+ read.ready <= UInt<1>("h01")
+ write.ready <= UInt<1>("h01")
+;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple9.fir b/test/passes/remove-accesses/simple9.fir
new file mode 100644
index 00000000..5405c42a
--- /dev/null
+++ b/test/passes/remove-accesses/simple9.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+ module top :
+ input T_4910 : UInt<1>
+ input T_4581 : UInt<1>
+ input reset : UInt<1>
+ input clock : Clock
+ output out : UInt<1>
+ reg T_4590 : UInt<1>[2], clock, reset, T_4590
+ T_4590[0] <= UInt(0)
+ T_4590[1] <= UInt(0)
+ out <= UInt(0)
+ when T_4910 :
+ out <= T_4590[T_4581]
+;CHECK: Done!
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 12:24:04 +0000