3 files changed, 36 insertions, 26 deletions
diff --git a/test/features/CondRead.fir b/test/features/CondRead.fir
deleted file mode 100644
index 5dd1d321..00000000
--- a/test/features/CondRead.fir
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
-circuit CondRead :
-  module CondRead :
-    input pred : UInt<1>
-    input index : UInt<6>
-    input clk : Clock
-    output out : UInt<20>
-
-    smem mem : UInt<20>[128],clk
-    
-    poison xxx : UInt<6>
-    wire data : UInt<20>
-    read accessor readport = mem[mux(pred,index,xxx)]
-    out <= readport
-
-
-; CHECK: read accessor readport = mem[mux(pred,index,index_0)]
-; CHECK: Done!
-
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir
index 356b5a68..5a81a62e 100644
--- a/test/features/InitAccessor.fir
+++ b/test/features/InitAccessor.fir
@@ -1,14 +1,13 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
+
 ;CHECK: Done!
 circuit Top : 
    module Top :
       input in : UInt<1>
       wire b : UInt<1>[3]
-      b.0 <= UInt(1)
-      b.1 <= UInt(1)
-      b.2 <= UInt(1)
+      b[0] <= UInt(1)
+      b[1] <= UInt(1)
+      b[2] <= UInt(1)
       node c = UInt(1)
-      infer accessor a = b[c]
       when in : 
-         a <= UInt(1)
+         b[c] <= UInt(1)
diff --git a/test/features/NestedAccess.fir b/test/features/NestedAccess.fir
new file mode 100644
index 00000000..bd3c436d
--- /dev/null
+++ b/test/features/NestedAccess.fir
@@ -0,0 +1,31 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p cw 2>&1 | tee %s.out | FileCheck %s
+;CHECK: Expand Connects
+circuit Top : 
+  module Top : 
+    input i : UInt<1>
+    input j : UInt<1>
+    wire a : { x : UInt<42> flip y : UInt<42>[2]}[2][3]
+    wire b : { x : UInt<42> flip y : UInt<42>[2]}
+    a[0][0].x <= UInt(0)
+    a[0][0].y[0] <= UInt(0)
+    a[0][0].y[1] <= UInt(0)
+    a[0][1].x <= UInt(0)
+    a[0][1].y[0] <= UInt(0)
+    a[0][1].y[1] <= UInt(0)
+    a[1][0].x <= UInt(0)
+    a[1][0].y[0] <= UInt(0)
+    a[1][0].y[1] <= UInt(0)
+    a[1][1].x <= UInt(0)
+    a[1][1].y[0] <= UInt(0)
+    a[1][1].y[1] <= UInt(0)
+    a[2][0].x <= UInt(0)
+    a[2][0].y[0] <= UInt(0)
+    a[2][0].y[1] <= UInt(0)
+    a[2][1].x <= UInt(0)
+    a[2][1].y[0] <= UInt(0)
+    a[2][1].y[1] <= UInt(0)
+    b.x <= UInt(0)
+    a[i][j] <= b
+;CHECK: Finished Expand Connects
+;CHECK: Done!
+