diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/passes/split-exp/print-args.fir | 14 | ||||
| -rw-r--r-- | test/passes/to-verilog/print-args.fir | 25 |
2 files changed, 39 insertions, 0 deletions
diff --git a/test/passes/split-exp/print-args.fir b/test/passes/split-exp/print-args.fir new file mode 100644 index 00000000..df21949d --- /dev/null +++ b/test/passes/split-exp/print-args.fir @@ -0,0 +1,14 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +; CHECK: Split Expressions +; CHECK: node GEN_0 = and(a, b) +; CHECK: printf(clk, UInt<1>("h1"), "%d\n", GEN_0) + +circuit Bug : + module Bug : + input clk : Clock + input a : UInt<1> + input b : UInt<1> + + printf(clk, UInt<1>(1), "%d\n", and(a, b)) + diff --git a/test/passes/to-verilog/print-args.fir b/test/passes/to-verilog/print-args.fir new file mode 100644 index 00000000..f0344366 --- /dev/null +++ b/test/passes/to-verilog/print-args.fir @@ -0,0 +1,25 @@ +; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s + +;CHECK: module Bug( +;CHECK: input clk, +;CHECK: input a, +;CHECK: input b +;CHECK: ); +;CHECK: wire GEN_0; +;CHECK: assign GEN_0 = a & b; +;CHECK: always @(posedge clk) begin +;CHECK: `ifndef SYNTHESIS +;CHECK: if(1'h1) begin +;CHECK: $fwrite(32'h80000002,"%d\n",GEN_0); +;CHECK: end +;CHECK: `endif +;CHECK: end +;CHECK: endmodule + +circuit Bug : + module Bug : + input clk : Clock + input a : UInt<1> + input b : UInt<1> + + printf(clk, UInt<1>(1), "%d\n", and(a, b)) |